| 1 | /* |
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| 2 | * Copyright (C) 2019 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | #ifndef _nbio_2_3_SH_MASK_HEADER |
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| 22 | #define |
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| 23 | |
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| 24 | |
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| 25 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
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| 26 | //BIF_BX_PF_MM_INDEX |
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| 27 | #define BIF_BX_PF_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
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| 28 | #define BIF_BX_PF_MM_INDEX__MM_APER__SHIFT 0x1f |
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| 29 | #define BIF_BX_PF_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
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| 30 | #define BIF_BX_PF_MM_INDEX__MM_APER_MASK 0x80000000L |
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| 31 | //BIF_BX_PF_MM_DATA |
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| 32 | #define BIF_BX_PF_MM_DATA__MM_DATA__SHIFT 0x0 |
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| 33 | #define BIF_BX_PF_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
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| 34 | //BIF_BX_PF_MM_INDEX_HI |
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| 35 | #define BIF_BX_PF_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
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| 36 | #define BIF_BX_PF_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
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| 37 | |
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| 38 | |
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| 39 | // addressBlock: nbio_nbif0_bif_bx_SYSDEC |
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| 40 | //SYSHUB_INDEX_OVLP |
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| 41 | #define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 |
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| 42 | #define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK 0x003FFFFFL |
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| 43 | //SYSHUB_DATA_OVLP |
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| 44 | #define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 |
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| 45 | #define SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK 0xFFFFFFFFL |
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| 46 | //PCIE_INDEX |
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| 47 | #define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 |
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| 48 | #define PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL |
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| 49 | //PCIE_DATA |
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| 50 | #define PCIE_DATA__PCIE_DATA__SHIFT 0x0 |
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| 51 | #define PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL |
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| 52 | //PCIE_INDEX2 |
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| 53 | #define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 |
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| 54 | #define PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL |
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| 55 | //PCIE_DATA2 |
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| 56 | #define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 |
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| 57 | #define PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL |
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| 58 | //SBIOS_SCRATCH_0 |
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| 59 | #define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 |
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| 60 | #define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
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| 61 | //SBIOS_SCRATCH_1 |
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| 62 | #define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 |
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| 63 | #define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
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| 64 | //SBIOS_SCRATCH_2 |
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| 65 | #define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 |
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| 66 | #define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
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| 67 | //SBIOS_SCRATCH_3 |
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| 68 | #define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 |
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| 69 | #define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL |
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| 70 | //BIOS_SCRATCH_0 |
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| 71 | #define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 |
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| 72 | #define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL |
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| 73 | //BIOS_SCRATCH_1 |
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| 74 | #define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 |
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| 75 | #define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL |
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| 76 | //BIOS_SCRATCH_2 |
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| 77 | #define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 |
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| 78 | #define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL |
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| 79 | //BIOS_SCRATCH_3 |
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| 80 | #define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 |
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| 81 | #define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL |
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| 82 | //BIOS_SCRATCH_4 |
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| 83 | #define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 |
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| 84 | #define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL |
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| 85 | //BIOS_SCRATCH_5 |
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| 86 | #define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 |
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| 87 | #define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL |
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| 88 | //BIOS_SCRATCH_6 |
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| 89 | #define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 |
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| 90 | #define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL |
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| 91 | //BIOS_SCRATCH_7 |
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| 92 | #define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 |
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| 93 | #define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL |
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| 94 | //BIOS_SCRATCH_8 |
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| 95 | #define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 |
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| 96 | #define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL |
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| 97 | //BIOS_SCRATCH_9 |
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| 98 | #define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 |
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| 99 | #define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL |
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| 100 | //BIOS_SCRATCH_10 |
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| 101 | #define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 |
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| 102 | #define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL |
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| 103 | //BIOS_SCRATCH_11 |
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| 104 | #define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 |
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| 105 | #define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL |
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| 106 | //BIOS_SCRATCH_12 |
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| 107 | #define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 |
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| 108 | #define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL |
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| 109 | //BIOS_SCRATCH_13 |
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| 110 | #define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 |
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| 111 | #define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL |
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| 112 | //BIOS_SCRATCH_14 |
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| 113 | #define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 |
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| 114 | #define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL |
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| 115 | //BIOS_SCRATCH_15 |
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| 116 | #define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 |
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| 117 | #define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL |
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| 118 | //BIF_RLC_INTR_CNTL |
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| 119 | #define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 |
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| 120 | #define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 |
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| 121 | #define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 |
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| 122 | #define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 |
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| 123 | #define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L |
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| 124 | #define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L |
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| 125 | #define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L |
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| 126 | #define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L |
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| 127 | //BIF_VCE_INTR_CNTL |
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| 128 | #define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 |
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| 129 | #define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 |
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| 130 | #define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 |
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| 131 | #define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 |
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| 132 | #define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L |
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| 133 | #define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L |
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| 134 | #define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L |
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| 135 | #define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L |
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| 136 | //BIF_UVD_INTR_CNTL |
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| 137 | #define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 |
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| 138 | #define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 |
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| 139 | #define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 |
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| 140 | #define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 |
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| 141 | #define BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT 0x1c |
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| 142 | #define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L |
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| 143 | #define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L |
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| 144 | #define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L |
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| 145 | #define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L |
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| 146 | #define BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK 0xF0000000L |
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| 147 | //GFX_MMIOREG_CAM_ADDR0 |
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| 148 | #define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 |
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| 149 | #define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL |
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| 150 | //GFX_MMIOREG_CAM_REMAP_ADDR0 |
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| 151 | #define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 |
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| 152 | #define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL |
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| 153 | //GFX_MMIOREG_CAM_ADDR1 |
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| 154 | #define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 |
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| 155 | #define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL |
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| 156 | //GFX_MMIOREG_CAM_REMAP_ADDR1 |
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| 157 | #define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 |
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| 158 | #define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL |
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| 159 | //GFX_MMIOREG_CAM_ADDR2 |
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| 160 | #define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 |
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| 161 | #define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL |
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| 162 | //GFX_MMIOREG_CAM_REMAP_ADDR2 |
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| 163 | #define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 |
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| 164 | #define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL |
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| 165 | //GFX_MMIOREG_CAM_ADDR3 |
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| 166 | #define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 |
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| 167 | #define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL |
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| 168 | //GFX_MMIOREG_CAM_REMAP_ADDR3 |
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| 169 | #define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 |
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| 170 | #define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL |
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| 171 | //GFX_MMIOREG_CAM_ADDR4 |
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| 172 | #define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 |
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| 173 | #define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL |
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| 174 | //GFX_MMIOREG_CAM_REMAP_ADDR4 |
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| 175 | #define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 |
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| 176 | #define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL |
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| 177 | //GFX_MMIOREG_CAM_ADDR5 |
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| 178 | #define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 |
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| 179 | #define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL |
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| 180 | //GFX_MMIOREG_CAM_REMAP_ADDR5 |
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| 181 | #define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 |
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| 182 | #define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL |
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| 183 | //GFX_MMIOREG_CAM_ADDR6 |
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| 184 | #define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 |
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| 185 | #define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL |
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| 186 | //GFX_MMIOREG_CAM_REMAP_ADDR6 |
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| 187 | #define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 |
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| 188 | #define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL |
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| 189 | //GFX_MMIOREG_CAM_ADDR7 |
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| 190 | #define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 |
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| 191 | #define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL |
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| 192 | //GFX_MMIOREG_CAM_REMAP_ADDR7 |
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| 193 | #define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 |
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| 194 | #define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL |
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| 195 | //GFX_MMIOREG_CAM_CNTL |
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| 196 | #define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 |
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| 197 | #define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL |
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| 198 | //GFX_MMIOREG_CAM_ZERO_CPL |
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| 199 | #define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 |
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| 200 | #define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL |
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| 201 | //GFX_MMIOREG_CAM_ONE_CPL |
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| 202 | #define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 |
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| 203 | #define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL |
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| 204 | //GFX_MMIOREG_CAM_PROGRAMMABLE_CPL |
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| 205 | #define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 |
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| 206 | #define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL |
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| 207 | |
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| 208 | |
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| 209 | // addressBlock: nbio_nbif0_syshub_mmreg_syshubdec |
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| 210 | //SYSHUB_INDEX |
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| 211 | #define SYSHUB_INDEX__INDEX__SHIFT 0x0 |
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| 212 | #define SYSHUB_INDEX__INDEX_MASK 0xFFFFFFFFL |
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| 213 | //SYSHUB_DATA |
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| 214 | #define SYSHUB_DATA__DATA__SHIFT 0x0 |
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| 215 | #define SYSHUB_DATA__DATA_MASK 0xFFFFFFFFL |
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| 216 | |
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| 217 | |
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| 218 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
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| 219 | //RCC_BIF_STRAP0 |
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| 220 | #define RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT 0x0 |
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| 221 | #define RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN__SHIFT 0x1 |
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| 222 | #define RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 |
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| 223 | #define RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 |
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| 224 | #define RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 |
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| 225 | #define RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 |
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| 226 | #define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 |
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| 227 | #define RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 |
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| 228 | #define RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa |
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| 229 | #define RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb |
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| 230 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc |
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| 231 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd |
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| 232 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe |
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| 233 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf |
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| 234 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 |
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| 235 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 |
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| 236 | #define RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 |
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| 237 | #define RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 |
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| 238 | #define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 |
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| 239 | #define RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a |
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| 240 | #define RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b |
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| 241 | #define RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d |
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| 242 | #define RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e |
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| 243 | #define RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f |
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| 244 | #define RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK 0x00000001L |
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| 245 | #define RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN_MASK 0x00000002L |
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| 246 | #define RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L |
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| 247 | #define RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L |
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| 248 | #define RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L |
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| 249 | #define RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L |
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| 250 | #define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L |
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| 251 | #define RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L |
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| 252 | #define RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L |
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| 253 | #define RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L |
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| 254 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L |
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| 255 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L |
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| 256 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L |
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| 257 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L |
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| 258 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L |
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| 259 | #define RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L |
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| 260 | #define RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L |
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| 261 | #define RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L |
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| 262 | #define RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L |
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| 263 | #define RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L |
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| 264 | #define RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L |
|---|
| 265 | #define RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L |
|---|
| 266 | #define RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L |
|---|
| 267 | #define RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L |
|---|
| 268 | //RCC_BIF_STRAP1 |
|---|
| 269 | #define RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 |
|---|
| 270 | #define RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 |
|---|
| 271 | #define RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 |
|---|
| 272 | #define RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 |
|---|
| 273 | #define RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN__SHIFT 0x4 |
|---|
| 274 | #define RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 |
|---|
| 275 | #define RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 |
|---|
| 276 | #define RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 |
|---|
| 277 | #define RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 |
|---|
| 278 | #define RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 |
|---|
| 279 | #define RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa |
|---|
| 280 | #define RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc |
|---|
| 281 | #define RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd |
|---|
| 282 | #define RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf |
|---|
| 283 | #define RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 |
|---|
| 284 | #define RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 |
|---|
| 285 | #define RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 |
|---|
| 286 | #define RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 |
|---|
| 287 | #define RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 |
|---|
| 288 | #define RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 |
|---|
| 289 | #define RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 |
|---|
| 290 | #define RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 |
|---|
| 291 | #define RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 |
|---|
| 292 | #define RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a |
|---|
| 293 | #define RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L |
|---|
| 294 | #define RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L |
|---|
| 295 | #define RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L |
|---|
| 296 | #define RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L |
|---|
| 297 | #define RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN_MASK 0x00000010L |
|---|
| 298 | #define RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L |
|---|
| 299 | #define RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L |
|---|
| 300 | #define RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L |
|---|
| 301 | #define RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L |
|---|
| 302 | #define RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L |
|---|
| 303 | #define RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L |
|---|
| 304 | #define RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L |
|---|
| 305 | #define RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L |
|---|
| 306 | #define RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L |
|---|
| 307 | #define RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L |
|---|
| 308 | #define RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L |
|---|
| 309 | #define RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L |
|---|
| 310 | #define RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L |
|---|
| 311 | #define RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L |
|---|
| 312 | #define RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L |
|---|
| 313 | #define RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L |
|---|
| 314 | #define RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L |
|---|
| 315 | #define RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L |
|---|
| 316 | #define RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L |
|---|
| 317 | //RCC_BIF_STRAP2 |
|---|
| 318 | #define RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 |
|---|
| 319 | #define RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 |
|---|
| 320 | #define RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 |
|---|
| 321 | #define RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 |
|---|
| 322 | #define RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 |
|---|
| 323 | #define RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 |
|---|
| 324 | #define RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 |
|---|
| 325 | #define RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa |
|---|
| 326 | #define RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xc |
|---|
| 327 | #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe |
|---|
| 328 | #define RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf |
|---|
| 329 | #define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 |
|---|
| 330 | #define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 |
|---|
| 331 | #define RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L |
|---|
| 332 | #define RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L |
|---|
| 333 | #define RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L |
|---|
| 334 | #define RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L |
|---|
| 335 | #define RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L |
|---|
| 336 | #define RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L |
|---|
| 337 | #define RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L |
|---|
| 338 | #define RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L |
|---|
| 339 | #define RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00003000L |
|---|
| 340 | #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L |
|---|
| 341 | #define RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L |
|---|
| 342 | #define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L |
|---|
| 343 | #define RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L |
|---|
| 344 | //RCC_BIF_STRAP3 |
|---|
| 345 | #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 |
|---|
| 346 | #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 |
|---|
| 347 | #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL |
|---|
| 348 | #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L |
|---|
| 349 | //RCC_BIF_STRAP4 |
|---|
| 350 | #define RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 |
|---|
| 351 | #define RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 |
|---|
| 352 | #define RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL |
|---|
| 353 | #define RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L |
|---|
| 354 | //RCC_BIF_STRAP5 |
|---|
| 355 | #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 |
|---|
| 356 | #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 |
|---|
| 357 | #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 |
|---|
| 358 | #define RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 |
|---|
| 359 | #define RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 |
|---|
| 360 | #define RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 |
|---|
| 361 | #define RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 |
|---|
| 362 | #define RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 |
|---|
| 363 | #define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 |
|---|
| 364 | #define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b |
|---|
| 365 | #define RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c |
|---|
| 366 | #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL |
|---|
| 367 | #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L |
|---|
| 368 | #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L |
|---|
| 369 | #define RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L |
|---|
| 370 | #define RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L |
|---|
| 371 | #define RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L |
|---|
| 372 | #define RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L |
|---|
| 373 | #define RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L |
|---|
| 374 | #define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L |
|---|
| 375 | #define RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L |
|---|
| 376 | #define RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L |
|---|
| 377 | //RCC_BIF_STRAP6 |
|---|
| 378 | #define RCC_BIF_STRAP6__RESERVED_BIF_STRAP3__SHIFT 0x0 |
|---|
| 379 | #define RCC_BIF_STRAP6__RESERVED_BIF_STRAP3_MASK 0xFFFFFFFFL |
|---|
| 380 | //RCC_DEV0_PORT_STRAP0 |
|---|
| 381 | #define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 |
|---|
| 382 | #define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 |
|---|
| 383 | #define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 |
|---|
| 384 | #define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 |
|---|
| 385 | #define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 |
|---|
| 386 | #define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 |
|---|
| 387 | #define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 |
|---|
| 388 | #define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 |
|---|
| 389 | #define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c |
|---|
| 390 | #define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f |
|---|
| 391 | #define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L |
|---|
| 392 | #define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L |
|---|
| 393 | #define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L |
|---|
| 394 | #define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L |
|---|
| 395 | #define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001FFFE0L |
|---|
| 396 | #define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L |
|---|
| 397 | #define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L |
|---|
| 398 | #define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L |
|---|
| 399 | #define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L |
|---|
| 400 | #define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L |
|---|
| 401 | //RCC_DEV0_PORT_STRAP1 |
|---|
| 402 | #define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 |
|---|
| 403 | #define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 |
|---|
| 404 | #define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL |
|---|
| 405 | #define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L |
|---|
| 406 | //RCC_DEV0_PORT_STRAP2 |
|---|
| 407 | #define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 |
|---|
| 408 | #define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 |
|---|
| 409 | #define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 |
|---|
| 410 | #define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 |
|---|
| 411 | #define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 |
|---|
| 412 | #define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 |
|---|
| 413 | #define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 |
|---|
| 414 | #define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 |
|---|
| 415 | #define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 |
|---|
| 416 | #define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 |
|---|
| 417 | #define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc |
|---|
| 418 | #define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd |
|---|
| 419 | #define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe |
|---|
| 420 | #define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf |
|---|
| 421 | #define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 |
|---|
| 422 | #define RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 |
|---|
| 423 | #define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x12 |
|---|
| 424 | #define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 |
|---|
| 425 | #define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 |
|---|
| 426 | #define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a |
|---|
| 427 | #define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d |
|---|
| 428 | #define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L |
|---|
| 429 | #define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L |
|---|
| 430 | #define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L |
|---|
| 431 | #define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L |
|---|
| 432 | #define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L |
|---|
| 433 | #define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L |
|---|
| 434 | #define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L |
|---|
| 435 | #define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L |
|---|
| 436 | #define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L |
|---|
| 437 | #define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L |
|---|
| 438 | #define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L |
|---|
| 439 | #define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L |
|---|
| 440 | #define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L |
|---|
| 441 | #define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L |
|---|
| 442 | #define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L |
|---|
| 443 | #define RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L |
|---|
| 444 | #define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x000C0000L |
|---|
| 445 | #define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L |
|---|
| 446 | #define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L |
|---|
| 447 | #define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L |
|---|
| 448 | #define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L |
|---|
| 449 | //RCC_DEV0_PORT_STRAP3 |
|---|
| 450 | #define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 |
|---|
| 451 | #define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 |
|---|
| 452 | #define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 |
|---|
| 453 | #define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 |
|---|
| 454 | #define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 |
|---|
| 455 | #define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 |
|---|
| 456 | #define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 |
|---|
| 457 | #define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 |
|---|
| 458 | #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb |
|---|
| 459 | #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe |
|---|
| 460 | #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 |
|---|
| 461 | #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 |
|---|
| 462 | #define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 |
|---|
| 463 | #define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b |
|---|
| 464 | #define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d |
|---|
| 465 | #define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e |
|---|
| 466 | #define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f |
|---|
| 467 | #define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L |
|---|
| 468 | #define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L |
|---|
| 469 | #define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L |
|---|
| 470 | #define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L |
|---|
| 471 | #define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L |
|---|
| 472 | #define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L |
|---|
| 473 | #define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L |
|---|
| 474 | #define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L |
|---|
| 475 | #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L |
|---|
| 476 | #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L |
|---|
| 477 | #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L |
|---|
| 478 | #define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L |
|---|
| 479 | #define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L |
|---|
| 480 | #define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L |
|---|
| 481 | #define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L |
|---|
| 482 | #define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0_MASK 0x40000000L |
|---|
| 483 | #define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L |
|---|
| 484 | //RCC_DEV0_PORT_STRAP4 |
|---|
| 485 | #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 |
|---|
| 486 | #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 |
|---|
| 487 | #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 |
|---|
| 488 | #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 |
|---|
| 489 | #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL |
|---|
| 490 | #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L |
|---|
| 491 | #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L |
|---|
| 492 | #define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L |
|---|
| 493 | //RCC_DEV0_PORT_STRAP5 |
|---|
| 494 | #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 |
|---|
| 495 | #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 |
|---|
| 496 | #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 |
|---|
| 497 | #define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 |
|---|
| 498 | #define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 |
|---|
| 499 | #define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 |
|---|
| 500 | #define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 |
|---|
| 501 | #define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 |
|---|
| 502 | #define RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 |
|---|
| 503 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 |
|---|
| 504 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 |
|---|
| 505 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 |
|---|
| 506 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a |
|---|
| 507 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b |
|---|
| 508 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c |
|---|
| 509 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d |
|---|
| 510 | #define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e |
|---|
| 511 | #define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f |
|---|
| 512 | #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL |
|---|
| 513 | #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L |
|---|
| 514 | #define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L |
|---|
| 515 | #define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L |
|---|
| 516 | #define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L |
|---|
| 517 | #define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L |
|---|
| 518 | #define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L |
|---|
| 519 | #define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L |
|---|
| 520 | #define RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L |
|---|
| 521 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L |
|---|
| 522 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L |
|---|
| 523 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L |
|---|
| 524 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L |
|---|
| 525 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L |
|---|
| 526 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L |
|---|
| 527 | #define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L |
|---|
| 528 | #define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L |
|---|
| 529 | #define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L |
|---|
| 530 | //RCC_DEV0_PORT_STRAP6 |
|---|
| 531 | #define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 |
|---|
| 532 | #define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 |
|---|
| 533 | #define RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 |
|---|
| 534 | #define RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 |
|---|
| 535 | #define RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 |
|---|
| 536 | #define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 |
|---|
| 537 | #define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 |
|---|
| 538 | #define RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 |
|---|
| 539 | #define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 |
|---|
| 540 | #define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc |
|---|
| 541 | #define RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 |
|---|
| 542 | #define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L |
|---|
| 543 | #define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L |
|---|
| 544 | #define RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L |
|---|
| 545 | #define RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L |
|---|
| 546 | #define RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L |
|---|
| 547 | #define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L |
|---|
| 548 | #define RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L |
|---|
| 549 | #define RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L |
|---|
| 550 | #define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L |
|---|
| 551 | #define RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L |
|---|
| 552 | #define RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L |
|---|
| 553 | //RCC_DEV0_PORT_STRAP7 |
|---|
| 554 | #define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 |
|---|
| 555 | #define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 |
|---|
| 556 | #define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc |
|---|
| 557 | #define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 |
|---|
| 558 | #define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 |
|---|
| 559 | #define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d |
|---|
| 560 | #define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL |
|---|
| 561 | #define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L |
|---|
| 562 | #define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L |
|---|
| 563 | #define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L |
|---|
| 564 | #define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L |
|---|
| 565 | #define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L |
|---|
| 566 | //RCC_DEV0_PORT_STRAP8 |
|---|
| 567 | #define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 |
|---|
| 568 | #define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 |
|---|
| 569 | #define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 |
|---|
| 570 | #define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 |
|---|
| 571 | #define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL |
|---|
| 572 | #define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L |
|---|
| 573 | #define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L |
|---|
| 574 | #define RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L |
|---|
| 575 | //RCC_DEV0_PORT_STRAP9 |
|---|
| 576 | #define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 |
|---|
| 577 | #define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 |
|---|
| 578 | #define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL |
|---|
| 579 | #define RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L |
|---|
| 580 | //RCC_DEV0_EPF0_STRAP0 |
|---|
| 581 | #define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
|---|
| 582 | #define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
|---|
| 583 | #define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
|---|
| 584 | #define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
|---|
| 585 | #define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
|---|
| 586 | #define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
|---|
| 587 | #define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
|---|
| 588 | #define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
|---|
| 589 | #define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 590 | #define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
|---|
| 591 | #define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
|---|
| 592 | #define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
|---|
| 593 | #define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
|---|
| 594 | #define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
|---|
| 595 | #define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
|---|
| 596 | #define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
|---|
| 597 | //RCC_DEV0_EPF0_STRAP1 |
|---|
| 598 | #define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
|---|
| 599 | #define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 |
|---|
| 600 | #define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 601 | #define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L |
|---|
| 602 | //RCC_DEV0_EPF0_STRAP13 |
|---|
| 603 | #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 |
|---|
| 604 | #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 |
|---|
| 605 | #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 |
|---|
| 606 | #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL |
|---|
| 607 | #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L |
|---|
| 608 | #define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L |
|---|
| 609 | //RCC_DEV0_EPF0_STRAP2 |
|---|
| 610 | #define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 |
|---|
| 611 | #define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 |
|---|
| 612 | #define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 |
|---|
| 613 | #define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 |
|---|
| 614 | #define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 |
|---|
| 615 | #define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 |
|---|
| 616 | #define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe |
|---|
| 617 | #define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf |
|---|
| 618 | #define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 |
|---|
| 619 | #define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 |
|---|
| 620 | #define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 |
|---|
| 621 | #define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 |
|---|
| 622 | #define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 |
|---|
| 623 | #define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 |
|---|
| 624 | #define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 |
|---|
| 625 | #define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 |
|---|
| 626 | #define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b |
|---|
| 627 | #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c |
|---|
| 628 | #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d |
|---|
| 629 | #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e |
|---|
| 630 | #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f |
|---|
| 631 | #define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L |
|---|
| 632 | #define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003EL |
|---|
| 633 | #define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L |
|---|
| 634 | #define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L |
|---|
| 635 | #define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L |
|---|
| 636 | #define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L |
|---|
| 637 | #define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L |
|---|
| 638 | #define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L |
|---|
| 639 | #define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L |
|---|
| 640 | #define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L |
|---|
| 641 | #define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L |
|---|
| 642 | #define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L |
|---|
| 643 | #define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L |
|---|
| 644 | #define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L |
|---|
| 645 | #define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L |
|---|
| 646 | #define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L |
|---|
| 647 | #define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L |
|---|
| 648 | #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L |
|---|
| 649 | #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L |
|---|
| 650 | #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L |
|---|
| 651 | #define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L |
|---|
| 652 | //RCC_DEV0_EPF0_STRAP3 |
|---|
| 653 | #define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 |
|---|
| 654 | #define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 |
|---|
| 655 | #define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 |
|---|
| 656 | #define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 |
|---|
| 657 | #define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 |
|---|
| 658 | #define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 |
|---|
| 659 | #define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 |
|---|
| 660 | #define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 |
|---|
| 661 | #define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 |
|---|
| 662 | #define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a |
|---|
| 663 | #define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b |
|---|
| 664 | #define RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c |
|---|
| 665 | #define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L |
|---|
| 666 | #define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L |
|---|
| 667 | #define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003FFFCL |
|---|
| 668 | #define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L |
|---|
| 669 | #define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L |
|---|
| 670 | #define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L |
|---|
| 671 | #define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L |
|---|
| 672 | #define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L |
|---|
| 673 | #define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0_MASK 0x02000000L |
|---|
| 674 | #define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L |
|---|
| 675 | #define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L |
|---|
| 676 | #define RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L |
|---|
| 677 | //RCC_DEV0_EPF0_STRAP4 |
|---|
| 678 | #define RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 |
|---|
| 679 | #define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 |
|---|
| 680 | #define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 |
|---|
| 681 | #define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 |
|---|
| 682 | #define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 |
|---|
| 683 | #define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c |
|---|
| 684 | #define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f |
|---|
| 685 | #define RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL |
|---|
| 686 | #define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L |
|---|
| 687 | #define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L |
|---|
| 688 | #define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L |
|---|
| 689 | #define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L |
|---|
| 690 | #define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L |
|---|
| 691 | #define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L |
|---|
| 692 | //RCC_DEV0_EPF0_STRAP5 |
|---|
| 693 | #define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 |
|---|
| 694 | #define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 695 | //RCC_DEV0_EPF0_STRAP8 |
|---|
| 696 | #define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 |
|---|
| 697 | #define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 |
|---|
| 698 | #define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 |
|---|
| 699 | #define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 |
|---|
| 700 | #define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 |
|---|
| 701 | #define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 |
|---|
| 702 | #define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 |
|---|
| 703 | #define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd |
|---|
| 704 | #define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xf |
|---|
| 705 | #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x11 |
|---|
| 706 | #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x14 |
|---|
| 707 | #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x18 |
|---|
| 708 | #define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a |
|---|
| 709 | #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b |
|---|
| 710 | #define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e |
|---|
| 711 | #define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L |
|---|
| 712 | #define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L |
|---|
| 713 | #define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00000010L |
|---|
| 714 | #define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00000060L |
|---|
| 715 | #define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L |
|---|
| 716 | #define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L |
|---|
| 717 | #define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L |
|---|
| 718 | #define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x00006000L |
|---|
| 719 | #define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00018000L |
|---|
| 720 | #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x000E0000L |
|---|
| 721 | #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00F00000L |
|---|
| 722 | #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03000000L |
|---|
| 723 | #define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L |
|---|
| 724 | #define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L |
|---|
| 725 | #define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L |
|---|
| 726 | //RCC_DEV0_EPF0_STRAP9 |
|---|
| 727 | #define RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 |
|---|
| 728 | #define RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 |
|---|
| 729 | #define RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 |
|---|
| 730 | #define RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 |
|---|
| 731 | #define RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 732 | #define RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L |
|---|
| 733 | #define RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L |
|---|
| 734 | #define RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L |
|---|
| 735 | //RCC_DEV0_EPF1_STRAP0 |
|---|
| 736 | #define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 |
|---|
| 737 | #define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 |
|---|
| 738 | #define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 |
|---|
| 739 | #define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c |
|---|
| 740 | #define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d |
|---|
| 741 | #define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e |
|---|
| 742 | #define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f |
|---|
| 743 | #define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL |
|---|
| 744 | #define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L |
|---|
| 745 | #define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L |
|---|
| 746 | #define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L |
|---|
| 747 | #define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L |
|---|
| 748 | #define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L |
|---|
| 749 | #define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L |
|---|
| 750 | //RCC_DEV0_EPF1_STRAP10 |
|---|
| 751 | #define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 752 | #define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 |
|---|
| 753 | #define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 754 | #define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL |
|---|
| 755 | //RCC_DEV0_EPF1_STRAP11 |
|---|
| 756 | #define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 757 | #define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 |
|---|
| 758 | #define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 759 | #define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL |
|---|
| 760 | //RCC_DEV0_EPF1_STRAP12 |
|---|
| 761 | #define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 762 | #define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 |
|---|
| 763 | #define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 764 | #define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL |
|---|
| 765 | //RCC_DEV0_EPF1_STRAP13 |
|---|
| 766 | #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 |
|---|
| 767 | #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 |
|---|
| 768 | #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 |
|---|
| 769 | #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL |
|---|
| 770 | #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L |
|---|
| 771 | #define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L |
|---|
| 772 | //RCC_DEV0_EPF1_STRAP2 |
|---|
| 773 | #define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 |
|---|
| 774 | #define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 |
|---|
| 775 | #define RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 |
|---|
| 776 | #define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe |
|---|
| 777 | #define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 |
|---|
| 778 | #define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 |
|---|
| 779 | #define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 |
|---|
| 780 | #define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 |
|---|
| 781 | #define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 |
|---|
| 782 | #define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 |
|---|
| 783 | #define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 |
|---|
| 784 | #define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 |
|---|
| 785 | #define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c |
|---|
| 786 | #define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d |
|---|
| 787 | #define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e |
|---|
| 788 | #define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f |
|---|
| 789 | #define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L |
|---|
| 790 | #define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L |
|---|
| 791 | #define RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L |
|---|
| 792 | #define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L |
|---|
| 793 | #define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L |
|---|
| 794 | #define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L |
|---|
| 795 | #define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L |
|---|
| 796 | #define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L |
|---|
| 797 | #define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L |
|---|
| 798 | #define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L |
|---|
| 799 | #define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L |
|---|
| 800 | #define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L |
|---|
| 801 | #define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L |
|---|
| 802 | #define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L |
|---|
| 803 | #define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L |
|---|
| 804 | #define RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L |
|---|
| 805 | //RCC_DEV0_EPF1_STRAP3 |
|---|
| 806 | #define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 |
|---|
| 807 | #define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 |
|---|
| 808 | #define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 |
|---|
| 809 | #define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 |
|---|
| 810 | #define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 |
|---|
| 811 | #define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 |
|---|
| 812 | #define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 |
|---|
| 813 | #define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 |
|---|
| 814 | #define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a |
|---|
| 815 | #define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b |
|---|
| 816 | #define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L |
|---|
| 817 | #define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L |
|---|
| 818 | #define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003FFFCL |
|---|
| 819 | #define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L |
|---|
| 820 | #define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L |
|---|
| 821 | #define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L |
|---|
| 822 | #define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L |
|---|
| 823 | #define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1_MASK 0x02000000L |
|---|
| 824 | #define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L |
|---|
| 825 | #define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L |
|---|
| 826 | //RCC_DEV0_EPF1_STRAP4 |
|---|
| 827 | #define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 |
|---|
| 828 | #define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 |
|---|
| 829 | #define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 |
|---|
| 830 | #define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 |
|---|
| 831 | #define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c |
|---|
| 832 | #define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f |
|---|
| 833 | #define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L |
|---|
| 834 | #define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L |
|---|
| 835 | #define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L |
|---|
| 836 | #define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L |
|---|
| 837 | #define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L |
|---|
| 838 | #define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L |
|---|
| 839 | //RCC_DEV0_EPF1_STRAP5 |
|---|
| 840 | #define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 |
|---|
| 841 | #define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL |
|---|
| 842 | //RCC_DEV0_EPF1_STRAP6 |
|---|
| 843 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 844 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 |
|---|
| 845 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 |
|---|
| 846 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 |
|---|
| 847 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 |
|---|
| 848 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 |
|---|
| 849 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 |
|---|
| 850 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 |
|---|
| 851 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 |
|---|
| 852 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 |
|---|
| 853 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 854 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L |
|---|
| 855 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L |
|---|
| 856 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1_MASK 0x00000070L |
|---|
| 857 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L |
|---|
| 858 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L |
|---|
| 859 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L |
|---|
| 860 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L |
|---|
| 861 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L |
|---|
| 862 | #define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L |
|---|
| 863 | //RCC_DEV0_EPF1_STRAP7 |
|---|
| 864 | #define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 865 | #define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 |
|---|
| 866 | #define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1__SHIFT 0x14 |
|---|
| 867 | #define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1__SHIFT 0x16 |
|---|
| 868 | #define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1__SHIFT 0x17 |
|---|
| 869 | #define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1__SHIFT 0x18 |
|---|
| 870 | #define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1__SHIFT 0x1a |
|---|
| 871 | #define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 872 | #define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1_MASK 0x0000001EL |
|---|
| 873 | #define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1_MASK 0x00300000L |
|---|
| 874 | #define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1_MASK 0x00400000L |
|---|
| 875 | #define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1_MASK 0x00800000L |
|---|
| 876 | #define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1_MASK 0x03000000L |
|---|
| 877 | #define RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1_MASK 0xFC000000L |
|---|
| 878 | |
|---|
| 879 | |
|---|
| 880 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
|---|
| 881 | //EP_PCIE_SCRATCH |
|---|
| 882 | #define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
|---|
| 883 | #define EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 884 | //EP_PCIE_CNTL |
|---|
| 885 | #define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
|---|
| 886 | #define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
|---|
| 887 | #define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
|---|
| 888 | #define EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
|---|
| 889 | #define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
|---|
| 890 | #define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
|---|
| 891 | //EP_PCIE_INT_CNTL |
|---|
| 892 | #define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
|---|
| 893 | #define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
|---|
| 894 | #define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
|---|
| 895 | #define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
|---|
| 896 | #define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
|---|
| 897 | #define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
|---|
| 898 | #define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
|---|
| 899 | #define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
|---|
| 900 | #define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
|---|
| 901 | #define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
|---|
| 902 | #define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
|---|
| 903 | #define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
|---|
| 904 | //EP_PCIE_INT_STATUS |
|---|
| 905 | #define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
|---|
| 906 | #define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
|---|
| 907 | #define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
|---|
| 908 | #define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
|---|
| 909 | #define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
|---|
| 910 | #define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
|---|
| 911 | #define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
|---|
| 912 | #define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
|---|
| 913 | #define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
|---|
| 914 | #define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
|---|
| 915 | #define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
|---|
| 916 | #define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
|---|
| 917 | //EP_PCIE_RX_CNTL2 |
|---|
| 918 | #define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
|---|
| 919 | #define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
|---|
| 920 | //EP_PCIE_BUS_CNTL |
|---|
| 921 | #define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
|---|
| 922 | #define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
|---|
| 923 | //EP_PCIE_CFG_CNTL |
|---|
| 924 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
|---|
| 925 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
|---|
| 926 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
|---|
| 927 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
|---|
| 928 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
|---|
| 929 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
|---|
| 930 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
|---|
| 931 | #define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
|---|
| 932 | //EP_PCIE_TX_LTR_CNTL |
|---|
| 933 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
|---|
| 934 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
|---|
| 935 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
|---|
| 936 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
|---|
| 937 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
|---|
| 938 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
|---|
| 939 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
|---|
| 940 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
|---|
| 941 | #define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
|---|
| 942 | #define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
|---|
| 943 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
|---|
| 944 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
|---|
| 945 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
|---|
| 946 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
|---|
| 947 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
|---|
| 948 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
|---|
| 949 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
|---|
| 950 | #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
|---|
| 951 | #define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
|---|
| 952 | #define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
|---|
| 953 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 954 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 955 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 956 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 957 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 958 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 959 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 960 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 961 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 962 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 963 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 964 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 965 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 966 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 967 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 968 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 969 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 970 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 971 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 972 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 973 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 974 | //PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 975 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 976 | #define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 977 | //EP_PCIE_STRAP_MISC |
|---|
| 978 | #define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d |
|---|
| 979 | #define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L |
|---|
| 980 | //EP_PCIE_STRAP_MISC2 |
|---|
| 981 | #define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 |
|---|
| 982 | #define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L |
|---|
| 983 | //EP_PCIE_F0_DPA_CAP |
|---|
| 984 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 985 | #define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 986 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 987 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 988 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 989 | #define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 990 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 991 | #define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 992 | //EP_PCIE_F0_DPA_LATENCY_INDICATOR |
|---|
| 993 | #define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 994 | #define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
|---|
| 995 | //EP_PCIE_F0_DPA_CNTL |
|---|
| 996 | #define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 997 | #define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
|---|
| 998 | #define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 999 | #define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
|---|
| 1000 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 1001 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 1002 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 1003 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 1004 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 1005 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 1006 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 1007 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 1008 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 1009 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 1010 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 1011 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 1012 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 1013 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 1014 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 1015 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 1016 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 1017 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 1018 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 1019 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 1020 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 1021 | //PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 1022 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 1023 | #define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 1024 | //EP_PCIE_PME_CONTROL |
|---|
| 1025 | #define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
|---|
| 1026 | #define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
|---|
| 1027 | //EP_PCIEP_RESERVED |
|---|
| 1028 | #define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
|---|
| 1029 | #define EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 1030 | //EP_PCIE_TX_CNTL |
|---|
| 1031 | #define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
|---|
| 1032 | #define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
|---|
| 1033 | #define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
|---|
| 1034 | #define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
|---|
| 1035 | #define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
|---|
| 1036 | #define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
|---|
| 1037 | #define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
|---|
| 1038 | #define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
|---|
| 1039 | #define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
|---|
| 1040 | #define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
|---|
| 1041 | //EP_PCIE_TX_REQUESTER_ID |
|---|
| 1042 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
|---|
| 1043 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
|---|
| 1044 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
|---|
| 1045 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
|---|
| 1046 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
|---|
| 1047 | #define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
|---|
| 1048 | //EP_PCIE_ERR_CNTL |
|---|
| 1049 | #define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
|---|
| 1050 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
|---|
| 1051 | #define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
|---|
| 1052 | #define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
|---|
| 1053 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 |
|---|
| 1054 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 |
|---|
| 1055 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a |
|---|
| 1056 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b |
|---|
| 1057 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c |
|---|
| 1058 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d |
|---|
| 1059 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e |
|---|
| 1060 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f |
|---|
| 1061 | #define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
|---|
| 1062 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
|---|
| 1063 | #define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
|---|
| 1064 | #define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
|---|
| 1065 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L |
|---|
| 1066 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L |
|---|
| 1067 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L |
|---|
| 1068 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L |
|---|
| 1069 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L |
|---|
| 1070 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L |
|---|
| 1071 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L |
|---|
| 1072 | #define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L |
|---|
| 1073 | //EP_PCIE_RX_CNTL |
|---|
| 1074 | #define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
|---|
| 1075 | #define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
|---|
| 1076 | #define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
|---|
| 1077 | #define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
|---|
| 1078 | #define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
|---|
| 1079 | #define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
|---|
| 1080 | #define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
|---|
| 1081 | #define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
|---|
| 1082 | #define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
|---|
| 1083 | #define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
|---|
| 1084 | #define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
|---|
| 1085 | #define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
|---|
| 1086 | #define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
|---|
| 1087 | #define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
|---|
| 1088 | #define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
|---|
| 1089 | #define EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
|---|
| 1090 | //EP_PCIE_LC_SPEED_CNTL |
|---|
| 1091 | #define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
|---|
| 1092 | #define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
|---|
| 1093 | #define EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 |
|---|
| 1094 | #define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
|---|
| 1095 | #define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
|---|
| 1096 | #define EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L |
|---|
| 1097 | |
|---|
| 1098 | |
|---|
| 1099 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
|---|
| 1100 | //DN_PCIE_RESERVED |
|---|
| 1101 | #define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
|---|
| 1102 | #define DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 1103 | //DN_PCIE_SCRATCH |
|---|
| 1104 | #define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
|---|
| 1105 | #define DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 1106 | //DN_PCIE_CNTL |
|---|
| 1107 | #define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
|---|
| 1108 | #define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
|---|
| 1109 | #define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
|---|
| 1110 | #define DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
|---|
| 1111 | #define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
|---|
| 1112 | #define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
|---|
| 1113 | //DN_PCIE_CONFIG_CNTL |
|---|
| 1114 | #define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
|---|
| 1115 | #define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
|---|
| 1116 | //DN_PCIE_RX_CNTL2 |
|---|
| 1117 | #define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
|---|
| 1118 | #define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
|---|
| 1119 | //DN_PCIE_BUS_CNTL |
|---|
| 1120 | #define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
|---|
| 1121 | #define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
|---|
| 1122 | #define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
|---|
| 1123 | #define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
|---|
| 1124 | //DN_PCIE_CFG_CNTL |
|---|
| 1125 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
|---|
| 1126 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
|---|
| 1127 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
|---|
| 1128 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
|---|
| 1129 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
|---|
| 1130 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
|---|
| 1131 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
|---|
| 1132 | #define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
|---|
| 1133 | //DN_PCIE_STRAP_F0 |
|---|
| 1134 | #define DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 |
|---|
| 1135 | #define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 |
|---|
| 1136 | #define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 |
|---|
| 1137 | #define DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L |
|---|
| 1138 | #define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L |
|---|
| 1139 | #define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L |
|---|
| 1140 | //DN_PCIE_STRAP_MISC |
|---|
| 1141 | #define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 |
|---|
| 1142 | #define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d |
|---|
| 1143 | #define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L |
|---|
| 1144 | #define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L |
|---|
| 1145 | //DN_PCIE_STRAP_MISC2 |
|---|
| 1146 | #define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 |
|---|
| 1147 | #define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L |
|---|
| 1148 | |
|---|
| 1149 | |
|---|
| 1150 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
|---|
| 1151 | //PCIE_ERR_CNTL |
|---|
| 1152 | #define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
|---|
| 1153 | #define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
|---|
| 1154 | #define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
|---|
| 1155 | #define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
|---|
| 1156 | #define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
|---|
| 1157 | #define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
|---|
| 1158 | #define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
|---|
| 1159 | #define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
|---|
| 1160 | //PCIE_RX_CNTL |
|---|
| 1161 | #define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
|---|
| 1162 | #define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
|---|
| 1163 | #define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
|---|
| 1164 | #define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
|---|
| 1165 | #define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
|---|
| 1166 | #define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
|---|
| 1167 | #define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
|---|
| 1168 | #define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
|---|
| 1169 | #define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
|---|
| 1170 | #define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
|---|
| 1171 | //PCIE_LC_SPEED_CNTL |
|---|
| 1172 | #define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
|---|
| 1173 | #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
|---|
| 1174 | #define PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 |
|---|
| 1175 | #define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
|---|
| 1176 | #define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
|---|
| 1177 | #define PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L |
|---|
| 1178 | //PCIE_LC_CNTL2 |
|---|
| 1179 | #define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
|---|
| 1180 | #define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
|---|
| 1181 | //PCIEP_STRAP_MISC |
|---|
| 1182 | #define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa |
|---|
| 1183 | #define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L |
|---|
| 1184 | //LTR_MSG_INFO_FROM_EP |
|---|
| 1185 | #define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
|---|
| 1186 | #define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
|---|
| 1187 | |
|---|
| 1188 | |
|---|
| 1189 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] |
|---|
| 1190 | //RCC_DEV0_EPF0_RCC_ERR_LOG |
|---|
| 1191 | #define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 1192 | #define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 1193 | #define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 1194 | #define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 1195 | //RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN |
|---|
| 1196 | #define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 1197 | #define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 1198 | //RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE |
|---|
| 1199 | #define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 1200 | #define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 1201 | //RCC_DEV0_EPF0_RCC_CONFIG_RESERVED |
|---|
| 1202 | #define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 1203 | #define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 1204 | //RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 1205 | #define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 1206 | #define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 1207 | #define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 1208 | #define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 1209 | |
|---|
| 1210 | |
|---|
| 1211 | // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 |
|---|
| 1212 | //RCC_ERR_INT_CNTL |
|---|
| 1213 | #define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 |
|---|
| 1214 | #define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L |
|---|
| 1215 | //RCC_BACO_CNTL_MISC |
|---|
| 1216 | #define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 |
|---|
| 1217 | #define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 |
|---|
| 1218 | #define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L |
|---|
| 1219 | #define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L |
|---|
| 1220 | //RCC_RESET_EN |
|---|
| 1221 | #define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf |
|---|
| 1222 | #define RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L |
|---|
| 1223 | //RCC_VDM_SUPPORT |
|---|
| 1224 | #define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 |
|---|
| 1225 | #define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 |
|---|
| 1226 | #define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 |
|---|
| 1227 | #define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 |
|---|
| 1228 | #define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 |
|---|
| 1229 | #define RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L |
|---|
| 1230 | #define RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L |
|---|
| 1231 | #define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L |
|---|
| 1232 | #define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L |
|---|
| 1233 | #define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L |
|---|
| 1234 | //RCC_MARGIN_PARAM_CNTL0 |
|---|
| 1235 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 |
|---|
| 1236 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 |
|---|
| 1237 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 |
|---|
| 1238 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 |
|---|
| 1239 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 |
|---|
| 1240 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 |
|---|
| 1241 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb |
|---|
| 1242 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 |
|---|
| 1243 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 |
|---|
| 1244 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L |
|---|
| 1245 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L |
|---|
| 1246 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L |
|---|
| 1247 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L |
|---|
| 1248 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L |
|---|
| 1249 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L |
|---|
| 1250 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L |
|---|
| 1251 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L |
|---|
| 1252 | #define RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L |
|---|
| 1253 | //RCC_MARGIN_PARAM_CNTL1 |
|---|
| 1254 | #define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 |
|---|
| 1255 | #define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 |
|---|
| 1256 | #define RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc |
|---|
| 1257 | #define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 |
|---|
| 1258 | #define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL |
|---|
| 1259 | #define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L |
|---|
| 1260 | #define RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L |
|---|
| 1261 | #define RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L |
|---|
| 1262 | //RCC_GPUIOV_REGION |
|---|
| 1263 | #define RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 |
|---|
| 1264 | #define RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 |
|---|
| 1265 | #define RCC_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L |
|---|
| 1266 | #define RCC_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L |
|---|
| 1267 | //RCC_PEER_REG_RANGE0 |
|---|
| 1268 | #define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 |
|---|
| 1269 | #define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 |
|---|
| 1270 | #define RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL |
|---|
| 1271 | #define RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L |
|---|
| 1272 | //RCC_PEER_REG_RANGE1 |
|---|
| 1273 | #define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 |
|---|
| 1274 | #define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 |
|---|
| 1275 | #define RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL |
|---|
| 1276 | #define RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L |
|---|
| 1277 | //RCC_BUS_CNTL |
|---|
| 1278 | #define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 |
|---|
| 1279 | #define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 |
|---|
| 1280 | #define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 |
|---|
| 1281 | #define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 |
|---|
| 1282 | #define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 |
|---|
| 1283 | #define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 |
|---|
| 1284 | #define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 |
|---|
| 1285 | #define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc |
|---|
| 1286 | #define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd |
|---|
| 1287 | #define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 |
|---|
| 1288 | #define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 |
|---|
| 1289 | #define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 |
|---|
| 1290 | #define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 |
|---|
| 1291 | #define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 |
|---|
| 1292 | #define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 |
|---|
| 1293 | #define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 |
|---|
| 1294 | #define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 |
|---|
| 1295 | #define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c |
|---|
| 1296 | #define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d |
|---|
| 1297 | #define RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L |
|---|
| 1298 | #define RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L |
|---|
| 1299 | #define RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L |
|---|
| 1300 | #define RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L |
|---|
| 1301 | #define RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L |
|---|
| 1302 | #define RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L |
|---|
| 1303 | #define RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L |
|---|
| 1304 | #define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L |
|---|
| 1305 | #define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L |
|---|
| 1306 | #define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L |
|---|
| 1307 | #define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L |
|---|
| 1308 | #define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L |
|---|
| 1309 | #define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L |
|---|
| 1310 | #define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L |
|---|
| 1311 | #define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L |
|---|
| 1312 | #define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L |
|---|
| 1313 | #define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L |
|---|
| 1314 | #define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L |
|---|
| 1315 | #define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L |
|---|
| 1316 | //RCC_CONFIG_CNTL |
|---|
| 1317 | #define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 |
|---|
| 1318 | #define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 |
|---|
| 1319 | #define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 |
|---|
| 1320 | #define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L |
|---|
| 1321 | #define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L |
|---|
| 1322 | #define RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L |
|---|
| 1323 | //RCC_CONFIG_F0_BASE |
|---|
| 1324 | #define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 |
|---|
| 1325 | #define RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL |
|---|
| 1326 | //RCC_CONFIG_APER_SIZE |
|---|
| 1327 | #define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 |
|---|
| 1328 | #define RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL |
|---|
| 1329 | //RCC_CONFIG_REG_APER_SIZE |
|---|
| 1330 | #define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 |
|---|
| 1331 | #define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x000FFFFFL |
|---|
| 1332 | //RCC_XDMA_LO |
|---|
| 1333 | #define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 |
|---|
| 1334 | #define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f |
|---|
| 1335 | #define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL |
|---|
| 1336 | #define RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L |
|---|
| 1337 | //RCC_XDMA_HI |
|---|
| 1338 | #define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 |
|---|
| 1339 | #define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL |
|---|
| 1340 | //RCC_FEATURES_CONTROL_MISC |
|---|
| 1341 | #define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 |
|---|
| 1342 | #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 |
|---|
| 1343 | #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 |
|---|
| 1344 | #define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 |
|---|
| 1345 | #define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 |
|---|
| 1346 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 |
|---|
| 1347 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa |
|---|
| 1348 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb |
|---|
| 1349 | #define 0xc |
|---|
| 1350 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd |
|---|
| 1351 | #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe |
|---|
| 1352 | #define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf |
|---|
| 1353 | #define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 |
|---|
| 1354 | #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 |
|---|
| 1355 | #define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 |
|---|
| 1356 | #define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 |
|---|
| 1357 | #define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L |
|---|
| 1358 | #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L |
|---|
| 1359 | #define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L |
|---|
| 1360 | #define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L |
|---|
| 1361 | #define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L |
|---|
| 1362 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L |
|---|
| 1363 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L |
|---|
| 1364 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L |
|---|
| 1365 | #define 0x00001000L |
|---|
| 1366 | #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L |
|---|
| 1367 | #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L |
|---|
| 1368 | #define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L |
|---|
| 1369 | #define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L |
|---|
| 1370 | #define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L |
|---|
| 1371 | #define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L |
|---|
| 1372 | #define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L |
|---|
| 1373 | //RCC_BUSNUM_CNTL1 |
|---|
| 1374 | #define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 |
|---|
| 1375 | #define RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL |
|---|
| 1376 | //RCC_BUSNUM_LIST0 |
|---|
| 1377 | #define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 |
|---|
| 1378 | #define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 |
|---|
| 1379 | #define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 |
|---|
| 1380 | #define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 |
|---|
| 1381 | #define RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL |
|---|
| 1382 | #define RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L |
|---|
| 1383 | #define RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L |
|---|
| 1384 | #define RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L |
|---|
| 1385 | //RCC_BUSNUM_LIST1 |
|---|
| 1386 | #define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 |
|---|
| 1387 | #define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 |
|---|
| 1388 | #define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 |
|---|
| 1389 | #define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 |
|---|
| 1390 | #define RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL |
|---|
| 1391 | #define RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L |
|---|
| 1392 | #define RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L |
|---|
| 1393 | #define RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L |
|---|
| 1394 | //RCC_BUSNUM_CNTL2 |
|---|
| 1395 | #define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 |
|---|
| 1396 | #define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 |
|---|
| 1397 | #define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 |
|---|
| 1398 | #define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 |
|---|
| 1399 | #define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL |
|---|
| 1400 | #define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L |
|---|
| 1401 | #define RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L |
|---|
| 1402 | #define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L |
|---|
| 1403 | //RCC_CAPTURE_HOST_BUSNUM |
|---|
| 1404 | #define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 |
|---|
| 1405 | #define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L |
|---|
| 1406 | //RCC_HOST_BUSNUM |
|---|
| 1407 | #define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 |
|---|
| 1408 | #define RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL |
|---|
| 1409 | //RCC_PEER0_FB_OFFSET_HI |
|---|
| 1410 | #define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 |
|---|
| 1411 | #define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL |
|---|
| 1412 | //RCC_PEER0_FB_OFFSET_LO |
|---|
| 1413 | #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 |
|---|
| 1414 | #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f |
|---|
| 1415 | #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL |
|---|
| 1416 | #define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L |
|---|
| 1417 | //RCC_PEER1_FB_OFFSET_HI |
|---|
| 1418 | #define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 |
|---|
| 1419 | #define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL |
|---|
| 1420 | //RCC_PEER1_FB_OFFSET_LO |
|---|
| 1421 | #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 |
|---|
| 1422 | #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f |
|---|
| 1423 | #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL |
|---|
| 1424 | #define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L |
|---|
| 1425 | //RCC_PEER2_FB_OFFSET_HI |
|---|
| 1426 | #define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 |
|---|
| 1427 | #define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL |
|---|
| 1428 | //RCC_PEER2_FB_OFFSET_LO |
|---|
| 1429 | #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 |
|---|
| 1430 | #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f |
|---|
| 1431 | #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL |
|---|
| 1432 | #define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L |
|---|
| 1433 | //RCC_PEER3_FB_OFFSET_HI |
|---|
| 1434 | #define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 |
|---|
| 1435 | #define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL |
|---|
| 1436 | //RCC_PEER3_FB_OFFSET_LO |
|---|
| 1437 | #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 |
|---|
| 1438 | #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f |
|---|
| 1439 | #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL |
|---|
| 1440 | #define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L |
|---|
| 1441 | //RCC_DEVFUNCNUM_LIST0 |
|---|
| 1442 | #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 |
|---|
| 1443 | #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 |
|---|
| 1444 | #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 |
|---|
| 1445 | #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 |
|---|
| 1446 | #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL |
|---|
| 1447 | #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L |
|---|
| 1448 | #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L |
|---|
| 1449 | #define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L |
|---|
| 1450 | //RCC_DEVFUNCNUM_LIST1 |
|---|
| 1451 | #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 |
|---|
| 1452 | #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 |
|---|
| 1453 | #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 |
|---|
| 1454 | #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 |
|---|
| 1455 | #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL |
|---|
| 1456 | #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L |
|---|
| 1457 | #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L |
|---|
| 1458 | #define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L |
|---|
| 1459 | //RCC_DEV0_LINK_CNTL |
|---|
| 1460 | #define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 |
|---|
| 1461 | #define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 |
|---|
| 1462 | #define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L |
|---|
| 1463 | #define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L |
|---|
| 1464 | //RCC_CMN_LINK_CNTL |
|---|
| 1465 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 |
|---|
| 1466 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 |
|---|
| 1467 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 |
|---|
| 1468 | #define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 |
|---|
| 1469 | #define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 |
|---|
| 1470 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L |
|---|
| 1471 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L |
|---|
| 1472 | #define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L |
|---|
| 1473 | #define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L |
|---|
| 1474 | #define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L |
|---|
| 1475 | //RCC_EP_REQUESTERID_RESTORE |
|---|
| 1476 | #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 |
|---|
| 1477 | #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 |
|---|
| 1478 | #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL |
|---|
| 1479 | #define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L |
|---|
| 1480 | //RCC_LTR_LSWITCH_CNTL |
|---|
| 1481 | #define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 1482 | #define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 1483 | //RCC_MH_ARB_CNTL |
|---|
| 1484 | #define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 |
|---|
| 1485 | #define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 |
|---|
| 1486 | #define RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L |
|---|
| 1487 | #define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL |
|---|
| 1488 | |
|---|
| 1489 | |
|---|
| 1490 | // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 |
|---|
| 1491 | //CC_BIF_BX_STRAP0 |
|---|
| 1492 | #define CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 |
|---|
| 1493 | #define CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L |
|---|
| 1494 | //CC_BIF_BX_PINSTRAP0 |
|---|
| 1495 | //BIF_MM_INDACCESS_CNTL |
|---|
| 1496 | #define BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0 |
|---|
| 1497 | #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 |
|---|
| 1498 | #define BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L |
|---|
| 1499 | #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L |
|---|
| 1500 | //BUS_CNTL |
|---|
| 1501 | #define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 |
|---|
| 1502 | #define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 |
|---|
| 1503 | #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa |
|---|
| 1504 | #define BUS_CNTL__SET_MC_TC__SHIFT 0xd |
|---|
| 1505 | #define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 |
|---|
| 1506 | #define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 |
|---|
| 1507 | #define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 |
|---|
| 1508 | #define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 |
|---|
| 1509 | #define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a |
|---|
| 1510 | #define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d |
|---|
| 1511 | #define BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e |
|---|
| 1512 | #define BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f |
|---|
| 1513 | #define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L |
|---|
| 1514 | #define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L |
|---|
| 1515 | #define BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L |
|---|
| 1516 | #define BUS_CNTL__SET_MC_TC_MASK 0x0000E000L |
|---|
| 1517 | #define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L |
|---|
| 1518 | #define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L |
|---|
| 1519 | #define BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L |
|---|
| 1520 | #define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L |
|---|
| 1521 | #define BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L |
|---|
| 1522 | #define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L |
|---|
| 1523 | #define BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L |
|---|
| 1524 | #define BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L |
|---|
| 1525 | //BIF_SCRATCH0 |
|---|
| 1526 | #define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 |
|---|
| 1527 | #define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL |
|---|
| 1528 | //BIF_SCRATCH1 |
|---|
| 1529 | #define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 |
|---|
| 1530 | #define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL |
|---|
| 1531 | //BX_RESET_EN |
|---|
| 1532 | #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 |
|---|
| 1533 | #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L |
|---|
| 1534 | //MM_CFGREGS_CNTL |
|---|
| 1535 | #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 |
|---|
| 1536 | #define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 |
|---|
| 1537 | #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f |
|---|
| 1538 | #define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L |
|---|
| 1539 | #define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L |
|---|
| 1540 | #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L |
|---|
| 1541 | //BX_RESET_CNTL |
|---|
| 1542 | #define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 |
|---|
| 1543 | #define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L |
|---|
| 1544 | //INTERRUPT_CNTL |
|---|
| 1545 | #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 |
|---|
| 1546 | #define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 |
|---|
| 1547 | #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 |
|---|
| 1548 | #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 |
|---|
| 1549 | #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 |
|---|
| 1550 | #define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf |
|---|
| 1551 | #define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 |
|---|
| 1552 | #define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 |
|---|
| 1553 | #define INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 |
|---|
| 1554 | #define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L |
|---|
| 1555 | #define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L |
|---|
| 1556 | #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L |
|---|
| 1557 | #define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L |
|---|
| 1558 | #define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L |
|---|
| 1559 | #define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L |
|---|
| 1560 | #define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L |
|---|
| 1561 | #define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L |
|---|
| 1562 | #define INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L |
|---|
| 1563 | //INTERRUPT_CNTL2 |
|---|
| 1564 | #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 |
|---|
| 1565 | #define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL |
|---|
| 1566 | //CLKREQB_PAD_CNTL |
|---|
| 1567 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 |
|---|
| 1568 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 |
|---|
| 1569 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 |
|---|
| 1570 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 |
|---|
| 1571 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 |
|---|
| 1572 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 |
|---|
| 1573 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 |
|---|
| 1574 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 |
|---|
| 1575 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 |
|---|
| 1576 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa |
|---|
| 1577 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb |
|---|
| 1578 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc |
|---|
| 1579 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd |
|---|
| 1580 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L |
|---|
| 1581 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L |
|---|
| 1582 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L |
|---|
| 1583 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L |
|---|
| 1584 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L |
|---|
| 1585 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L |
|---|
| 1586 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L |
|---|
| 1587 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L |
|---|
| 1588 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L |
|---|
| 1589 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L |
|---|
| 1590 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L |
|---|
| 1591 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L |
|---|
| 1592 | #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L |
|---|
| 1593 | //BIF_FEATURES_CONTROL_MISC |
|---|
| 1594 | #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 |
|---|
| 1595 | #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 |
|---|
| 1596 | #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 |
|---|
| 1597 | #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 |
|---|
| 1598 | #define BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb |
|---|
| 1599 | #define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc |
|---|
| 1600 | #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd |
|---|
| 1601 | #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe |
|---|
| 1602 | #define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf |
|---|
| 1603 | #define BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 |
|---|
| 1604 | #define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 |
|---|
| 1605 | #define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L |
|---|
| 1606 | #define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L |
|---|
| 1607 | #define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L |
|---|
| 1608 | #define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L |
|---|
| 1609 | #define BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L |
|---|
| 1610 | #define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L |
|---|
| 1611 | #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L |
|---|
| 1612 | #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L |
|---|
| 1613 | #define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L |
|---|
| 1614 | #define BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x00FF0000L |
|---|
| 1615 | #define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L |
|---|
| 1616 | //BIF_DOORBELL_CNTL |
|---|
| 1617 | #define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 |
|---|
| 1618 | #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 |
|---|
| 1619 | #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 |
|---|
| 1620 | #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 |
|---|
| 1621 | #define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 |
|---|
| 1622 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 |
|---|
| 1623 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 |
|---|
| 1624 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a |
|---|
| 1625 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b |
|---|
| 1626 | #define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L |
|---|
| 1627 | #define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L |
|---|
| 1628 | #define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L |
|---|
| 1629 | #define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L |
|---|
| 1630 | #define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L |
|---|
| 1631 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L |
|---|
| 1632 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L |
|---|
| 1633 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L |
|---|
| 1634 | #define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L |
|---|
| 1635 | //BIF_DOORBELL_INT_CNTL |
|---|
| 1636 | #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 |
|---|
| 1637 | #define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 |
|---|
| 1638 | #define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 |
|---|
| 1639 | #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 |
|---|
| 1640 | #define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 |
|---|
| 1641 | #define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 |
|---|
| 1642 | #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 |
|---|
| 1643 | #define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 |
|---|
| 1644 | #define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a |
|---|
| 1645 | #define BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c |
|---|
| 1646 | #define BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d |
|---|
| 1647 | #define BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e |
|---|
| 1648 | #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L |
|---|
| 1649 | #define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L |
|---|
| 1650 | #define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L |
|---|
| 1651 | #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L |
|---|
| 1652 | #define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L |
|---|
| 1653 | #define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L |
|---|
| 1654 | #define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L |
|---|
| 1655 | #define BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L |
|---|
| 1656 | #define BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L |
|---|
| 1657 | #define BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L |
|---|
| 1658 | #define BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L |
|---|
| 1659 | #define BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L |
|---|
| 1660 | //BIF_FB_EN |
|---|
| 1661 | #define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 |
|---|
| 1662 | #define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 |
|---|
| 1663 | #define BIF_FB_EN__FB_READ_EN_MASK 0x00000001L |
|---|
| 1664 | #define BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L |
|---|
| 1665 | //BIF_INTR_CNTL |
|---|
| 1666 | #define BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 |
|---|
| 1667 | #define BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L |
|---|
| 1668 | //BIF_MST_TRANS_PENDING_VF |
|---|
| 1669 | #define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 1670 | #define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL |
|---|
| 1671 | //BIF_SLV_TRANS_PENDING_VF |
|---|
| 1672 | #define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 |
|---|
| 1673 | #define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL |
|---|
| 1674 | //BACO_CNTL |
|---|
| 1675 | #define BACO_CNTL__BACO_EN__SHIFT 0x0 |
|---|
| 1676 | #define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 |
|---|
| 1677 | #define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 |
|---|
| 1678 | #define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 |
|---|
| 1679 | #define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 |
|---|
| 1680 | #define BACO_CNTL__BACO_MODE__SHIFT 0x8 |
|---|
| 1681 | #define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 |
|---|
| 1682 | #define BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10 |
|---|
| 1683 | #define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f |
|---|
| 1684 | #define BACO_CNTL__BACO_EN_MASK 0x00000001L |
|---|
| 1685 | #define BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L |
|---|
| 1686 | #define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L |
|---|
| 1687 | #define BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L |
|---|
| 1688 | #define BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L |
|---|
| 1689 | #define BACO_CNTL__BACO_MODE_MASK 0x00000100L |
|---|
| 1690 | #define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L |
|---|
| 1691 | #define BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L |
|---|
| 1692 | #define BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L |
|---|
| 1693 | //BIF_BACO_EXIT_TIME0 |
|---|
| 1694 | #define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 |
|---|
| 1695 | #define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL |
|---|
| 1696 | //BIF_BACO_EXIT_TIMER1 |
|---|
| 1697 | #define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 |
|---|
| 1698 | #define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 |
|---|
| 1699 | #define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a |
|---|
| 1700 | #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b |
|---|
| 1701 | #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c |
|---|
| 1702 | #define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d |
|---|
| 1703 | #define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f |
|---|
| 1704 | #define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL |
|---|
| 1705 | #define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L |
|---|
| 1706 | #define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L |
|---|
| 1707 | #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L |
|---|
| 1708 | #define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L |
|---|
| 1709 | #define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L |
|---|
| 1710 | #define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L |
|---|
| 1711 | //BIF_BACO_EXIT_TIMER2 |
|---|
| 1712 | #define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 |
|---|
| 1713 | #define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL |
|---|
| 1714 | //BIF_BACO_EXIT_TIMER3 |
|---|
| 1715 | #define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 |
|---|
| 1716 | #define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL |
|---|
| 1717 | //BIF_BACO_EXIT_TIMER4 |
|---|
| 1718 | #define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 |
|---|
| 1719 | #define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL |
|---|
| 1720 | //MEM_TYPE_CNTL |
|---|
| 1721 | #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 |
|---|
| 1722 | #define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L |
|---|
| 1723 | //NBIF_GFX_ADDR_LUT_CNTL |
|---|
| 1724 | #define NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 |
|---|
| 1725 | #define NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 |
|---|
| 1726 | #define NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L |
|---|
| 1727 | #define NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L |
|---|
| 1728 | //NBIF_GFX_ADDR_LUT_0 |
|---|
| 1729 | #define NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 |
|---|
| 1730 | #define NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL |
|---|
| 1731 | //NBIF_GFX_ADDR_LUT_1 |
|---|
| 1732 | #define NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 |
|---|
| 1733 | #define NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL |
|---|
| 1734 | //NBIF_GFX_ADDR_LUT_2 |
|---|
| 1735 | #define NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 |
|---|
| 1736 | #define NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL |
|---|
| 1737 | //NBIF_GFX_ADDR_LUT_3 |
|---|
| 1738 | #define NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 |
|---|
| 1739 | #define NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL |
|---|
| 1740 | //NBIF_GFX_ADDR_LUT_4 |
|---|
| 1741 | #define NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 |
|---|
| 1742 | #define NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL |
|---|
| 1743 | //NBIF_GFX_ADDR_LUT_5 |
|---|
| 1744 | #define NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 |
|---|
| 1745 | #define NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL |
|---|
| 1746 | //NBIF_GFX_ADDR_LUT_6 |
|---|
| 1747 | #define NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 |
|---|
| 1748 | #define NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL |
|---|
| 1749 | //NBIF_GFX_ADDR_LUT_7 |
|---|
| 1750 | #define NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 |
|---|
| 1751 | #define NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL |
|---|
| 1752 | //NBIF_GFX_ADDR_LUT_8 |
|---|
| 1753 | #define NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 |
|---|
| 1754 | #define NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL |
|---|
| 1755 | //NBIF_GFX_ADDR_LUT_9 |
|---|
| 1756 | #define NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 |
|---|
| 1757 | #define NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL |
|---|
| 1758 | //NBIF_GFX_ADDR_LUT_10 |
|---|
| 1759 | #define NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 |
|---|
| 1760 | #define NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL |
|---|
| 1761 | //NBIF_GFX_ADDR_LUT_11 |
|---|
| 1762 | #define NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 |
|---|
| 1763 | #define NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL |
|---|
| 1764 | //NBIF_GFX_ADDR_LUT_12 |
|---|
| 1765 | #define NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 |
|---|
| 1766 | #define NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL |
|---|
| 1767 | //NBIF_GFX_ADDR_LUT_13 |
|---|
| 1768 | #define NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 |
|---|
| 1769 | #define NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL |
|---|
| 1770 | //NBIF_GFX_ADDR_LUT_14 |
|---|
| 1771 | #define NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 |
|---|
| 1772 | #define NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL |
|---|
| 1773 | //NBIF_GFX_ADDR_LUT_15 |
|---|
| 1774 | #define NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 |
|---|
| 1775 | #define NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL |
|---|
| 1776 | //REMAP_HDP_MEM_FLUSH_CNTL |
|---|
| 1777 | #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
|---|
| 1778 | #define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
|---|
| 1779 | //REMAP_HDP_REG_FLUSH_CNTL |
|---|
| 1780 | #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 |
|---|
| 1781 | #define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL |
|---|
| 1782 | //BIF_RB_CNTL |
|---|
| 1783 | #define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
|---|
| 1784 | #define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 |
|---|
| 1785 | #define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 |
|---|
| 1786 | #define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 |
|---|
| 1787 | #define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 |
|---|
| 1788 | #define BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a |
|---|
| 1789 | #define BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d |
|---|
| 1790 | #define BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e |
|---|
| 1791 | #define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f |
|---|
| 1792 | #define BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
|---|
| 1793 | #define BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
|---|
| 1794 | #define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L |
|---|
| 1795 | #define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L |
|---|
| 1796 | #define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L |
|---|
| 1797 | #define BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L |
|---|
| 1798 | #define BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L |
|---|
| 1799 | #define BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L |
|---|
| 1800 | #define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L |
|---|
| 1801 | //BIF_RB_BASE |
|---|
| 1802 | #define BIF_RB_BASE__ADDR__SHIFT 0x0 |
|---|
| 1803 | #define BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
|---|
| 1804 | //BIF_RB_RPTR |
|---|
| 1805 | #define BIF_RB_RPTR__OFFSET__SHIFT 0x2 |
|---|
| 1806 | #define BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL |
|---|
| 1807 | //BIF_RB_WPTR |
|---|
| 1808 | #define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 |
|---|
| 1809 | #define BIF_RB_WPTR__OFFSET__SHIFT 0x2 |
|---|
| 1810 | #define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L |
|---|
| 1811 | #define BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL |
|---|
| 1812 | //BIF_RB_WPTR_ADDR_HI |
|---|
| 1813 | #define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 |
|---|
| 1814 | #define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL |
|---|
| 1815 | //BIF_RB_WPTR_ADDR_LO |
|---|
| 1816 | #define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 |
|---|
| 1817 | #define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
|---|
| 1818 | //MAILBOX_INDEX |
|---|
| 1819 | #define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 |
|---|
| 1820 | #define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL |
|---|
| 1821 | //BIF_MP1_INTR_CTRL |
|---|
| 1822 | #define BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 |
|---|
| 1823 | #define BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L |
|---|
| 1824 | //BIF_UVD_GPUIOV_CFG_SIZE |
|---|
| 1825 | #define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 |
|---|
| 1826 | #define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
|---|
| 1827 | //BIF_VCE_GPUIOV_CFG_SIZE |
|---|
| 1828 | #define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 |
|---|
| 1829 | #define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
|---|
| 1830 | //BIF_GFX_SDMA_GPUIOV_CFG_SIZE |
|---|
| 1831 | #define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 |
|---|
| 1832 | #define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL |
|---|
| 1833 | //BIF_PERSTB_PAD_CNTL |
|---|
| 1834 | #define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 |
|---|
| 1835 | #define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL |
|---|
| 1836 | //BIF_PX_EN_PAD_CNTL |
|---|
| 1837 | #define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 |
|---|
| 1838 | #define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL |
|---|
| 1839 | //BIF_REFPADKIN_PAD_CNTL |
|---|
| 1840 | #define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 |
|---|
| 1841 | #define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL |
|---|
| 1842 | //BIF_CLKREQB_PAD_CNTL |
|---|
| 1843 | #define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 |
|---|
| 1844 | #define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL |
|---|
| 1845 | //BIF_PWRBRK_PAD_CNTL |
|---|
| 1846 | #define BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 |
|---|
| 1847 | #define BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL |
|---|
| 1848 | //BIF_WAKEB_PAD_CNTL |
|---|
| 1849 | #define BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT 0x0 |
|---|
| 1850 | #define BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT 0x1 |
|---|
| 1851 | #define BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT 0x2 |
|---|
| 1852 | #define BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT 0x3 |
|---|
| 1853 | #define BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT 0x4 |
|---|
| 1854 | #define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT 0x5 |
|---|
| 1855 | #define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT 0x6 |
|---|
| 1856 | #define BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT 0x7 |
|---|
| 1857 | #define BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK 0x00000001L |
|---|
| 1858 | #define BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK 0x00000002L |
|---|
| 1859 | #define BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK 0x00000004L |
|---|
| 1860 | #define BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK 0x00000008L |
|---|
| 1861 | #define BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK 0x00000010L |
|---|
| 1862 | #define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK 0x00000020L |
|---|
| 1863 | #define BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK 0x00000040L |
|---|
| 1864 | #define BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK 0x00000080L |
|---|
| 1865 | //BIF_VAUX_PRESENT_PAD_CNTL |
|---|
| 1866 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT 0x0 |
|---|
| 1867 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT 0x1 |
|---|
| 1868 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT 0x2 |
|---|
| 1869 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT 0x3 |
|---|
| 1870 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT 0x4 |
|---|
| 1871 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT 0x5 |
|---|
| 1872 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK 0x00000001L |
|---|
| 1873 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK 0x00000002L |
|---|
| 1874 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK 0x00000004L |
|---|
| 1875 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK 0x00000008L |
|---|
| 1876 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK 0x00000010L |
|---|
| 1877 | #define BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK 0x00000020L |
|---|
| 1878 | |
|---|
| 1879 | |
|---|
| 1880 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
|---|
| 1881 | //BIF_BX_PF_BIF_BME_STATUS |
|---|
| 1882 | #define BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 1883 | #define BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 1884 | #define BIF_BX_PF_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 1885 | #define BIF_BX_PF_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 1886 | //BIF_BX_PF_BIF_ATOMIC_ERR_LOG |
|---|
| 1887 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 1888 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 1889 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 1890 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 1891 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 1892 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 1893 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 1894 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 1895 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 1896 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 1897 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 1898 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 1899 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 1900 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 1901 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 1902 | #define BIF_BX_PF_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 1903 | //BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 1904 | #define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 1905 | #define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 1906 | //BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 1907 | #define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 1908 | #define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 1909 | //BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 1910 | #define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 1911 | #define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 1912 | #define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 1913 | #define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 1914 | #define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 1915 | #define BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 1916 | //BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 1917 | #define BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 1918 | #define BIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 1919 | //BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 1920 | #define BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 1921 | #define BIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 1922 | //BIF_BX_PF_GPU_HDP_FLUSH_REQ |
|---|
| 1923 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 1924 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 1925 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 1926 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 1927 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 1928 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 1929 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 1930 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 1931 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 1932 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 1933 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 1934 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 1935 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 1936 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 1937 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 1938 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 1939 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 1940 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 1941 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 1942 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 1943 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 1944 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 1945 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 1946 | #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 1947 | //BIF_BX_PF_GPU_HDP_FLUSH_DONE |
|---|
| 1948 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 1949 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 1950 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 1951 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 1952 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 1953 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 1954 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 1955 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 1956 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 1957 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 1958 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 1959 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 1960 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 1961 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 1962 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 1963 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 1964 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 1965 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 1966 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 1967 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 1968 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 1969 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 1970 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 1971 | #define BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 1972 | //BIF_BX_PF_BIF_TRANS_PENDING |
|---|
| 1973 | #define BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 1974 | #define BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 1975 | #define BIF_BX_PF_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 1976 | #define BIF_BX_PF_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 1977 | //BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 1978 | #define BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 1979 | #define BIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 1980 | //BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 1981 | #define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 1982 | #define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 1983 | //BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 1984 | #define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 1985 | #define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 1986 | //BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 1987 | #define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 1988 | #define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 1989 | //BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 1990 | #define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 1991 | #define BIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 1992 | //BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 1993 | #define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 1994 | #define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 1995 | //BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 1996 | #define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 1997 | #define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 1998 | //BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 1999 | #define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 2000 | #define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 2001 | //BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 2002 | #define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 2003 | #define BIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 2004 | //BIF_BX_PF_MAILBOX_CONTROL |
|---|
| 2005 | #define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 2006 | #define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 2007 | #define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 2008 | #define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 2009 | #define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 2010 | #define BIF_BX_PF_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 2011 | #define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 2012 | #define BIF_BX_PF_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 2013 | //BIF_BX_PF_MAILBOX_INT_CNTL |
|---|
| 2014 | #define BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 2015 | #define BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 2016 | #define BIF_BX_PF_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 2017 | #define BIF_BX_PF_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 2018 | //BIF_BX_PF_BIF_VMHV_MAILBOX |
|---|
| 2019 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 2020 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 2021 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 2022 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 2023 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 2024 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 2025 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 2026 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 2027 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 2028 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 2029 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 2030 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 2031 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 2032 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 2033 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 2034 | #define BIF_BX_PF_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 2035 | |
|---|
| 2036 | |
|---|
| 2037 | // addressBlock: nbio_nbif0_gdc_GDCDEC |
|---|
| 2038 | //A2S_CNTL_CL0 |
|---|
| 2039 | #define A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 |
|---|
| 2040 | #define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 |
|---|
| 2041 | #define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 |
|---|
| 2042 | #define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 |
|---|
| 2043 | #define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 |
|---|
| 2044 | #define A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa |
|---|
| 2045 | #define A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc |
|---|
| 2046 | #define A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe |
|---|
| 2047 | #define A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 |
|---|
| 2048 | #define A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 |
|---|
| 2049 | #define A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 |
|---|
| 2050 | #define A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT 0x16 |
|---|
| 2051 | #define A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT 0x18 |
|---|
| 2052 | #define A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L |
|---|
| 2053 | #define A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000CL |
|---|
| 2054 | #define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L |
|---|
| 2055 | #define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L |
|---|
| 2056 | #define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L |
|---|
| 2057 | #define A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000C00L |
|---|
| 2058 | #define A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L |
|---|
| 2059 | #define A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000C000L |
|---|
| 2060 | #define A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L |
|---|
| 2061 | #define A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000C0000L |
|---|
| 2062 | #define A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L |
|---|
| 2063 | #define A2S_CNTL_CL0__RDRSP_ERRMAP_MASK 0x00C00000L |
|---|
| 2064 | #define A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK 0x07000000L |
|---|
| 2065 | //A2S_CNTL_CL1 |
|---|
| 2066 | #define A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0 |
|---|
| 2067 | #define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2 |
|---|
| 2068 | #define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4 |
|---|
| 2069 | #define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 |
|---|
| 2070 | #define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 |
|---|
| 2071 | #define A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa |
|---|
| 2072 | #define A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc |
|---|
| 2073 | #define A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe |
|---|
| 2074 | #define A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10 |
|---|
| 2075 | #define A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12 |
|---|
| 2076 | #define A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14 |
|---|
| 2077 | #define A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT 0x16 |
|---|
| 2078 | #define A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT 0x18 |
|---|
| 2079 | #define A2S_CNTL_CL1__NSNOOP_MAP_MASK 0x00000003L |
|---|
| 2080 | #define A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK 0x0000000CL |
|---|
| 2081 | #define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK 0x00000030L |
|---|
| 2082 | #define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L |
|---|
| 2083 | #define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L |
|---|
| 2084 | #define A2S_CNTL_CL1__BLKLVL_MAP_MASK 0x00000C00L |
|---|
| 2085 | #define A2S_CNTL_CL1__DATERR_MAP_MASK 0x00003000L |
|---|
| 2086 | #define A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK 0x0000C000L |
|---|
| 2087 | #define A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK 0x00030000L |
|---|
| 2088 | #define A2S_CNTL_CL1__RESP_WR_MAP_MASK 0x000C0000L |
|---|
| 2089 | #define A2S_CNTL_CL1__RESP_RD_MAP_MASK 0x00300000L |
|---|
| 2090 | #define A2S_CNTL_CL1__RDRSP_ERRMAP_MASK 0x00C00000L |
|---|
| 2091 | #define A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK 0x07000000L |
|---|
| 2092 | //A2S_CNTL3_CL0 |
|---|
| 2093 | #define A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT 0x0 |
|---|
| 2094 | #define A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT 0x2 |
|---|
| 2095 | #define A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT 0x3 |
|---|
| 2096 | #define A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT 0x4 |
|---|
| 2097 | #define A2S_CNTL3_CL0__FORCE_WR_PH_MASK 0x00000003L |
|---|
| 2098 | #define A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK 0x00000004L |
|---|
| 2099 | #define A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK 0x00000008L |
|---|
| 2100 | #define A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK 0x000003F0L |
|---|
| 2101 | //A2S_CNTL3_CL1 |
|---|
| 2102 | #define A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT 0x0 |
|---|
| 2103 | #define A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT 0x2 |
|---|
| 2104 | #define A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT 0x3 |
|---|
| 2105 | #define A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT 0x4 |
|---|
| 2106 | #define A2S_CNTL3_CL1__FORCE_WR_PH_MASK 0x00000003L |
|---|
| 2107 | #define A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK 0x00000004L |
|---|
| 2108 | #define A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK 0x00000008L |
|---|
| 2109 | #define A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK 0x000003F0L |
|---|
| 2110 | //A2S_CNTL_SW0 |
|---|
| 2111 | #define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 |
|---|
| 2112 | #define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 |
|---|
| 2113 | #define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 |
|---|
| 2114 | #define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L |
|---|
| 2115 | #define A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L |
|---|
| 2116 | #define A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L |
|---|
| 2117 | //A2S_CNTL_SW1 |
|---|
| 2118 | #define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 |
|---|
| 2119 | #define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 |
|---|
| 2120 | #define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 |
|---|
| 2121 | #define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK 0x00000200L |
|---|
| 2122 | #define A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK 0x00FF0000L |
|---|
| 2123 | #define A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK 0xFF000000L |
|---|
| 2124 | //A2S_CNTL_SW2 |
|---|
| 2125 | #define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 |
|---|
| 2126 | #define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 |
|---|
| 2127 | #define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 |
|---|
| 2128 | #define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK 0x00000200L |
|---|
| 2129 | #define A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK 0x00FF0000L |
|---|
| 2130 | #define A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK 0xFF000000L |
|---|
| 2131 | //A2S_CPLBUF_ALLOC_CNTL |
|---|
| 2132 | #define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD__SHIFT 0x0 |
|---|
| 2133 | #define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD__SHIFT 0x14 |
|---|
| 2134 | #define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD__SHIFT 0x18 |
|---|
| 2135 | #define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD__SHIFT 0x1c |
|---|
| 2136 | #define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD_MASK 0x0000000FL |
|---|
| 2137 | #define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD_MASK 0x00F00000L |
|---|
| 2138 | #define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD_MASK 0x0F000000L |
|---|
| 2139 | #define A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD_MASK 0xF0000000L |
|---|
| 2140 | //A2S_TAG_ALLOC_0 |
|---|
| 2141 | #define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0 |
|---|
| 2142 | #define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8 |
|---|
| 2143 | #define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10 |
|---|
| 2144 | #define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL |
|---|
| 2145 | #define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L |
|---|
| 2146 | #define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L |
|---|
| 2147 | //A2S_TAG_ALLOC_1 |
|---|
| 2148 | #define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0 |
|---|
| 2149 | #define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10 |
|---|
| 2150 | #define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18 |
|---|
| 2151 | #define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL |
|---|
| 2152 | #define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L |
|---|
| 2153 | #define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L |
|---|
| 2154 | //A2S_MISC_CNTL |
|---|
| 2155 | #define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 |
|---|
| 2156 | #define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 |
|---|
| 2157 | #define A2S_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x3 |
|---|
| 2158 | #define A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4 |
|---|
| 2159 | #define A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5 |
|---|
| 2160 | #define A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6 |
|---|
| 2161 | #define A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7 |
|---|
| 2162 | #define A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8 |
|---|
| 2163 | #define A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9 |
|---|
| 2164 | #define A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa |
|---|
| 2165 | #define A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10 |
|---|
| 2166 | #define A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15 |
|---|
| 2167 | #define A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L |
|---|
| 2168 | #define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L |
|---|
| 2169 | #define A2S_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000008L |
|---|
| 2170 | #define A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L |
|---|
| 2171 | #define A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L |
|---|
| 2172 | #define A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L |
|---|
| 2173 | #define A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L |
|---|
| 2174 | #define A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L |
|---|
| 2175 | #define A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L |
|---|
| 2176 | #define A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L |
|---|
| 2177 | #define A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L |
|---|
| 2178 | #define A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L |
|---|
| 2179 | //NGDC_SDP_PORT_CTRL |
|---|
| 2180 | #define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 |
|---|
| 2181 | #define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL |
|---|
| 2182 | //SHUB_REGS_IF_CTL |
|---|
| 2183 | #define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 |
|---|
| 2184 | #define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L |
|---|
| 2185 | //NGDC_MGCG_CTRL |
|---|
| 2186 | #define NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 |
|---|
| 2187 | #define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 |
|---|
| 2188 | #define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 |
|---|
| 2189 | #define NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa |
|---|
| 2190 | #define NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb |
|---|
| 2191 | #define NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc |
|---|
| 2192 | #define NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd |
|---|
| 2193 | #define NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L |
|---|
| 2194 | #define NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L |
|---|
| 2195 | #define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL |
|---|
| 2196 | #define NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L |
|---|
| 2197 | #define NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L |
|---|
| 2198 | #define NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L |
|---|
| 2199 | #define NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L |
|---|
| 2200 | //NGDC_RESERVED_0 |
|---|
| 2201 | #define NGDC_RESERVED_0__RESERVED__SHIFT 0x0 |
|---|
| 2202 | #define NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 2203 | //NGDC_RESERVED_1 |
|---|
| 2204 | #define NGDC_RESERVED_1__RESERVED__SHIFT 0x0 |
|---|
| 2205 | #define NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 2206 | //NGDC_SDP_PORT_CTRL_SOCCLK |
|---|
| 2207 | #define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0 |
|---|
| 2208 | #define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x000000FFL |
|---|
| 2209 | //BIF_SDMA0_DOORBELL_RANGE |
|---|
| 2210 | #define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
|---|
| 2211 | #define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
|---|
| 2212 | #define BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
|---|
| 2213 | #define BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
|---|
| 2214 | //BIF_SDMA1_DOORBELL_RANGE |
|---|
| 2215 | #define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
|---|
| 2216 | #define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
|---|
| 2217 | #define BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
|---|
| 2218 | #define BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
|---|
| 2219 | //BIF_IH_DOORBELL_RANGE |
|---|
| 2220 | #define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
|---|
| 2221 | #define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
|---|
| 2222 | #define BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
|---|
| 2223 | #define BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
|---|
| 2224 | //BIF_MMSCH0_DOORBELL_RANGE |
|---|
| 2225 | #define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
|---|
| 2226 | #define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
|---|
| 2227 | #define BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
|---|
| 2228 | #define BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
|---|
| 2229 | //BIF_ACV_DOORBELL_RANGE |
|---|
| 2230 | #define BIF_ACV_DOORBELL_RANGE__OFFSET__SHIFT 0x2 |
|---|
| 2231 | #define BIF_ACV_DOORBELL_RANGE__SIZE__SHIFT 0x10 |
|---|
| 2232 | #define BIF_ACV_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL |
|---|
| 2233 | #define BIF_ACV_DOORBELL_RANGE__SIZE_MASK 0x001F0000L |
|---|
| 2234 | //BIF_DOORBELL_FENCE_CNTL |
|---|
| 2235 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT 0x0 |
|---|
| 2236 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT 0x1 |
|---|
| 2237 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT 0x2 |
|---|
| 2238 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ACV_ENABLE__SHIFT 0x3 |
|---|
| 2239 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x10 |
|---|
| 2240 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK 0x00000001L |
|---|
| 2241 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK 0x00000002L |
|---|
| 2242 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK 0x00000004L |
|---|
| 2243 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ACV_ENABLE_MASK 0x00000008L |
|---|
| 2244 | #define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00010000L |
|---|
| 2245 | //S2A_MISC_CNTL |
|---|
| 2246 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 |
|---|
| 2247 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 |
|---|
| 2248 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 |
|---|
| 2249 | #define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 |
|---|
| 2250 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_ACV_DIS__SHIFT 0x4 |
|---|
| 2251 | #define S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 |
|---|
| 2252 | #define S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa |
|---|
| 2253 | #define S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc |
|---|
| 2254 | #define S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 |
|---|
| 2255 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L |
|---|
| 2256 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L |
|---|
| 2257 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L |
|---|
| 2258 | #define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L |
|---|
| 2259 | #define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_ACV_DIS_MASK 0x00000010L |
|---|
| 2260 | #define S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L |
|---|
| 2261 | #define S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L |
|---|
| 2262 | #define S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L |
|---|
| 2263 | #define S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L |
|---|
| 2264 | //NGDC_PG_MISC_CTRL |
|---|
| 2265 | #define NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa |
|---|
| 2266 | #define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0xb |
|---|
| 2267 | #define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0xc |
|---|
| 2268 | #define NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM__SHIFT 0xd |
|---|
| 2269 | #define NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe |
|---|
| 2270 | #define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0xf |
|---|
| 2271 | #define NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 |
|---|
| 2272 | #define NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f |
|---|
| 2273 | #define NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L |
|---|
| 2274 | #define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000800L |
|---|
| 2275 | #define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00001000L |
|---|
| 2276 | #define NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM_MASK 0x00002000L |
|---|
| 2277 | #define NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L |
|---|
| 2278 | #define NGDC_PG_MISC_CTRL__NGDC_PG_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00008000L |
|---|
| 2279 | #define NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L |
|---|
| 2280 | #define NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L |
|---|
| 2281 | //NGDC_PGMST_CTRL |
|---|
| 2282 | #define NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0 |
|---|
| 2283 | #define NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8 |
|---|
| 2284 | #define NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa |
|---|
| 2285 | #define NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe |
|---|
| 2286 | #define NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL |
|---|
| 2287 | #define NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L |
|---|
| 2288 | #define NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L |
|---|
| 2289 | #define NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L |
|---|
| 2290 | //NGDC_PGSLV_CTRL |
|---|
| 2291 | #define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 |
|---|
| 2292 | #define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 |
|---|
| 2293 | #define NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa |
|---|
| 2294 | #define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL |
|---|
| 2295 | #define NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L |
|---|
| 2296 | #define NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L |
|---|
| 2297 | |
|---|
| 2298 | |
|---|
| 2299 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 |
|---|
| 2300 | //RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO |
|---|
| 2301 | #define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 2302 | #define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 2303 | //RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI |
|---|
| 2304 | #define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 2305 | #define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 2306 | //RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA |
|---|
| 2307 | #define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 2308 | #define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 2309 | //RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL |
|---|
| 2310 | #define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 2311 | #define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 2312 | //RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO |
|---|
| 2313 | #define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 2314 | #define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 2315 | //RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI |
|---|
| 2316 | #define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 2317 | #define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 2318 | //RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA |
|---|
| 2319 | #define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 2320 | #define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 2321 | //RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL |
|---|
| 2322 | #define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 2323 | #define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 2324 | //RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO |
|---|
| 2325 | #define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 2326 | #define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 2327 | //RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI |
|---|
| 2328 | #define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 2329 | #define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 2330 | //RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA |
|---|
| 2331 | #define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 2332 | #define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 2333 | //RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL |
|---|
| 2334 | #define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 2335 | #define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 2336 | //RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO |
|---|
| 2337 | #define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 2338 | #define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 2339 | //RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI |
|---|
| 2340 | #define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 2341 | #define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 2342 | //RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA |
|---|
| 2343 | #define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 2344 | #define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 2345 | //RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL |
|---|
| 2346 | #define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 2347 | #define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 2348 | //RCC_DEV0_EPF0_GFXMSIX_PBA |
|---|
| 2349 | #define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 2350 | #define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 2351 | #define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 2352 | #define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 2353 | #define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 2354 | #define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 2355 | #define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 2356 | #define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 2357 | |
|---|
| 2358 | |
|---|
| 2359 | // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp |
|---|
| 2360 | //PSWUSCFG0_0_VENDOR_ID |
|---|
| 2361 | #define PSWUSCFG0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 2362 | #define PSWUSCFG0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 2363 | //PSWUSCFG0_0_DEVICE_ID |
|---|
| 2364 | #define PSWUSCFG0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 2365 | #define PSWUSCFG0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 2366 | //PSWUSCFG0_0_COMMAND |
|---|
| 2367 | #define PSWUSCFG0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 2368 | #define PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 2369 | #define PSWUSCFG0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 2370 | #define PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 2371 | #define PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 2372 | #define PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 2373 | #define PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 2374 | #define PSWUSCFG0_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 2375 | #define PSWUSCFG0_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 2376 | #define PSWUSCFG0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 2377 | #define PSWUSCFG0_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 2378 | #define PSWUSCFG0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 2379 | #define PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 2380 | #define PSWUSCFG0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 2381 | #define PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 2382 | #define PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 2383 | #define PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 2384 | #define PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 2385 | #define PSWUSCFG0_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 2386 | #define PSWUSCFG0_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 2387 | #define PSWUSCFG0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 2388 | #define PSWUSCFG0_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 2389 | //PSWUSCFG0_0_STATUS |
|---|
| 2390 | #define PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 2391 | #define PSWUSCFG0_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 2392 | #define PSWUSCFG0_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 2393 | #define PSWUSCFG0_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 2394 | #define PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 2395 | #define PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 2396 | #define PSWUSCFG0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 2397 | #define PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 2398 | #define PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 2399 | #define PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 2400 | #define PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 2401 | #define PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 2402 | #define PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 2403 | #define PSWUSCFG0_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 2404 | #define PSWUSCFG0_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 2405 | #define PSWUSCFG0_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 2406 | #define PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 2407 | #define PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 2408 | #define PSWUSCFG0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 2409 | #define PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 2410 | #define PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 2411 | #define PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 2412 | #define PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 2413 | #define PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 2414 | //PSWUSCFG0_0_REVISION_ID |
|---|
| 2415 | #define PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 2416 | #define PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 2417 | #define PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 2418 | #define PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 2419 | //PSWUSCFG0_0_PROG_INTERFACE |
|---|
| 2420 | #define PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 2421 | #define PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 2422 | //PSWUSCFG0_0_SUB_CLASS |
|---|
| 2423 | #define PSWUSCFG0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 2424 | #define PSWUSCFG0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 2425 | //PSWUSCFG0_0_BASE_CLASS |
|---|
| 2426 | #define PSWUSCFG0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 2427 | #define PSWUSCFG0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 2428 | //PSWUSCFG0_0_CACHE_LINE |
|---|
| 2429 | #define PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 2430 | #define PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 2431 | //PSWUSCFG0_0_LATENCY |
|---|
| 2432 | #define PSWUSCFG0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 2433 | #define PSWUSCFG0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 2434 | //PSWUSCFG0_0_HEADER |
|---|
| 2435 | #define 0x0 |
|---|
| 2436 | #define 0x7 |
|---|
| 2437 | #define 0x7FL |
|---|
| 2438 | #define 0x80L |
|---|
| 2439 | //PSWUSCFG0_0_BIST |
|---|
| 2440 | #define PSWUSCFG0_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 2441 | #define PSWUSCFG0_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 2442 | #define PSWUSCFG0_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 2443 | #define PSWUSCFG0_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 2444 | #define PSWUSCFG0_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 2445 | #define PSWUSCFG0_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 2446 | //PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY |
|---|
| 2447 | #define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
|---|
| 2448 | #define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
|---|
| 2449 | #define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
|---|
| 2450 | #define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
|---|
| 2451 | #define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
|---|
| 2452 | #define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
|---|
| 2453 | #define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
|---|
| 2454 | #define PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
|---|
| 2455 | //PSWUSCFG0_0_IO_BASE_LIMIT |
|---|
| 2456 | #define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
|---|
| 2457 | #define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
|---|
| 2458 | #define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
|---|
| 2459 | #define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
|---|
| 2460 | #define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
|---|
| 2461 | #define PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
|---|
| 2462 | #define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
|---|
| 2463 | #define PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
|---|
| 2464 | //PSWUSCFG0_0_SECONDARY_STATUS |
|---|
| 2465 | #define PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 2466 | #define PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 2467 | #define PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 2468 | #define PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 2469 | #define PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 2470 | #define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 2471 | #define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 2472 | #define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 2473 | #define PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 2474 | #define PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 2475 | #define PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 2476 | #define PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 2477 | #define PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 2478 | #define PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 2479 | #define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 2480 | #define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 2481 | #define PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 2482 | #define PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 2483 | //PSWUSCFG0_0_MEM_BASE_LIMIT |
|---|
| 2484 | #define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 2485 | #define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
|---|
| 2486 | #define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 2487 | #define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
|---|
| 2488 | #define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 2489 | #define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
|---|
| 2490 | #define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 2491 | #define PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
|---|
| 2492 | //PSWUSCFG0_0_PREF_BASE_LIMIT |
|---|
| 2493 | #define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 2494 | #define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
|---|
| 2495 | #define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 2496 | #define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
|---|
| 2497 | #define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 2498 | #define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
|---|
| 2499 | #define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 2500 | #define PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
|---|
| 2501 | //PSWUSCFG0_0_PREF_BASE_UPPER |
|---|
| 2502 | #define PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
|---|
| 2503 | #define PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
|---|
| 2504 | //PSWUSCFG0_0_PREF_LIMIT_UPPER |
|---|
| 2505 | #define PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
|---|
| 2506 | #define PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
|---|
| 2507 | //PSWUSCFG0_0_IO_BASE_LIMIT_HI |
|---|
| 2508 | #define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
|---|
| 2509 | #define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
|---|
| 2510 | #define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
|---|
| 2511 | #define PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
|---|
| 2512 | //PSWUSCFG0_0_CAP_PTR |
|---|
| 2513 | #define PSWUSCFG0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 2514 | #define PSWUSCFG0_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 2515 | //PSWUSCFG0_0_ROM_BASE_ADDR |
|---|
| 2516 | #define PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 2517 | #define PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 2518 | //PSWUSCFG0_0_INTERRUPT_LINE |
|---|
| 2519 | #define PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 2520 | #define PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 2521 | //PSWUSCFG0_0_INTERRUPT_PIN |
|---|
| 2522 | #define PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 2523 | #define PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 2524 | //PSWUSCFG0_0_IRQ_BRIDGE_CNTL |
|---|
| 2525 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
|---|
| 2526 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
|---|
| 2527 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
|---|
| 2528 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
|---|
| 2529 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
|---|
| 2530 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
|---|
| 2531 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
|---|
| 2532 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
|---|
| 2533 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
|---|
| 2534 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
|---|
| 2535 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
|---|
| 2536 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
|---|
| 2537 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
|---|
| 2538 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
|---|
| 2539 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
|---|
| 2540 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
|---|
| 2541 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
|---|
| 2542 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
|---|
| 2543 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
|---|
| 2544 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
|---|
| 2545 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
|---|
| 2546 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
|---|
| 2547 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
|---|
| 2548 | #define PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
|---|
| 2549 | //PSWUSCFG0_0_EXT_BRIDGE_CNTL |
|---|
| 2550 | #define PSWUSCFG0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
|---|
| 2551 | #define PSWUSCFG0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
|---|
| 2552 | //PSWUSCFG0_0_VENDOR_CAP_LIST |
|---|
| 2553 | #define PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2554 | #define PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 2555 | #define PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 2556 | #define PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 2557 | #define PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 2558 | #define PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 2559 | //PSWUSCFG0_0_ADAPTER_ID_W |
|---|
| 2560 | #define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 2561 | #define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 2562 | #define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 2563 | #define PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 2564 | //PSWUSCFG0_0_PMI_CAP_LIST |
|---|
| 2565 | #define PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2566 | #define PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 2567 | #define PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 2568 | #define PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 2569 | //PSWUSCFG0_0_PMI_CAP |
|---|
| 2570 | #define PSWUSCFG0_0_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 2571 | #define PSWUSCFG0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 2572 | #define PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 2573 | #define PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 2574 | #define PSWUSCFG0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 2575 | #define PSWUSCFG0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 2576 | #define PSWUSCFG0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 2577 | #define PSWUSCFG0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 2578 | #define PSWUSCFG0_0_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 2579 | #define PSWUSCFG0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 2580 | #define PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 2581 | #define PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 2582 | #define PSWUSCFG0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 2583 | #define PSWUSCFG0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 2584 | #define PSWUSCFG0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 2585 | #define PSWUSCFG0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 2586 | //PSWUSCFG0_0_PMI_STATUS_CNTL |
|---|
| 2587 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 2588 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 2589 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 2590 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 2591 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 2592 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 2593 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 2594 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 2595 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 2596 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 2597 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 2598 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 2599 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 2600 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 2601 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 2602 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 2603 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 2604 | #define PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 2605 | //PSWUSCFG0_0_PCIE_CAP_LIST |
|---|
| 2606 | #define PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2607 | #define PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 2608 | #define PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 2609 | #define PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 2610 | //PSWUSCFG0_0_PCIE_CAP |
|---|
| 2611 | #define PSWUSCFG0_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 2612 | #define PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 2613 | #define PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 2614 | #define PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 2615 | #define PSWUSCFG0_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 2616 | #define PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 2617 | #define PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 2618 | #define PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 2619 | //PSWUSCFG0_0_DEVICE_CAP |
|---|
| 2620 | #define PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 2621 | #define PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 2622 | #define PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 2623 | #define PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 2624 | #define PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 2625 | #define PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 2626 | #define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 2627 | #define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 2628 | #define PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 2629 | #define PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 2630 | #define PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 2631 | #define PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 2632 | #define PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 2633 | #define PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 2634 | #define PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 2635 | #define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 2636 | #define PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 2637 | #define PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 2638 | //PSWUSCFG0_0_DEVICE_CNTL |
|---|
| 2639 | #define PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 2640 | #define PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 2641 | #define PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 2642 | #define PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 2643 | #define PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 2644 | #define PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 2645 | #define PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 2646 | #define PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 2647 | #define PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 2648 | #define PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 2649 | #define PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 2650 | #define PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
|---|
| 2651 | #define PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 2652 | #define PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 2653 | #define PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 2654 | #define PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 2655 | #define PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 2656 | #define PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 2657 | #define PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 2658 | #define PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 2659 | #define PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 2660 | #define PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 2661 | #define PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 2662 | #define PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
|---|
| 2663 | //PSWUSCFG0_0_DEVICE_STATUS |
|---|
| 2664 | #define PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 2665 | #define PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 2666 | #define PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 2667 | #define PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 2668 | #define PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 2669 | #define PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 2670 | #define PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 2671 | #define PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 2672 | #define PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 2673 | #define PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 2674 | #define PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 2675 | #define PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 2676 | //PSWUSCFG0_0_LINK_CAP |
|---|
| 2677 | #define PSWUSCFG0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 2678 | #define PSWUSCFG0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 2679 | #define PSWUSCFG0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 2680 | #define PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 2681 | #define PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 2682 | #define PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 2683 | #define PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 2684 | #define PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 2685 | #define PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 2686 | #define PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 2687 | #define PSWUSCFG0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 2688 | #define PSWUSCFG0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 2689 | #define PSWUSCFG0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 2690 | #define PSWUSCFG0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 2691 | #define PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 2692 | #define PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 2693 | #define PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 2694 | #define PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 2695 | #define PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 2696 | #define PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 2697 | #define PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 2698 | #define PSWUSCFG0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 2699 | //PSWUSCFG0_0_LINK_CNTL |
|---|
| 2700 | #define PSWUSCFG0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 2701 | #define PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 2702 | #define PSWUSCFG0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 2703 | #define PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 2704 | #define PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 2705 | #define PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 2706 | #define PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 2707 | #define PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 2708 | #define PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 2709 | #define PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 2710 | #define PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 2711 | #define PSWUSCFG0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 2712 | #define PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 2713 | #define PSWUSCFG0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 2714 | #define PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 2715 | #define PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 2716 | #define PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 2717 | #define PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 2718 | #define PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 2719 | #define PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 2720 | #define PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 2721 | #define PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 2722 | //PSWUSCFG0_0_LINK_STATUS |
|---|
| 2723 | #define PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 2724 | #define PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 2725 | #define PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 2726 | #define PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 2727 | #define PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 2728 | #define PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 2729 | #define PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 2730 | #define PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 2731 | #define PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 2732 | #define PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 2733 | #define PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 2734 | #define PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 2735 | #define PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 2736 | #define PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 2737 | //PSWUSCFG0_0_DEVICE_CAP2 |
|---|
| 2738 | #define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 2739 | #define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 2740 | #define PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 2741 | #define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 2742 | #define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 2743 | #define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 2744 | #define PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 2745 | #define PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 2746 | #define PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 2747 | #define PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 2748 | #define PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 2749 | #define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 2750 | #define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 2751 | #define PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 2752 | #define PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 2753 | #define PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 2754 | #define PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 2755 | #define PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 2756 | #define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 2757 | #define PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 2758 | #define PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 2759 | #define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 2760 | #define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 2761 | #define PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 2762 | #define PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 2763 | #define PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 2764 | #define PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 2765 | #define PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 2766 | #define PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 2767 | #define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 2768 | #define PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 2769 | #define PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 2770 | #define PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 2771 | #define PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 2772 | #define PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 2773 | #define PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 2774 | //PSWUSCFG0_0_DEVICE_CNTL2 |
|---|
| 2775 | #define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 2776 | #define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 2777 | #define PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 2778 | #define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 2779 | #define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 2780 | #define PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 2781 | #define PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 2782 | #define PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 2783 | #define PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 2784 | #define PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 2785 | #define PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 2786 | #define PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 2787 | #define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 2788 | #define PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 2789 | #define PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 2790 | #define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 2791 | #define PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 2792 | #define PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 2793 | #define PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 2794 | #define PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 2795 | #define PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 2796 | #define PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 2797 | #define PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 2798 | #define PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 2799 | //PSWUSCFG0_0_DEVICE_STATUS2 |
|---|
| 2800 | #define PSWUSCFG0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 2801 | #define PSWUSCFG0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 2802 | //PSWUSCFG0_0_LINK_CAP2 |
|---|
| 2803 | #define PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 2804 | #define PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 2805 | #define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 2806 | #define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 2807 | #define PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 2808 | #define PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 2809 | #define PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
|---|
| 2810 | #define PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 2811 | #define PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 2812 | #define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 2813 | #define PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 2814 | #define PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 2815 | #define PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 2816 | #define PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
|---|
| 2817 | //PSWUSCFG0_0_LINK_CNTL2 |
|---|
| 2818 | #define PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 2819 | #define PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 2820 | #define PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 2821 | #define PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 2822 | #define PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 2823 | #define PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 2824 | #define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 2825 | #define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 2826 | #define PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 2827 | #define PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 2828 | #define PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 2829 | #define PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 2830 | #define PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 2831 | #define PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 2832 | #define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 2833 | #define PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 2834 | //PSWUSCFG0_0_LINK_STATUS2 |
|---|
| 2835 | #define PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 2836 | #define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 2837 | #define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 2838 | #define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 2839 | #define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 2840 | #define PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 2841 | #define PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 2842 | #define PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 2843 | #define PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 2844 | #define PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 2845 | #define PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 2846 | #define PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 2847 | #define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 2848 | #define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 2849 | #define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 2850 | #define PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 2851 | #define PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 2852 | #define PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 2853 | #define PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 2854 | #define PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 2855 | #define PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 2856 | #define PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 2857 | //PSWUSCFG0_0_MSI_CAP_LIST |
|---|
| 2858 | #define PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2859 | #define PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 2860 | #define PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 2861 | #define PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 2862 | //PSWUSCFG0_0_MSI_MSG_CNTL |
|---|
| 2863 | #define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 2864 | #define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 2865 | #define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 2866 | #define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 2867 | #define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 2868 | #define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 2869 | #define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 2870 | #define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 2871 | #define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 2872 | #define PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 2873 | //PSWUSCFG0_0_MSI_MSG_ADDR_LO |
|---|
| 2874 | #define PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 2875 | #define PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 2876 | //PSWUSCFG0_0_MSI_MSG_ADDR_HI |
|---|
| 2877 | #define PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 2878 | #define PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 2879 | //PSWUSCFG0_0_MSI_MSG_DATA |
|---|
| 2880 | #define PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 2881 | #define PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 2882 | //PSWUSCFG0_0_MSI_MSG_DATA_64 |
|---|
| 2883 | #define PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 2884 | #define PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 2885 | //PSWUSCFG0_0_SSID_CAP_LIST |
|---|
| 2886 | #define PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2887 | #define PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 2888 | #define PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 2889 | #define PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 2890 | //PSWUSCFG0_0_SSID_CAP |
|---|
| 2891 | #define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 2892 | #define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 2893 | #define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 2894 | #define PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 2895 | //PSWUSCFG0_0_MSI_MAP_CAP_LIST |
|---|
| 2896 | #define PSWUSCFG0_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2897 | #define PSWUSCFG0_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 2898 | #define PSWUSCFG0_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 2899 | #define PSWUSCFG0_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 2900 | //PSWUSCFG0_0_MSI_MAP_CAP |
|---|
| 2901 | #define PSWUSCFG0_0_MSI_MAP_CAP__EN__SHIFT 0x0 |
|---|
| 2902 | #define PSWUSCFG0_0_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
|---|
| 2903 | #define PSWUSCFG0_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
|---|
| 2904 | #define PSWUSCFG0_0_MSI_MAP_CAP__EN_MASK 0x0001L |
|---|
| 2905 | #define PSWUSCFG0_0_MSI_MAP_CAP__FIXD_MASK 0x0002L |
|---|
| 2906 | #define PSWUSCFG0_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
|---|
| 2907 | //PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 2908 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2909 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2910 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2911 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2912 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2913 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2914 | //PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 2915 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 2916 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 2917 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 2918 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 2919 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 2920 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 2921 | //PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 2922 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 2923 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 2924 | //PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 2925 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 2926 | #define PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 2927 | //PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST |
|---|
| 2928 | #define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2929 | #define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2930 | #define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2931 | #define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2932 | #define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2933 | #define PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2934 | //PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1 |
|---|
| 2935 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 2936 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 2937 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 2938 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 2939 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 2940 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 2941 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 2942 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 2943 | //PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2 |
|---|
| 2944 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 2945 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 2946 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 2947 | #define PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 2948 | //PSWUSCFG0_0_PCIE_PORT_VC_CNTL |
|---|
| 2949 | #define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 2950 | #define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 2951 | #define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 2952 | #define PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 2953 | //PSWUSCFG0_0_PCIE_PORT_VC_STATUS |
|---|
| 2954 | #define PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 2955 | #define PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 2956 | //PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP |
|---|
| 2957 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 2958 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 2959 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 2960 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 2961 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 2962 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 2963 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
|---|
| 2964 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 2965 | //PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL |
|---|
| 2966 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 2967 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 2968 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 2969 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 2970 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 2971 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 2972 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 2973 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 2974 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 2975 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 2976 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 2977 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 2978 | //PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS |
|---|
| 2979 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 2980 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 2981 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 2982 | #define PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 2983 | //PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP |
|---|
| 2984 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 2985 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 2986 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 2987 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 2988 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 2989 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 2990 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
|---|
| 2991 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 2992 | //PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL |
|---|
| 2993 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
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| 2994 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
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| 2995 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
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| 2996 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
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| 2997 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
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| 2998 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
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| 2999 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
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| 3000 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
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| 3001 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
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| 3002 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
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| 3003 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
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| 3004 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
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| 3005 | //PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS |
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| 3006 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
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| 3007 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
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| 3008 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
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| 3009 | #define PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
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| 3010 | //PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
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| 3011 | #define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 3012 | #define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 3013 | #define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 3014 | #define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 3015 | #define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 3016 | #define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 3017 | //PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1 |
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| 3018 | #define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
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| 3019 | #define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
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| 3020 | //PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2 |
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| 3021 | #define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
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| 3022 | #define PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
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| 3023 | //PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 3024 | #define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 3025 | #define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 3026 | #define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 3027 | #define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 3028 | #define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 3029 | #define PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 3030 | //PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS |
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| 3031 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 3032 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 3033 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 3034 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 3035 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 3036 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 3037 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 3038 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 3039 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 3040 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 3041 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 3042 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 3043 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 3044 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 3045 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 3046 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 3047 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
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| 3048 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 3049 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 3050 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 3051 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 3052 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 3053 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 3054 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 3055 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 3056 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 3057 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 3058 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 3059 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 3060 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 3061 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 3062 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 3063 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 3064 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
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| 3065 | //PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK |
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| 3066 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 3067 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 3068 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 3069 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 3070 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 3071 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 3072 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 3073 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 3074 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 3075 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 3076 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 3077 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 3078 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 3079 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 3080 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 3081 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 3082 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
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| 3083 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 3084 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 3085 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 3086 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 3087 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 3088 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 3089 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 3090 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 3091 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 3092 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 3093 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 3094 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 3095 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 3096 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 3097 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 3098 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 3099 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
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| 3100 | //PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY |
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| 3101 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 3102 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 3103 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 3104 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 3105 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 3106 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 3107 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 3108 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 3109 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 3110 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 3111 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 3112 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 3113 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 3114 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 3115 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 3116 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 3117 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
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| 3118 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 3119 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 3120 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 3121 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 3122 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 3123 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 3124 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 3125 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 3126 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 3127 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 3128 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 3129 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 3130 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 3131 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 3132 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 3133 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 3134 | #define PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
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| 3135 | //PSWUSCFG0_0_PCIE_CORR_ERR_STATUS |
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| 3136 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 3137 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 3138 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 3139 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 3140 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 3141 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 3142 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 3143 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 3144 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 3145 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 3146 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 3147 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 3148 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 3149 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 3150 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 3151 | #define PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 3152 | //PSWUSCFG0_0_PCIE_CORR_ERR_MASK |
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| 3153 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 3154 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 3155 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 3156 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 3157 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 3158 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 3159 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 3160 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 3161 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 3162 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 3163 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 3164 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 3165 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 3166 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
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| 3167 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 3168 | #define PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 3169 | //PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 3170 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 3171 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 3172 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 3173 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 3174 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 3175 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 3176 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 3177 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 3178 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 3179 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 3180 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 3181 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 3182 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 3183 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 3184 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 3185 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 3186 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 3187 | #define PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
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| 3188 | //PSWUSCFG0_0_PCIE_HDR_LOG0 |
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| 3189 | #define PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 3190 | #define PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
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| 3191 | //PSWUSCFG0_0_PCIE_HDR_LOG1 |
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| 3192 | #define PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
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| 3193 | #define PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
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| 3194 | //PSWUSCFG0_0_PCIE_HDR_LOG2 |
|---|
| 3195 | #define PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 3196 | #define PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
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| 3197 | //PSWUSCFG0_0_PCIE_HDR_LOG3 |
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| 3198 | #define PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
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| 3199 | #define PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 3200 | //PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 3201 | #define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 3202 | #define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 3203 | //PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 3204 | #define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 3205 | #define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 3206 | //PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 3207 | #define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 3208 | #define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 3209 | //PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 3210 | #define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 3211 | #define PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 3212 | //PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 3213 | #define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 3214 | #define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 3215 | #define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 3216 | #define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 3217 | #define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 3218 | #define PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 3219 | //PSWUSCFG0_0_PCIE_LINK_CNTL3 |
|---|
| 3220 | #define PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 3221 | #define PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
|---|
| 3222 | #define PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
|---|
| 3223 | #define PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 3224 | #define PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 3225 | #define PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
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| 3226 | //PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS |
|---|
| 3227 | #define PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 3228 | #define PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
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| 3229 | //PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 3230 | #define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3231 | #define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3232 | #define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3233 | #define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3234 | #define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 3235 | #define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3236 | #define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3237 | #define PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3238 | //PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL |
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| 3239 | #define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 3240 | #define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3241 | #define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 3242 | #define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3243 | #define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 3244 | #define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3245 | #define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3246 | #define PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3247 | //PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL |
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| 3248 | #define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 3249 | #define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3250 | #define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3251 | #define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3252 | #define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3253 | #define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3254 | #define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3255 | #define PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3256 | //PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL |
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| 3257 | #define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3258 | #define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3259 | #define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3260 | #define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3261 | #define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3262 | #define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3263 | #define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3264 | #define PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3265 | //PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL |
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| 3266 | #define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3267 | #define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3268 | #define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3269 | #define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3270 | #define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3271 | #define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3272 | #define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3273 | #define PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3274 | //PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 3275 | #define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3276 | #define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3277 | #define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3278 | #define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3279 | #define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3280 | #define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3281 | #define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3282 | #define PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3283 | //PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 3284 | #define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3285 | #define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3286 | #define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3287 | #define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3288 | #define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3289 | #define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3290 | #define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3291 | #define PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3292 | //PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 3293 | #define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3294 | #define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3295 | #define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3296 | #define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3297 | #define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3298 | #define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3299 | #define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3300 | #define PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3301 | //PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 3302 | #define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3303 | #define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3304 | #define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3305 | #define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3306 | #define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3307 | #define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3308 | #define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3309 | #define PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3310 | //PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 3311 | #define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3312 | #define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3313 | #define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3314 | #define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3315 | #define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3316 | #define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3317 | #define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3318 | #define PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3319 | //PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 3320 | #define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3321 | #define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3322 | #define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3323 | #define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3324 | #define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3325 | #define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3326 | #define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3327 | #define PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3328 | //PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 3329 | #define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3330 | #define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3331 | #define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3332 | #define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3333 | #define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3334 | #define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3335 | #define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3336 | #define PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3337 | //PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 3338 | #define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3339 | #define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3340 | #define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3341 | #define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3342 | #define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3343 | #define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3344 | #define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3345 | #define PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3346 | //PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 3347 | #define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3348 | #define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3349 | #define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3350 | #define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3351 | #define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3352 | #define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3353 | #define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3354 | #define PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3355 | //PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 3356 | #define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3357 | #define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3358 | #define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3359 | #define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3360 | #define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3361 | #define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3362 | #define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3363 | #define PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3364 | //PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 3365 | #define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 3366 | #define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 3367 | #define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 3368 | #define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 3369 | #define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 3370 | #define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 3371 | #define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 3372 | #define PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 3373 | //PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST |
|---|
| 3374 | #define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 3375 | #define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 3376 | #define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 3377 | #define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 3378 | #define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 3379 | #define PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 3380 | //PSWUSCFG0_0_PCIE_ACS_CAP |
|---|
| 3381 | #define PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 3382 | #define PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 3383 | #define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 3384 | #define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 3385 | #define PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 3386 | #define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 3387 | #define PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 3388 | #define PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 3389 | #define PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 3390 | #define PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 3391 | #define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 3392 | #define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 3393 | #define PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 3394 | #define PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 3395 | #define PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 3396 | #define PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 3397 | //PSWUSCFG0_0_PCIE_ACS_CNTL |
|---|
| 3398 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 3399 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 3400 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 3401 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 3402 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 3403 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 3404 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 3405 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 3406 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 3407 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 3408 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 3409 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 3410 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 3411 | #define PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 3412 | //PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST |
|---|
| 3413 | #define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 3414 | #define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 3415 | #define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 3416 | #define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 3417 | #define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 3418 | #define PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 3419 | //PSWUSCFG0_0_PCIE_MC_CAP |
|---|
| 3420 | #define PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
|---|
| 3421 | #define PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
|---|
| 3422 | #define PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
|---|
| 3423 | #define PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
|---|
| 3424 | #define PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
|---|
| 3425 | #define PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
|---|
| 3426 | //PSWUSCFG0_0_PCIE_MC_CNTL |
|---|
| 3427 | #define PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
|---|
| 3428 | #define PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
|---|
| 3429 | #define PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
|---|
| 3430 | #define PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
|---|
| 3431 | //PSWUSCFG0_0_PCIE_MC_ADDR0 |
|---|
| 3432 | #define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
|---|
| 3433 | #define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
|---|
| 3434 | #define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
|---|
| 3435 | #define PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
|---|
| 3436 | //PSWUSCFG0_0_PCIE_MC_ADDR1 |
|---|
| 3437 | #define PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
|---|
| 3438 | #define PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
|---|
| 3439 | //PSWUSCFG0_0_PCIE_MC_RCV0 |
|---|
| 3440 | #define PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
|---|
| 3441 | #define PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
|---|
| 3442 | //PSWUSCFG0_0_PCIE_MC_RCV1 |
|---|
| 3443 | #define PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
|---|
| 3444 | #define PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
|---|
| 3445 | //PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0 |
|---|
| 3446 | #define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
|---|
| 3447 | #define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
|---|
| 3448 | //PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1 |
|---|
| 3449 | #define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
|---|
| 3450 | #define PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
|---|
| 3451 | //PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
|---|
| 3452 | #define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
|---|
| 3453 | #define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
|---|
| 3454 | //PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
|---|
| 3455 | #define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
|---|
| 3456 | #define PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
|---|
| 3457 | //PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0 |
|---|
| 3458 | #define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
|---|
| 3459 | #define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
|---|
| 3460 | #define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
|---|
| 3461 | #define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
|---|
| 3462 | //PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1 |
|---|
| 3463 | #define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
|---|
| 3464 | #define PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
|---|
| 3465 | //PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST |
|---|
| 3466 | #define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 3467 | #define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 3468 | #define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 3469 | #define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 3470 | #define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 3471 | #define PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 3472 | //PSWUSCFG0_0_PCIE_LTR_CAP |
|---|
| 3473 | #define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 3474 | #define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
|---|
| 3475 | #define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 3476 | #define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 3477 | #define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 3478 | #define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 3479 | #define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 3480 | #define PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 3481 | //PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 3482 | #define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 3483 | #define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 3484 | #define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 3485 | #define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 3486 | #define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 3487 | #define PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 3488 | //PSWUSCFG0_0_PCIE_ARI_CAP |
|---|
| 3489 | #define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 3490 | #define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 3491 | #define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 3492 | #define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 3493 | #define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 3494 | #define PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 3495 | //PSWUSCFG0_0_PCIE_ARI_CNTL |
|---|
| 3496 | #define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 3497 | #define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 3498 | #define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 3499 | #define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 3500 | #define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 3501 | #define PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 3502 | //PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST |
|---|
| 3503 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 3504 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 3505 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 3506 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 3507 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 3508 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 3509 | //PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP |
|---|
| 3510 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
|---|
| 3511 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
|---|
| 3512 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
|---|
| 3513 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
|---|
| 3514 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
|---|
| 3515 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
|---|
| 3516 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
|---|
| 3517 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
|---|
| 3518 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
|---|
| 3519 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
|---|
| 3520 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
|---|
| 3521 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
|---|
| 3522 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
|---|
| 3523 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
|---|
| 3524 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
|---|
| 3525 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
|---|
| 3526 | //PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL |
|---|
| 3527 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
|---|
| 3528 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
|---|
| 3529 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
|---|
| 3530 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
|---|
| 3531 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
|---|
| 3532 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
|---|
| 3533 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
|---|
| 3534 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
|---|
| 3535 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
|---|
| 3536 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
|---|
| 3537 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
|---|
| 3538 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
|---|
| 3539 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
|---|
| 3540 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
|---|
| 3541 | //PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2 |
|---|
| 3542 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
|---|
| 3543 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
|---|
| 3544 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
|---|
| 3545 | #define PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
|---|
| 3546 | //PSWUSCFG0_0_PCIE_ESM_CAP_LIST |
|---|
| 3547 | #define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 3548 | #define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 3549 | #define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 3550 | #define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 3551 | #define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 3552 | #define PSWUSCFG0_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 3553 | //PSWUSCFG0_0_PCIE_ESM_HEADER_1 |
|---|
| 3554 | #define 0x0 |
|---|
| 3555 | #define 0x10 |
|---|
| 3556 | #define 0x14 |
|---|
| 3557 | #define 0x0000FFFFL |
|---|
| 3558 | #define 0x000F0000L |
|---|
| 3559 | #define 0xFFF00000L |
|---|
| 3560 | //PSWUSCFG0_0_PCIE_ESM_HEADER_2 |
|---|
| 3561 | #define 0x0 |
|---|
| 3562 | #define 0xFFFFL |
|---|
| 3563 | //PSWUSCFG0_0_PCIE_ESM_STATUS |
|---|
| 3564 | #define PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
|---|
| 3565 | #define PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
|---|
| 3566 | #define PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
|---|
| 3567 | #define PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
|---|
| 3568 | //PSWUSCFG0_0_PCIE_ESM_CTRL |
|---|
| 3569 | #define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
|---|
| 3570 | #define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
|---|
| 3571 | #define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
|---|
| 3572 | #define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
|---|
| 3573 | #define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
|---|
| 3574 | #define PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
|---|
| 3575 | //PSWUSCFG0_0_PCIE_ESM_CAP_1 |
|---|
| 3576 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
|---|
| 3577 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
|---|
| 3578 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
|---|
| 3579 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
|---|
| 3580 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
|---|
| 3581 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
|---|
| 3582 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
|---|
| 3583 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
|---|
| 3584 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
|---|
| 3585 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
|---|
| 3586 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
|---|
| 3587 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
|---|
| 3588 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
|---|
| 3589 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
|---|
| 3590 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
|---|
| 3591 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
|---|
| 3592 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
|---|
| 3593 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
|---|
| 3594 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
|---|
| 3595 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
|---|
| 3596 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
|---|
| 3597 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
|---|
| 3598 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
|---|
| 3599 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
|---|
| 3600 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
|---|
| 3601 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
|---|
| 3602 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
|---|
| 3603 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
|---|
| 3604 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
|---|
| 3605 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
|---|
| 3606 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
|---|
| 3607 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
|---|
| 3608 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
|---|
| 3609 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
|---|
| 3610 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
|---|
| 3611 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
|---|
| 3612 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
|---|
| 3613 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
|---|
| 3614 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
|---|
| 3615 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
|---|
| 3616 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
|---|
| 3617 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
|---|
| 3618 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
|---|
| 3619 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
|---|
| 3620 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
|---|
| 3621 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
|---|
| 3622 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
|---|
| 3623 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
|---|
| 3624 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
|---|
| 3625 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
|---|
| 3626 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
|---|
| 3627 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
|---|
| 3628 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
|---|
| 3629 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
|---|
| 3630 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
|---|
| 3631 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
|---|
| 3632 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
|---|
| 3633 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
|---|
| 3634 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
|---|
| 3635 | #define PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
|---|
| 3636 | //PSWUSCFG0_0_PCIE_ESM_CAP_2 |
|---|
| 3637 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
|---|
| 3638 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
|---|
| 3639 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
|---|
| 3640 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
|---|
| 3641 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
|---|
| 3642 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
|---|
| 3643 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
|---|
| 3644 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
|---|
| 3645 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
|---|
| 3646 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
|---|
| 3647 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
|---|
| 3648 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
|---|
| 3649 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
|---|
| 3650 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
|---|
| 3651 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
|---|
| 3652 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
|---|
| 3653 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
|---|
| 3654 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
|---|
| 3655 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
|---|
| 3656 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
|---|
| 3657 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
|---|
| 3658 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
|---|
| 3659 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
|---|
| 3660 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
|---|
| 3661 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
|---|
| 3662 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
|---|
| 3663 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
|---|
| 3664 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
|---|
| 3665 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
|---|
| 3666 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
|---|
| 3667 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
|---|
| 3668 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
|---|
| 3669 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
|---|
| 3670 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
|---|
| 3671 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
|---|
| 3672 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
|---|
| 3673 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
|---|
| 3674 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
|---|
| 3675 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
|---|
| 3676 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
|---|
| 3677 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
|---|
| 3678 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
|---|
| 3679 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
|---|
| 3680 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
|---|
| 3681 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
|---|
| 3682 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
|---|
| 3683 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
|---|
| 3684 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
|---|
| 3685 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
|---|
| 3686 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
|---|
| 3687 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
|---|
| 3688 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
|---|
| 3689 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
|---|
| 3690 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
|---|
| 3691 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
|---|
| 3692 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
|---|
| 3693 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
|---|
| 3694 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
|---|
| 3695 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
|---|
| 3696 | #define PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
|---|
| 3697 | //PSWUSCFG0_0_PCIE_ESM_CAP_3 |
|---|
| 3698 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
|---|
| 3699 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
|---|
| 3700 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
|---|
| 3701 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
|---|
| 3702 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
|---|
| 3703 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
|---|
| 3704 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
|---|
| 3705 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
|---|
| 3706 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
|---|
| 3707 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
|---|
| 3708 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
|---|
| 3709 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
|---|
| 3710 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
|---|
| 3711 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
|---|
| 3712 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
|---|
| 3713 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
|---|
| 3714 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
|---|
| 3715 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
|---|
| 3716 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
|---|
| 3717 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
|---|
| 3718 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
|---|
| 3719 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
|---|
| 3720 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
|---|
| 3721 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
|---|
| 3722 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
|---|
| 3723 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
|---|
| 3724 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
|---|
| 3725 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
|---|
| 3726 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
|---|
| 3727 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
|---|
| 3728 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
|---|
| 3729 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
|---|
| 3730 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
|---|
| 3731 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
|---|
| 3732 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
|---|
| 3733 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
|---|
| 3734 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
|---|
| 3735 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
|---|
| 3736 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
|---|
| 3737 | #define PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
|---|
| 3738 | //PSWUSCFG0_0_PCIE_ESM_CAP_4 |
|---|
| 3739 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
|---|
| 3740 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
|---|
| 3741 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
|---|
| 3742 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
|---|
| 3743 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
|---|
| 3744 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
|---|
| 3745 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
|---|
| 3746 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
|---|
| 3747 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
|---|
| 3748 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
|---|
| 3749 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
|---|
| 3750 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
|---|
| 3751 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
|---|
| 3752 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
|---|
| 3753 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
|---|
| 3754 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
|---|
| 3755 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
|---|
| 3756 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
|---|
| 3757 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
|---|
| 3758 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
|---|
| 3759 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
|---|
| 3760 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
|---|
| 3761 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
|---|
| 3762 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
|---|
| 3763 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
|---|
| 3764 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
|---|
| 3765 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
|---|
| 3766 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
|---|
| 3767 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
|---|
| 3768 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
|---|
| 3769 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
|---|
| 3770 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
|---|
| 3771 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
|---|
| 3772 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
|---|
| 3773 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
|---|
| 3774 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
|---|
| 3775 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
|---|
| 3776 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
|---|
| 3777 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
|---|
| 3778 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
|---|
| 3779 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
|---|
| 3780 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
|---|
| 3781 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
|---|
| 3782 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
|---|
| 3783 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
|---|
| 3784 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
|---|
| 3785 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
|---|
| 3786 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
|---|
| 3787 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
|---|
| 3788 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
|---|
| 3789 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
|---|
| 3790 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
|---|
| 3791 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
|---|
| 3792 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
|---|
| 3793 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
|---|
| 3794 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
|---|
| 3795 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
|---|
| 3796 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
|---|
| 3797 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
|---|
| 3798 | #define PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
|---|
| 3799 | //PSWUSCFG0_0_PCIE_ESM_CAP_5 |
|---|
| 3800 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
|---|
| 3801 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
|---|
| 3802 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
|---|
| 3803 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
|---|
| 3804 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
|---|
| 3805 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
|---|
| 3806 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
|---|
| 3807 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
|---|
| 3808 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
|---|
| 3809 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
|---|
| 3810 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
|---|
| 3811 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
|---|
| 3812 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
|---|
| 3813 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
|---|
| 3814 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
|---|
| 3815 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
|---|
| 3816 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
|---|
| 3817 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
|---|
| 3818 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
|---|
| 3819 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
|---|
| 3820 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
|---|
| 3821 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
|---|
| 3822 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
|---|
| 3823 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
|---|
| 3824 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
|---|
| 3825 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
|---|
| 3826 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
|---|
| 3827 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
|---|
| 3828 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
|---|
| 3829 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
|---|
| 3830 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
|---|
| 3831 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
|---|
| 3832 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
|---|
| 3833 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
|---|
| 3834 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
|---|
| 3835 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
|---|
| 3836 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
|---|
| 3837 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
|---|
| 3838 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
|---|
| 3839 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
|---|
| 3840 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
|---|
| 3841 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
|---|
| 3842 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
|---|
| 3843 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
|---|
| 3844 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
|---|
| 3845 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
|---|
| 3846 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
|---|
| 3847 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
|---|
| 3848 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
|---|
| 3849 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
|---|
| 3850 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
|---|
| 3851 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
|---|
| 3852 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
|---|
| 3853 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
|---|
| 3854 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
|---|
| 3855 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
|---|
| 3856 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
|---|
| 3857 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
|---|
| 3858 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
|---|
| 3859 | #define PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
|---|
| 3860 | //PSWUSCFG0_0_PCIE_ESM_CAP_6 |
|---|
| 3861 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
|---|
| 3862 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
|---|
| 3863 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
|---|
| 3864 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
|---|
| 3865 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
|---|
| 3866 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
|---|
| 3867 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
|---|
| 3868 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
|---|
| 3869 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
|---|
| 3870 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
|---|
| 3871 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
|---|
| 3872 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
|---|
| 3873 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
|---|
| 3874 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
|---|
| 3875 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
|---|
| 3876 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
|---|
| 3877 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
|---|
| 3878 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
|---|
| 3879 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
|---|
| 3880 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
|---|
| 3881 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
|---|
| 3882 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
|---|
| 3883 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
|---|
| 3884 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
|---|
| 3885 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
|---|
| 3886 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
|---|
| 3887 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
|---|
| 3888 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
|---|
| 3889 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
|---|
| 3890 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
|---|
| 3891 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
|---|
| 3892 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
|---|
| 3893 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
|---|
| 3894 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
|---|
| 3895 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
|---|
| 3896 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
|---|
| 3897 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
|---|
| 3898 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
|---|
| 3899 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
|---|
| 3900 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
|---|
| 3901 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
|---|
| 3902 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
|---|
| 3903 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
|---|
| 3904 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
|---|
| 3905 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
|---|
| 3906 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
|---|
| 3907 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
|---|
| 3908 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
|---|
| 3909 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
|---|
| 3910 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
|---|
| 3911 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
|---|
| 3912 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
|---|
| 3913 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
|---|
| 3914 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
|---|
| 3915 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
|---|
| 3916 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
|---|
| 3917 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
|---|
| 3918 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
|---|
| 3919 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
|---|
| 3920 | #define PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
|---|
| 3921 | //PSWUSCFG0_0_PCIE_ESM_CAP_7 |
|---|
| 3922 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
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| 3923 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
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| 3924 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
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| 3925 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
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| 3926 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
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| 3927 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
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| 3928 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
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| 3929 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
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| 3930 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
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| 3931 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
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| 3932 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
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| 3933 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
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| 3934 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
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| 3935 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
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| 3936 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
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| 3937 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
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| 3938 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
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| 3939 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
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| 3940 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
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| 3941 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
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| 3942 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
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| 3943 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
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| 3944 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
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| 3945 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
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| 3946 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
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| 3947 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
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| 3948 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
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| 3949 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
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| 3950 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
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| 3951 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
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| 3952 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
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| 3953 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
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| 3954 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
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| 3955 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
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| 3956 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
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| 3957 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
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| 3958 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
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| 3959 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
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| 3960 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
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| 3961 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
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| 3962 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
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| 3963 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
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| 3964 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
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| 3965 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
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| 3966 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
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| 3967 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
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| 3968 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
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| 3969 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
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| 3970 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
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| 3971 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
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| 3972 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
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| 3973 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
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| 3974 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
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| 3975 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
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| 3976 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
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| 3977 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
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| 3978 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
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| 3979 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
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| 3980 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
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| 3981 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
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| 3982 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
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| 3983 | #define PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
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| 3984 | //PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST |
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| 3985 | #define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 3986 | #define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 3987 | #define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 3988 | #define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 3989 | #define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 3990 | #define PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 3991 | //PSWUSCFG0_0_DATA_LINK_FEATURE_CAP |
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| 3992 | #define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0 |
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| 3993 | #define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1 |
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| 3994 | #define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
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| 3995 | #define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L |
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| 3996 | #define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL |
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| 3997 | #define PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
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| 3998 | //PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS |
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| 3999 | #define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
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| 4000 | #define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
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| 4001 | #define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
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| 4002 | #define PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
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| 4003 | //PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST |
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| 4004 | #define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 4005 | #define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 4006 | #define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 4007 | #define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 4008 | #define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 4009 | #define PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 4010 | //PSWUSCFG0_0_LINK_CAP_16GT |
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| 4011 | #define PSWUSCFG0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
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| 4012 | #define PSWUSCFG0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
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| 4013 | //PSWUSCFG0_0_LINK_CNTL_16GT |
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| 4014 | #define PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
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| 4015 | #define PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
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| 4016 | //PSWUSCFG0_0_LINK_STATUS_16GT |
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| 4017 | #define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
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| 4018 | #define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
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| 4019 | #define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
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| 4020 | #define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
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| 4021 | #define PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
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| 4022 | #define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
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| 4023 | #define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
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| 4024 | #define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
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| 4025 | #define PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
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| 4026 | #define PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
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| 4027 | //PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
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| 4028 | #define PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
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| 4029 | #define PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
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| 4030 | //PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT |
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| 4031 | #define PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
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| 4032 | #define PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
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| 4033 | //PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT |
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| 4034 | #define PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
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| 4035 | #define PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
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| 4036 | //PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT |
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| 4037 | #define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4038 | #define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4039 | #define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4040 | #define PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4041 | //PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT |
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| 4042 | #define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4043 | #define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4044 | #define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4045 | #define PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4046 | //PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT |
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| 4047 | #define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4048 | #define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4049 | #define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4050 | #define PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4051 | //PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT |
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| 4052 | #define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4053 | #define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4054 | #define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4055 | #define PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4056 | //PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT |
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| 4057 | #define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4058 | #define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4059 | #define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4060 | #define PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4061 | //PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT |
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| 4062 | #define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4063 | #define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4064 | #define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4065 | #define PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4066 | //PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT |
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| 4067 | #define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4068 | #define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4069 | #define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4070 | #define PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4071 | //PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT |
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| 4072 | #define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4073 | #define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4074 | #define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4075 | #define PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4076 | //PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT |
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| 4077 | #define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4078 | #define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4079 | #define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4080 | #define PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4081 | //PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT |
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| 4082 | #define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4083 | #define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4084 | #define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4085 | #define PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4086 | //PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT |
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| 4087 | #define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4088 | #define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4089 | #define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4090 | #define PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4091 | //PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT |
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| 4092 | #define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4093 | #define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4094 | #define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 4095 | #define PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 4096 | //PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT |
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| 4097 | #define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 4098 | #define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 4099 | #define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 4100 | #define PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 4101 | //PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT |
|---|
| 4102 | #define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4103 | #define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4104 | #define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 4105 | #define PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 4106 | //PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 4107 | #define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4108 | #define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4109 | #define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 4110 | #define PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 4111 | //PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 4112 | #define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4113 | #define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4114 | #define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 4115 | #define PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 4116 | //PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 4117 | #define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 4118 | #define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 4119 | #define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 4120 | #define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 4121 | #define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 4122 | #define PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 4123 | //PSWUSCFG0_0_MARGINING_PORT_CAP |
|---|
| 4124 | #define PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 4125 | #define PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 4126 | //PSWUSCFG0_0_MARGINING_PORT_STATUS |
|---|
| 4127 | #define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
|---|
| 4128 | #define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
|---|
| 4129 | #define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
|---|
| 4130 | #define PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
|---|
| 4131 | //PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL |
|---|
| 4132 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4133 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4134 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4135 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4136 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4137 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4138 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 4139 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4140 | //PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS |
|---|
| 4141 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4142 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4143 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4144 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4145 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4146 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4147 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4148 | #define PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4149 | //PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL |
|---|
| 4150 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4151 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4152 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4153 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4154 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4155 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4156 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 4157 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4158 | //PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS |
|---|
| 4159 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4160 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4161 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4162 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4163 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4164 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4165 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4166 | #define PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4167 | //PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL |
|---|
| 4168 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4169 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4170 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4171 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4172 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4173 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4174 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 4175 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4176 | //PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS |
|---|
| 4177 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4178 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4179 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4180 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4181 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4182 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4183 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4184 | #define PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4185 | //PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL |
|---|
| 4186 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4187 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4188 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4189 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4190 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4191 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4192 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 4193 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4194 | //PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS |
|---|
| 4195 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4196 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4197 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4198 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4199 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4200 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4201 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4202 | #define PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4203 | //PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL |
|---|
| 4204 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4205 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4206 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4207 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4208 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4209 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4210 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 4211 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4212 | //PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS |
|---|
| 4213 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4214 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4215 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4216 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4217 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4218 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4219 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4220 | #define PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4221 | //PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL |
|---|
| 4222 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4223 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4224 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4225 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4226 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4227 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4228 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 4229 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4230 | //PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS |
|---|
| 4231 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4232 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4233 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4234 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4235 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4236 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4237 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4238 | #define PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4239 | //PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL |
|---|
| 4240 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4241 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4242 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4243 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4244 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4245 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4246 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 4247 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4248 | //PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS |
|---|
| 4249 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4250 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4251 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4252 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4253 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4254 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4255 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4256 | #define PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4257 | //PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL |
|---|
| 4258 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4259 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4260 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4261 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4262 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4263 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4264 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 4265 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4266 | //PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS |
|---|
| 4267 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4268 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4269 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4270 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4271 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4272 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4273 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4274 | #define PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4275 | //PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL |
|---|
| 4276 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4277 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4278 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4279 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4280 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4281 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4282 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 4283 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4284 | //PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS |
|---|
| 4285 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4286 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4287 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4288 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4289 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4290 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4291 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4292 | #define PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4293 | //PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL |
|---|
| 4294 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4295 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4296 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4297 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4298 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4299 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4300 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 4301 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4302 | //PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS |
|---|
| 4303 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4304 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4305 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4306 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4307 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4308 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4309 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4310 | #define PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4311 | //PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL |
|---|
| 4312 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4313 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4314 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4315 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4316 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4317 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4318 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 4319 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4320 | //PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS |
|---|
| 4321 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4322 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4323 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4324 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4325 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4326 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4327 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4328 | #define PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4329 | //PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL |
|---|
| 4330 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4331 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4332 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4333 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4334 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4335 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4336 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 4337 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4338 | //PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS |
|---|
| 4339 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4340 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4341 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4342 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4343 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4344 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4345 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4346 | #define PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4347 | //PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL |
|---|
| 4348 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4349 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4350 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4351 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4352 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4353 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4354 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 4355 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4356 | //PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS |
|---|
| 4357 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4358 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4359 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4360 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4361 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4362 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4363 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4364 | #define PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4365 | //PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL |
|---|
| 4366 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4367 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4368 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4369 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4370 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4371 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4372 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 4373 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4374 | //PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS |
|---|
| 4375 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4376 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4377 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4378 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4379 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4380 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4381 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4382 | #define PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4383 | //PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL |
|---|
| 4384 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4385 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4386 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4387 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4388 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4389 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4390 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 4391 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4392 | //PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS |
|---|
| 4393 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4394 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4395 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4396 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4397 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4398 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4399 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4400 | #define PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4401 | //PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL |
|---|
| 4402 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 4403 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 4404 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 4405 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 4406 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 4407 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 4408 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 4409 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 4410 | //PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS |
|---|
| 4411 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 4412 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 4413 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 4414 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 4415 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 4416 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 4417 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 4418 | #define PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 4419 | //PSWUSCFG0_0_PCIE_CCIX_CAP_LIST |
|---|
| 4420 | #define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 4421 | #define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 4422 | #define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 4423 | #define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 4424 | #define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 4425 | #define PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 4426 | //PSWUSCFG0_0_PCIE_CCIX_HEADER_1 |
|---|
| 4427 | #define 0x0 |
|---|
| 4428 | #define 0x10 |
|---|
| 4429 | #define 0x14 |
|---|
| 4430 | #define 0x0000FFFFL |
|---|
| 4431 | #define 0x000F0000L |
|---|
| 4432 | #define 0xFFF00000L |
|---|
| 4433 | //PSWUSCFG0_0_PCIE_CCIX_HEADER_2 |
|---|
| 4434 | #define 0x0 |
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| 4435 | #define 0xFFFFL |
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| 4436 | //PSWUSCFG0_0_PCIE_CCIX_CAP |
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| 4437 | #define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0 |
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| 4438 | #define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1 |
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| 4439 | #define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3 |
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| 4440 | #define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4 |
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| 4441 | #define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8 |
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| 4442 | #define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L |
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| 4443 | #define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L |
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| 4444 | #define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L |
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| 4445 | #define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L |
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| 4446 | #define PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L |
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| 4447 | //PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP |
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| 4448 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0 |
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| 4449 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1 |
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| 4450 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2 |
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| 4451 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5 |
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| 4452 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9 |
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| 4453 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe |
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| 4454 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L |
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| 4455 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L |
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| 4456 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L |
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| 4457 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L |
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| 4458 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L |
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| 4459 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L |
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| 4460 | //PSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP |
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| 4461 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0 |
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| 4462 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL |
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| 4463 | //PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS |
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| 4464 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0 |
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| 4465 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7 |
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| 4466 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL |
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| 4467 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L |
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| 4468 | //PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL |
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| 4469 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0 |
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| 4470 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7 |
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| 4471 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8 |
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| 4472 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf |
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| 4473 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10 |
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| 4474 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14 |
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| 4475 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18 |
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| 4476 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19 |
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| 4477 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a |
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| 4478 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL |
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| 4479 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L |
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| 4480 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L |
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| 4481 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L |
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| 4482 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L |
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| 4483 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L |
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| 4484 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L |
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| 4485 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L |
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| 4486 | #define PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L |
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| 4487 | //PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT |
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| 4488 | #define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4489 | #define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4490 | #define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4491 | #define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4492 | //PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT |
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| 4493 | #define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4494 | #define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4495 | #define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4496 | #define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4497 | //PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT |
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| 4498 | #define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4499 | #define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4500 | #define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4501 | #define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4502 | //PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT |
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| 4503 | #define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4504 | #define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4505 | #define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4506 | #define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4507 | //PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT |
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| 4508 | #define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4509 | #define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4510 | #define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4511 | #define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4512 | //PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT |
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| 4513 | #define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4514 | #define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4515 | #define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4516 | #define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4517 | //PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT |
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| 4518 | #define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4519 | #define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4520 | #define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4521 | #define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4522 | //PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT |
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| 4523 | #define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4524 | #define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4525 | #define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4526 | #define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4527 | //PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT |
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| 4528 | #define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4529 | #define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4530 | #define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4531 | #define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4532 | //PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT |
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| 4533 | #define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4534 | #define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4535 | #define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4536 | #define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4537 | //PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT |
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| 4538 | #define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4539 | #define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4540 | #define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4541 | #define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4542 | //PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT |
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| 4543 | #define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4544 | #define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4545 | #define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4546 | #define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4547 | //PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT |
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| 4548 | #define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4549 | #define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4550 | #define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4551 | #define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4552 | //PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT |
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| 4553 | #define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4554 | #define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4555 | #define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4556 | #define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4557 | //PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT |
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| 4558 | #define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4559 | #define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4560 | #define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4561 | #define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4562 | //PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT |
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| 4563 | #define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0 |
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| 4564 | #define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4 |
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| 4565 | #define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL |
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| 4566 | #define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L |
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| 4567 | //PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT |
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| 4568 | #define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0 |
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| 4569 | #define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4 |
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| 4570 | #define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL |
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| 4571 | #define PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L |
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| 4572 | //PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT |
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| 4573 | #define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0 |
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| 4574 | #define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4 |
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| 4575 | #define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL |
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| 4576 | #define PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L |
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| 4577 | //PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT |
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| 4578 | #define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0 |
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| 4579 | #define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4 |
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| 4580 | #define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL |
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| 4581 | #define PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L |
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| 4582 | //PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT |
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| 4583 | #define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0 |
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| 4584 | #define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4 |
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| 4585 | #define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL |
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| 4586 | #define PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L |
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| 4587 | //PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT |
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| 4588 | #define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0 |
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| 4589 | #define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4 |
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| 4590 | #define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL |
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| 4591 | #define PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L |
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| 4592 | //PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT |
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| 4593 | #define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4594 | #define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4595 | #define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4596 | #define PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4597 | //PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT |
|---|
| 4598 | #define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4599 | #define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4600 | #define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4601 | #define PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4602 | //PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT |
|---|
| 4603 | #define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4604 | #define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4605 | #define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4606 | #define PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4607 | //PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT |
|---|
| 4608 | #define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4609 | #define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4610 | #define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4611 | #define PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4612 | //PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT |
|---|
| 4613 | #define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4614 | #define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4615 | #define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4616 | #define PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4617 | //PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT |
|---|
| 4618 | #define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4619 | #define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4620 | #define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4621 | #define PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4622 | //PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT |
|---|
| 4623 | #define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4624 | #define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4625 | #define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4626 | #define PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4627 | //PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT |
|---|
| 4628 | #define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4629 | #define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4630 | #define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4631 | #define PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4632 | //PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT |
|---|
| 4633 | #define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4634 | #define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4635 | #define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4636 | #define PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4637 | //PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT |
|---|
| 4638 | #define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4639 | #define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4640 | #define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4641 | #define PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4642 | //PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT |
|---|
| 4643 | #define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 4644 | #define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 4645 | #define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 4646 | #define PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 4647 | //PSWUSCFG0_0_PCIE_CCIX_TRANS_CAP |
|---|
| 4648 | #define PSWUSCFG0_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0 |
|---|
| 4649 | #define PSWUSCFG0_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L |
|---|
| 4650 | //PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL |
|---|
| 4651 | #define PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0 |
|---|
| 4652 | #define PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE__SHIFT 0x1 |
|---|
| 4653 | #define PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L |
|---|
| 4654 | #define PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE_MASK 0x00000002L |
|---|
| 4655 | |
|---|
| 4656 | |
|---|
| 4657 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
|---|
| 4658 | //BIF_CFG_DEV0_EPF0_0_VENDOR_ID |
|---|
| 4659 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 4660 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 4661 | //BIF_CFG_DEV0_EPF0_0_DEVICE_ID |
|---|
| 4662 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 4663 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 4664 | //BIF_CFG_DEV0_EPF0_0_COMMAND |
|---|
| 4665 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 4666 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 4667 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 4668 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 4669 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 4670 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 4671 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 4672 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 4673 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 4674 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 4675 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 4676 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 4677 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 4678 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 4679 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 4680 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 4681 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 4682 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 4683 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 4684 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 4685 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 4686 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 4687 | //BIF_CFG_DEV0_EPF0_0_STATUS |
|---|
| 4688 | #define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 4689 | #define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 4690 | #define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 4691 | #define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 4692 | #define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 4693 | #define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 4694 | #define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 4695 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 4696 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 4697 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 4698 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 4699 | #define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 4700 | #define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 4701 | #define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 4702 | #define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 4703 | #define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 4704 | #define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 4705 | #define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 4706 | #define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 4707 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 4708 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 4709 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 4710 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 4711 | #define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 4712 | //BIF_CFG_DEV0_EPF0_0_REVISION_ID |
|---|
| 4713 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 4714 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 4715 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 4716 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 4717 | //BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE |
|---|
| 4718 | #define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 4719 | #define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 4720 | //BIF_CFG_DEV0_EPF0_0_SUB_CLASS |
|---|
| 4721 | #define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 4722 | #define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 4723 | //BIF_CFG_DEV0_EPF0_0_BASE_CLASS |
|---|
| 4724 | #define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 4725 | #define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 4726 | //BIF_CFG_DEV0_EPF0_0_CACHE_LINE |
|---|
| 4727 | #define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 4728 | #define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 4729 | //BIF_CFG_DEV0_EPF0_0_LATENCY |
|---|
| 4730 | #define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 4731 | #define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 4732 | //BIF_CFG_DEV0_EPF0_0_HEADER |
|---|
| 4733 | #define 0x0 |
|---|
| 4734 | #define 0x7 |
|---|
| 4735 | #define 0x7FL |
|---|
| 4736 | #define 0x80L |
|---|
| 4737 | //BIF_CFG_DEV0_EPF0_0_BIST |
|---|
| 4738 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 4739 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 4740 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 4741 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 4742 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 4743 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 4744 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 |
|---|
| 4745 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 4746 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 4747 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 |
|---|
| 4748 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 4749 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 4750 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 |
|---|
| 4751 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 4752 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 4753 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 |
|---|
| 4754 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 4755 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 4756 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 |
|---|
| 4757 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 4758 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 4759 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 |
|---|
| 4760 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 4761 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 4762 | //BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR |
|---|
| 4763 | #define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 4764 | #define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 4765 | //BIF_CFG_DEV0_EPF0_0_ADAPTER_ID |
|---|
| 4766 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 4767 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 4768 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 4769 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 4770 | //BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR |
|---|
| 4771 | #define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 4772 | #define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 4773 | //BIF_CFG_DEV0_EPF0_0_CAP_PTR |
|---|
| 4774 | #define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 4775 | #define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 4776 | //BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE |
|---|
| 4777 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 4778 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 4779 | //BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN |
|---|
| 4780 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 4781 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 4782 | //BIF_CFG_DEV0_EPF0_0_MIN_GRANT |
|---|
| 4783 | #define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 4784 | #define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 4785 | //BIF_CFG_DEV0_EPF0_0_MAX_LATENCY |
|---|
| 4786 | #define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 4787 | #define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 4788 | //BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST |
|---|
| 4789 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 4790 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 4791 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 4792 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 4793 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 4794 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 4795 | //BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W |
|---|
| 4796 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 4797 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 4798 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 4799 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 4800 | //BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST |
|---|
| 4801 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 4802 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 4803 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 4804 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 4805 | //BIF_CFG_DEV0_EPF0_0_PMI_CAP |
|---|
| 4806 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 4807 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 4808 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 4809 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 4810 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 4811 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 4812 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 4813 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 4814 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 4815 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 4816 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 4817 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 4818 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 4819 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 4820 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 4821 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 4822 | //BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL |
|---|
| 4823 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 4824 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 4825 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 4826 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 4827 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 4828 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 4829 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 4830 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 4831 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 4832 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 4833 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 4834 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 4835 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 4836 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 4837 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 4838 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 4839 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 4840 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 4841 | //BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST |
|---|
| 4842 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 4843 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 4844 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 4845 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 4846 | //BIF_CFG_DEV0_EPF0_0_PCIE_CAP |
|---|
| 4847 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 4848 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 4849 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 4850 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 4851 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 4852 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 4853 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 4854 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 4855 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CAP |
|---|
| 4856 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 4857 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 4858 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 4859 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 4860 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 4861 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 4862 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 4863 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 4864 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 4865 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 4866 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 4867 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 4868 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 4869 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 4870 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 4871 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 4872 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 4873 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 4874 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL |
|---|
| 4875 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 4876 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 4877 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 4878 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 4879 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 4880 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 4881 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 4882 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 4883 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 4884 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 4885 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 4886 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 4887 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 4888 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 4889 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 4890 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 4891 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 4892 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 4893 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 4894 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 4895 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 4896 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 4897 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 4898 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 4899 | //BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS |
|---|
| 4900 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 4901 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 4902 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 4903 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 4904 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 4905 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 4906 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 4907 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 4908 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 4909 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 4910 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 4911 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 4912 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 4913 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 4914 | //BIF_CFG_DEV0_EPF0_0_LINK_CAP |
|---|
| 4915 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 4916 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 4917 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 4918 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 4919 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 4920 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 4921 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 4922 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 4923 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 4924 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 4925 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 4926 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 4927 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 4928 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 4929 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 4930 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 4931 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 4932 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 4933 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 4934 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 4935 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 4936 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 4937 | //BIF_CFG_DEV0_EPF0_0_LINK_CNTL |
|---|
| 4938 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 4939 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 4940 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 4941 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 4942 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 4943 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 4944 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 4945 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 4946 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 4947 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 4948 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 4949 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 4950 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 4951 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 4952 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 4953 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 4954 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 4955 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 4956 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 4957 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 4958 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 4959 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 4960 | //BIF_CFG_DEV0_EPF0_0_LINK_STATUS |
|---|
| 4961 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 4962 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 4963 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 4964 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 4965 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 4966 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 4967 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 4968 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 4969 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 4970 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 4971 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 4972 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 4973 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 4974 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 4975 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 |
|---|
| 4976 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 4977 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 4978 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 4979 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 4980 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 4981 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 4982 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 4983 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 4984 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 4985 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 4986 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 4987 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 4988 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 4989 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 4990 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 4991 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 4992 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 4993 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 4994 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 4995 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 4996 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 4997 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 4998 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 4999 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 5000 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 5001 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 5002 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 5003 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 5004 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 5005 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 5006 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 5007 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 5008 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 5009 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 5010 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 5011 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 5012 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 5013 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 5014 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 5015 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 5016 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 |
|---|
| 5017 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 5018 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 5019 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 5020 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 5021 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 5022 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 5023 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 5024 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 5025 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 5026 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 5027 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 5028 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 5029 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 5030 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 5031 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 5032 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 5033 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 5034 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 5035 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 5036 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 5037 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 5038 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 5039 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 5040 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 5041 | //BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 |
|---|
| 5042 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 5043 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 5044 | //BIF_CFG_DEV0_EPF0_0_LINK_CAP2 |
|---|
| 5045 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 5046 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 5047 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 5048 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 5049 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 5050 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 5051 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 5052 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 5053 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 5054 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 5055 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 5056 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 5057 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 5058 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 5059 | //BIF_CFG_DEV0_EPF0_0_LINK_CNTL2 |
|---|
| 5060 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 5061 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 5062 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 5063 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 5064 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 5065 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 5066 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 5067 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 5068 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 5069 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 5070 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 5071 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 5072 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 5073 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 5074 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 5075 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 5076 | //BIF_CFG_DEV0_EPF0_0_LINK_STATUS2 |
|---|
| 5077 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 5078 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 5079 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 5080 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 5081 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 5082 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 5083 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 5084 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 5085 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 5086 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 5087 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 5088 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 5089 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 5090 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 5091 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 5092 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 5093 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 5094 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 5095 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 5096 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 5097 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 5098 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 5099 | //BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST |
|---|
| 5100 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5101 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 5102 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 5103 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 5104 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL |
|---|
| 5105 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 5106 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 5107 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 5108 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 5109 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 5110 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 5111 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 5112 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 5113 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 5114 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 5115 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO |
|---|
| 5116 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 5117 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 5118 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI |
|---|
| 5119 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 5120 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 5121 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA |
|---|
| 5122 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 5123 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 5124 | //BIF_CFG_DEV0_EPF0_0_MSI_MASK |
|---|
| 5125 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 5126 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 5127 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 |
|---|
| 5128 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 5129 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 5130 | //BIF_CFG_DEV0_EPF0_0_MSI_MASK_64 |
|---|
| 5131 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 5132 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 5133 | //BIF_CFG_DEV0_EPF0_0_MSI_PENDING |
|---|
| 5134 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 5135 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 5136 | //BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 |
|---|
| 5137 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 5138 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 5139 | //BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST |
|---|
| 5140 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5141 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 5142 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 5143 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 5144 | //BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL |
|---|
| 5145 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 5146 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 5147 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 5148 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 5149 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 5150 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 5151 | //BIF_CFG_DEV0_EPF0_0_MSIX_TABLE |
|---|
| 5152 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 5153 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 5154 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 5155 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 5156 | //BIF_CFG_DEV0_EPF0_0_MSIX_PBA |
|---|
| 5157 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 5158 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 5159 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 5160 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 5161 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 5162 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5163 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5164 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5165 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5166 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5167 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5168 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 5169 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 5170 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 5171 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 5172 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 5173 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 5174 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 5175 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 5176 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 5177 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 5178 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 5179 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 5180 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 5181 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST |
|---|
| 5182 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5183 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5184 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5185 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5186 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5187 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5188 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 |
|---|
| 5189 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 5190 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 5191 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 5192 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 5193 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 5194 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 5195 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 5196 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 5197 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 |
|---|
| 5198 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 5199 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 5200 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 5201 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 5202 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL |
|---|
| 5203 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 5204 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 5205 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 5206 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 5207 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS |
|---|
| 5208 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 5209 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 5210 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP |
|---|
| 5211 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 5212 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 5213 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 5214 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 5215 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 5216 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 5217 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 5218 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 5219 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL |
|---|
| 5220 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 5221 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 5222 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 5223 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 5224 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 5225 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 5226 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 5227 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 5228 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 5229 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 5230 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 5231 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 5232 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS |
|---|
| 5233 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 5234 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 5235 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 5236 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 5237 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP |
|---|
| 5238 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 5239 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 5240 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 5241 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 5242 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 5243 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 5244 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 5245 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 5246 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL |
|---|
| 5247 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 5248 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 5249 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 5250 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 5251 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 5252 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 5253 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 5254 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 5255 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 5256 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 5257 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 5258 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 5259 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS |
|---|
| 5260 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 5261 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 5262 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 5263 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 5264 | //BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 5265 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5266 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5267 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5268 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5269 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5270 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5271 | //BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 5272 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 5273 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 5274 | //BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 5275 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 5276 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 5277 | //BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 5278 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5279 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5280 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5281 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5282 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5283 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5284 | //BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 5285 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 5286 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 5287 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 5288 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 5289 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 5290 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 5291 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 5292 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 5293 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 5294 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 5295 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 5296 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 5297 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 5298 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 5299 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 5300 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 5301 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 5302 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 5303 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 5304 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 5305 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 5306 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 5307 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 5308 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 5309 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 5310 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 5311 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 5312 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 5313 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 5314 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 5315 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 5316 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 5317 | //BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK |
|---|
| 5318 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 5319 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 5320 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 5321 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 5322 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 5323 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 5324 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 5325 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 5326 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 5327 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 5328 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 5329 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 5330 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 5331 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 5332 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 5333 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 5334 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 5335 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 5336 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 5337 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 5338 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 5339 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 5340 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 5341 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 5342 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 5343 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 5344 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 5345 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 5346 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 5347 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 5348 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 5349 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 5350 | //BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 5351 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 5352 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 5353 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 5354 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 5355 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 5356 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 5357 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 5358 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 5359 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 5360 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 5361 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 5362 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 5363 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 5364 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 5365 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 5366 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 5367 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 5368 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 5369 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 5370 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 5371 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 5372 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 5373 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 5374 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 5375 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 5376 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 5377 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 5378 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 5379 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 5380 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 5381 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 5382 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 5383 | //BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS |
|---|
| 5384 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 5385 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 5386 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 5387 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 5388 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 5389 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 5390 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 5391 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 5392 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 5393 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 5394 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 5395 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 5396 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 5397 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 5398 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 5399 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 5400 | //BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK |
|---|
| 5401 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 5402 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 5403 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 5404 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 5405 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 5406 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 5407 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 5408 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 5409 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 5410 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 5411 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 5412 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 5413 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 5414 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 5415 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 5416 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 5417 | //BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 5418 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 5419 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 5420 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 5421 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 5422 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 5423 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 5424 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 5425 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 5426 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 5427 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 5428 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 5429 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 5430 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 5431 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 5432 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 5433 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 5434 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 5435 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 5436 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 |
|---|
| 5437 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 5438 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 5439 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 |
|---|
| 5440 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 5441 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 5442 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 |
|---|
| 5443 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 5444 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 5445 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 |
|---|
| 5446 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 5447 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 5448 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 5449 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 5450 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 5451 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 5452 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 5453 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 5454 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 5455 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 5456 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 5457 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 5458 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 5459 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 5460 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST |
|---|
| 5461 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5462 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5463 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5464 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5465 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5466 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5467 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP |
|---|
| 5468 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 5469 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 5470 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL |
|---|
| 5471 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 5472 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 5473 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 5474 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 5475 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 5476 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 5477 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP |
|---|
| 5478 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 5479 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 5480 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL |
|---|
| 5481 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 5482 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 5483 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 5484 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 5485 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 5486 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 5487 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP |
|---|
| 5488 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 5489 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 5490 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL |
|---|
| 5491 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 5492 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 5493 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 5494 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 5495 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 5496 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 5497 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP |
|---|
| 5498 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 5499 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 5500 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL |
|---|
| 5501 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 5502 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 5503 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 5504 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 5505 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 5506 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 5507 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP |
|---|
| 5508 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 5509 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 5510 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL |
|---|
| 5511 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 5512 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 5513 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 5514 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 5515 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 5516 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 5517 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP |
|---|
| 5518 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 5519 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 5520 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL |
|---|
| 5521 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 5522 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 5523 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 5524 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 5525 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 5526 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 5527 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 5528 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5529 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5530 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5531 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5532 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5533 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5534 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 5535 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 5536 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 5537 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA |
|---|
| 5538 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 5539 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 5540 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 5541 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 5542 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 5543 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 5544 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 5545 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 5546 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 5547 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 5548 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 5549 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 5550 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP |
|---|
| 5551 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 5552 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 5553 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST |
|---|
| 5554 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5555 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5556 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5557 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5558 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5559 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5560 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP |
|---|
| 5561 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 5562 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 5563 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 5564 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 5565 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 5566 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 5567 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 5568 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 5569 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 5570 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 5571 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 5572 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 5573 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 5574 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS |
|---|
| 5575 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 5576 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 5577 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 5578 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 5579 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL |
|---|
| 5580 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 5581 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 5582 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 5583 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 5584 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 5585 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 5586 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 5587 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 5588 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 5589 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 5590 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 5591 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 5592 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 5593 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 5594 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 5595 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 5596 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 5597 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 5598 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 5599 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 5600 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 5601 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 5602 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 5603 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 5604 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 5605 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 5606 | //BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 5607 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5608 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5609 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5610 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5611 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5612 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5613 | //BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 |
|---|
| 5614 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 5615 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
|---|
| 5616 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
|---|
| 5617 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 5618 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 5619 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
|---|
| 5620 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS |
|---|
| 5621 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 5622 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
|---|
| 5623 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 5624 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
|---|
| 5625 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 5626 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5627 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5628 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5629 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5630 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5631 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5632 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5633 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5634 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5635 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5636 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL |
|---|
| 5637 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5638 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5639 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5640 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5641 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5642 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5643 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5644 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5645 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5646 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5647 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL |
|---|
| 5648 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5649 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5650 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5651 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5652 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5653 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5654 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5655 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5656 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5657 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5658 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL |
|---|
| 5659 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5660 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5661 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5662 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5663 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5664 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5665 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5666 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5667 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5668 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5669 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL |
|---|
| 5670 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5671 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5672 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5673 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5674 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5675 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5676 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5677 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5678 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5679 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5680 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 5681 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5682 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5683 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5684 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5685 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5686 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5687 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5688 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5689 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5690 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5691 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 5692 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5693 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5694 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5695 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5696 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5697 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5698 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5699 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5700 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5701 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5702 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 5703 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5704 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5705 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5706 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5707 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5708 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5709 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5710 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5711 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5712 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5713 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 5714 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5715 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5716 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5717 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5718 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5719 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5720 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5721 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5722 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5723 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5724 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 5725 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5726 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5727 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5728 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5729 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5730 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5731 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5732 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5733 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5734 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5735 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 5736 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5737 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5738 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5739 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5740 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5741 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5742 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5743 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5744 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5745 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5746 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 5747 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5748 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5749 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5750 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5751 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5752 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5753 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5754 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5755 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5756 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5757 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 5758 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5759 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5760 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5761 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5762 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5763 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5764 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5765 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5766 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5767 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5768 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 5769 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5770 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5771 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5772 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5773 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5774 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5775 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5776 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5777 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5778 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5779 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 5780 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5781 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5782 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5783 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5784 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5785 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5786 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5787 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5788 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5789 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5790 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 5791 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 5792 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 5793 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 5794 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 5795 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 5796 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 5797 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 5798 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 5799 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 5800 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 5801 | //BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST |
|---|
| 5802 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5803 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5804 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5805 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5806 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5807 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5808 | //BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP |
|---|
| 5809 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 5810 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 5811 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 5812 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 5813 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 5814 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 5815 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 5816 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 5817 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 5818 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 5819 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 5820 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 5821 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 5822 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 5823 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 5824 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 5825 | //BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL |
|---|
| 5826 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 5827 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 5828 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 5829 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 5830 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 5831 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 5832 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 5833 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 5834 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 5835 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 5836 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 5837 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 5838 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 5839 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 5840 | //BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 5841 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5842 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5843 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5844 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5845 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5846 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5847 | //BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP |
|---|
| 5848 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 5849 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 5850 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 5851 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 5852 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 5853 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 5854 | //BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL |
|---|
| 5855 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 5856 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 5857 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 5858 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 5859 | //BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST |
|---|
| 5860 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5861 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5862 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5863 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5864 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5865 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5866 | //BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL |
|---|
| 5867 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
|---|
| 5868 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
|---|
| 5869 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
|---|
| 5870 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
|---|
| 5871 | //BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS |
|---|
| 5872 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
|---|
| 5873 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
|---|
| 5874 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
|---|
| 5875 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
|---|
| 5876 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
|---|
| 5877 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
|---|
| 5878 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
|---|
| 5879 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
|---|
| 5880 | //BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
|---|
| 5881 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
|---|
| 5882 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
|---|
| 5883 | //BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
|---|
| 5884 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
|---|
| 5885 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
|---|
| 5886 | //BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST |
|---|
| 5887 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5888 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5889 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5890 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5891 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5892 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5893 | //BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP |
|---|
| 5894 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 5895 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 5896 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 5897 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 5898 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 5899 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 5900 | //BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL |
|---|
| 5901 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 5902 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 5903 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 5904 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 5905 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 5906 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 5907 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST |
|---|
| 5908 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5909 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5910 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5911 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5912 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5913 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5914 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP |
|---|
| 5915 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
|---|
| 5916 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
|---|
| 5917 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
|---|
| 5918 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
|---|
| 5919 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
|---|
| 5920 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
|---|
| 5921 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL |
|---|
| 5922 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
|---|
| 5923 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
|---|
| 5924 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
|---|
| 5925 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
|---|
| 5926 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 |
|---|
| 5927 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
|---|
| 5928 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
|---|
| 5929 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
|---|
| 5930 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
|---|
| 5931 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 |
|---|
| 5932 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
|---|
| 5933 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
|---|
| 5934 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 |
|---|
| 5935 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
|---|
| 5936 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
|---|
| 5937 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 |
|---|
| 5938 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
|---|
| 5939 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
|---|
| 5940 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 |
|---|
| 5941 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
|---|
| 5942 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
|---|
| 5943 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 |
|---|
| 5944 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
|---|
| 5945 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
|---|
| 5946 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
|---|
| 5947 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
|---|
| 5948 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
|---|
| 5949 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
|---|
| 5950 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
|---|
| 5951 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
|---|
| 5952 | //BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST |
|---|
| 5953 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5954 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5955 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5956 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5957 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5958 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5959 | //BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP |
|---|
| 5960 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 5961 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
|---|
| 5962 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 5963 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 5964 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 5965 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 5966 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 5967 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 5968 | //BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 5969 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5970 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5971 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5972 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5973 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5974 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5975 | //BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP |
|---|
| 5976 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 5977 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 5978 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 5979 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 5980 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 5981 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 5982 | //BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL |
|---|
| 5983 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 5984 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 5985 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 5986 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 5987 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 5988 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 5989 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST |
|---|
| 5990 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 5991 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 5992 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 5993 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 5994 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 5995 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 5996 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP |
|---|
| 5997 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
|---|
| 5998 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
|---|
| 5999 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
|---|
| 6000 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
|---|
| 6001 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
|---|
| 6002 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
|---|
| 6003 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
|---|
| 6004 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
|---|
| 6005 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL |
|---|
| 6006 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
|---|
| 6007 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
|---|
| 6008 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
|---|
| 6009 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
|---|
| 6010 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
|---|
| 6011 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
|---|
| 6012 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
|---|
| 6013 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
|---|
| 6014 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
|---|
| 6015 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
|---|
| 6016 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
|---|
| 6017 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
|---|
| 6018 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS |
|---|
| 6019 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
|---|
| 6020 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
|---|
| 6021 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS |
|---|
| 6022 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
|---|
| 6023 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
|---|
| 6024 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS |
|---|
| 6025 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
|---|
| 6026 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
|---|
| 6027 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS |
|---|
| 6028 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
|---|
| 6029 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
|---|
| 6030 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK |
|---|
| 6031 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
|---|
| 6032 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
|---|
| 6033 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET |
|---|
| 6034 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
|---|
| 6035 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
|---|
| 6036 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE |
|---|
| 6037 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
|---|
| 6038 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
|---|
| 6039 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID |
|---|
| 6040 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
|---|
| 6041 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
|---|
| 6042 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
|---|
| 6043 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
|---|
| 6044 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 6045 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
|---|
| 6046 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
|---|
| 6047 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 6048 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 |
|---|
| 6049 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 6050 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 6051 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 |
|---|
| 6052 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 6053 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 6054 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 |
|---|
| 6055 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 6056 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 6057 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 |
|---|
| 6058 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 6059 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 6060 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 |
|---|
| 6061 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 6062 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 6063 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 |
|---|
| 6064 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 6065 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 6066 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
|---|
| 6067 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 |
|---|
| 6068 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
|---|
| 6069 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L |
|---|
| 6070 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 6071 | //BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 6072 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 6073 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 6074 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 6075 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 6076 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 6077 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 6078 | //BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP |
|---|
| 6079 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 6080 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 6081 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 6082 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 6083 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 6084 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 6085 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 6086 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 6087 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 6088 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 6089 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 6090 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 6091 | //BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL |
|---|
| 6092 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 6093 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 6094 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 6095 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 6096 | //BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST |
|---|
| 6097 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 6098 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 6099 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 6100 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 6101 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 6102 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 6103 | //BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP |
|---|
| 6104 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 6105 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
|---|
| 6106 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 6107 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
|---|
| 6108 | //BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS |
|---|
| 6109 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 6110 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
|---|
| 6111 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 6112 | #define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
|---|
| 6113 | //BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST |
|---|
| 6114 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 6115 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 6116 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 6117 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 6118 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 6119 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 6120 | //BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT |
|---|
| 6121 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
|---|
| 6122 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 6123 | //BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT |
|---|
| 6124 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
|---|
| 6125 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 6126 | //BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT |
|---|
| 6127 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
|---|
| 6128 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
|---|
| 6129 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
|---|
| 6130 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
|---|
| 6131 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
|---|
| 6132 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
|---|
| 6133 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
|---|
| 6134 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
|---|
| 6135 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
|---|
| 6136 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
|---|
| 6137 | //BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
|---|
| 6138 | #define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 6139 | #define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 6140 | //BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT |
|---|
| 6141 | #define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 6142 | #define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 6143 | //BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT |
|---|
| 6144 | #define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 6145 | #define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 6146 | //BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT |
|---|
| 6147 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6148 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6149 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6150 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6151 | //BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT |
|---|
| 6152 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6153 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6154 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6155 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6156 | //BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT |
|---|
| 6157 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6158 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6159 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6160 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6161 | //BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT |
|---|
| 6162 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6163 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6164 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6165 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6166 | //BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT |
|---|
| 6167 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6168 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6169 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6170 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6171 | //BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT |
|---|
| 6172 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6173 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6174 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6175 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6176 | //BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT |
|---|
| 6177 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6178 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6179 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6180 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6181 | //BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT |
|---|
| 6182 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6183 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6184 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6185 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6186 | //BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT |
|---|
| 6187 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6188 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6189 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6190 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6191 | //BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT |
|---|
| 6192 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6193 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6194 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6195 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6196 | //BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT |
|---|
| 6197 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6198 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6199 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6200 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6201 | //BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT |
|---|
| 6202 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6203 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6204 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6205 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6206 | //BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT |
|---|
| 6207 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6208 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6209 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6210 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6211 | //BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT |
|---|
| 6212 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6213 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6214 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6215 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6216 | //BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 6217 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6218 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6219 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6220 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6221 | //BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 6222 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 6223 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 6224 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 6225 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 6226 | //BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 6227 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 6228 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 6229 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 6230 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 6231 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 6232 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 6233 | //BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP |
|---|
| 6234 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 6235 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 6236 | //BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS |
|---|
| 6237 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
|---|
| 6238 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
|---|
| 6239 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
|---|
| 6240 | #define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
|---|
| 6241 | //BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL |
|---|
| 6242 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6243 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6244 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6245 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6246 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6247 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6248 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 6249 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6250 | //BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS |
|---|
| 6251 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6252 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6253 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6254 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6255 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6256 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6257 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6258 | #define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6259 | //BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL |
|---|
| 6260 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6261 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6262 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6263 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6264 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6265 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6266 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 6267 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6268 | //BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS |
|---|
| 6269 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6270 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6271 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6272 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6273 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6274 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6275 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6276 | #define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6277 | //BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL |
|---|
| 6278 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6279 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6280 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6281 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6282 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6283 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6284 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 6285 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6286 | //BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS |
|---|
| 6287 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6288 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6289 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6290 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6291 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6292 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6293 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6294 | #define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6295 | //BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL |
|---|
| 6296 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6297 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6298 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6299 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6300 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6301 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6302 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 6303 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6304 | //BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS |
|---|
| 6305 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6306 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6307 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6308 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6309 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6310 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6311 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6312 | #define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6313 | //BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL |
|---|
| 6314 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6315 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6316 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6317 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6318 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6319 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6320 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 6321 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6322 | //BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS |
|---|
| 6323 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6324 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6325 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6326 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6327 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6328 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6329 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6330 | #define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6331 | //BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL |
|---|
| 6332 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6333 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6334 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6335 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6336 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6337 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6338 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 6339 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6340 | //BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS |
|---|
| 6341 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6342 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6343 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6344 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6345 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6346 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6347 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6348 | #define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6349 | //BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL |
|---|
| 6350 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6351 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6352 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6353 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6354 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6355 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6356 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 6357 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6358 | //BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS |
|---|
| 6359 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6360 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6361 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6362 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6363 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6364 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6365 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6366 | #define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6367 | //BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL |
|---|
| 6368 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6369 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6370 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6371 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6372 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6373 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6374 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 6375 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6376 | //BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS |
|---|
| 6377 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6378 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6379 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6380 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6381 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6382 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6383 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6384 | #define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6385 | //BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL |
|---|
| 6386 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6387 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6388 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6389 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6390 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6391 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6392 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 6393 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6394 | //BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS |
|---|
| 6395 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6396 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6397 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6398 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6399 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6400 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6401 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6402 | #define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6403 | //BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL |
|---|
| 6404 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6405 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6406 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6407 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6408 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6409 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6410 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 6411 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6412 | //BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS |
|---|
| 6413 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6414 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6415 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6416 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6417 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6418 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6419 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6420 | #define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6421 | //BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL |
|---|
| 6422 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6423 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6424 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6425 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6426 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6427 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6428 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 6429 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6430 | //BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS |
|---|
| 6431 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6432 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6433 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6434 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6435 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6436 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6437 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6438 | #define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6439 | //BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL |
|---|
| 6440 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6441 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6442 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6443 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6444 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6445 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6446 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 6447 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6448 | //BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS |
|---|
| 6449 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6450 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6451 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6452 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6453 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6454 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6455 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6456 | #define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6457 | //BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL |
|---|
| 6458 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6459 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6460 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6461 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6462 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6463 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6464 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 6465 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6466 | //BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS |
|---|
| 6467 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6468 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6469 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6470 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6471 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6472 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6473 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6474 | #define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6475 | //BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL |
|---|
| 6476 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6477 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6478 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6479 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6480 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6481 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6482 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 6483 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6484 | //BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS |
|---|
| 6485 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6486 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6487 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6488 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6489 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6490 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6491 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6492 | #define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6493 | //BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL |
|---|
| 6494 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6495 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6496 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6497 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6498 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6499 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6500 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 6501 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6502 | //BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS |
|---|
| 6503 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6504 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6505 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6506 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6507 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6508 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6509 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6510 | #define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6511 | //BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL |
|---|
| 6512 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 6513 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 6514 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 6515 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 6516 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 6517 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 6518 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 6519 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 6520 | //BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS |
|---|
| 6521 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 6522 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 6523 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 6524 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 6525 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 6526 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 6527 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 6528 | #define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 6529 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
|---|
| 6530 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 6531 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 6532 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 6533 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 6534 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 6535 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 6536 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP |
|---|
| 6537 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 6538 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 6539 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL |
|---|
| 6540 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 6541 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 6542 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 6543 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 6544 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 6545 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 6546 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP |
|---|
| 6547 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 6548 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 6549 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL |
|---|
| 6550 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 6551 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 6552 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 6553 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 6554 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 6555 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 6556 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP |
|---|
| 6557 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 6558 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 6559 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL |
|---|
| 6560 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 6561 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 6562 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 6563 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 6564 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 6565 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 6566 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP |
|---|
| 6567 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 6568 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 6569 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL |
|---|
| 6570 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 6571 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 6572 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 6573 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 6574 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 6575 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 6576 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP |
|---|
| 6577 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 6578 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 6579 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL |
|---|
| 6580 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 6581 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 6582 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 6583 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 6584 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 6585 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 6586 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP |
|---|
| 6587 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 6588 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 6589 | //BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL |
|---|
| 6590 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 6591 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 6592 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 6593 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 6594 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 6595 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 6596 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
|---|
| 6597 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
|---|
| 6598 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
|---|
| 6599 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
|---|
| 6600 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
|---|
| 6601 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
|---|
| 6602 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 6603 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
|---|
| 6604 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
|---|
| 6605 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
|---|
| 6606 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 6607 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 6608 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
|---|
| 6609 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 6610 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
|---|
| 6611 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
|---|
| 6612 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
|---|
| 6613 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
|---|
| 6614 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
|---|
| 6615 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
|---|
| 6616 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
|---|
| 6617 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
|---|
| 6618 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
|---|
| 6619 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
|---|
| 6620 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
|---|
| 6621 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
|---|
| 6622 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
|---|
| 6623 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
|---|
| 6624 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc |
|---|
| 6625 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd |
|---|
| 6626 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe |
|---|
| 6627 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf |
|---|
| 6628 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
|---|
| 6629 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
|---|
| 6630 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
|---|
| 6631 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
|---|
| 6632 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
|---|
| 6633 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
|---|
| 6634 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
|---|
| 6635 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
|---|
| 6636 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
|---|
| 6637 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
|---|
| 6638 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
|---|
| 6639 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
|---|
| 6640 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
|---|
| 6641 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
|---|
| 6642 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L |
|---|
| 6643 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L |
|---|
| 6644 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L |
|---|
| 6645 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L |
|---|
| 6646 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
|---|
| 6647 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
|---|
| 6648 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
|---|
| 6649 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
|---|
| 6650 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
|---|
| 6651 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
|---|
| 6652 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
|---|
| 6653 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
|---|
| 6654 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
|---|
| 6655 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
|---|
| 6656 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
|---|
| 6657 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
|---|
| 6658 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
|---|
| 6659 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
|---|
| 6660 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
|---|
| 6661 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc |
|---|
| 6662 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd |
|---|
| 6663 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe |
|---|
| 6664 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf |
|---|
| 6665 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
|---|
| 6666 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
|---|
| 6667 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
|---|
| 6668 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
|---|
| 6669 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
|---|
| 6670 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
|---|
| 6671 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
|---|
| 6672 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
|---|
| 6673 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
|---|
| 6674 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
|---|
| 6675 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
|---|
| 6676 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
|---|
| 6677 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
|---|
| 6678 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
|---|
| 6679 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L |
|---|
| 6680 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L |
|---|
| 6681 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L |
|---|
| 6682 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L |
|---|
| 6683 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
|---|
| 6684 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
|---|
| 6685 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
|---|
| 6686 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
|---|
| 6687 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
|---|
| 6688 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
|---|
| 6689 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
|---|
| 6690 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
|---|
| 6691 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
|---|
| 6692 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
|---|
| 6693 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
|---|
| 6694 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 6695 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
|---|
| 6696 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 6697 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
|---|
| 6698 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
|---|
| 6699 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 6700 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 6701 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 6702 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
|---|
| 6703 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
|---|
| 6704 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
|---|
| 6705 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
|---|
| 6706 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
|---|
| 6707 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
|---|
| 6708 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
|---|
| 6709 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
|---|
| 6710 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
|---|
| 6711 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
|---|
| 6712 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
|---|
| 6713 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
|---|
| 6714 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
|---|
| 6715 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
|---|
| 6716 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
|---|
| 6717 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
|---|
| 6718 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
|---|
| 6719 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
|---|
| 6720 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
|---|
| 6721 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
|---|
| 6722 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
|---|
| 6723 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
|---|
| 6724 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
|---|
| 6725 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
|---|
| 6726 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
|---|
| 6727 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
|---|
| 6728 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
|---|
| 6729 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
|---|
| 6730 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
|---|
| 6731 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
|---|
| 6732 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
|---|
| 6733 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
|---|
| 6734 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
|---|
| 6735 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
|---|
| 6736 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
|---|
| 6737 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
|---|
| 6738 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
|---|
| 6739 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
|---|
| 6740 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
|---|
| 6741 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
|---|
| 6742 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
|---|
| 6743 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
|---|
| 6744 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
|---|
| 6745 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
|---|
| 6746 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
|---|
| 6747 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
|---|
| 6748 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
|---|
| 6749 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
|---|
| 6750 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
|---|
| 6751 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
|---|
| 6752 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
|---|
| 6753 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
|---|
| 6754 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
|---|
| 6755 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
|---|
| 6756 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
|---|
| 6757 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
|---|
| 6758 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
|---|
| 6759 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
|---|
| 6760 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
|---|
| 6761 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
|---|
| 6762 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
|---|
| 6763 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
|---|
| 6764 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
|---|
| 6765 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
|---|
| 6766 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
|---|
| 6767 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
|---|
| 6768 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
|---|
| 6769 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 |
|---|
| 6770 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 |
|---|
| 6771 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 |
|---|
| 6772 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 |
|---|
| 6773 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 |
|---|
| 6774 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 |
|---|
| 6775 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 |
|---|
| 6776 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 |
|---|
| 6777 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 |
|---|
| 6778 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 |
|---|
| 6779 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa |
|---|
| 6780 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb |
|---|
| 6781 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc |
|---|
| 6782 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd |
|---|
| 6783 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe |
|---|
| 6784 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf |
|---|
| 6785 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 |
|---|
| 6786 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 |
|---|
| 6787 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 |
|---|
| 6788 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 |
|---|
| 6789 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 |
|---|
| 6790 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 |
|---|
| 6791 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 |
|---|
| 6792 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 |
|---|
| 6793 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 |
|---|
| 6794 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 |
|---|
| 6795 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a |
|---|
| 6796 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b |
|---|
| 6797 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c |
|---|
| 6798 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d |
|---|
| 6799 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e |
|---|
| 6800 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f |
|---|
| 6801 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L |
|---|
| 6802 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L |
|---|
| 6803 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L |
|---|
| 6804 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L |
|---|
| 6805 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L |
|---|
| 6806 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L |
|---|
| 6807 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L |
|---|
| 6808 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L |
|---|
| 6809 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L |
|---|
| 6810 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L |
|---|
| 6811 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L |
|---|
| 6812 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L |
|---|
| 6813 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L |
|---|
| 6814 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L |
|---|
| 6815 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L |
|---|
| 6816 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L |
|---|
| 6817 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L |
|---|
| 6818 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L |
|---|
| 6819 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L |
|---|
| 6820 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L |
|---|
| 6821 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L |
|---|
| 6822 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L |
|---|
| 6823 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L |
|---|
| 6824 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L |
|---|
| 6825 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L |
|---|
| 6826 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L |
|---|
| 6827 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L |
|---|
| 6828 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L |
|---|
| 6829 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L |
|---|
| 6830 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L |
|---|
| 6831 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L |
|---|
| 6832 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L |
|---|
| 6833 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
|---|
| 6834 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
|---|
| 6835 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
|---|
| 6836 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
|---|
| 6837 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
|---|
| 6838 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
|---|
| 6839 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
|---|
| 6840 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
|---|
| 6841 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
|---|
| 6842 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
|---|
| 6843 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
|---|
| 6844 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
|---|
| 6845 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
|---|
| 6846 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
|---|
| 6847 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
|---|
| 6848 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
|---|
| 6849 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18 |
|---|
| 6850 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
|---|
| 6851 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
|---|
| 6852 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
|---|
| 6853 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L |
|---|
| 6854 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION |
|---|
| 6855 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 |
|---|
| 6856 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 |
|---|
| 6857 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L |
|---|
| 6858 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L |
|---|
| 6859 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE |
|---|
| 6860 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 |
|---|
| 6861 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f |
|---|
| 6862 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL |
|---|
| 6863 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L |
|---|
| 6864 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
|---|
| 6865 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
|---|
| 6866 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
|---|
| 6867 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6868 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6869 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
|---|
| 6870 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
|---|
| 6871 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
|---|
| 6872 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6873 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6874 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
|---|
| 6875 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
|---|
| 6876 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
|---|
| 6877 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6878 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6879 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
|---|
| 6880 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
|---|
| 6881 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
|---|
| 6882 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6883 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6884 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
|---|
| 6885 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
|---|
| 6886 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
|---|
| 6887 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6888 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6889 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
|---|
| 6890 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
|---|
| 6891 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
|---|
| 6892 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6893 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6894 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
|---|
| 6895 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
|---|
| 6896 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
|---|
| 6897 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6898 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6899 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
|---|
| 6900 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
|---|
| 6901 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
|---|
| 6902 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6903 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6904 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
|---|
| 6905 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
|---|
| 6906 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
|---|
| 6907 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6908 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6909 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
|---|
| 6910 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
|---|
| 6911 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
|---|
| 6912 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6913 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6914 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
|---|
| 6915 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
|---|
| 6916 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
|---|
| 6917 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6918 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6919 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
|---|
| 6920 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
|---|
| 6921 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
|---|
| 6922 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6923 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6924 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
|---|
| 6925 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
|---|
| 6926 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
|---|
| 6927 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6928 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6929 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
|---|
| 6930 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
|---|
| 6931 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
|---|
| 6932 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6933 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6934 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
|---|
| 6935 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
|---|
| 6936 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
|---|
| 6937 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6938 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6939 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
|---|
| 6940 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
|---|
| 6941 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
|---|
| 6942 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6943 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6944 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB |
|---|
| 6945 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0 |
|---|
| 6946 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10 |
|---|
| 6947 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6948 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6949 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB |
|---|
| 6950 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0 |
|---|
| 6951 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10 |
|---|
| 6952 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6953 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6954 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB |
|---|
| 6955 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0 |
|---|
| 6956 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10 |
|---|
| 6957 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6958 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6959 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB |
|---|
| 6960 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0 |
|---|
| 6961 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10 |
|---|
| 6962 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6963 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6964 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB |
|---|
| 6965 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0 |
|---|
| 6966 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10 |
|---|
| 6967 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6968 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6969 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB |
|---|
| 6970 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0 |
|---|
| 6971 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10 |
|---|
| 6972 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6973 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6974 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB |
|---|
| 6975 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0 |
|---|
| 6976 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10 |
|---|
| 6977 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6978 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6979 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB |
|---|
| 6980 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0 |
|---|
| 6981 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10 |
|---|
| 6982 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6983 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6984 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB |
|---|
| 6985 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0 |
|---|
| 6986 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10 |
|---|
| 6987 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6988 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6989 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB |
|---|
| 6990 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0 |
|---|
| 6991 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10 |
|---|
| 6992 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6993 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6994 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB |
|---|
| 6995 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0 |
|---|
| 6996 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10 |
|---|
| 6997 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 6998 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 6999 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB |
|---|
| 7000 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0 |
|---|
| 7001 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10 |
|---|
| 7002 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 7003 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 7004 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB |
|---|
| 7005 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0 |
|---|
| 7006 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10 |
|---|
| 7007 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 7008 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 7009 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB |
|---|
| 7010 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0 |
|---|
| 7011 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10 |
|---|
| 7012 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 7013 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 7014 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB |
|---|
| 7015 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0 |
|---|
| 7016 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10 |
|---|
| 7017 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 7018 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 7019 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
|---|
| 7020 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 7021 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 7022 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
|---|
| 7023 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 7024 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 7025 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
|---|
| 7026 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 7027 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 7028 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
|---|
| 7029 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 7030 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 7031 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
|---|
| 7032 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 7033 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 7034 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
|---|
| 7035 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 7036 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 7037 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
|---|
| 7038 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 7039 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 7040 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
|---|
| 7041 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 7042 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 7043 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
|---|
| 7044 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 7045 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 7046 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
|---|
| 7047 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
|---|
| 7048 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 7049 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
|---|
| 7050 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
|---|
| 7051 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 7052 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
|---|
| 7053 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
|---|
| 7054 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 7055 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
|---|
| 7056 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
|---|
| 7057 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 7058 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
|---|
| 7059 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
|---|
| 7060 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 7061 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
|---|
| 7062 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
|---|
| 7063 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 7064 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
|---|
| 7065 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
|---|
| 7066 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 7067 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
|---|
| 7068 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
|---|
| 7069 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 7070 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
|---|
| 7071 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
|---|
| 7072 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 7073 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
|---|
| 7074 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 7075 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 7076 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
|---|
| 7077 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 7078 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 7079 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
|---|
| 7080 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 7081 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 7082 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
|---|
| 7083 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 7084 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 7085 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
|---|
| 7086 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 7087 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 7088 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
|---|
| 7089 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 7090 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 7091 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
|---|
| 7092 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 7093 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 7094 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
|---|
| 7095 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 7096 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 7097 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
|---|
| 7098 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 7099 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 7100 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 |
|---|
| 7101 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0 |
|---|
| 7102 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 7103 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 |
|---|
| 7104 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0 |
|---|
| 7105 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 7106 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 |
|---|
| 7107 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0 |
|---|
| 7108 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 7109 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 |
|---|
| 7110 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0 |
|---|
| 7111 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 7112 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 |
|---|
| 7113 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0 |
|---|
| 7114 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 7115 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 |
|---|
| 7116 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0 |
|---|
| 7117 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 7118 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 |
|---|
| 7119 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0 |
|---|
| 7120 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 7121 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 |
|---|
| 7122 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0 |
|---|
| 7123 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 7124 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 |
|---|
| 7125 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0 |
|---|
| 7126 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 7127 | |
|---|
| 7128 | |
|---|
| 7129 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
|---|
| 7130 | //BIF_CFG_DEV0_EPF1_0_VENDOR_ID |
|---|
| 7131 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 7132 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 7133 | //BIF_CFG_DEV0_EPF1_0_DEVICE_ID |
|---|
| 7134 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 7135 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 7136 | //BIF_CFG_DEV0_EPF1_0_COMMAND |
|---|
| 7137 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 7138 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 7139 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 7140 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 7141 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 7142 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 7143 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 7144 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 7145 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 7146 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 7147 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 7148 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 7149 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 7150 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 7151 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 7152 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 7153 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 7154 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 7155 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 7156 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 7157 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 7158 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 7159 | //BIF_CFG_DEV0_EPF1_0_STATUS |
|---|
| 7160 | #define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 7161 | #define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 7162 | #define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 7163 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 7164 | #define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 7165 | #define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 7166 | #define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 7167 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 7168 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 7169 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 7170 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 7171 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 7172 | #define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 7173 | #define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 7174 | #define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 7175 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 7176 | #define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 7177 | #define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 7178 | #define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 7179 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 7180 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 7181 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 7182 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 7183 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 7184 | //BIF_CFG_DEV0_EPF1_0_REVISION_ID |
|---|
| 7185 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 7186 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 7187 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 7188 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 7189 | //BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE |
|---|
| 7190 | #define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 7191 | #define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 7192 | //BIF_CFG_DEV0_EPF1_0_SUB_CLASS |
|---|
| 7193 | #define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 7194 | #define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 7195 | //BIF_CFG_DEV0_EPF1_0_BASE_CLASS |
|---|
| 7196 | #define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 7197 | #define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 7198 | //BIF_CFG_DEV0_EPF1_0_CACHE_LINE |
|---|
| 7199 | #define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 7200 | #define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 7201 | //BIF_CFG_DEV0_EPF1_0_LATENCY |
|---|
| 7202 | #define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 7203 | #define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 7204 | //BIF_CFG_DEV0_EPF1_0_HEADER |
|---|
| 7205 | #define 0x0 |
|---|
| 7206 | #define 0x7 |
|---|
| 7207 | #define 0x7FL |
|---|
| 7208 | #define 0x80L |
|---|
| 7209 | //BIF_CFG_DEV0_EPF1_0_BIST |
|---|
| 7210 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 7211 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 7212 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 7213 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 7214 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 7215 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 7216 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 |
|---|
| 7217 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 7218 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 7219 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 |
|---|
| 7220 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 7221 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 7222 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 |
|---|
| 7223 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 7224 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 7225 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 |
|---|
| 7226 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 7227 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 7228 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 |
|---|
| 7229 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 7230 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 7231 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 |
|---|
| 7232 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 7233 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 7234 | //BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR |
|---|
| 7235 | #define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 7236 | #define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 7237 | //BIF_CFG_DEV0_EPF1_0_ADAPTER_ID |
|---|
| 7238 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 7239 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 7240 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 7241 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 7242 | //BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR |
|---|
| 7243 | #define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 7244 | #define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 7245 | //BIF_CFG_DEV0_EPF1_0_CAP_PTR |
|---|
| 7246 | #define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 7247 | #define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 7248 | //BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE |
|---|
| 7249 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 7250 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 7251 | //BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN |
|---|
| 7252 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 7253 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 7254 | //BIF_CFG_DEV0_EPF1_0_MIN_GRANT |
|---|
| 7255 | #define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 7256 | #define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 7257 | //BIF_CFG_DEV0_EPF1_0_MAX_LATENCY |
|---|
| 7258 | #define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 7259 | #define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 7260 | //BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST |
|---|
| 7261 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 7262 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 7263 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 7264 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 7265 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 7266 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 7267 | //BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W |
|---|
| 7268 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 7269 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 7270 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 7271 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 7272 | //BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST |
|---|
| 7273 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 7274 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 7275 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 7276 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 7277 | //BIF_CFG_DEV0_EPF1_0_PMI_CAP |
|---|
| 7278 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 7279 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 7280 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 7281 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 7282 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 7283 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 7284 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 7285 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 7286 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 7287 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 7288 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 7289 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 7290 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 7291 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 7292 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 7293 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 7294 | //BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL |
|---|
| 7295 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 7296 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 7297 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 7298 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 7299 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 7300 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 7301 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 7302 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 7303 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 7304 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 7305 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 7306 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 7307 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 7308 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 7309 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 7310 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 7311 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 7312 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 7313 | //BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST |
|---|
| 7314 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 7315 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 7316 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 7317 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 7318 | //BIF_CFG_DEV0_EPF1_0_PCIE_CAP |
|---|
| 7319 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 7320 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 7321 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 7322 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 7323 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 7324 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 7325 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 7326 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 7327 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CAP |
|---|
| 7328 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 7329 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 7330 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 7331 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 7332 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 7333 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 7334 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 7335 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 7336 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 7337 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 7338 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 7339 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 7340 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 7341 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 7342 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 7343 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 7344 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 7345 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 7346 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL |
|---|
| 7347 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 7348 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 7349 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 7350 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 7351 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 7352 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 7353 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 7354 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 7355 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 7356 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 7357 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 7358 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 7359 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 7360 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 7361 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 7362 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 7363 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 7364 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 7365 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 7366 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 7367 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 7368 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 7369 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 7370 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 7371 | //BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS |
|---|
| 7372 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 7373 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 7374 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 7375 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 7376 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 7377 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 7378 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 7379 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 7380 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 7381 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 7382 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 7383 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 7384 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 7385 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 7386 | //BIF_CFG_DEV0_EPF1_0_LINK_CAP |
|---|
| 7387 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 7388 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 7389 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 7390 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 7391 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 7392 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 7393 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 7394 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 7395 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 7396 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 7397 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 7398 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 7399 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 7400 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 7401 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 7402 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 7403 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 7404 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 7405 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 7406 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 7407 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 7408 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 7409 | //BIF_CFG_DEV0_EPF1_0_LINK_CNTL |
|---|
| 7410 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 7411 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 7412 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 7413 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 7414 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 7415 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 7416 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 7417 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 7418 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 7419 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 7420 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 7421 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 7422 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 7423 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 7424 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 7425 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 7426 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 7427 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 7428 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 7429 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 7430 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 7431 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 7432 | //BIF_CFG_DEV0_EPF1_0_LINK_STATUS |
|---|
| 7433 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 7434 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 7435 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 7436 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 7437 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 7438 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 7439 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 7440 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 7441 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 7442 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 7443 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 7444 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 7445 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 7446 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 7447 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 |
|---|
| 7448 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 7449 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 7450 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 7451 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 7452 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 7453 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 7454 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 7455 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 7456 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 7457 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 7458 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 7459 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 7460 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 7461 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 7462 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 7463 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 7464 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 7465 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 7466 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 7467 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 7468 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 7469 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 7470 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 7471 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 7472 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 7473 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 7474 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 7475 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 7476 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 7477 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 7478 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 7479 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 7480 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 7481 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 7482 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 7483 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 7484 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 7485 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 7486 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 7487 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 7488 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 |
|---|
| 7489 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 7490 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 7491 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 7492 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 7493 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 7494 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 7495 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 7496 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 7497 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 7498 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 7499 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 7500 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 7501 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 7502 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 7503 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 7504 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 7505 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 7506 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 7507 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 7508 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 7509 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 7510 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 7511 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 7512 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 7513 | //BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 |
|---|
| 7514 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 7515 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 7516 | //BIF_CFG_DEV0_EPF1_0_LINK_CAP2 |
|---|
| 7517 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 7518 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 7519 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 7520 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 7521 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 7522 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 7523 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 7524 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 7525 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 7526 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 7527 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 7528 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 7529 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 7530 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 7531 | //BIF_CFG_DEV0_EPF1_0_LINK_CNTL2 |
|---|
| 7532 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 7533 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 7534 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 7535 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 7536 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 7537 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 7538 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 7539 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 7540 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 7541 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 7542 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 7543 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 7544 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 7545 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 7546 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 7547 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 7548 | //BIF_CFG_DEV0_EPF1_0_LINK_STATUS2 |
|---|
| 7549 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 7550 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 7551 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 7552 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 7553 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 7554 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 7555 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 7556 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 7557 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 7558 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 7559 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 7560 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 7561 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 7562 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 7563 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 7564 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 7565 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 7566 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 7567 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 7568 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 7569 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 7570 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 7571 | //BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST |
|---|
| 7572 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 7573 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 7574 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 7575 | #define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 7576 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL |
|---|
| 7577 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 7578 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 7579 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 7580 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 7581 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 7582 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 7583 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 7584 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 7585 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 7586 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 7587 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO |
|---|
| 7588 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 7589 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 7590 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI |
|---|
| 7591 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 7592 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 7593 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA |
|---|
| 7594 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 7595 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 7596 | //BIF_CFG_DEV0_EPF1_0_MSI_MASK |
|---|
| 7597 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 7598 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 7599 | //BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 |
|---|
| 7600 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 7601 | #define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 7602 | //BIF_CFG_DEV0_EPF1_0_MSI_MASK_64 |
|---|
| 7603 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 7604 | #define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 7605 | //BIF_CFG_DEV0_EPF1_0_MSI_PENDING |
|---|
| 7606 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 7607 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 7608 | //BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 |
|---|
| 7609 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 7610 | #define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 7611 | //BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST |
|---|
| 7612 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 7613 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 7614 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 7615 | #define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 7616 | //BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL |
|---|
| 7617 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 7618 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 7619 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 7620 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 7621 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 7622 | #define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 7623 | //BIF_CFG_DEV0_EPF1_0_MSIX_TABLE |
|---|
| 7624 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 7625 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 7626 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 7627 | #define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 7628 | //BIF_CFG_DEV0_EPF1_0_MSIX_PBA |
|---|
| 7629 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 7630 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 7631 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 7632 | #define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 7633 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 7634 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 7635 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 7636 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 7637 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 7638 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 7639 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 7640 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 7641 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 7642 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 7643 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 7644 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 7645 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 7646 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 7647 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 7648 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 7649 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 7650 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 7651 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 7652 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 7653 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST |
|---|
| 7654 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 7655 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 7656 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 7657 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 7658 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 7659 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 7660 | //BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 |
|---|
| 7661 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 7662 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 7663 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 7664 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 7665 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 7666 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 7667 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 7668 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 7669 | //BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 |
|---|
| 7670 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 7671 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 7672 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 7673 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 7674 | //BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL |
|---|
| 7675 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 7676 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 7677 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 7678 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 7679 | //BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS |
|---|
| 7680 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 7681 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 7682 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP |
|---|
| 7683 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 7684 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 7685 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 7686 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 7687 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 7688 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 7689 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 7690 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 7691 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL |
|---|
| 7692 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 7693 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 7694 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 7695 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 7696 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 7697 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 7698 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 7699 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 7700 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 7701 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 7702 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 7703 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 7704 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS |
|---|
| 7705 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 7706 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 7707 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 7708 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 7709 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP |
|---|
| 7710 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 7711 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 7712 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 7713 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 7714 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 7715 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 7716 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 7717 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 7718 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL |
|---|
| 7719 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 7720 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 7721 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 7722 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 7723 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 7724 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 7725 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 7726 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 7727 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 7728 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 7729 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 7730 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 7731 | //BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS |
|---|
| 7732 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 7733 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 7734 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 7735 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 7736 | //BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 7737 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 7738 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 7739 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 7740 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 7741 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 7742 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 7743 | //BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 7744 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 7745 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 7746 | //BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 7747 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 7748 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 7749 | //BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 7750 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 7751 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 7752 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 7753 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 7754 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 7755 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 7756 | //BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 7757 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 7758 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 7759 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 7760 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 7761 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 7762 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 7763 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 7764 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 7765 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 7766 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 7767 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 7768 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 7769 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 7770 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 7771 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 7772 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 7773 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 7774 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 7775 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 7776 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 7777 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 7778 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 7779 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 7780 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 7781 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 7782 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 7783 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 7784 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 7785 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 7786 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 7787 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 7788 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 7789 | //BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK |
|---|
| 7790 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 7791 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 7792 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 7793 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 7794 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 7795 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 7796 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 7797 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 7798 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 7799 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 7800 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 7801 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 7802 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 7803 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 7804 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 7805 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 7806 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 7807 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 7808 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 7809 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 7810 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 7811 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 7812 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 7813 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 7814 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 7815 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 7816 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 7817 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 7818 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 7819 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 7820 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 7821 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 7822 | //BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 7823 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 7824 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 7825 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 7826 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 7827 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 7828 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 7829 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 7830 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 7831 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 7832 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 7833 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 7834 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 7835 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 7836 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 7837 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 7838 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 7839 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 7840 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 7841 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 7842 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 7843 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 7844 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 7845 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 7846 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 7847 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 7848 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 7849 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 7850 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 7851 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 7852 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 7853 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 7854 | #define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 7855 | //BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS |
|---|
| 7856 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 7857 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 7858 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 7859 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 7860 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 7861 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 7862 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 7863 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 7864 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 7865 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 7866 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 7867 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 7868 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 7869 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 7870 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 7871 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 7872 | //BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK |
|---|
| 7873 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 7874 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 7875 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 7876 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 7877 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 7878 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 7879 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 7880 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 7881 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 7882 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 7883 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 7884 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 7885 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 7886 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 7887 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 7888 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 7889 | //BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 7890 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 7891 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 7892 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 7893 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 7894 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 7895 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 7896 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 7897 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 7898 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 7899 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 7900 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 7901 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 7902 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 7903 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 7904 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 7905 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 7906 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 7907 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 7908 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 |
|---|
| 7909 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 7910 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 7911 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 |
|---|
| 7912 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 7913 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 7914 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 |
|---|
| 7915 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 7916 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 7917 | //BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 |
|---|
| 7918 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 7919 | #define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 7920 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 7921 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 7922 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 7923 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 7924 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 7925 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 7926 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 7927 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 7928 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 7929 | //BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 7930 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 7931 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 7932 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST |
|---|
| 7933 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 7934 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 7935 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 7936 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 7937 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 7938 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 7939 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP |
|---|
| 7940 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 7941 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 7942 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL |
|---|
| 7943 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 7944 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 7945 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 7946 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 7947 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 7948 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 7949 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP |
|---|
| 7950 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 7951 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 7952 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL |
|---|
| 7953 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 7954 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 7955 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 7956 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 7957 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 7958 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 7959 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP |
|---|
| 7960 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 7961 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 7962 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL |
|---|
| 7963 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 7964 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 7965 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 7966 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 7967 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 7968 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 7969 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP |
|---|
| 7970 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 7971 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 7972 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL |
|---|
| 7973 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 7974 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 7975 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 7976 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 7977 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 7978 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 7979 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP |
|---|
| 7980 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 7981 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 7982 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL |
|---|
| 7983 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 7984 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 7985 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 7986 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 7987 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 7988 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 7989 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP |
|---|
| 7990 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 7991 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 7992 | //BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL |
|---|
| 7993 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 7994 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 7995 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 7996 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 7997 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 7998 | #define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 7999 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 8000 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8001 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8002 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8003 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8004 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8005 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8006 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 8007 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 8008 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 8009 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA |
|---|
| 8010 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 8011 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 8012 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 8013 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 8014 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 8015 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 8016 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 8017 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 8018 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 8019 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 8020 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 8021 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 8022 | //BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP |
|---|
| 8023 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 8024 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 8025 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST |
|---|
| 8026 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8027 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8028 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8029 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8030 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8031 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8032 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP |
|---|
| 8033 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 8034 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 8035 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 8036 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 8037 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 8038 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 8039 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 8040 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 8041 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 8042 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 8043 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 8044 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 8045 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 8046 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS |
|---|
| 8047 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 8048 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 8049 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 8050 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 8051 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL |
|---|
| 8052 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 8053 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 8054 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 8055 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 8056 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 8057 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 8058 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 8059 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 8060 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 8061 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 8062 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 8063 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 8064 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 8065 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 8066 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 8067 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 8068 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 8069 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 8070 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 8071 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 8072 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 8073 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 8074 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 8075 | //BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 8076 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 8077 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 8078 | //BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 8079 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8080 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8081 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8082 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8083 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8084 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8085 | //BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 |
|---|
| 8086 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 8087 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
|---|
| 8088 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
|---|
| 8089 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 8090 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 8091 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
|---|
| 8092 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS |
|---|
| 8093 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 8094 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
|---|
| 8095 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 8096 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
|---|
| 8097 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 8098 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8099 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8100 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8101 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8102 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8103 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8104 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8105 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8106 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8107 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8108 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL |
|---|
| 8109 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8110 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8111 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8112 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8113 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8114 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8115 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8116 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8117 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8118 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8119 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL |
|---|
| 8120 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8121 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8122 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8123 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8124 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8125 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8126 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8127 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8128 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8129 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8130 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL |
|---|
| 8131 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8132 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8133 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8134 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8135 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8136 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8137 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8138 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8139 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8140 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8141 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL |
|---|
| 8142 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8143 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8144 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8145 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8146 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8147 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8148 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8149 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8150 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8151 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8152 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 8153 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8154 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8155 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8156 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8157 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8158 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8159 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8160 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8161 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8162 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8163 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 8164 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8165 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8166 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8167 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8168 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8169 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8170 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8171 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8172 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8173 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8174 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 8175 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8176 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8177 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8178 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8179 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8180 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8181 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8182 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8183 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8184 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8185 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 8186 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8187 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8188 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8189 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8190 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8191 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8192 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8193 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8194 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8195 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8196 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 8197 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8198 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8199 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8200 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8201 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8202 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8203 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8204 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8205 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8206 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8207 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 8208 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8209 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8210 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8211 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8212 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8213 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8214 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8215 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8216 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8217 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8218 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 8219 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8220 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8221 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8222 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8223 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8224 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8225 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8226 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8227 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8228 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8229 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 8230 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8231 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8232 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8233 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8234 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8235 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8236 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8237 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8238 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8239 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8240 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 8241 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8242 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8243 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8244 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8245 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8246 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8247 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8248 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8249 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8250 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8251 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 8252 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8253 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8254 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8255 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8256 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8257 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8258 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8259 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8260 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8261 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8262 | //BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 8263 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 8264 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 8265 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 8266 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 8267 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 8268 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 8269 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 8270 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 8271 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 8272 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 8273 | //BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST |
|---|
| 8274 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8275 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8276 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8277 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8278 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8279 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8280 | //BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP |
|---|
| 8281 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 8282 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 8283 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 8284 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 8285 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 8286 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 8287 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 8288 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 8289 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 8290 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 8291 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 8292 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 8293 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 8294 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 8295 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 8296 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 8297 | //BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL |
|---|
| 8298 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 8299 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 8300 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 8301 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 8302 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 8303 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 8304 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 8305 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 8306 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 8307 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 8308 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 8309 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 8310 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 8311 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 8312 | //BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 8313 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8314 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8315 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8316 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8317 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8318 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8319 | //BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP |
|---|
| 8320 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 8321 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 8322 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 8323 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 8324 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 8325 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 8326 | //BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL |
|---|
| 8327 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 8328 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 8329 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 8330 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 8331 | //BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST |
|---|
| 8332 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8333 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8334 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8335 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8336 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8337 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8338 | //BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL |
|---|
| 8339 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
|---|
| 8340 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
|---|
| 8341 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
|---|
| 8342 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
|---|
| 8343 | //BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS |
|---|
| 8344 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
|---|
| 8345 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
|---|
| 8346 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
|---|
| 8347 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
|---|
| 8348 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
|---|
| 8349 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
|---|
| 8350 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
|---|
| 8351 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
|---|
| 8352 | //BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
|---|
| 8353 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
|---|
| 8354 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
|---|
| 8355 | //BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
|---|
| 8356 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
|---|
| 8357 | #define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
|---|
| 8358 | //BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST |
|---|
| 8359 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8360 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8361 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8362 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8363 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8364 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8365 | //BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP |
|---|
| 8366 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 8367 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 8368 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 8369 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 8370 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 8371 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 8372 | //BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL |
|---|
| 8373 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 8374 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 8375 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 8376 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 8377 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 8378 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 8379 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST |
|---|
| 8380 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8381 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8382 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8383 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8384 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8385 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8386 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP |
|---|
| 8387 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
|---|
| 8388 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
|---|
| 8389 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
|---|
| 8390 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
|---|
| 8391 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
|---|
| 8392 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
|---|
| 8393 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL |
|---|
| 8394 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
|---|
| 8395 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
|---|
| 8396 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
|---|
| 8397 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
|---|
| 8398 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 |
|---|
| 8399 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
|---|
| 8400 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
|---|
| 8401 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
|---|
| 8402 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
|---|
| 8403 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 |
|---|
| 8404 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
|---|
| 8405 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
|---|
| 8406 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 |
|---|
| 8407 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
|---|
| 8408 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
|---|
| 8409 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 |
|---|
| 8410 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
|---|
| 8411 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
|---|
| 8412 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 |
|---|
| 8413 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
|---|
| 8414 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
|---|
| 8415 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 |
|---|
| 8416 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
|---|
| 8417 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
|---|
| 8418 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
|---|
| 8419 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
|---|
| 8420 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
|---|
| 8421 | //BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
|---|
| 8422 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
|---|
| 8423 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
|---|
| 8424 | //BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST |
|---|
| 8425 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8426 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8427 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8428 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8429 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8430 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8431 | //BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP |
|---|
| 8432 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 8433 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
|---|
| 8434 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 8435 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 8436 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 8437 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 8438 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 8439 | #define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 8440 | //BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 8441 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8442 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8443 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8444 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8445 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8446 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8447 | //BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP |
|---|
| 8448 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 8449 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 8450 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 8451 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 8452 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 8453 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 8454 | //BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL |
|---|
| 8455 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 8456 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 8457 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 8458 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 8459 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 8460 | #define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 8461 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST |
|---|
| 8462 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8463 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8464 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8465 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8466 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8467 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8468 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP |
|---|
| 8469 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
|---|
| 8470 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
|---|
| 8471 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
|---|
| 8472 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
|---|
| 8473 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
|---|
| 8474 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
|---|
| 8475 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
|---|
| 8476 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
|---|
| 8477 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL |
|---|
| 8478 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
|---|
| 8479 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
|---|
| 8480 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
|---|
| 8481 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
|---|
| 8482 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
|---|
| 8483 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
|---|
| 8484 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
|---|
| 8485 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
|---|
| 8486 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
|---|
| 8487 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
|---|
| 8488 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
|---|
| 8489 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
|---|
| 8490 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS |
|---|
| 8491 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
|---|
| 8492 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
|---|
| 8493 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS |
|---|
| 8494 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
|---|
| 8495 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
|---|
| 8496 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS |
|---|
| 8497 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
|---|
| 8498 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
|---|
| 8499 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS |
|---|
| 8500 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
|---|
| 8501 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
|---|
| 8502 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK |
|---|
| 8503 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
|---|
| 8504 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
|---|
| 8505 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET |
|---|
| 8506 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
|---|
| 8507 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
|---|
| 8508 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE |
|---|
| 8509 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
|---|
| 8510 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
|---|
| 8511 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID |
|---|
| 8512 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
|---|
| 8513 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
|---|
| 8514 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
|---|
| 8515 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
|---|
| 8516 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 8517 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
|---|
| 8518 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
|---|
| 8519 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 8520 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 |
|---|
| 8521 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 8522 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 8523 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 |
|---|
| 8524 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 8525 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 8526 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 |
|---|
| 8527 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 8528 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 8529 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 |
|---|
| 8530 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 8531 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 8532 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 |
|---|
| 8533 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 8534 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 8535 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 |
|---|
| 8536 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 8537 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 8538 | //BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
|---|
| 8539 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 |
|---|
| 8540 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
|---|
| 8541 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L |
|---|
| 8542 | #define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 8543 | //BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 8544 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8545 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8546 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8547 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8548 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8549 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8550 | //BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP |
|---|
| 8551 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 8552 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 8553 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 8554 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 8555 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 8556 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 8557 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 8558 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 8559 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 8560 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 8561 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 8562 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 8563 | //BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL |
|---|
| 8564 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 8565 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 8566 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 8567 | #define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 8568 | //BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST |
|---|
| 8569 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8570 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8571 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8572 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8573 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8574 | #define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8575 | //BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP |
|---|
| 8576 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 8577 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
|---|
| 8578 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 8579 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
|---|
| 8580 | //BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS |
|---|
| 8581 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 8582 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
|---|
| 8583 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 8584 | #define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
|---|
| 8585 | //BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST |
|---|
| 8586 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8587 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8588 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8589 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8590 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8591 | #define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8592 | //BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT |
|---|
| 8593 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
|---|
| 8594 | #define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 8595 | //BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT |
|---|
| 8596 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
|---|
| 8597 | #define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 8598 | //BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT |
|---|
| 8599 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
|---|
| 8600 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
|---|
| 8601 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
|---|
| 8602 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
|---|
| 8603 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
|---|
| 8604 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
|---|
| 8605 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
|---|
| 8606 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
|---|
| 8607 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
|---|
| 8608 | #define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
|---|
| 8609 | //BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
|---|
| 8610 | #define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 8611 | #define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 8612 | //BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT |
|---|
| 8613 | #define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 8614 | #define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 8615 | //BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT |
|---|
| 8616 | #define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 8617 | #define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 8618 | //BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT |
|---|
| 8619 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8620 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8621 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8622 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8623 | //BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT |
|---|
| 8624 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8625 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8626 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8627 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8628 | //BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT |
|---|
| 8629 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8630 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8631 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8632 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8633 | //BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT |
|---|
| 8634 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8635 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8636 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8637 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8638 | //BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT |
|---|
| 8639 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8640 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8641 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8642 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8643 | //BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT |
|---|
| 8644 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8645 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8646 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8647 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8648 | //BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT |
|---|
| 8649 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8650 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8651 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8652 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8653 | //BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT |
|---|
| 8654 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8655 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8656 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8657 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8658 | //BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT |
|---|
| 8659 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8660 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8661 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8662 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8663 | //BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT |
|---|
| 8664 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8665 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8666 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8667 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8668 | //BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT |
|---|
| 8669 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8670 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8671 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8672 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8673 | //BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT |
|---|
| 8674 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8675 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8676 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8677 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8678 | //BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT |
|---|
| 8679 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8680 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8681 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8682 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8683 | //BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT |
|---|
| 8684 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8685 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8686 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8687 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8688 | //BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 8689 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8690 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8691 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8692 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8693 | //BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 8694 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 8695 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 8696 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 8697 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 8698 | //BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 8699 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 8700 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 8701 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 8702 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 8703 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 8704 | #define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 8705 | //BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP |
|---|
| 8706 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 8707 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 8708 | //BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS |
|---|
| 8709 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
|---|
| 8710 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
|---|
| 8711 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
|---|
| 8712 | #define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
|---|
| 8713 | //BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL |
|---|
| 8714 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8715 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8716 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8717 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8718 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8719 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8720 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 8721 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8722 | //BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS |
|---|
| 8723 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8724 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8725 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8726 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8727 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8728 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8729 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8730 | #define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8731 | //BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL |
|---|
| 8732 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8733 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8734 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8735 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8736 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8737 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8738 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 8739 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8740 | //BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS |
|---|
| 8741 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8742 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8743 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8744 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8745 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8746 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8747 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8748 | #define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8749 | //BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL |
|---|
| 8750 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8751 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8752 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8753 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8754 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8755 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8756 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 8757 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8758 | //BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS |
|---|
| 8759 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8760 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8761 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8762 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8763 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8764 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8765 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8766 | #define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8767 | //BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL |
|---|
| 8768 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8769 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8770 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8771 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8772 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8773 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8774 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 8775 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8776 | //BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS |
|---|
| 8777 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8778 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8779 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8780 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8781 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8782 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8783 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8784 | #define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8785 | //BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL |
|---|
| 8786 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8787 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8788 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8789 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8790 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8791 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8792 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 8793 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8794 | //BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS |
|---|
| 8795 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8796 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8797 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8798 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8799 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8800 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8801 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8802 | #define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8803 | //BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL |
|---|
| 8804 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8805 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8806 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8807 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8808 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8809 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8810 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 8811 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8812 | //BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS |
|---|
| 8813 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8814 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8815 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8816 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8817 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8818 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8819 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8820 | #define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8821 | //BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL |
|---|
| 8822 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8823 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8824 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8825 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8826 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8827 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8828 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 8829 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8830 | //BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS |
|---|
| 8831 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8832 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8833 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8834 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8835 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8836 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8837 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8838 | #define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8839 | //BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL |
|---|
| 8840 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8841 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8842 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8843 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8844 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8845 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8846 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 8847 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8848 | //BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS |
|---|
| 8849 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8850 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8851 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8852 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8853 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8854 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8855 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8856 | #define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8857 | //BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL |
|---|
| 8858 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8859 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8860 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8861 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8862 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8863 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8864 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 8865 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8866 | //BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS |
|---|
| 8867 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8868 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8869 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8870 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8871 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8872 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8873 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8874 | #define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8875 | //BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL |
|---|
| 8876 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8877 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8878 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8879 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8880 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8881 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8882 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 8883 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8884 | //BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS |
|---|
| 8885 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8886 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8887 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8888 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8889 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8890 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8891 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8892 | #define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8893 | //BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL |
|---|
| 8894 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8895 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8896 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8897 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8898 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8899 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8900 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 8901 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8902 | //BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS |
|---|
| 8903 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8904 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8905 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8906 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8907 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8908 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8909 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8910 | #define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8911 | //BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL |
|---|
| 8912 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8913 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8914 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8915 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8916 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8917 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8918 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 8919 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8920 | //BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS |
|---|
| 8921 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8922 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8923 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8924 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8925 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8926 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8927 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8928 | #define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8929 | //BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL |
|---|
| 8930 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8931 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8932 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8933 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8934 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8935 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8936 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 8937 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8938 | //BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS |
|---|
| 8939 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8940 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8941 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8942 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8943 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8944 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8945 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8946 | #define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8947 | //BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL |
|---|
| 8948 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8949 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8950 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8951 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8952 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8953 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8954 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 8955 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8956 | //BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS |
|---|
| 8957 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8958 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8959 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8960 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8961 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8962 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8963 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8964 | #define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8965 | //BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL |
|---|
| 8966 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8967 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8968 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8969 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8970 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8971 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8972 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 8973 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8974 | //BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS |
|---|
| 8975 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8976 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8977 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8978 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8979 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8980 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8981 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 8982 | #define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 8983 | //BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL |
|---|
| 8984 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 8985 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 8986 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 8987 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 8988 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 8989 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 8990 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 8991 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 8992 | //BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS |
|---|
| 8993 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 8994 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 8995 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 8996 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 8997 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 8998 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 8999 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 9000 | #define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 9001 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
|---|
| 9002 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 9003 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 9004 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 9005 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 9006 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 9007 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 9008 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP |
|---|
| 9009 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 9010 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 9011 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL |
|---|
| 9012 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 9013 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 9014 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 9015 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 9016 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 9017 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 9018 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP |
|---|
| 9019 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 9020 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 9021 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL |
|---|
| 9022 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 9023 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 9024 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 9025 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 9026 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 9027 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 9028 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP |
|---|
| 9029 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 9030 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 9031 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL |
|---|
| 9032 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 9033 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 9034 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 9035 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 9036 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 9037 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 9038 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP |
|---|
| 9039 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 9040 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 9041 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL |
|---|
| 9042 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 9043 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 9044 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 9045 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 9046 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 9047 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 9048 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP |
|---|
| 9049 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 9050 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 9051 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL |
|---|
| 9052 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 9053 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 9054 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 9055 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 9056 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 9057 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 9058 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP |
|---|
| 9059 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 9060 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 9061 | //BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL |
|---|
| 9062 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 9063 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 9064 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 9065 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 9066 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 9067 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 9068 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
|---|
| 9069 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
|---|
| 9070 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
|---|
| 9071 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
|---|
| 9072 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
|---|
| 9073 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
|---|
| 9074 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 9075 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
|---|
| 9076 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
|---|
| 9077 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
|---|
| 9078 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 9079 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 9080 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
|---|
| 9081 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 9082 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
|---|
| 9083 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
|---|
| 9084 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
|---|
| 9085 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
|---|
| 9086 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
|---|
| 9087 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
|---|
| 9088 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
|---|
| 9089 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
|---|
| 9090 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
|---|
| 9091 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
|---|
| 9092 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
|---|
| 9093 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
|---|
| 9094 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
|---|
| 9095 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
|---|
| 9096 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc |
|---|
| 9097 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd |
|---|
| 9098 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe |
|---|
| 9099 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf |
|---|
| 9100 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
|---|
| 9101 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
|---|
| 9102 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
|---|
| 9103 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
|---|
| 9104 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
|---|
| 9105 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
|---|
| 9106 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
|---|
| 9107 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
|---|
| 9108 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
|---|
| 9109 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
|---|
| 9110 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
|---|
| 9111 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
|---|
| 9112 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
|---|
| 9113 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
|---|
| 9114 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L |
|---|
| 9115 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L |
|---|
| 9116 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L |
|---|
| 9117 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L |
|---|
| 9118 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
|---|
| 9119 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
|---|
| 9120 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
|---|
| 9121 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
|---|
| 9122 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
|---|
| 9123 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
|---|
| 9124 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
|---|
| 9125 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
|---|
| 9126 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
|---|
| 9127 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
|---|
| 9128 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
|---|
| 9129 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
|---|
| 9130 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
|---|
| 9131 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
|---|
| 9132 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
|---|
| 9133 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc |
|---|
| 9134 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd |
|---|
| 9135 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe |
|---|
| 9136 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf |
|---|
| 9137 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
|---|
| 9138 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
|---|
| 9139 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
|---|
| 9140 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
|---|
| 9141 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
|---|
| 9142 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
|---|
| 9143 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
|---|
| 9144 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
|---|
| 9145 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
|---|
| 9146 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
|---|
| 9147 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
|---|
| 9148 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
|---|
| 9149 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
|---|
| 9150 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
|---|
| 9151 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L |
|---|
| 9152 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L |
|---|
| 9153 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L |
|---|
| 9154 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L |
|---|
| 9155 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
|---|
| 9156 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
|---|
| 9157 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
|---|
| 9158 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
|---|
| 9159 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
|---|
| 9160 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
|---|
| 9161 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
|---|
| 9162 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
|---|
| 9163 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
|---|
| 9164 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
|---|
| 9165 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
|---|
| 9166 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 9167 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
|---|
| 9168 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 9169 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
|---|
| 9170 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
|---|
| 9171 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 9172 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 9173 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 9174 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
|---|
| 9175 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
|---|
| 9176 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
|---|
| 9177 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
|---|
| 9178 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
|---|
| 9179 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
|---|
| 9180 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
|---|
| 9181 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
|---|
| 9182 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
|---|
| 9183 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
|---|
| 9184 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
|---|
| 9185 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
|---|
| 9186 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
|---|
| 9187 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
|---|
| 9188 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
|---|
| 9189 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
|---|
| 9190 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
|---|
| 9191 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
|---|
| 9192 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
|---|
| 9193 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
|---|
| 9194 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
|---|
| 9195 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
|---|
| 9196 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
|---|
| 9197 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
|---|
| 9198 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
|---|
| 9199 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
|---|
| 9200 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
|---|
| 9201 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
|---|
| 9202 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
|---|
| 9203 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
|---|
| 9204 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
|---|
| 9205 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
|---|
| 9206 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
|---|
| 9207 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
|---|
| 9208 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
|---|
| 9209 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
|---|
| 9210 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
|---|
| 9211 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
|---|
| 9212 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
|---|
| 9213 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
|---|
| 9214 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
|---|
| 9215 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
|---|
| 9216 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
|---|
| 9217 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
|---|
| 9218 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
|---|
| 9219 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
|---|
| 9220 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
|---|
| 9221 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
|---|
| 9222 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
|---|
| 9223 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
|---|
| 9224 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
|---|
| 9225 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
|---|
| 9226 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
|---|
| 9227 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
|---|
| 9228 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
|---|
| 9229 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
|---|
| 9230 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
|---|
| 9231 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
|---|
| 9232 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
|---|
| 9233 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
|---|
| 9234 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
|---|
| 9235 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
|---|
| 9236 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
|---|
| 9237 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
|---|
| 9238 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
|---|
| 9239 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
|---|
| 9240 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
|---|
| 9241 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 |
|---|
| 9242 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 |
|---|
| 9243 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 |
|---|
| 9244 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 |
|---|
| 9245 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 |
|---|
| 9246 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 |
|---|
| 9247 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 |
|---|
| 9248 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 |
|---|
| 9249 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 |
|---|
| 9250 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 |
|---|
| 9251 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa |
|---|
| 9252 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb |
|---|
| 9253 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc |
|---|
| 9254 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd |
|---|
| 9255 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe |
|---|
| 9256 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf |
|---|
| 9257 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 |
|---|
| 9258 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 |
|---|
| 9259 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 |
|---|
| 9260 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 |
|---|
| 9261 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 |
|---|
| 9262 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 |
|---|
| 9263 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 |
|---|
| 9264 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 |
|---|
| 9265 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 |
|---|
| 9266 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 |
|---|
| 9267 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a |
|---|
| 9268 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b |
|---|
| 9269 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c |
|---|
| 9270 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d |
|---|
| 9271 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e |
|---|
| 9272 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f |
|---|
| 9273 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L |
|---|
| 9274 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L |
|---|
| 9275 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L |
|---|
| 9276 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L |
|---|
| 9277 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L |
|---|
| 9278 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L |
|---|
| 9279 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L |
|---|
| 9280 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L |
|---|
| 9281 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L |
|---|
| 9282 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L |
|---|
| 9283 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L |
|---|
| 9284 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L |
|---|
| 9285 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L |
|---|
| 9286 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L |
|---|
| 9287 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L |
|---|
| 9288 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L |
|---|
| 9289 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L |
|---|
| 9290 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L |
|---|
| 9291 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L |
|---|
| 9292 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L |
|---|
| 9293 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L |
|---|
| 9294 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L |
|---|
| 9295 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L |
|---|
| 9296 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L |
|---|
| 9297 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L |
|---|
| 9298 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L |
|---|
| 9299 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L |
|---|
| 9300 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L |
|---|
| 9301 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L |
|---|
| 9302 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L |
|---|
| 9303 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L |
|---|
| 9304 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L |
|---|
| 9305 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
|---|
| 9306 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
|---|
| 9307 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
|---|
| 9308 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
|---|
| 9309 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
|---|
| 9310 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
|---|
| 9311 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
|---|
| 9312 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
|---|
| 9313 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
|---|
| 9314 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
|---|
| 9315 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
|---|
| 9316 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
|---|
| 9317 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
|---|
| 9318 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
|---|
| 9319 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
|---|
| 9320 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
|---|
| 9321 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18 |
|---|
| 9322 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
|---|
| 9323 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
|---|
| 9324 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
|---|
| 9325 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L |
|---|
| 9326 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION |
|---|
| 9327 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 |
|---|
| 9328 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 |
|---|
| 9329 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L |
|---|
| 9330 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L |
|---|
| 9331 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE |
|---|
| 9332 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 |
|---|
| 9333 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f |
|---|
| 9334 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL |
|---|
| 9335 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L |
|---|
| 9336 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
|---|
| 9337 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
|---|
| 9338 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
|---|
| 9339 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9340 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9341 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
|---|
| 9342 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
|---|
| 9343 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
|---|
| 9344 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9345 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9346 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
|---|
| 9347 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
|---|
| 9348 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
|---|
| 9349 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9350 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9351 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
|---|
| 9352 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
|---|
| 9353 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
|---|
| 9354 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9355 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9356 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
|---|
| 9357 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
|---|
| 9358 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
|---|
| 9359 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9360 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9361 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
|---|
| 9362 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
|---|
| 9363 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
|---|
| 9364 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9365 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9366 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
|---|
| 9367 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
|---|
| 9368 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
|---|
| 9369 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9370 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9371 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
|---|
| 9372 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
|---|
| 9373 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
|---|
| 9374 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9375 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9376 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
|---|
| 9377 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
|---|
| 9378 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
|---|
| 9379 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9380 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9381 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
|---|
| 9382 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
|---|
| 9383 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
|---|
| 9384 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9385 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9386 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
|---|
| 9387 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
|---|
| 9388 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
|---|
| 9389 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9390 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9391 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
|---|
| 9392 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
|---|
| 9393 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
|---|
| 9394 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9395 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9396 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
|---|
| 9397 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
|---|
| 9398 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
|---|
| 9399 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9400 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9401 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
|---|
| 9402 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
|---|
| 9403 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
|---|
| 9404 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9405 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9406 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
|---|
| 9407 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
|---|
| 9408 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
|---|
| 9409 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9410 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9411 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
|---|
| 9412 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
|---|
| 9413 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
|---|
| 9414 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9415 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9416 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB |
|---|
| 9417 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0 |
|---|
| 9418 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10 |
|---|
| 9419 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9420 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9421 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB |
|---|
| 9422 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0 |
|---|
| 9423 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10 |
|---|
| 9424 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9425 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9426 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB |
|---|
| 9427 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0 |
|---|
| 9428 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10 |
|---|
| 9429 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9430 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9431 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB |
|---|
| 9432 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0 |
|---|
| 9433 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10 |
|---|
| 9434 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9435 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9436 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB |
|---|
| 9437 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0 |
|---|
| 9438 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10 |
|---|
| 9439 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9440 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9441 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB |
|---|
| 9442 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0 |
|---|
| 9443 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10 |
|---|
| 9444 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9445 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9446 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB |
|---|
| 9447 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0 |
|---|
| 9448 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10 |
|---|
| 9449 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9450 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9451 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB |
|---|
| 9452 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0 |
|---|
| 9453 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10 |
|---|
| 9454 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9455 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9456 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB |
|---|
| 9457 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0 |
|---|
| 9458 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10 |
|---|
| 9459 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9460 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9461 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB |
|---|
| 9462 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0 |
|---|
| 9463 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10 |
|---|
| 9464 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9465 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9466 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB |
|---|
| 9467 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0 |
|---|
| 9468 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10 |
|---|
| 9469 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9470 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9471 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB |
|---|
| 9472 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0 |
|---|
| 9473 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10 |
|---|
| 9474 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9475 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9476 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB |
|---|
| 9477 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0 |
|---|
| 9478 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10 |
|---|
| 9479 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9480 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9481 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB |
|---|
| 9482 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0 |
|---|
| 9483 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10 |
|---|
| 9484 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9485 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9486 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB |
|---|
| 9487 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0 |
|---|
| 9488 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10 |
|---|
| 9489 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 9490 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 9491 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
|---|
| 9492 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 9493 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 9494 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
|---|
| 9495 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 9496 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 9497 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
|---|
| 9498 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 9499 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 9500 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
|---|
| 9501 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 9502 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 9503 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
|---|
| 9504 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 9505 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 9506 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
|---|
| 9507 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 9508 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 9509 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
|---|
| 9510 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 9511 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 9512 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
|---|
| 9513 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 9514 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 9515 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
|---|
| 9516 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 9517 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 9518 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
|---|
| 9519 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
|---|
| 9520 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 9521 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
|---|
| 9522 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
|---|
| 9523 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 9524 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
|---|
| 9525 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
|---|
| 9526 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 9527 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
|---|
| 9528 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
|---|
| 9529 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 9530 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
|---|
| 9531 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
|---|
| 9532 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 9533 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
|---|
| 9534 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
|---|
| 9535 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 9536 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
|---|
| 9537 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
|---|
| 9538 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 9539 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
|---|
| 9540 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
|---|
| 9541 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 9542 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
|---|
| 9543 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
|---|
| 9544 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 9545 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
|---|
| 9546 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 9547 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 9548 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
|---|
| 9549 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 9550 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 9551 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
|---|
| 9552 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 9553 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 9554 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
|---|
| 9555 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 9556 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 9557 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
|---|
| 9558 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 9559 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 9560 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
|---|
| 9561 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 9562 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 9563 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
|---|
| 9564 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 9565 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 9566 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
|---|
| 9567 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 9568 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 9569 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
|---|
| 9570 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 9571 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 9572 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 |
|---|
| 9573 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0 |
|---|
| 9574 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 9575 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 |
|---|
| 9576 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0 |
|---|
| 9577 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 9578 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 |
|---|
| 9579 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0 |
|---|
| 9580 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 9581 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 |
|---|
| 9582 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0 |
|---|
| 9583 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 9584 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 |
|---|
| 9585 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0 |
|---|
| 9586 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 9587 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 |
|---|
| 9588 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0 |
|---|
| 9589 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 9590 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 |
|---|
| 9591 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0 |
|---|
| 9592 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 9593 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 |
|---|
| 9594 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0 |
|---|
| 9595 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 9596 | //BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 |
|---|
| 9597 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0 |
|---|
| 9598 | #define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 9599 | |
|---|
| 9600 | |
|---|
| 9601 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
|---|
| 9602 | //BIF_CFG_DEV0_EPF2_0_VENDOR_ID |
|---|
| 9603 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 9604 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 9605 | //BIF_CFG_DEV0_EPF2_0_DEVICE_ID |
|---|
| 9606 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 9607 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 9608 | //BIF_CFG_DEV0_EPF2_0_COMMAND |
|---|
| 9609 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 9610 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 9611 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 9612 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 9613 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 9614 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 9615 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 9616 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 9617 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 9618 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 9619 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 9620 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 9621 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 9622 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 9623 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 9624 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 9625 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 9626 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 9627 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 9628 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 9629 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 9630 | #define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 9631 | //BIF_CFG_DEV0_EPF2_0_STATUS |
|---|
| 9632 | #define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 9633 | #define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 9634 | #define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 9635 | #define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 9636 | #define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 9637 | #define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 9638 | #define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 9639 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 9640 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 9641 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 9642 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 9643 | #define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 9644 | #define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 9645 | #define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 9646 | #define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 9647 | #define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 9648 | #define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 9649 | #define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 9650 | #define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 9651 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 9652 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 9653 | #define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 9654 | #define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 9655 | #define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 9656 | //BIF_CFG_DEV0_EPF2_0_REVISION_ID |
|---|
| 9657 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 9658 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 9659 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 9660 | #define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 9661 | //BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE |
|---|
| 9662 | #define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 9663 | #define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 9664 | //BIF_CFG_DEV0_EPF2_0_SUB_CLASS |
|---|
| 9665 | #define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 9666 | #define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 9667 | //BIF_CFG_DEV0_EPF2_0_BASE_CLASS |
|---|
| 9668 | #define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 9669 | #define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 9670 | //BIF_CFG_DEV0_EPF2_0_CACHE_LINE |
|---|
| 9671 | #define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 9672 | #define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 9673 | //BIF_CFG_DEV0_EPF2_0_LATENCY |
|---|
| 9674 | #define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 9675 | #define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 9676 | //BIF_CFG_DEV0_EPF2_0_HEADER |
|---|
| 9677 | #define 0x0 |
|---|
| 9678 | #define 0x7 |
|---|
| 9679 | #define 0x7FL |
|---|
| 9680 | #define 0x80L |
|---|
| 9681 | //BIF_CFG_DEV0_EPF2_0_BIST |
|---|
| 9682 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 9683 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 9684 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 9685 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 9686 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 9687 | #define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 9688 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 |
|---|
| 9689 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 9690 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 9691 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 |
|---|
| 9692 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 9693 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 9694 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 |
|---|
| 9695 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 9696 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 9697 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 |
|---|
| 9698 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 9699 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 9700 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 |
|---|
| 9701 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 9702 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 9703 | //BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 |
|---|
| 9704 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 9705 | #define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 9706 | //BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR |
|---|
| 9707 | #define BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 9708 | #define BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 9709 | //BIF_CFG_DEV0_EPF2_0_ADAPTER_ID |
|---|
| 9710 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 9711 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 9712 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 9713 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 9714 | //BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR |
|---|
| 9715 | #define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 9716 | #define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 9717 | //BIF_CFG_DEV0_EPF2_0_CAP_PTR |
|---|
| 9718 | #define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 9719 | #define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 9720 | //BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE |
|---|
| 9721 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 9722 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 9723 | //BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN |
|---|
| 9724 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 9725 | #define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 9726 | //BIF_CFG_DEV0_EPF2_0_MIN_GRANT |
|---|
| 9727 | #define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 9728 | #define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 9729 | //BIF_CFG_DEV0_EPF2_0_MAX_LATENCY |
|---|
| 9730 | #define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 9731 | #define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 9732 | //BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST |
|---|
| 9733 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 9734 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 9735 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 9736 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 9737 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 9738 | #define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 9739 | //BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W |
|---|
| 9740 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 9741 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 9742 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 9743 | #define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 9744 | //BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST |
|---|
| 9745 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 9746 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 9747 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 9748 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 9749 | //BIF_CFG_DEV0_EPF2_0_PMI_CAP |
|---|
| 9750 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 9751 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 9752 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 9753 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 9754 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 9755 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 9756 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 9757 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 9758 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 9759 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 9760 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 9761 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 9762 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 9763 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 9764 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 9765 | #define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 9766 | //BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL |
|---|
| 9767 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 9768 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 9769 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 9770 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 9771 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 9772 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 9773 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 9774 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 9775 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 9776 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 9777 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 9778 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 9779 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 9780 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 9781 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 9782 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 9783 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 9784 | #define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 9785 | //BIF_CFG_DEV0_EPF2_0_SBRN |
|---|
| 9786 | #define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT 0x0 |
|---|
| 9787 | #define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK 0xFFL |
|---|
| 9788 | //BIF_CFG_DEV0_EPF2_0_FLADJ |
|---|
| 9789 | #define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT 0x0 |
|---|
| 9790 | #define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC__SHIFT 0x6 |
|---|
| 9791 | #define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK 0x3FL |
|---|
| 9792 | #define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC_MASK 0x40L |
|---|
| 9793 | //BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD |
|---|
| 9794 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
|---|
| 9795 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
|---|
| 9796 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
|---|
| 9797 | #define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
|---|
| 9798 | //BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST |
|---|
| 9799 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 9800 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 9801 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 9802 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 9803 | //BIF_CFG_DEV0_EPF2_0_PCIE_CAP |
|---|
| 9804 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 9805 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 9806 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 9807 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 9808 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 9809 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 9810 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 9811 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 9812 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CAP |
|---|
| 9813 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 9814 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 9815 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 9816 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 9817 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 9818 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 9819 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 9820 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 9821 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 9822 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 9823 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 9824 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 9825 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 9826 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 9827 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 9828 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 9829 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 9830 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 9831 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL |
|---|
| 9832 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 9833 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 9834 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 9835 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 9836 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 9837 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 9838 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 9839 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 9840 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 9841 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 9842 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 9843 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 9844 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 9845 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 9846 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 9847 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 9848 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 9849 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 9850 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 9851 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 9852 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 9853 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 9854 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 9855 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 9856 | //BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS |
|---|
| 9857 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 9858 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 9859 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 9860 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 9861 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 9862 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 9863 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 9864 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 9865 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 9866 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 9867 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 9868 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 9869 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 9870 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 9871 | //BIF_CFG_DEV0_EPF2_0_LINK_CAP |
|---|
| 9872 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 9873 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 9874 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 9875 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 9876 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 9877 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 9878 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 9879 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 9880 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 9881 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 9882 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 9883 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 9884 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 9885 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 9886 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 9887 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 9888 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 9889 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 9890 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 9891 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 9892 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 9893 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 9894 | //BIF_CFG_DEV0_EPF2_0_LINK_CNTL |
|---|
| 9895 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 9896 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 9897 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 9898 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 9899 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 9900 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 9901 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 9902 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 9903 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 9904 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 9905 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 9906 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 9907 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 9908 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 9909 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 9910 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 9911 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 9912 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 9913 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 9914 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 9915 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 9916 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 9917 | //BIF_CFG_DEV0_EPF2_0_LINK_STATUS |
|---|
| 9918 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 9919 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 9920 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 9921 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 9922 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 9923 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 9924 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 9925 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 9926 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 9927 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 9928 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 9929 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 9930 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 9931 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 9932 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 |
|---|
| 9933 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 9934 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 9935 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 9936 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 9937 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 9938 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 9939 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 9940 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 9941 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 9942 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 9943 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 9944 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 9945 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 9946 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 9947 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 9948 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 9949 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 9950 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 9951 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 9952 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 9953 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 9954 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 9955 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 9956 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 9957 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 9958 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 9959 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 9960 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 9961 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 9962 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 9963 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 9964 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 9965 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 9966 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 9967 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 9968 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 9969 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 9970 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 9971 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 9972 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 9973 | //BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 |
|---|
| 9974 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 9975 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 9976 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 9977 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 9978 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 9979 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 9980 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 9981 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 9982 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 9983 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 9984 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 9985 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 9986 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 9987 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 9988 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 9989 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 9990 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 9991 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 9992 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
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| 9993 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
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| 9994 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 9995 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
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| 9996 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 9997 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 9998 | //BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 |
|---|
| 9999 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 10000 | #define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 10001 | //BIF_CFG_DEV0_EPF2_0_LINK_CAP2 |
|---|
| 10002 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 10003 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 10004 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 10005 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 10006 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 10007 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 10008 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 10009 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 10010 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 10011 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 10012 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 10013 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 10014 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 10015 | #define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 10016 | //BIF_CFG_DEV0_EPF2_0_LINK_CNTL2 |
|---|
| 10017 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 10018 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 10019 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 10020 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 10021 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 10022 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 10023 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 10024 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 10025 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 10026 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 10027 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 10028 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 10029 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 10030 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 10031 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 10032 | #define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 10033 | //BIF_CFG_DEV0_EPF2_0_LINK_STATUS2 |
|---|
| 10034 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 10035 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 10036 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 10037 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 10038 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 10039 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 10040 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 10041 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 10042 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 10043 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 10044 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 10045 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 10046 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 10047 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 10048 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 10049 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 10050 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 10051 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 10052 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 10053 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 10054 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 10055 | #define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 10056 | //BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST |
|---|
| 10057 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10058 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 10059 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 10060 | #define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 10061 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL |
|---|
| 10062 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 10063 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 10064 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 10065 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 10066 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 10067 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 10068 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 10069 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 10070 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 10071 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 10072 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO |
|---|
| 10073 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 10074 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 10075 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI |
|---|
| 10076 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 10077 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 10078 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA |
|---|
| 10079 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 10080 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 10081 | //BIF_CFG_DEV0_EPF2_0_MSI_MASK |
|---|
| 10082 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 10083 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 10084 | //BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 |
|---|
| 10085 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 10086 | #define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 10087 | //BIF_CFG_DEV0_EPF2_0_MSI_MASK_64 |
|---|
| 10088 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 10089 | #define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 10090 | //BIF_CFG_DEV0_EPF2_0_MSI_PENDING |
|---|
| 10091 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 10092 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 10093 | //BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 |
|---|
| 10094 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 10095 | #define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 10096 | //BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST |
|---|
| 10097 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10098 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 10099 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 10100 | #define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 10101 | //BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL |
|---|
| 10102 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 10103 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 10104 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 10105 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 10106 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 10107 | #define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 10108 | //BIF_CFG_DEV0_EPF2_0_MSIX_TABLE |
|---|
| 10109 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 10110 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 10111 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 10112 | #define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 10113 | //BIF_CFG_DEV0_EPF2_0_MSIX_PBA |
|---|
| 10114 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 10115 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 10116 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 10117 | #define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 10118 | //BIF_CFG_DEV0_EPF2_0_SATA_CAP_0 |
|---|
| 10119 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
|---|
| 10120 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
|---|
| 10121 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
|---|
| 10122 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
|---|
| 10123 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
|---|
| 10124 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
|---|
| 10125 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 10126 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
|---|
| 10127 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
|---|
| 10128 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
|---|
| 10129 | //BIF_CFG_DEV0_EPF2_0_SATA_CAP_1 |
|---|
| 10130 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
|---|
| 10131 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
|---|
| 10132 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
|---|
| 10133 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
|---|
| 10134 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
|---|
| 10135 | #define BIF_CFG_DEV0_EPF2_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
|---|
| 10136 | //BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX |
|---|
| 10137 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
|---|
| 10138 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
|---|
| 10139 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
|---|
| 10140 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
|---|
| 10141 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
|---|
| 10142 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
|---|
| 10143 | //BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA |
|---|
| 10144 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
|---|
| 10145 | #define BIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
|---|
| 10146 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 10147 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10148 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 10149 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 10150 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 10151 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 10152 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 10153 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 10154 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 10155 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 10156 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 10157 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 10158 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 10159 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 10160 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 10161 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 10162 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 10163 | //BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 10164 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 10165 | #define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 10166 | //BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 10167 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10168 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 10169 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 10170 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 10171 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 10172 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 10173 | //BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS |
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| 10174 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 10175 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 10176 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 10177 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 10178 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 10179 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 10180 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 10181 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 10182 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 10183 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 10184 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 10185 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 10186 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 10187 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 10188 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 10189 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 10190 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 10191 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 10192 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 10193 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 10194 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 10195 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 10196 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 10197 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 10198 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 10199 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 10200 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 10201 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 10202 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 10203 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 10204 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 10205 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 10206 | //BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK |
|---|
| 10207 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 10208 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 10209 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 10210 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 10211 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 10212 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 10213 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 10214 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 10215 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 10216 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 10217 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 10218 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 10219 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 10220 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 10221 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 10222 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 10223 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 10224 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 10225 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 10226 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 10227 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 10228 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 10229 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 10230 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 10231 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 10232 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 10233 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 10234 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 10235 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 10236 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 10237 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 10238 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 10239 | //BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 10240 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 10241 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 10242 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 10243 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 10244 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 10245 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 10246 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 10247 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 10248 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 10249 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 10250 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 10251 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 10252 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 10253 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 10254 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 10255 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 10256 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 10257 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 10258 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 10259 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 10260 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 10261 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 10262 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 10263 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 10264 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 10265 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 10266 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 10267 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 10268 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 10269 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 10270 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 10271 | #define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 10272 | //BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS |
|---|
| 10273 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 10274 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 10275 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 10276 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 10277 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 10278 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 10279 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 10280 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 10281 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 10282 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 10283 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 10284 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 10285 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 10286 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 10287 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 10288 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 10289 | //BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK |
|---|
| 10290 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 10291 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 10292 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 10293 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 10294 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 10295 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 10296 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 10297 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 10298 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 10299 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 10300 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 10301 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 10302 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 10303 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 10304 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 10305 | #define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 10306 | //BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 10307 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 10308 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 10309 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 10310 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 10311 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 10312 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 10313 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 10314 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 10315 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 10316 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 10317 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 10318 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 10319 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 10320 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 10321 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 10322 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 10323 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 10324 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 10325 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 |
|---|
| 10326 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 10327 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 10328 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 |
|---|
| 10329 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 10330 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 10331 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 |
|---|
| 10332 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 10333 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 10334 | //BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 |
|---|
| 10335 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 10336 | #define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 10337 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 10338 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 10339 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 10340 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 10341 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 10342 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 10343 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 10344 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 10345 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 10346 | //BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 10347 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 10348 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 10349 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST |
|---|
| 10350 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10351 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 10352 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 10353 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 10354 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 10355 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 10356 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP |
|---|
| 10357 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 10358 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 10359 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL |
|---|
| 10360 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 10361 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 10362 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 10363 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 10364 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 10365 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 10366 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP |
|---|
| 10367 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 10368 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 10369 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL |
|---|
| 10370 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 10371 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 10372 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 10373 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 10374 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 10375 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 10376 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP |
|---|
| 10377 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 10378 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 10379 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL |
|---|
| 10380 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 10381 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 10382 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 10383 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 10384 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 10385 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 10386 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP |
|---|
| 10387 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 10388 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 10389 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL |
|---|
| 10390 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 10391 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 10392 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 10393 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 10394 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 10395 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 10396 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP |
|---|
| 10397 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 10398 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 10399 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL |
|---|
| 10400 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 10401 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 10402 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 10403 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 10404 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 10405 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 10406 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP |
|---|
| 10407 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 10408 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 10409 | //BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL |
|---|
| 10410 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 10411 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 10412 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 10413 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 10414 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 10415 | #define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 10416 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 10417 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10418 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 10419 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 10420 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 10421 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 10422 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 10423 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 10424 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 10425 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 10426 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA |
|---|
| 10427 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 10428 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 10429 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 10430 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 10431 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 10432 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 10433 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 10434 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 10435 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 10436 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 10437 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 10438 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 10439 | //BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP |
|---|
| 10440 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 10441 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 10442 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST |
|---|
| 10443 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10444 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 10445 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 10446 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 10447 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 10448 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 10449 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP |
|---|
| 10450 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 10451 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 10452 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 10453 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 10454 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 10455 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 10456 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 10457 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 10458 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 10459 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 10460 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 10461 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 10462 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 10463 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS |
|---|
| 10464 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 10465 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 10466 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 10467 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 10468 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL |
|---|
| 10469 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 10470 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 10471 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 10472 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 10473 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 10474 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 10475 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 10476 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 10477 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 10478 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 10479 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 10480 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 10481 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 10482 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 10483 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 10484 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 10485 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 10486 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 10487 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 10488 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 10489 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 10490 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 10491 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 10492 | //BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 10493 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 10494 | #define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 10495 | //BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST |
|---|
| 10496 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10497 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 10498 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 10499 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 10500 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 10501 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 10502 | //BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP |
|---|
| 10503 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 10504 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 10505 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 10506 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 10507 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 10508 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 10509 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 10510 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 10511 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 10512 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 10513 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 10514 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 10515 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 10516 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 10517 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 10518 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 10519 | //BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL |
|---|
| 10520 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 10521 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 10522 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 10523 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 10524 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 10525 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 10526 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 10527 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 10528 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 10529 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 10530 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 10531 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 10532 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 10533 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 10534 | //BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST |
|---|
| 10535 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10536 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 10537 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 10538 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 10539 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 10540 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 10541 | //BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP |
|---|
| 10542 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 10543 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 10544 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 10545 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 10546 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 10547 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 10548 | //BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL |
|---|
| 10549 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 10550 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 10551 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 10552 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 10553 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 10554 | #define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 10555 | //BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 10556 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10557 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 10558 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 10559 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 10560 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 10561 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 10562 | //BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP |
|---|
| 10563 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 10564 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 10565 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 10566 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 10567 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 10568 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 10569 | //BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL |
|---|
| 10570 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 10571 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 10572 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 10573 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 10574 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 10575 | #define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 10576 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 10577 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 10578 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 10579 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 10580 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 10581 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 10582 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 10583 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP |
|---|
| 10584 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 10585 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 10586 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 10587 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 10588 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 10589 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 10590 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 10591 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 10592 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 10593 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 10594 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 10595 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 10596 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL |
|---|
| 10597 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 10598 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 10599 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 10600 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 10601 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0 |
|---|
| 10602 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10603 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10604 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10605 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10606 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1 |
|---|
| 10607 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10608 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10609 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10610 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10611 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2 |
|---|
| 10612 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10613 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10614 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10615 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10616 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3 |
|---|
| 10617 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10618 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10619 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10620 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10621 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4 |
|---|
| 10622 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10623 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10624 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10625 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10626 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5 |
|---|
| 10627 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10628 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10629 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10630 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10631 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6 |
|---|
| 10632 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10633 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10634 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10635 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10636 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7 |
|---|
| 10637 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10638 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10639 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10640 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10641 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8 |
|---|
| 10642 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10643 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10644 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10645 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10646 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9 |
|---|
| 10647 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10648 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10649 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10650 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10651 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10 |
|---|
| 10652 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10653 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10654 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10655 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10656 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11 |
|---|
| 10657 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10658 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10659 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10660 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10661 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12 |
|---|
| 10662 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10663 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10664 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10665 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10666 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13 |
|---|
| 10667 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10668 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10669 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10670 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10671 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14 |
|---|
| 10672 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10673 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10674 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10675 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10676 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15 |
|---|
| 10677 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10678 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10679 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10680 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10681 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16 |
|---|
| 10682 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10683 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10684 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10685 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10686 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17 |
|---|
| 10687 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10688 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10689 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10690 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10691 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18 |
|---|
| 10692 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10693 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10694 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10695 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10696 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19 |
|---|
| 10697 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10698 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10699 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10700 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10701 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20 |
|---|
| 10702 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10703 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10704 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10705 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10706 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21 |
|---|
| 10707 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10708 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10709 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10710 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10711 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22 |
|---|
| 10712 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10713 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10714 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10715 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10716 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23 |
|---|
| 10717 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10718 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10719 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10720 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10721 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24 |
|---|
| 10722 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10723 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10724 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10725 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10726 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25 |
|---|
| 10727 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10728 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10729 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10730 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10731 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26 |
|---|
| 10732 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10733 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10734 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10735 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10736 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27 |
|---|
| 10737 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10738 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10739 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10740 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10741 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28 |
|---|
| 10742 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10743 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10744 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10745 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10746 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29 |
|---|
| 10747 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10748 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10749 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10750 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10751 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30 |
|---|
| 10752 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10753 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10754 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10755 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10756 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31 |
|---|
| 10757 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10758 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10759 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10760 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10761 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32 |
|---|
| 10762 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10763 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10764 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10765 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10766 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33 |
|---|
| 10767 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10768 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10769 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10770 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10771 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34 |
|---|
| 10772 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10773 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10774 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10775 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10776 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35 |
|---|
| 10777 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10778 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10779 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10780 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10781 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36 |
|---|
| 10782 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10783 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10784 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10785 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10786 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37 |
|---|
| 10787 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10788 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10789 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10790 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10791 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38 |
|---|
| 10792 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10793 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10794 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10795 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10796 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39 |
|---|
| 10797 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10798 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10799 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10800 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10801 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40 |
|---|
| 10802 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10803 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10804 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10805 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10806 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41 |
|---|
| 10807 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10808 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10809 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10810 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10811 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42 |
|---|
| 10812 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10813 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10814 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10815 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10816 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43 |
|---|
| 10817 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10818 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10819 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10820 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10821 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44 |
|---|
| 10822 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10823 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10824 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10825 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10826 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45 |
|---|
| 10827 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10828 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10829 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10830 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10831 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46 |
|---|
| 10832 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10833 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10834 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10835 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10836 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47 |
|---|
| 10837 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10838 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10839 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10840 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10841 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48 |
|---|
| 10842 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10843 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10844 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10845 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10846 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49 |
|---|
| 10847 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10848 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10849 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10850 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10851 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50 |
|---|
| 10852 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10853 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10854 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10855 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10856 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51 |
|---|
| 10857 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10858 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10859 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10860 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10861 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52 |
|---|
| 10862 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10863 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10864 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10865 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10866 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53 |
|---|
| 10867 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10868 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10869 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10870 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10871 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54 |
|---|
| 10872 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10873 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10874 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10875 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10876 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55 |
|---|
| 10877 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10878 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10879 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10880 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10881 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56 |
|---|
| 10882 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10883 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10884 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10885 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10886 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57 |
|---|
| 10887 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10888 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10889 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10890 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10891 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58 |
|---|
| 10892 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10893 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10894 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10895 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10896 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59 |
|---|
| 10897 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10898 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10899 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10900 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10901 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60 |
|---|
| 10902 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10903 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10904 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10905 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10906 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61 |
|---|
| 10907 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10908 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10909 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10910 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10911 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62 |
|---|
| 10912 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10913 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10914 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10915 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10916 | //BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63 |
|---|
| 10917 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 10918 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 10919 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 10920 | #define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 10921 | |
|---|
| 10922 | |
|---|
| 10923 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
|---|
| 10924 | //BIF_CFG_DEV0_EPF3_0_VENDOR_ID |
|---|
| 10925 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 10926 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 10927 | //BIF_CFG_DEV0_EPF3_0_DEVICE_ID |
|---|
| 10928 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 10929 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 10930 | //BIF_CFG_DEV0_EPF3_0_COMMAND |
|---|
| 10931 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 10932 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 10933 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 10934 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 10935 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 10936 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 10937 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 10938 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 10939 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 10940 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 10941 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 10942 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 10943 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 10944 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 10945 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 10946 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 10947 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 10948 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 10949 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 10950 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 10951 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 10952 | #define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 10953 | //BIF_CFG_DEV0_EPF3_0_STATUS |
|---|
| 10954 | #define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 10955 | #define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 10956 | #define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 10957 | #define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 10958 | #define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 10959 | #define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 10960 | #define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 10961 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 10962 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 10963 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 10964 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 10965 | #define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 10966 | #define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 10967 | #define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 10968 | #define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 10969 | #define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 10970 | #define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 10971 | #define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 10972 | #define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 10973 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 10974 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 10975 | #define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 10976 | #define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 10977 | #define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 10978 | //BIF_CFG_DEV0_EPF3_0_REVISION_ID |
|---|
| 10979 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 10980 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 10981 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 10982 | #define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 10983 | //BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE |
|---|
| 10984 | #define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 10985 | #define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 10986 | //BIF_CFG_DEV0_EPF3_0_SUB_CLASS |
|---|
| 10987 | #define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 10988 | #define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 10989 | //BIF_CFG_DEV0_EPF3_0_BASE_CLASS |
|---|
| 10990 | #define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 10991 | #define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 10992 | //BIF_CFG_DEV0_EPF3_0_CACHE_LINE |
|---|
| 10993 | #define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 10994 | #define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 10995 | //BIF_CFG_DEV0_EPF3_0_LATENCY |
|---|
| 10996 | #define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 10997 | #define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 10998 | //BIF_CFG_DEV0_EPF3_0_HEADER |
|---|
| 10999 | #define 0x0 |
|---|
| 11000 | #define 0x7 |
|---|
| 11001 | #define 0x7FL |
|---|
| 11002 | #define 0x80L |
|---|
| 11003 | //BIF_CFG_DEV0_EPF3_0_BIST |
|---|
| 11004 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 11005 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 11006 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 11007 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 11008 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 11009 | #define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 11010 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 |
|---|
| 11011 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 11012 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 11013 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 |
|---|
| 11014 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 11015 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 11016 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 |
|---|
| 11017 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 11018 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 11019 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 |
|---|
| 11020 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 11021 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 11022 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 |
|---|
| 11023 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 11024 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 11025 | //BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 |
|---|
| 11026 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 11027 | #define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 11028 | //BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR |
|---|
| 11029 | #define BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 11030 | #define BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 11031 | //BIF_CFG_DEV0_EPF3_0_ADAPTER_ID |
|---|
| 11032 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 11033 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 11034 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 11035 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 11036 | //BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR |
|---|
| 11037 | #define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 11038 | #define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 11039 | //BIF_CFG_DEV0_EPF3_0_CAP_PTR |
|---|
| 11040 | #define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 11041 | #define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 11042 | //BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE |
|---|
| 11043 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 11044 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 11045 | //BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN |
|---|
| 11046 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 11047 | #define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 11048 | //BIF_CFG_DEV0_EPF3_0_MIN_GRANT |
|---|
| 11049 | #define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 11050 | #define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 11051 | //BIF_CFG_DEV0_EPF3_0_MAX_LATENCY |
|---|
| 11052 | #define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 11053 | #define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 11054 | //BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST |
|---|
| 11055 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11056 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 11057 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 11058 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 11059 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 11060 | #define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 11061 | //BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W |
|---|
| 11062 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 11063 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 11064 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 11065 | #define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 11066 | //BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST |
|---|
| 11067 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11068 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 11069 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 11070 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 11071 | //BIF_CFG_DEV0_EPF3_0_PMI_CAP |
|---|
| 11072 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 11073 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 11074 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 11075 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 11076 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 11077 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 11078 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 11079 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 11080 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 11081 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 11082 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 11083 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 11084 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 11085 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 11086 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 11087 | #define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 11088 | //BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL |
|---|
| 11089 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 11090 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 11091 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 11092 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 11093 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 11094 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 11095 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 11096 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 11097 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 11098 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 11099 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 11100 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 11101 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 11102 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 11103 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 11104 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 11105 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 11106 | #define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 11107 | //BIF_CFG_DEV0_EPF3_0_SBRN |
|---|
| 11108 | #define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT 0x0 |
|---|
| 11109 | #define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK 0xFFL |
|---|
| 11110 | //BIF_CFG_DEV0_EPF3_0_FLADJ |
|---|
| 11111 | #define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT 0x0 |
|---|
| 11112 | #define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC__SHIFT 0x6 |
|---|
| 11113 | #define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK 0x3FL |
|---|
| 11114 | #define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC_MASK 0x40L |
|---|
| 11115 | //BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD |
|---|
| 11116 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT 0x0 |
|---|
| 11117 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
|---|
| 11118 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK 0x0FL |
|---|
| 11119 | #define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK 0xF0L |
|---|
| 11120 | //BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST |
|---|
| 11121 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11122 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 11123 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 11124 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 11125 | //BIF_CFG_DEV0_EPF3_0_PCIE_CAP |
|---|
| 11126 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 11127 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 11128 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 11129 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 11130 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 11131 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 11132 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 11133 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 11134 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CAP |
|---|
| 11135 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 11136 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 11137 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 11138 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 11139 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 11140 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 11141 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 11142 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 11143 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 11144 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 11145 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 11146 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 11147 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 11148 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 11149 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 11150 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 11151 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 11152 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 11153 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL |
|---|
| 11154 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 11155 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 11156 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 11157 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 11158 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 11159 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 11160 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 11161 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 11162 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 11163 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 11164 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 11165 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 11166 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 11167 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 11168 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 11169 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 11170 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 11171 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 11172 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 11173 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 11174 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 11175 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 11176 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 11177 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 11178 | //BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS |
|---|
| 11179 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 11180 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 11181 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 11182 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 11183 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 11184 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 11185 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 11186 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 11187 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 11188 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 11189 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 11190 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 11191 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 11192 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 11193 | //BIF_CFG_DEV0_EPF3_0_LINK_CAP |
|---|
| 11194 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 11195 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 11196 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 11197 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 11198 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 11199 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 11200 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 11201 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 11202 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 11203 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 11204 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 11205 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 11206 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 11207 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 11208 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 11209 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 11210 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 11211 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 11212 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 11213 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 11214 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 11215 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 11216 | //BIF_CFG_DEV0_EPF3_0_LINK_CNTL |
|---|
| 11217 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 11218 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 11219 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 11220 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 11221 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 11222 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 11223 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 11224 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 11225 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 11226 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 11227 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 11228 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 11229 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 11230 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 11231 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 11232 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 11233 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 11234 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 11235 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 11236 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 11237 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 11238 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 11239 | //BIF_CFG_DEV0_EPF3_0_LINK_STATUS |
|---|
| 11240 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 11241 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 11242 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 11243 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 11244 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 11245 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 11246 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 11247 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 11248 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 11249 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 11250 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 11251 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 11252 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 11253 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 11254 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 |
|---|
| 11255 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 11256 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 11257 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 11258 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 11259 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 11260 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 11261 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 11262 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 11263 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 11264 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 11265 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 11266 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 11267 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 11268 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 11269 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 11270 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 11271 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 11272 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 11273 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 11274 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 11275 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 11276 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 11277 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 11278 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 11279 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 11280 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 11281 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 11282 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 11283 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 11284 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 11285 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 11286 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 11287 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 11288 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 11289 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 11290 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 11291 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 11292 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 11293 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 11294 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 11295 | //BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 |
|---|
| 11296 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 11297 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 11298 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 11299 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 11300 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 11301 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 11302 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 11303 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 11304 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 11305 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 11306 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 11307 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 11308 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 11309 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 11310 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 11311 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 11312 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 11313 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 11314 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 11315 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 11316 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 11317 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 11318 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 11319 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 11320 | //BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 |
|---|
| 11321 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 11322 | #define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 11323 | //BIF_CFG_DEV0_EPF3_0_LINK_CAP2 |
|---|
| 11324 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 11325 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 11326 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 11327 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 11328 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 11329 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 11330 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 11331 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 11332 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 11333 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 11334 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 11335 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 11336 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 11337 | #define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 11338 | //BIF_CFG_DEV0_EPF3_0_LINK_CNTL2 |
|---|
| 11339 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 11340 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 11341 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 11342 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 11343 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 11344 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 11345 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 11346 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 11347 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 11348 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 11349 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 11350 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 11351 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 11352 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 11353 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 11354 | #define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 11355 | //BIF_CFG_DEV0_EPF3_0_LINK_STATUS2 |
|---|
| 11356 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 11357 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 11358 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 11359 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 11360 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 11361 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 11362 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 11363 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 11364 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 11365 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 11366 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 11367 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 11368 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 11369 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 11370 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 11371 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 11372 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 11373 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 11374 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 11375 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 11376 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 11377 | #define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 11378 | //BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST |
|---|
| 11379 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11380 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 11381 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 11382 | #define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 11383 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL |
|---|
| 11384 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 11385 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 11386 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 11387 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 11388 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 11389 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 11390 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 11391 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 11392 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 11393 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 11394 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO |
|---|
| 11395 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 11396 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 11397 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI |
|---|
| 11398 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 11399 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 11400 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA |
|---|
| 11401 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 11402 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 11403 | //BIF_CFG_DEV0_EPF3_0_MSI_MASK |
|---|
| 11404 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 11405 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 11406 | //BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 |
|---|
| 11407 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 11408 | #define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 11409 | //BIF_CFG_DEV0_EPF3_0_MSI_MASK_64 |
|---|
| 11410 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 11411 | #define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 11412 | //BIF_CFG_DEV0_EPF3_0_MSI_PENDING |
|---|
| 11413 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 11414 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 11415 | //BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 |
|---|
| 11416 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 11417 | #define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 11418 | //BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST |
|---|
| 11419 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11420 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 11421 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 11422 | #define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 11423 | //BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL |
|---|
| 11424 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 11425 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 11426 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 11427 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 11428 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 11429 | #define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 11430 | //BIF_CFG_DEV0_EPF3_0_MSIX_TABLE |
|---|
| 11431 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 11432 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 11433 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 11434 | #define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 11435 | //BIF_CFG_DEV0_EPF3_0_MSIX_PBA |
|---|
| 11436 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 11437 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 11438 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 11439 | #define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 11440 | //BIF_CFG_DEV0_EPF3_0_SATA_CAP_0 |
|---|
| 11441 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
|---|
| 11442 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
|---|
| 11443 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
|---|
| 11444 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
|---|
| 11445 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
|---|
| 11446 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
|---|
| 11447 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 11448 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
|---|
| 11449 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
|---|
| 11450 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
|---|
| 11451 | //BIF_CFG_DEV0_EPF3_0_SATA_CAP_1 |
|---|
| 11452 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
|---|
| 11453 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
|---|
| 11454 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
|---|
| 11455 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
|---|
| 11456 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
|---|
| 11457 | #define BIF_CFG_DEV0_EPF3_0_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
|---|
| 11458 | //BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX |
|---|
| 11459 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
|---|
| 11460 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
|---|
| 11461 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
|---|
| 11462 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
|---|
| 11463 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
|---|
| 11464 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
|---|
| 11465 | //BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA |
|---|
| 11466 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
|---|
| 11467 | #define BIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
|---|
| 11468 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 11469 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11470 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 11471 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 11472 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 11473 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 11474 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 11475 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 11476 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 11477 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 11478 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 11479 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 11480 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 11481 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 11482 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 11483 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 11484 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 11485 | //BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 11486 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 11487 | #define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 11488 | //BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 11489 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11490 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 11491 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 11492 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 11493 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 11494 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 11495 | //BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 11496 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 11497 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 11498 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 11499 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 11500 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 11501 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 11502 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 11503 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 11504 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 11505 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 11506 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 11507 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 11508 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 11509 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 11510 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 11511 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 11512 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 11513 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 11514 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 11515 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 11516 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 11517 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 11518 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 11519 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 11520 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 11521 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 11522 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 11523 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 11524 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 11525 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 11526 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 11527 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 11528 | //BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK |
|---|
| 11529 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 11530 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 11531 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 11532 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 11533 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 11534 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 11535 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 11536 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 11537 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 11538 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 11539 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 11540 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 11541 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 11542 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 11543 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 11544 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 11545 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 11546 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 11547 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 11548 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 11549 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 11550 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 11551 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 11552 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 11553 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 11554 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 11555 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 11556 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 11557 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 11558 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 11559 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 11560 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 11561 | //BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 11562 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 11563 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 11564 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 11565 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 11566 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 11567 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 11568 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 11569 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 11570 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 11571 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 11572 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 11573 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 11574 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 11575 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 11576 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 11577 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 11578 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 11579 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 11580 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 11581 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 11582 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 11583 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 11584 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 11585 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 11586 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 11587 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 11588 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 11589 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 11590 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 11591 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 11592 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 11593 | #define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 11594 | //BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS |
|---|
| 11595 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 11596 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 11597 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 11598 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 11599 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 11600 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 11601 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 11602 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 11603 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 11604 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 11605 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 11606 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 11607 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 11608 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 11609 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 11610 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 11611 | //BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK |
|---|
| 11612 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 11613 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 11614 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 11615 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 11616 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 11617 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 11618 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 11619 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 11620 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 11621 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 11622 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 11623 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 11624 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 11625 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 11626 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 11627 | #define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 11628 | //BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 11629 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 11630 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 11631 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 11632 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 11633 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 11634 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 11635 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 11636 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 11637 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 11638 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 11639 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 11640 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 11641 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 11642 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 11643 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 11644 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 11645 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 11646 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 11647 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 |
|---|
| 11648 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 11649 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 11650 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 |
|---|
| 11651 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 11652 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 11653 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 |
|---|
| 11654 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 11655 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 11656 | //BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 |
|---|
| 11657 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 11658 | #define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 11659 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 11660 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 11661 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 11662 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 11663 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 11664 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 11665 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 11666 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 11667 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 11668 | //BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 11669 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 11670 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 11671 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST |
|---|
| 11672 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11673 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 11674 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 11675 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 11676 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 11677 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 11678 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP |
|---|
| 11679 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 11680 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 11681 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL |
|---|
| 11682 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 11683 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 11684 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 11685 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 11686 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 11687 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 11688 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP |
|---|
| 11689 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 11690 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 11691 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL |
|---|
| 11692 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 11693 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 11694 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 11695 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 11696 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 11697 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 11698 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP |
|---|
| 11699 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 11700 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 11701 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL |
|---|
| 11702 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 11703 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 11704 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 11705 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 11706 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 11707 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 11708 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP |
|---|
| 11709 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 11710 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 11711 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL |
|---|
| 11712 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 11713 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 11714 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 11715 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 11716 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 11717 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 11718 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP |
|---|
| 11719 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 11720 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 11721 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL |
|---|
| 11722 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 11723 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 11724 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 11725 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 11726 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 11727 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 11728 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP |
|---|
| 11729 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 11730 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 11731 | //BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL |
|---|
| 11732 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 11733 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 11734 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 11735 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 11736 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 11737 | #define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 11738 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 11739 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11740 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 11741 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 11742 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 11743 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 11744 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 11745 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 11746 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 11747 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 11748 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA |
|---|
| 11749 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 11750 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 11751 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 11752 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 11753 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 11754 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 11755 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 11756 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 11757 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 11758 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 11759 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 11760 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 11761 | //BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP |
|---|
| 11762 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 11763 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 11764 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST |
|---|
| 11765 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11766 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 11767 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 11768 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 11769 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 11770 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 11771 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP |
|---|
| 11772 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 11773 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 11774 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 11775 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 11776 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 11777 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 11778 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 11779 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 11780 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 11781 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 11782 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 11783 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 11784 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 11785 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS |
|---|
| 11786 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 11787 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 11788 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 11789 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 11790 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL |
|---|
| 11791 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 11792 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 11793 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 11794 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 11795 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 11796 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 11797 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 11798 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 11799 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 11800 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 11801 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 11802 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 11803 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 11804 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 11805 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 11806 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 11807 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 11808 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 11809 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 11810 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 11811 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 11812 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 11813 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 11814 | //BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 11815 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 11816 | #define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 11817 | //BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST |
|---|
| 11818 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11819 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 11820 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 11821 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 11822 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 11823 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 11824 | //BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP |
|---|
| 11825 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 11826 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 11827 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 11828 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 11829 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 11830 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 11831 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 11832 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 11833 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 11834 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 11835 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 11836 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 11837 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 11838 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 11839 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 11840 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 11841 | //BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL |
|---|
| 11842 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 11843 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 11844 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 11845 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 11846 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 11847 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 11848 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 11849 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 11850 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 11851 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 11852 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 11853 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 11854 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 11855 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 11856 | //BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST |
|---|
| 11857 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11858 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 11859 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 11860 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 11861 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 11862 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 11863 | //BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP |
|---|
| 11864 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 11865 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 11866 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 11867 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 11868 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 11869 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 11870 | //BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL |
|---|
| 11871 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 11872 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 11873 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 11874 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 11875 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 11876 | #define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 11877 | //BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 11878 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11879 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 11880 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 11881 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 11882 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 11883 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 11884 | //BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP |
|---|
| 11885 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 11886 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 11887 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 11888 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 11889 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 11890 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 11891 | //BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL |
|---|
| 11892 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 11893 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 11894 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 11895 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 11896 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 11897 | #define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 11898 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 11899 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 11900 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 11901 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 11902 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 11903 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 11904 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 11905 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP |
|---|
| 11906 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 11907 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 11908 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 11909 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 11910 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 11911 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 11912 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 11913 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 11914 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 11915 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 11916 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 11917 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 11918 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL |
|---|
| 11919 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 11920 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 11921 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 11922 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 11923 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0 |
|---|
| 11924 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11925 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11926 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11927 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11928 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1 |
|---|
| 11929 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11930 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11931 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11932 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11933 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2 |
|---|
| 11934 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11935 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11936 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11937 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11938 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3 |
|---|
| 11939 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11940 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11941 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11942 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11943 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4 |
|---|
| 11944 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11945 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11946 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11947 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11948 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5 |
|---|
| 11949 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11950 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11951 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11952 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11953 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6 |
|---|
| 11954 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11955 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11956 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11957 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11958 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7 |
|---|
| 11959 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11960 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11961 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11962 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11963 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8 |
|---|
| 11964 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11965 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11966 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11967 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11968 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9 |
|---|
| 11969 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11970 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11971 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11972 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11973 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10 |
|---|
| 11974 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11975 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11976 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11977 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11978 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11 |
|---|
| 11979 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11980 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11981 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11982 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11983 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12 |
|---|
| 11984 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11985 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11986 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11987 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11988 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13 |
|---|
| 11989 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11990 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11991 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11992 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11993 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14 |
|---|
| 11994 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 11995 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 11996 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 11997 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 11998 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15 |
|---|
| 11999 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12000 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12001 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12002 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12003 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16 |
|---|
| 12004 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12005 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12006 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12007 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12008 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17 |
|---|
| 12009 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12010 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12011 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12012 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12013 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18 |
|---|
| 12014 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12015 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12016 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12017 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12018 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19 |
|---|
| 12019 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12020 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12021 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12022 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12023 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20 |
|---|
| 12024 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12025 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12026 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12027 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12028 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21 |
|---|
| 12029 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12030 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12031 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12032 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12033 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22 |
|---|
| 12034 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12035 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12036 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12037 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12038 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23 |
|---|
| 12039 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12040 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12041 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12042 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12043 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24 |
|---|
| 12044 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12045 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12046 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12047 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12048 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25 |
|---|
| 12049 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12050 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12051 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12052 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12053 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26 |
|---|
| 12054 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12055 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12056 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12057 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12058 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27 |
|---|
| 12059 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12060 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12061 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12062 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12063 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28 |
|---|
| 12064 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12065 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12066 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12067 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12068 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29 |
|---|
| 12069 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12070 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12071 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12072 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12073 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30 |
|---|
| 12074 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12075 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12076 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12077 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12078 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31 |
|---|
| 12079 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12080 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12081 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12082 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12083 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32 |
|---|
| 12084 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12085 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12086 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12087 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12088 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33 |
|---|
| 12089 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12090 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12091 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12092 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12093 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34 |
|---|
| 12094 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12095 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12096 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12097 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12098 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35 |
|---|
| 12099 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12100 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12101 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12102 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12103 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36 |
|---|
| 12104 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12105 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12106 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12107 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12108 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37 |
|---|
| 12109 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12110 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12111 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12112 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12113 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38 |
|---|
| 12114 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12115 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12116 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12117 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12118 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39 |
|---|
| 12119 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12120 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12121 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12122 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12123 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40 |
|---|
| 12124 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12125 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12126 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12127 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12128 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41 |
|---|
| 12129 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12130 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12131 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12132 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12133 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42 |
|---|
| 12134 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12135 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12136 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12137 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12138 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43 |
|---|
| 12139 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12140 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12141 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12142 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12143 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44 |
|---|
| 12144 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12145 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12146 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12147 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12148 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45 |
|---|
| 12149 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12150 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12151 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12152 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12153 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46 |
|---|
| 12154 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12155 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12156 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12157 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12158 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47 |
|---|
| 12159 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12160 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12161 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12162 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12163 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48 |
|---|
| 12164 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12165 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12166 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12167 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12168 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49 |
|---|
| 12169 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12170 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12171 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12172 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12173 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50 |
|---|
| 12174 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12175 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12176 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12177 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12178 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51 |
|---|
| 12179 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12180 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12181 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12182 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12183 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52 |
|---|
| 12184 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12185 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12186 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12187 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12188 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53 |
|---|
| 12189 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12190 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12191 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12192 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12193 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54 |
|---|
| 12194 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12195 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12196 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12197 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12198 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55 |
|---|
| 12199 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12200 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12201 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12202 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12203 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56 |
|---|
| 12204 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12205 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12206 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12207 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12208 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57 |
|---|
| 12209 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12210 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12211 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12212 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12213 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58 |
|---|
| 12214 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12215 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12216 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12217 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12218 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59 |
|---|
| 12219 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12220 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12221 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12222 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12223 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60 |
|---|
| 12224 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12225 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12226 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12227 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12228 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61 |
|---|
| 12229 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12230 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12231 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12232 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12233 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62 |
|---|
| 12234 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12235 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12236 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12237 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12238 | //BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63 |
|---|
| 12239 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 12240 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 12241 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 12242 | #define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 12243 | |
|---|
| 12244 | |
|---|
| 12245 | // addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect |
|---|
| 12246 | //SYSHUB_DS_CTRL_SOCCLK |
|---|
| 12247 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 |
|---|
| 12248 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 |
|---|
| 12249 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 |
|---|
| 12250 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 |
|---|
| 12251 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 |
|---|
| 12252 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 |
|---|
| 12253 | #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x8 |
|---|
| 12254 | #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x9 |
|---|
| 12255 | #define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c |
|---|
| 12256 | #define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f |
|---|
| 12257 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000001L |
|---|
| 12258 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L |
|---|
| 12259 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000004L |
|---|
| 12260 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000008L |
|---|
| 12261 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000010L |
|---|
| 12262 | #define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000020L |
|---|
| 12263 | #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000100L |
|---|
| 12264 | #define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000200L |
|---|
| 12265 | #define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L |
|---|
| 12266 | #define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK 0x80000000L |
|---|
| 12267 | //SYSHUB_DS_CTRL2_SOCCLK |
|---|
| 12268 | #define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 |
|---|
| 12269 | #define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK 0x0000FFFFL |
|---|
| 12270 | //SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK |
|---|
| 12271 | #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 |
|---|
| 12272 | #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 |
|---|
| 12273 | #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0x10 |
|---|
| 12274 | #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK 0x00000001L |
|---|
| 12275 | #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK 0x00000002L |
|---|
| 12276 | #define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK 0x00010000L |
|---|
| 12277 | //SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK |
|---|
| 12278 | #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 |
|---|
| 12279 | #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 |
|---|
| 12280 | #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0x10 |
|---|
| 12281 | #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK 0x00000001L |
|---|
| 12282 | #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK 0x00000002L |
|---|
| 12283 | #define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK 0x00010000L |
|---|
| 12284 | //SYSHUB_TRANS_IDLE_SOCCLK |
|---|
| 12285 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF0_SOCCLK__SHIFT 0x0 |
|---|
| 12286 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF1_SOCCLK__SHIFT 0x1 |
|---|
| 12287 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF2_SOCCLK__SHIFT 0x2 |
|---|
| 12288 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF3_SOCCLK__SHIFT 0x3 |
|---|
| 12289 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF4_SOCCLK__SHIFT 0x4 |
|---|
| 12290 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF5_SOCCLK__SHIFT 0x5 |
|---|
| 12291 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF6_SOCCLK__SHIFT 0x6 |
|---|
| 12292 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF7_SOCCLK__SHIFT 0x7 |
|---|
| 12293 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF8_SOCCLK__SHIFT 0x8 |
|---|
| 12294 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF9_SOCCLK__SHIFT 0x9 |
|---|
| 12295 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF10_SOCCLK__SHIFT 0xa |
|---|
| 12296 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF11_SOCCLK__SHIFT 0xb |
|---|
| 12297 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF12_SOCCLK__SHIFT 0xc |
|---|
| 12298 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF13_SOCCLK__SHIFT 0xd |
|---|
| 12299 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF14_SOCCLK__SHIFT 0xe |
|---|
| 12300 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF15_SOCCLK__SHIFT 0xf |
|---|
| 12301 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF16_SOCCLK__SHIFT 0x10 |
|---|
| 12302 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF17_SOCCLK__SHIFT 0x11 |
|---|
| 12303 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF18_SOCCLK__SHIFT 0x12 |
|---|
| 12304 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF19_SOCCLK__SHIFT 0x13 |
|---|
| 12305 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF20_SOCCLK__SHIFT 0x14 |
|---|
| 12306 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF21_SOCCLK__SHIFT 0x15 |
|---|
| 12307 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF22_SOCCLK__SHIFT 0x16 |
|---|
| 12308 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF23_SOCCLK__SHIFT 0x17 |
|---|
| 12309 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF24_SOCCLK__SHIFT 0x18 |
|---|
| 12310 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF25_SOCCLK__SHIFT 0x19 |
|---|
| 12311 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF26_SOCCLK__SHIFT 0x1a |
|---|
| 12312 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF27_SOCCLK__SHIFT 0x1b |
|---|
| 12313 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF28_SOCCLK__SHIFT 0x1c |
|---|
| 12314 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF29_SOCCLK__SHIFT 0x1d |
|---|
| 12315 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF30_SOCCLK__SHIFT 0x1e |
|---|
| 12316 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_PF_SOCCLK__SHIFT 0x1f |
|---|
| 12317 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF0_SOCCLK_MASK 0x00000001L |
|---|
| 12318 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF1_SOCCLK_MASK 0x00000002L |
|---|
| 12319 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF2_SOCCLK_MASK 0x00000004L |
|---|
| 12320 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF3_SOCCLK_MASK 0x00000008L |
|---|
| 12321 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF4_SOCCLK_MASK 0x00000010L |
|---|
| 12322 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF5_SOCCLK_MASK 0x00000020L |
|---|
| 12323 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF6_SOCCLK_MASK 0x00000040L |
|---|
| 12324 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF7_SOCCLK_MASK 0x00000080L |
|---|
| 12325 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF8_SOCCLK_MASK 0x00000100L |
|---|
| 12326 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF9_SOCCLK_MASK 0x00000200L |
|---|
| 12327 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF10_SOCCLK_MASK 0x00000400L |
|---|
| 12328 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF11_SOCCLK_MASK 0x00000800L |
|---|
| 12329 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF12_SOCCLK_MASK 0x00001000L |
|---|
| 12330 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF13_SOCCLK_MASK 0x00002000L |
|---|
| 12331 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF14_SOCCLK_MASK 0x00004000L |
|---|
| 12332 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF15_SOCCLK_MASK 0x00008000L |
|---|
| 12333 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF16_SOCCLK_MASK 0x00010000L |
|---|
| 12334 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF17_SOCCLK_MASK 0x00020000L |
|---|
| 12335 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF18_SOCCLK_MASK 0x00040000L |
|---|
| 12336 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF19_SOCCLK_MASK 0x00080000L |
|---|
| 12337 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF20_SOCCLK_MASK 0x00100000L |
|---|
| 12338 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF21_SOCCLK_MASK 0x00200000L |
|---|
| 12339 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF22_SOCCLK_MASK 0x00400000L |
|---|
| 12340 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF23_SOCCLK_MASK 0x00800000L |
|---|
| 12341 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF24_SOCCLK_MASK 0x01000000L |
|---|
| 12342 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF25_SOCCLK_MASK 0x02000000L |
|---|
| 12343 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF26_SOCCLK_MASK 0x04000000L |
|---|
| 12344 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF27_SOCCLK_MASK 0x08000000L |
|---|
| 12345 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF28_SOCCLK_MASK 0x10000000L |
|---|
| 12346 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF29_SOCCLK_MASK 0x20000000L |
|---|
| 12347 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_VF30_SOCCLK_MASK 0x40000000L |
|---|
| 12348 | #define SYSHUB_TRANS_IDLE_SOCCLK__SYSHUB_TRANS_IDLE_PF_SOCCLK_MASK 0x80000000L |
|---|
| 12349 | //SYSHUB_HP_TIMER_SOCCLK |
|---|
| 12350 | #define SYSHUB_HP_TIMER_SOCCLK__SYSHUB_HP_TIMER_SOCCLK__SHIFT 0x0 |
|---|
| 12351 | #define SYSHUB_HP_TIMER_SOCCLK__SYSHUB_HP_TIMER_SOCCLK_MASK 0xFFFFFFFFL |
|---|
| 12352 | //SYSHUB_MGCG_CTRL_SOCCLK |
|---|
| 12353 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT 0x0 |
|---|
| 12354 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT 0x1 |
|---|
| 12355 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT 0x2 |
|---|
| 12356 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT 0xa |
|---|
| 12357 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT 0xb |
|---|
| 12358 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REG_DIS_SOCCLK__SHIFT 0xc |
|---|
| 12359 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT 0xd |
|---|
| 12360 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK 0x00000001L |
|---|
| 12361 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK 0x00000002L |
|---|
| 12362 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK 0x000003FCL |
|---|
| 12363 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK 0x00000400L |
|---|
| 12364 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK 0x00000800L |
|---|
| 12365 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REG_DIS_SOCCLK_MASK 0x00001000L |
|---|
| 12366 | #define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK 0x00002000L |
|---|
| 12367 | //SYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK |
|---|
| 12368 | #define SYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK__SYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK__SHIFT 0x0 |
|---|
| 12369 | #define SYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK__SYSHUB_CPF_DOORBELL_RS_RESET_SOCCLK_MASK 0x00000001L |
|---|
| 12370 | //SYSHUB_SCRATCH_SOCCLK |
|---|
| 12371 | #define SYSHUB_SCRATCH_SOCCLK__SCRATCH_SOCCLK__SHIFT 0x0 |
|---|
| 12372 | #define SYSHUB_SCRATCH_SOCCLK__SCRATCH_SOCCLK_MASK 0xFFFFFFFFL |
|---|
| 12373 | //SYSHUB_CL_MASK_SOCCLK |
|---|
| 12374 | #define SYSHUB_CL_MASK_SOCCLK__DBGU_MASK_DIS_SOCCLK__SHIFT 0x0 |
|---|
| 12375 | #define SYSHUB_CL_MASK_SOCCLK__MP1DRAM_MASK_DIS_SOCCLK__SHIFT 0x1 |
|---|
| 12376 | #define SYSHUB_CL_MASK_SOCCLK__MP1_MASK_DIS_SOCCLK__SHIFT 0x2 |
|---|
| 12377 | #define SYSHUB_CL_MASK_SOCCLK__DBGU_MASK_DIS_SOCCLK_MASK 0x00000001L |
|---|
| 12378 | #define SYSHUB_CL_MASK_SOCCLK__MP1DRAM_MASK_DIS_SOCCLK_MASK 0x00000002L |
|---|
| 12379 | #define SYSHUB_CL_MASK_SOCCLK__MP1_MASK_DIS_SOCCLK_MASK 0x00000004L |
|---|
| 12380 | //SYSHUB_HANG_CNTL_SOCCLK |
|---|
| 12381 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL0__SHIFT 0x0 |
|---|
| 12382 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL1__SHIFT 0x1 |
|---|
| 12383 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL2__SHIFT 0x2 |
|---|
| 12384 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL0__SHIFT 0x3 |
|---|
| 12385 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL1__SHIFT 0x4 |
|---|
| 12386 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL2__SHIFT 0x5 |
|---|
| 12387 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL0_MASK 0x00000001L |
|---|
| 12388 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL1_MASK 0x00000002L |
|---|
| 12389 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW0_CL2_MASK 0x00000004L |
|---|
| 12390 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL0_MASK 0x00000008L |
|---|
| 12391 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL1_MASK 0x00000010L |
|---|
| 12392 | #define SYSHUB_HANG_CNTL_SOCCLK__DROP_UNEXPECTED_RESP_DIS_SOCCLK_SW1_CL2_MASK 0x00000020L |
|---|
| 12393 | //HST_CLK0_SW0_CL0_CNTL |
|---|
| 12394 | #define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
|---|
| 12395 | #define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
|---|
| 12396 | #define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
|---|
| 12397 | #define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
|---|
| 12398 | //HST_CLK0_SW0_CL1_CNTL |
|---|
| 12399 | #define HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
|---|
| 12400 | #define HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
|---|
| 12401 | #define HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
|---|
| 12402 | #define HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
|---|
| 12403 | //HST_CLK0_SW0_CL2_CNTL |
|---|
| 12404 | #define HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
|---|
| 12405 | #define HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
|---|
| 12406 | #define HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
|---|
| 12407 | #define HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
|---|
| 12408 | //HST_CLK0_SW1_CL0_CNTL |
|---|
| 12409 | #define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
|---|
| 12410 | #define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
|---|
| 12411 | #define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
|---|
| 12412 | #define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
|---|
| 12413 | //HST_CLK0_SW1_CL1_CNTL |
|---|
| 12414 | #define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
|---|
| 12415 | #define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
|---|
| 12416 | #define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
|---|
| 12417 | #define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
|---|
| 12418 | //HST_CLK0_SW1_CL2_CNTL |
|---|
| 12419 | #define HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
|---|
| 12420 | #define HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
|---|
| 12421 | #define HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
|---|
| 12422 | #define HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
|---|
| 12423 | //DMA_CLK0_SW0_SYSHUB_QOS_CNTL |
|---|
| 12424 | #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 |
|---|
| 12425 | #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 |
|---|
| 12426 | #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 |
|---|
| 12427 | #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK 0x00000001L |
|---|
| 12428 | #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK 0x0000001EL |
|---|
| 12429 | #define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK 0x000001E0L |
|---|
| 12430 | //DMA_CLK0_SW0_CL0_CNTL |
|---|
| 12431 | #define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
|---|
| 12432 | #define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
|---|
| 12433 | #define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
|---|
| 12434 | #define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
|---|
| 12435 | #define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
|---|
| 12436 | #define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
|---|
| 12437 | #define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
|---|
| 12438 | #define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
|---|
| 12439 | #define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
|---|
| 12440 | #define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
|---|
| 12441 | #define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
|---|
| 12442 | #define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
|---|
| 12443 | //DMA_CLK0_SW0_CL1_CNTL |
|---|
| 12444 | #define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
|---|
| 12445 | #define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
|---|
| 12446 | #define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 |
|---|
| 12447 | #define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 |
|---|
| 12448 | #define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 |
|---|
| 12449 | #define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 |
|---|
| 12450 | #define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
|---|
| 12451 | #define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
|---|
| 12452 | #define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L |
|---|
| 12453 | #define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L |
|---|
| 12454 | #define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L |
|---|
| 12455 | #define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L |
|---|
| 12456 | //SYSHUB_DS_CTRL_SHUBCLK |
|---|
| 12457 | #define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c |
|---|
| 12458 | #define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f |
|---|
| 12459 | #define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x10000000L |
|---|
| 12460 | #define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK 0x80000000L |
|---|
| 12461 | //SYSHUB_DS_CTRL2_SHUBCLK |
|---|
| 12462 | #define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 |
|---|
| 12463 | #define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK 0x0000FFFFL |
|---|
| 12464 | //SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK |
|---|
| 12465 | //SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK |
|---|
| 12466 | //SYSHUB_MGCG_CTRL_SHUBCLK |
|---|
| 12467 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT 0x0 |
|---|
| 12468 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT 0x1 |
|---|
| 12469 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT 0x2 |
|---|
| 12470 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT 0xa |
|---|
| 12471 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT 0xb |
|---|
| 12472 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REG_DIS_SHUBCLK__SHIFT 0xc |
|---|
| 12473 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_AER_DIS_SHUBCLK__SHIFT 0xd |
|---|
| 12474 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK 0x00000001L |
|---|
| 12475 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK 0x00000002L |
|---|
| 12476 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK 0x000003FCL |
|---|
| 12477 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK 0x00000400L |
|---|
| 12478 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK 0x00000800L |
|---|
| 12479 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REG_DIS_SHUBCLK_MASK 0x00001000L |
|---|
| 12480 | #define SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_AER_DIS_SHUBCLK_MASK 0x00002000L |
|---|
| 12481 | //SYSHUB_SCRATCH_SHUBCLK |
|---|
| 12482 | #define SYSHUB_SCRATCH_SHUBCLK__SCRATCH_SHUBCLK__SHIFT 0x0 |
|---|
| 12483 | #define SYSHUB_SCRATCH_SHUBCLK__SCRATCH_SHUBCLK_MASK 0xFFFFFFFFL |
|---|
| 12484 | //SYSHUB_SELECT_SHUBCLK |
|---|
| 12485 | #define SYSHUB_SELECT_SHUBCLK__SELECT_USB0__SHIFT 0x0 |
|---|
| 12486 | #define SYSHUB_SELECT_SHUBCLK__SELECT_USB1__SHIFT 0x1 |
|---|
| 12487 | #define SYSHUB_SELECT_SHUBCLK__SELECT_USB0_MASK 0x00000001L |
|---|
| 12488 | #define SYSHUB_SELECT_SHUBCLK__SELECT_USB1_MASK 0x00000002L |
|---|
| 12489 | //SYSHUB_SCRATCH_LCLK |
|---|
| 12490 | #define SYSHUB_SCRATCH_LCLK__SCRATCH_LCLK__SHIFT 0x0 |
|---|
| 12491 | #define SYSHUB_SCRATCH_LCLK__SCRATCH_LCLK_MASK 0xFFFFFFFFL |
|---|
| 12492 | //NIC400_0_ASIB_0_FN_MOD |
|---|
| 12493 | #define NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
|---|
| 12494 | #define NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
|---|
| 12495 | #define NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
|---|
| 12496 | #define NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
|---|
| 12497 | //NIC400_0_AMIB_0_FN_MOD_BM_ISS |
|---|
| 12498 | #define NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
|---|
| 12499 | #define NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
|---|
| 12500 | #define NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
|---|
| 12501 | #define NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
|---|
| 12502 | //NIC400_0_AMIB_1_FN_MOD_BM_ISS |
|---|
| 12503 | #define NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
|---|
| 12504 | #define NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
|---|
| 12505 | #define NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
|---|
| 12506 | #define NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
|---|
| 12507 | //NIC400_0_AMIB_2_FN_MOD_BM_ISS |
|---|
| 12508 | #define NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
|---|
| 12509 | #define NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
|---|
| 12510 | #define NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
|---|
| 12511 | #define NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
|---|
| 12512 | //NIC400_0_IB_0_FN_MOD |
|---|
| 12513 | #define NIC400_0_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
|---|
| 12514 | #define NIC400_0_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
|---|
| 12515 | #define NIC400_0_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
|---|
| 12516 | #define NIC400_0_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
|---|
| 12517 | //NIC400_1_ASIB_0_FN_MOD |
|---|
| 12518 | #define NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
|---|
| 12519 | #define NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
|---|
| 12520 | #define NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
|---|
| 12521 | #define NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
|---|
| 12522 | //NIC400_1_AMIB_0_FN_MOD_BM_ISS |
|---|
| 12523 | #define NIC400_1_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
|---|
| 12524 | #define NIC400_1_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
|---|
| 12525 | #define NIC400_1_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
|---|
| 12526 | #define NIC400_1_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
|---|
| 12527 | //NIC400_1_AMIB_1_FN_MOD_BM_ISS |
|---|
| 12528 | #define NIC400_1_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
|---|
| 12529 | #define NIC400_1_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
|---|
| 12530 | #define NIC400_1_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
|---|
| 12531 | #define NIC400_1_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
|---|
| 12532 | //NIC400_1_AMIB_2_FN_MOD_BM_ISS |
|---|
| 12533 | #define NIC400_1_AMIB_2_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
|---|
| 12534 | #define NIC400_1_AMIB_2_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
|---|
| 12535 | #define NIC400_1_AMIB_2_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
|---|
| 12536 | #define NIC400_1_AMIB_2_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
|---|
| 12537 | //NIC400_1_IB_0_FN_MOD |
|---|
| 12538 | #define NIC400_1_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
|---|
| 12539 | #define NIC400_1_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
|---|
| 12540 | #define NIC400_1_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
|---|
| 12541 | #define NIC400_1_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
|---|
| 12542 | //NIC400_2_AMIB_0_FN_MOD_BM_ISS |
|---|
| 12543 | #define NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT 0x0 |
|---|
| 12544 | #define NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT 0x1 |
|---|
| 12545 | #define NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK 0x00000001L |
|---|
| 12546 | #define NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK 0x00000002L |
|---|
| 12547 | //NIC400_2_ASIB_0_FN_MOD |
|---|
| 12548 | #define NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
|---|
| 12549 | #define NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
|---|
| 12550 | #define NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
|---|
| 12551 | #define NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
|---|
| 12552 | //NIC400_2_ASIB_0_QOS_CNTL |
|---|
| 12553 | #define NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT 0x0 |
|---|
| 12554 | #define NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT 0x1 |
|---|
| 12555 | #define NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT 0x2 |
|---|
| 12556 | #define NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT 0x3 |
|---|
| 12557 | #define NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT 0x4 |
|---|
| 12558 | #define NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT 0x5 |
|---|
| 12559 | #define NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT 0x6 |
|---|
| 12560 | #define NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT 0x7 |
|---|
| 12561 | #define NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT 0x10 |
|---|
| 12562 | #define NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT 0x14 |
|---|
| 12563 | #define NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate_MASK 0x00000001L |
|---|
| 12564 | #define NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate_MASK 0x00000002L |
|---|
| 12565 | #define NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate_MASK 0x00000004L |
|---|
| 12566 | #define NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc_MASK 0x00000008L |
|---|
| 12567 | #define NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc_MASK 0x00000010L |
|---|
| 12568 | #define NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot_MASK 0x00000020L |
|---|
| 12569 | #define NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot_MASK 0x00000040L |
|---|
| 12570 | #define NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot_MASK 0x00000080L |
|---|
| 12571 | #define NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc_MASK 0x00010000L |
|---|
| 12572 | #define NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc_MASK 0x00100000L |
|---|
| 12573 | //NIC400_2_ASIB_0_MAX_OT |
|---|
| 12574 | #define NIC400_2_ASIB_0_MAX_OT__aw_max_otf__SHIFT 0x0 |
|---|
| 12575 | #define NIC400_2_ASIB_0_MAX_OT__aw_max_oti__SHIFT 0x8 |
|---|
| 12576 | #define NIC400_2_ASIB_0_MAX_OT__ar_max_otf__SHIFT 0x10 |
|---|
| 12577 | #define NIC400_2_ASIB_0_MAX_OT__ar_max_oti__SHIFT 0x18 |
|---|
| 12578 | #define NIC400_2_ASIB_0_MAX_OT__aw_max_otf_MASK 0x000000FFL |
|---|
| 12579 | #define NIC400_2_ASIB_0_MAX_OT__aw_max_oti_MASK 0x00003F00L |
|---|
| 12580 | #define NIC400_2_ASIB_0_MAX_OT__ar_max_otf_MASK 0x00FF0000L |
|---|
| 12581 | #define NIC400_2_ASIB_0_MAX_OT__ar_max_oti_MASK 0x3F000000L |
|---|
| 12582 | //NIC400_2_ASIB_0_MAX_COMB_OT |
|---|
| 12583 | #define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 |
|---|
| 12584 | #define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 |
|---|
| 12585 | #define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL |
|---|
| 12586 | #define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L |
|---|
| 12587 | //NIC400_2_ASIB_0_AW_P |
|---|
| 12588 | #define NIC400_2_ASIB_0_AW_P__aw_p__SHIFT 0x18 |
|---|
| 12589 | #define NIC400_2_ASIB_0_AW_P__aw_p_MASK 0xFF000000L |
|---|
| 12590 | //NIC400_2_ASIB_0_AW_B |
|---|
| 12591 | #define NIC400_2_ASIB_0_AW_B__aw_b__SHIFT 0x0 |
|---|
| 12592 | #define NIC400_2_ASIB_0_AW_B__aw_b_MASK 0x0000FFFFL |
|---|
| 12593 | //NIC400_2_ASIB_0_AW_R |
|---|
| 12594 | #define NIC400_2_ASIB_0_AW_R__aw_r__SHIFT 0x14 |
|---|
| 12595 | #define NIC400_2_ASIB_0_AW_R__aw_r_MASK 0xFFF00000L |
|---|
| 12596 | //NIC400_2_ASIB_0_AR_P |
|---|
| 12597 | #define NIC400_2_ASIB_0_AR_P__ar_p__SHIFT 0x18 |
|---|
| 12598 | #define NIC400_2_ASIB_0_AR_P__ar_p_MASK 0xFF000000L |
|---|
| 12599 | //NIC400_2_ASIB_0_AR_B |
|---|
| 12600 | #define NIC400_2_ASIB_0_AR_B__ar_b__SHIFT 0x0 |
|---|
| 12601 | #define NIC400_2_ASIB_0_AR_B__ar_b_MASK 0x0000FFFFL |
|---|
| 12602 | //NIC400_2_ASIB_0_AR_R |
|---|
| 12603 | #define NIC400_2_ASIB_0_AR_R__ar_r__SHIFT 0x14 |
|---|
| 12604 | #define NIC400_2_ASIB_0_AR_R__ar_r_MASK 0xFFF00000L |
|---|
| 12605 | //NIC400_2_ASIB_0_TARGET_FC |
|---|
| 12606 | #define NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT 0x0 |
|---|
| 12607 | #define NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT 0x10 |
|---|
| 12608 | #define NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL |
|---|
| 12609 | #define NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L |
|---|
| 12610 | //NIC400_2_ASIB_0_KI_FC |
|---|
| 12611 | #define NIC400_2_ASIB_0_KI_FC__aw_tgt_latency__SHIFT 0x0 |
|---|
| 12612 | #define NIC400_2_ASIB_0_KI_FC__ar_tgt_latency__SHIFT 0x8 |
|---|
| 12613 | #define NIC400_2_ASIB_0_KI_FC__aw_tgt_latency_MASK 0x00000007L |
|---|
| 12614 | #define NIC400_2_ASIB_0_KI_FC__ar_tgt_latency_MASK 0x00000700L |
|---|
| 12615 | //NIC400_2_ASIB_0_QOS_RANGE |
|---|
| 12616 | #define NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT 0x0 |
|---|
| 12617 | #define NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT 0x8 |
|---|
| 12618 | #define NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT 0x10 |
|---|
| 12619 | #define NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT 0x18 |
|---|
| 12620 | #define NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos_MASK 0x0000000FL |
|---|
| 12621 | #define NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos_MASK 0x00000F00L |
|---|
| 12622 | #define NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos_MASK 0x000F0000L |
|---|
| 12623 | #define NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos_MASK 0x0F000000L |
|---|
| 12624 | //NIC400_2_ASIB_1_FN_MOD |
|---|
| 12625 | #define NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 |
|---|
| 12626 | #define NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 |
|---|
| 12627 | #define NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L |
|---|
| 12628 | #define NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L |
|---|
| 12629 | //NIC400_2_ASIB_1_QOS_CNTL |
|---|
| 12630 | #define NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT 0x0 |
|---|
| 12631 | #define NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT 0x1 |
|---|
| 12632 | #define NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT 0x2 |
|---|
| 12633 | #define NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT 0x3 |
|---|
| 12634 | #define NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT 0x4 |
|---|
| 12635 | #define NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT 0x5 |
|---|
| 12636 | #define NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT 0x6 |
|---|
| 12637 | #define NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT 0x7 |
|---|
| 12638 | #define NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT 0x10 |
|---|
| 12639 | #define NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT 0x14 |
|---|
| 12640 | #define NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate_MASK 0x00000001L |
|---|
| 12641 | #define NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate_MASK 0x00000002L |
|---|
| 12642 | #define NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate_MASK 0x00000004L |
|---|
| 12643 | #define NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc_MASK 0x00000008L |
|---|
| 12644 | #define NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc_MASK 0x00000010L |
|---|
| 12645 | #define NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot_MASK 0x00000020L |
|---|
| 12646 | #define NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot_MASK 0x00000040L |
|---|
| 12647 | #define NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot_MASK 0x00000080L |
|---|
| 12648 | #define NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc_MASK 0x00010000L |
|---|
| 12649 | #define NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc_MASK 0x00100000L |
|---|
| 12650 | //NIC400_2_ASIB_1_MAX_OT |
|---|
| 12651 | #define NIC400_2_ASIB_1_MAX_OT__aw_max_otf__SHIFT 0x0 |
|---|
| 12652 | #define NIC400_2_ASIB_1_MAX_OT__aw_max_oti__SHIFT 0x8 |
|---|
| 12653 | #define NIC400_2_ASIB_1_MAX_OT__ar_max_otf__SHIFT 0x10 |
|---|
| 12654 | #define NIC400_2_ASIB_1_MAX_OT__ar_max_oti__SHIFT 0x18 |
|---|
| 12655 | #define NIC400_2_ASIB_1_MAX_OT__aw_max_otf_MASK 0x000000FFL |
|---|
| 12656 | #define NIC400_2_ASIB_1_MAX_OT__aw_max_oti_MASK 0x00003F00L |
|---|
| 12657 | #define NIC400_2_ASIB_1_MAX_OT__ar_max_otf_MASK 0x00FF0000L |
|---|
| 12658 | #define NIC400_2_ASIB_1_MAX_OT__ar_max_oti_MASK 0x3F000000L |
|---|
| 12659 | //NIC400_2_ASIB_1_MAX_COMB_OT |
|---|
| 12660 | #define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 |
|---|
| 12661 | #define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 |
|---|
| 12662 | #define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL |
|---|
| 12663 | #define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L |
|---|
| 12664 | //NIC400_2_ASIB_1_AW_P |
|---|
| 12665 | #define NIC400_2_ASIB_1_AW_P__aw_p__SHIFT 0x18 |
|---|
| 12666 | #define NIC400_2_ASIB_1_AW_P__aw_p_MASK 0xFF000000L |
|---|
| 12667 | //NIC400_2_ASIB_1_AW_B |
|---|
| 12668 | #define NIC400_2_ASIB_1_AW_B__aw_b__SHIFT 0x0 |
|---|
| 12669 | #define NIC400_2_ASIB_1_AW_B__aw_b_MASK 0x0000FFFFL |
|---|
| 12670 | //NIC400_2_ASIB_1_AW_R |
|---|
| 12671 | #define NIC400_2_ASIB_1_AW_R__aw_r__SHIFT 0x14 |
|---|
| 12672 | #define NIC400_2_ASIB_1_AW_R__aw_r_MASK 0xFFF00000L |
|---|
| 12673 | //NIC400_2_ASIB_1_AR_P |
|---|
| 12674 | #define NIC400_2_ASIB_1_AR_P__ar_p__SHIFT 0x18 |
|---|
| 12675 | #define NIC400_2_ASIB_1_AR_P__ar_p_MASK 0xFF000000L |
|---|
| 12676 | //NIC400_2_ASIB_1_AR_B |
|---|
| 12677 | #define NIC400_2_ASIB_1_AR_B__ar_b__SHIFT 0x0 |
|---|
| 12678 | #define NIC400_2_ASIB_1_AR_B__ar_b_MASK 0x0000FFFFL |
|---|
| 12679 | //NIC400_2_ASIB_1_AR_R |
|---|
| 12680 | #define NIC400_2_ASIB_1_AR_R__ar_r__SHIFT 0x14 |
|---|
| 12681 | #define NIC400_2_ASIB_1_AR_R__ar_r_MASK 0xFFF00000L |
|---|
| 12682 | //NIC400_2_ASIB_1_TARGET_FC |
|---|
| 12683 | #define NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT 0x0 |
|---|
| 12684 | #define NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT 0x10 |
|---|
| 12685 | #define NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL |
|---|
| 12686 | #define NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L |
|---|
| 12687 | //NIC400_2_ASIB_1_KI_FC |
|---|
| 12688 | #define NIC400_2_ASIB_1_KI_FC__aw_tgt_latency__SHIFT 0x0 |
|---|
| 12689 | #define NIC400_2_ASIB_1_KI_FC__ar_tgt_latency__SHIFT 0x8 |
|---|
| 12690 | #define NIC400_2_ASIB_1_KI_FC__aw_tgt_latency_MASK 0x00000007L |
|---|
| 12691 | #define NIC400_2_ASIB_1_KI_FC__ar_tgt_latency_MASK 0x00000700L |
|---|
| 12692 | //NIC400_2_ASIB_1_QOS_RANGE |
|---|
| 12693 | #define NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT 0x0 |
|---|
| 12694 | #define NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT 0x8 |
|---|
| 12695 | #define NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT 0x10 |
|---|
| 12696 | #define NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT 0x18 |
|---|
| 12697 | #define NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos_MASK 0x0000000FL |
|---|
| 12698 | #define NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos_MASK 0x00000F00L |
|---|
| 12699 | #define NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos_MASK 0x000F0000L |
|---|
| 12700 | #define NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos_MASK 0x0F000000L |
|---|
| 12701 | //NIC400_2_IB_0_FN_MOD |
|---|
| 12702 | #define NIC400_2_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 |
|---|
| 12703 | #define NIC400_2_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 |
|---|
| 12704 | #define NIC400_2_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L |
|---|
| 12705 | #define NIC400_2_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L |
|---|
| 12706 | |
|---|
| 12707 | |
|---|
| 12708 | // addressBlock: nbio_nbif0_nbif_sion_SIONDEC |
|---|
| 12709 | //SION_CL0_RdRsp_BurstTarget_REG0 |
|---|
| 12710 | #define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12711 | #define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12712 | //SION_CL0_RdRsp_BurstTarget_REG1 |
|---|
| 12713 | #define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12714 | #define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12715 | //SION_CL0_RdRsp_TimeSlot_REG0 |
|---|
| 12716 | #define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12717 | #define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12718 | //SION_CL0_RdRsp_TimeSlot_REG1 |
|---|
| 12719 | #define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12720 | #define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12721 | //SION_CL0_WrRsp_BurstTarget_REG0 |
|---|
| 12722 | #define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12723 | #define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12724 | //SION_CL0_WrRsp_BurstTarget_REG1 |
|---|
| 12725 | #define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12726 | #define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12727 | //SION_CL0_WrRsp_TimeSlot_REG0 |
|---|
| 12728 | #define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12729 | #define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12730 | //SION_CL0_WrRsp_TimeSlot_REG1 |
|---|
| 12731 | #define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12732 | #define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12733 | //SION_CL0_Req_BurstTarget_REG0 |
|---|
| 12734 | #define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12735 | #define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12736 | //SION_CL0_Req_BurstTarget_REG1 |
|---|
| 12737 | #define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12738 | #define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12739 | //SION_CL0_Req_TimeSlot_REG0 |
|---|
| 12740 | #define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12741 | #define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12742 | //SION_CL0_Req_TimeSlot_REG1 |
|---|
| 12743 | #define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12744 | #define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12745 | //SION_CL0_ReqPoolCredit_Alloc_REG0 |
|---|
| 12746 | #define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12747 | #define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12748 | //SION_CL0_ReqPoolCredit_Alloc_REG1 |
|---|
| 12749 | #define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12750 | #define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12751 | //SION_CL0_DataPoolCredit_Alloc_REG0 |
|---|
| 12752 | #define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12753 | #define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12754 | //SION_CL0_DataPoolCredit_Alloc_REG1 |
|---|
| 12755 | #define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12756 | #define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12757 | //SION_CL0_RdRspPoolCredit_Alloc_REG0 |
|---|
| 12758 | #define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12759 | #define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12760 | //SION_CL0_RdRspPoolCredit_Alloc_REG1 |
|---|
| 12761 | #define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12762 | #define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12763 | //SION_CL0_WrRspPoolCredit_Alloc_REG0 |
|---|
| 12764 | #define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12765 | #define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12766 | //SION_CL0_WrRspPoolCredit_Alloc_REG1 |
|---|
| 12767 | #define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12768 | #define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12769 | //SION_CL1_RdRsp_BurstTarget_REG0 |
|---|
| 12770 | #define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12771 | #define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12772 | //SION_CL1_RdRsp_BurstTarget_REG1 |
|---|
| 12773 | #define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12774 | #define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12775 | //SION_CL1_RdRsp_TimeSlot_REG0 |
|---|
| 12776 | #define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12777 | #define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12778 | //SION_CL1_RdRsp_TimeSlot_REG1 |
|---|
| 12779 | #define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12780 | #define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12781 | //SION_CL1_WrRsp_BurstTarget_REG0 |
|---|
| 12782 | #define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12783 | #define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12784 | //SION_CL1_WrRsp_BurstTarget_REG1 |
|---|
| 12785 | #define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12786 | #define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12787 | //SION_CL1_WrRsp_TimeSlot_REG0 |
|---|
| 12788 | #define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12789 | #define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12790 | //SION_CL1_WrRsp_TimeSlot_REG1 |
|---|
| 12791 | #define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12792 | #define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12793 | //SION_CL1_Req_BurstTarget_REG0 |
|---|
| 12794 | #define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12795 | #define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12796 | //SION_CL1_Req_BurstTarget_REG1 |
|---|
| 12797 | #define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12798 | #define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12799 | //SION_CL1_Req_TimeSlot_REG0 |
|---|
| 12800 | #define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12801 | #define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12802 | //SION_CL1_Req_TimeSlot_REG1 |
|---|
| 12803 | #define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12804 | #define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12805 | //SION_CL1_ReqPoolCredit_Alloc_REG0 |
|---|
| 12806 | #define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12807 | #define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12808 | //SION_CL1_ReqPoolCredit_Alloc_REG1 |
|---|
| 12809 | #define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12810 | #define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12811 | //SION_CL1_DataPoolCredit_Alloc_REG0 |
|---|
| 12812 | #define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12813 | #define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12814 | //SION_CL1_DataPoolCredit_Alloc_REG1 |
|---|
| 12815 | #define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12816 | #define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12817 | //SION_CL1_RdRspPoolCredit_Alloc_REG0 |
|---|
| 12818 | #define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12819 | #define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12820 | //SION_CL1_RdRspPoolCredit_Alloc_REG1 |
|---|
| 12821 | #define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12822 | #define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12823 | //SION_CL1_WrRspPoolCredit_Alloc_REG0 |
|---|
| 12824 | #define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12825 | #define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12826 | //SION_CL1_WrRspPoolCredit_Alloc_REG1 |
|---|
| 12827 | #define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12828 | #define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12829 | //SION_CL2_RdRsp_BurstTarget_REG0 |
|---|
| 12830 | #define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12831 | #define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12832 | //SION_CL2_RdRsp_BurstTarget_REG1 |
|---|
| 12833 | #define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12834 | #define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12835 | //SION_CL2_RdRsp_TimeSlot_REG0 |
|---|
| 12836 | #define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12837 | #define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12838 | //SION_CL2_RdRsp_TimeSlot_REG1 |
|---|
| 12839 | #define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12840 | #define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12841 | //SION_CL2_WrRsp_BurstTarget_REG0 |
|---|
| 12842 | #define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12843 | #define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12844 | //SION_CL2_WrRsp_BurstTarget_REG1 |
|---|
| 12845 | #define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12846 | #define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12847 | //SION_CL2_WrRsp_TimeSlot_REG0 |
|---|
| 12848 | #define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12849 | #define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12850 | //SION_CL2_WrRsp_TimeSlot_REG1 |
|---|
| 12851 | #define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12852 | #define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12853 | //SION_CL2_Req_BurstTarget_REG0 |
|---|
| 12854 | #define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12855 | #define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12856 | //SION_CL2_Req_BurstTarget_REG1 |
|---|
| 12857 | #define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12858 | #define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12859 | //SION_CL2_Req_TimeSlot_REG0 |
|---|
| 12860 | #define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12861 | #define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12862 | //SION_CL2_Req_TimeSlot_REG1 |
|---|
| 12863 | #define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12864 | #define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12865 | //SION_CL2_ReqPoolCredit_Alloc_REG0 |
|---|
| 12866 | #define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12867 | #define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12868 | //SION_CL2_ReqPoolCredit_Alloc_REG1 |
|---|
| 12869 | #define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12870 | #define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12871 | //SION_CL2_DataPoolCredit_Alloc_REG0 |
|---|
| 12872 | #define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12873 | #define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12874 | //SION_CL2_DataPoolCredit_Alloc_REG1 |
|---|
| 12875 | #define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12876 | #define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12877 | //SION_CL2_RdRspPoolCredit_Alloc_REG0 |
|---|
| 12878 | #define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12879 | #define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12880 | //SION_CL2_RdRspPoolCredit_Alloc_REG1 |
|---|
| 12881 | #define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12882 | #define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12883 | //SION_CL2_WrRspPoolCredit_Alloc_REG0 |
|---|
| 12884 | #define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12885 | #define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12886 | //SION_CL2_WrRspPoolCredit_Alloc_REG1 |
|---|
| 12887 | #define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12888 | #define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12889 | //SION_CL3_RdRsp_BurstTarget_REG0 |
|---|
| 12890 | #define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12891 | #define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12892 | //SION_CL3_RdRsp_BurstTarget_REG1 |
|---|
| 12893 | #define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12894 | #define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12895 | //SION_CL3_RdRsp_TimeSlot_REG0 |
|---|
| 12896 | #define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12897 | #define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12898 | //SION_CL3_RdRsp_TimeSlot_REG1 |
|---|
| 12899 | #define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12900 | #define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12901 | //SION_CL3_WrRsp_BurstTarget_REG0 |
|---|
| 12902 | #define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12903 | #define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12904 | //SION_CL3_WrRsp_BurstTarget_REG1 |
|---|
| 12905 | #define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12906 | #define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12907 | //SION_CL3_WrRsp_TimeSlot_REG0 |
|---|
| 12908 | #define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12909 | #define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12910 | //SION_CL3_WrRsp_TimeSlot_REG1 |
|---|
| 12911 | #define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12912 | #define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12913 | //SION_CL3_Req_BurstTarget_REG0 |
|---|
| 12914 | #define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 |
|---|
| 12915 | #define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL |
|---|
| 12916 | //SION_CL3_Req_BurstTarget_REG1 |
|---|
| 12917 | #define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 |
|---|
| 12918 | #define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL |
|---|
| 12919 | //SION_CL3_Req_TimeSlot_REG0 |
|---|
| 12920 | #define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 |
|---|
| 12921 | #define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL |
|---|
| 12922 | //SION_CL3_Req_TimeSlot_REG1 |
|---|
| 12923 | #define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 |
|---|
| 12924 | #define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL |
|---|
| 12925 | //SION_CL3_ReqPoolCredit_Alloc_REG0 |
|---|
| 12926 | #define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12927 | #define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12928 | //SION_CL3_ReqPoolCredit_Alloc_REG1 |
|---|
| 12929 | #define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12930 | #define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12931 | //SION_CL3_DataPoolCredit_Alloc_REG0 |
|---|
| 12932 | #define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12933 | #define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12934 | //SION_CL3_DataPoolCredit_Alloc_REG1 |
|---|
| 12935 | #define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12936 | #define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12937 | //SION_CL3_RdRspPoolCredit_Alloc_REG0 |
|---|
| 12938 | #define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12939 | #define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12940 | //SION_CL3_RdRspPoolCredit_Alloc_REG1 |
|---|
| 12941 | #define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12942 | #define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12943 | //SION_CL3_WrRspPoolCredit_Alloc_REG0 |
|---|
| 12944 | #define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 |
|---|
| 12945 | #define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL |
|---|
| 12946 | //SION_CL3_WrRspPoolCredit_Alloc_REG1 |
|---|
| 12947 | #define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 |
|---|
| 12948 | #define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL |
|---|
| 12949 | //SION_CNTL_REG0 |
|---|
| 12950 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 |
|---|
| 12951 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 |
|---|
| 12952 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 |
|---|
| 12953 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 |
|---|
| 12954 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 |
|---|
| 12955 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 |
|---|
| 12956 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 |
|---|
| 12957 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 |
|---|
| 12958 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 |
|---|
| 12959 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 |
|---|
| 12960 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa |
|---|
| 12961 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb |
|---|
| 12962 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc |
|---|
| 12963 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd |
|---|
| 12964 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe |
|---|
| 12965 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf |
|---|
| 12966 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 |
|---|
| 12967 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 |
|---|
| 12968 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 |
|---|
| 12969 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 |
|---|
| 12970 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L |
|---|
| 12971 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L |
|---|
| 12972 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L |
|---|
| 12973 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L |
|---|
| 12974 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L |
|---|
| 12975 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L |
|---|
| 12976 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L |
|---|
| 12977 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L |
|---|
| 12978 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L |
|---|
| 12979 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L |
|---|
| 12980 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L |
|---|
| 12981 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L |
|---|
| 12982 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L |
|---|
| 12983 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L |
|---|
| 12984 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L |
|---|
| 12985 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L |
|---|
| 12986 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L |
|---|
| 12987 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L |
|---|
| 12988 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L |
|---|
| 12989 | #define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L |
|---|
| 12990 | //SION_CNTL_REG1 |
|---|
| 12991 | #define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 |
|---|
| 12992 | #define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8 |
|---|
| 12993 | #define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL |
|---|
| 12994 | #define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK 0x0000FF00L |
|---|
| 12995 | |
|---|
| 12996 | |
|---|
| 12997 | // addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC |
|---|
| 12998 | //SHUB_PF_FLR_RST |
|---|
| 12999 | #define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 |
|---|
| 13000 | #define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 |
|---|
| 13001 | #define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 |
|---|
| 13002 | #define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 |
|---|
| 13003 | #define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L |
|---|
| 13004 | #define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L |
|---|
| 13005 | #define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L |
|---|
| 13006 | #define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L |
|---|
| 13007 | //SHUB_GFX_DRV_VPU_RST |
|---|
| 13008 | #define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 |
|---|
| 13009 | #define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L |
|---|
| 13010 | //SHUB_LINK_RESET |
|---|
| 13011 | #define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0 |
|---|
| 13012 | #define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1 |
|---|
| 13013 | #define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT 0x2 |
|---|
| 13014 | #define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L |
|---|
| 13015 | #define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L |
|---|
| 13016 | #define SHUB_LINK_RESET__LINK_P2_RESET_MASK 0x00000004L |
|---|
| 13017 | //SHUB_PF0_VF_FLR_RST |
|---|
| 13018 | #define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 |
|---|
| 13019 | #define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 |
|---|
| 13020 | #define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 |
|---|
| 13021 | #define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 |
|---|
| 13022 | #define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 |
|---|
| 13023 | #define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 |
|---|
| 13024 | #define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 |
|---|
| 13025 | #define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 |
|---|
| 13026 | #define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 |
|---|
| 13027 | #define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 |
|---|
| 13028 | #define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa |
|---|
| 13029 | #define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb |
|---|
| 13030 | #define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc |
|---|
| 13031 | #define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd |
|---|
| 13032 | #define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe |
|---|
| 13033 | #define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf |
|---|
| 13034 | #define SHUB_PF0_VF_FLR_RST__PF0_VF16_FLR_RST__SHIFT 0x10 |
|---|
| 13035 | #define SHUB_PF0_VF_FLR_RST__PF0_VF17_FLR_RST__SHIFT 0x11 |
|---|
| 13036 | #define SHUB_PF0_VF_FLR_RST__PF0_VF18_FLR_RST__SHIFT 0x12 |
|---|
| 13037 | #define SHUB_PF0_VF_FLR_RST__PF0_VF19_FLR_RST__SHIFT 0x13 |
|---|
| 13038 | #define SHUB_PF0_VF_FLR_RST__PF0_VF20_FLR_RST__SHIFT 0x14 |
|---|
| 13039 | #define SHUB_PF0_VF_FLR_RST__PF0_VF21_FLR_RST__SHIFT 0x15 |
|---|
| 13040 | #define SHUB_PF0_VF_FLR_RST__PF0_VF22_FLR_RST__SHIFT 0x16 |
|---|
| 13041 | #define SHUB_PF0_VF_FLR_RST__PF0_VF23_FLR_RST__SHIFT 0x17 |
|---|
| 13042 | #define SHUB_PF0_VF_FLR_RST__PF0_VF24_FLR_RST__SHIFT 0x18 |
|---|
| 13043 | #define SHUB_PF0_VF_FLR_RST__PF0_VF25_FLR_RST__SHIFT 0x19 |
|---|
| 13044 | #define SHUB_PF0_VF_FLR_RST__PF0_VF26_FLR_RST__SHIFT 0x1a |
|---|
| 13045 | #define SHUB_PF0_VF_FLR_RST__PF0_VF27_FLR_RST__SHIFT 0x1b |
|---|
| 13046 | #define SHUB_PF0_VF_FLR_RST__PF0_VF28_FLR_RST__SHIFT 0x1c |
|---|
| 13047 | #define SHUB_PF0_VF_FLR_RST__PF0_VF29_FLR_RST__SHIFT 0x1d |
|---|
| 13048 | #define SHUB_PF0_VF_FLR_RST__PF0_VF30_FLR_RST__SHIFT 0x1e |
|---|
| 13049 | #define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f |
|---|
| 13050 | #define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L |
|---|
| 13051 | #define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L |
|---|
| 13052 | #define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L |
|---|
| 13053 | #define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L |
|---|
| 13054 | #define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L |
|---|
| 13055 | #define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L |
|---|
| 13056 | #define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L |
|---|
| 13057 | #define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L |
|---|
| 13058 | #define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L |
|---|
| 13059 | #define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L |
|---|
| 13060 | #define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L |
|---|
| 13061 | #define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L |
|---|
| 13062 | #define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L |
|---|
| 13063 | #define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L |
|---|
| 13064 | #define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L |
|---|
| 13065 | #define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L |
|---|
| 13066 | #define SHUB_PF0_VF_FLR_RST__PF0_VF16_FLR_RST_MASK 0x00010000L |
|---|
| 13067 | #define SHUB_PF0_VF_FLR_RST__PF0_VF17_FLR_RST_MASK 0x00020000L |
|---|
| 13068 | #define SHUB_PF0_VF_FLR_RST__PF0_VF18_FLR_RST_MASK 0x00040000L |
|---|
| 13069 | #define SHUB_PF0_VF_FLR_RST__PF0_VF19_FLR_RST_MASK 0x00080000L |
|---|
| 13070 | #define SHUB_PF0_VF_FLR_RST__PF0_VF20_FLR_RST_MASK 0x00100000L |
|---|
| 13071 | #define SHUB_PF0_VF_FLR_RST__PF0_VF21_FLR_RST_MASK 0x00200000L |
|---|
| 13072 | #define SHUB_PF0_VF_FLR_RST__PF0_VF22_FLR_RST_MASK 0x00400000L |
|---|
| 13073 | #define SHUB_PF0_VF_FLR_RST__PF0_VF23_FLR_RST_MASK 0x00800000L |
|---|
| 13074 | #define SHUB_PF0_VF_FLR_RST__PF0_VF24_FLR_RST_MASK 0x01000000L |
|---|
| 13075 | #define SHUB_PF0_VF_FLR_RST__PF0_VF25_FLR_RST_MASK 0x02000000L |
|---|
| 13076 | #define SHUB_PF0_VF_FLR_RST__PF0_VF26_FLR_RST_MASK 0x04000000L |
|---|
| 13077 | #define SHUB_PF0_VF_FLR_RST__PF0_VF27_FLR_RST_MASK 0x08000000L |
|---|
| 13078 | #define SHUB_PF0_VF_FLR_RST__PF0_VF28_FLR_RST_MASK 0x10000000L |
|---|
| 13079 | #define SHUB_PF0_VF_FLR_RST__PF0_VF29_FLR_RST_MASK 0x20000000L |
|---|
| 13080 | #define SHUB_PF0_VF_FLR_RST__PF0_VF30_FLR_RST_MASK 0x40000000L |
|---|
| 13081 | #define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L |
|---|
| 13082 | //SHUB_HARD_RST_CTRL |
|---|
| 13083 | #define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 |
|---|
| 13084 | #define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 |
|---|
| 13085 | #define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 |
|---|
| 13086 | #define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 |
|---|
| 13087 | #define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 |
|---|
| 13088 | #define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 |
|---|
| 13089 | #define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L |
|---|
| 13090 | #define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L |
|---|
| 13091 | #define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L |
|---|
| 13092 | #define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L |
|---|
| 13093 | #define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L |
|---|
| 13094 | #define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L |
|---|
| 13095 | //SHUB_SOFT_RST_CTRL |
|---|
| 13096 | #define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 |
|---|
| 13097 | #define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 |
|---|
| 13098 | #define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 |
|---|
| 13099 | #define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 |
|---|
| 13100 | #define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 |
|---|
| 13101 | #define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 |
|---|
| 13102 | #define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L |
|---|
| 13103 | #define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L |
|---|
| 13104 | #define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L |
|---|
| 13105 | #define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L |
|---|
| 13106 | #define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L |
|---|
| 13107 | #define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L |
|---|
| 13108 | //SHUB_SDP_PORT_RST |
|---|
| 13109 | #define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST__SHIFT 0x0 |
|---|
| 13110 | #define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT 0x1 |
|---|
| 13111 | #define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0x2 |
|---|
| 13112 | #define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT 0x3 |
|---|
| 13113 | #define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4 |
|---|
| 13114 | #define SHUB_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST__SHIFT 0x5 |
|---|
| 13115 | #define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT 0x6 |
|---|
| 13116 | #define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT 0x7 |
|---|
| 13117 | #define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8 |
|---|
| 13118 | #define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9 |
|---|
| 13119 | #define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18 |
|---|
| 13120 | #define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST_MASK 0x00000001L |
|---|
| 13121 | #define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK 0x00000002L |
|---|
| 13122 | #define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00000004L |
|---|
| 13123 | #define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK 0x00000008L |
|---|
| 13124 | #define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L |
|---|
| 13125 | #define SHUB_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST_MASK 0x00000020L |
|---|
| 13126 | #define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK 0x00000040L |
|---|
| 13127 | #define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK 0x00000080L |
|---|
| 13128 | #define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L |
|---|
| 13129 | #define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L |
|---|
| 13130 | #define SHUB_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L |
|---|
| 13131 | |
|---|
| 13132 | |
|---|
| 13133 | // addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk |
|---|
| 13134 | //GDCL_RAS_CENTRAL_STATUS |
|---|
| 13135 | #define GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_EgStall_det__SHIFT 0x0 |
|---|
| 13136 | #define GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_ErrEvent_det__SHIFT 0x1 |
|---|
| 13137 | #define GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_EgStall_det__SHIFT 0x2 |
|---|
| 13138 | #define GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_ErrEvent_det__SHIFT 0x3 |
|---|
| 13139 | #define GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_EgStall_det_MASK 0x00000001L |
|---|
| 13140 | #define GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_ErrEvent_det_MASK 0x00000002L |
|---|
| 13141 | #define GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_EgStall_det_MASK 0x00000004L |
|---|
| 13142 | #define GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_ErrEvent_det_MASK 0x00000008L |
|---|
| 13143 | //GDCSOC_RAS_CENTRAL_STATUS |
|---|
| 13144 | #define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT 0x0 |
|---|
| 13145 | #define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT 0x1 |
|---|
| 13146 | #define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT 0x2 |
|---|
| 13147 | #define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT 0x3 |
|---|
| 13148 | #define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK 0x00000001L |
|---|
| 13149 | #define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK 0x00000002L |
|---|
| 13150 | #define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK 0x00000004L |
|---|
| 13151 | #define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK 0x00000008L |
|---|
| 13152 | //GDCSOC_RAS_LEAF0_CTRL |
|---|
| 13153 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 13154 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 13155 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT 0x2 |
|---|
| 13156 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 13157 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 13158 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 13159 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 13160 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 13161 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 13162 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 13163 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 13164 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 13165 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 13166 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK 0x00000004L |
|---|
| 13167 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 13168 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 13169 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 13170 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 13171 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 13172 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 13173 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 13174 | #define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 13175 | //GDCSOC_RAS_LEAF1_CTRL |
|---|
| 13176 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 13177 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 13178 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT 0x2 |
|---|
| 13179 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 13180 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 13181 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 13182 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 13183 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 13184 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 13185 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 13186 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 13187 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 13188 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 13189 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK 0x00000004L |
|---|
| 13190 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 13191 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 13192 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 13193 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 13194 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 13195 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 13196 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 13197 | #define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 13198 | //GDCSOC_RAS_LEAF2_CTRL |
|---|
| 13199 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 13200 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 13201 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT 0x2 |
|---|
| 13202 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 13203 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 13204 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 13205 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 13206 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 13207 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 13208 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 13209 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 13210 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 |
|---|
| 13211 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 13212 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 13213 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK 0x00000004L |
|---|
| 13214 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 13215 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 13216 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 13217 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 13218 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 13219 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 13220 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 13221 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 13222 | #define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L |
|---|
| 13223 | //GDCSOC_RAS_LEAF3_CTRL |
|---|
| 13224 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 13225 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 13226 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT 0x2 |
|---|
| 13227 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 13228 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 13229 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 13230 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 13231 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 13232 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 13233 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 13234 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 13235 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 13236 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 13237 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK 0x00000004L |
|---|
| 13238 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 13239 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 13240 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 13241 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 13242 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 13243 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 13244 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 13245 | #define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 13246 | //GDCSOC_RAS_LEAF4_CTRL |
|---|
| 13247 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 13248 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 13249 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT 0x2 |
|---|
| 13250 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 13251 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 13252 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 13253 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 13254 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 13255 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 13256 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 13257 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 13258 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 13259 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 13260 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK 0x00000004L |
|---|
| 13261 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 13262 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 13263 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 13264 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 13265 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 13266 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 13267 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 13268 | #define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 13269 | //GDCSOC_RAS_LEAF5_CTRL |
|---|
| 13270 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 13271 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 13272 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN__SHIFT 0x2 |
|---|
| 13273 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 13274 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 13275 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 13276 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 13277 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 13278 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 13279 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 13280 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 13281 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 13282 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 13283 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN_MASK 0x00000004L |
|---|
| 13284 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 13285 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 13286 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 13287 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 13288 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 13289 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 13290 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 13291 | #define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 13292 | //GDCSOC_RAS_LEAF2_MISC_CTRL |
|---|
| 13293 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN__SHIFT 0x0 |
|---|
| 13294 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN__SHIFT 0x1 |
|---|
| 13295 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT 0x8 |
|---|
| 13296 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT 0x9 |
|---|
| 13297 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS__SHIFT 0xc |
|---|
| 13298 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN__SHIFT 0x10 |
|---|
| 13299 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN__SHIFT 0x11 |
|---|
| 13300 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN_MASK 0x00000001L |
|---|
| 13301 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN_MASK 0x00000002L |
|---|
| 13302 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK 0x00000100L |
|---|
| 13303 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK 0x00000200L |
|---|
| 13304 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_MASK 0x00001000L |
|---|
| 13305 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN_MASK 0x00010000L |
|---|
| 13306 | #define GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN_MASK 0x00020000L |
|---|
| 13307 | //GDCSOC_RAS_LEAF2_MISC_CTRL2 |
|---|
| 13308 | #define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID__SHIFT 0x0 |
|---|
| 13309 | #define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG__SHIFT 0x8 |
|---|
| 13310 | #define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET__SHIFT 0x14 |
|---|
| 13311 | #define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_MASK 0x0000007FL |
|---|
| 13312 | #define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_MASK 0x0003FF00L |
|---|
| 13313 | #define GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET_MASK 0x3FF00000L |
|---|
| 13314 | //GDCSOC_RAS_LEAF0_STATUS |
|---|
| 13315 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 13316 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT 0x1 |
|---|
| 13317 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 13318 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 13319 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 13320 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 13321 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 13322 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 13323 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK 0x00000002L |
|---|
| 13324 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 13325 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 13326 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 13327 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 13328 | #define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 13329 | //GDCSOC_RAS_LEAF1_STATUS |
|---|
| 13330 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 13331 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT 0x1 |
|---|
| 13332 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 13333 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 13334 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 13335 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 13336 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 13337 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 13338 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK 0x00000002L |
|---|
| 13339 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 13340 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 13341 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 13342 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 13343 | #define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 13344 | //GDCSOC_RAS_LEAF2_STATUS |
|---|
| 13345 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 13346 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT 0x1 |
|---|
| 13347 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 13348 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 13349 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 13350 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 13351 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 13352 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 13353 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK 0x00000002L |
|---|
| 13354 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 13355 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 13356 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 13357 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 13358 | #define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 13359 | //GDCSOC_RAS_LEAF3_STATUS |
|---|
| 13360 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 13361 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT 0x1 |
|---|
| 13362 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 13363 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 13364 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 13365 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 13366 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 13367 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 13368 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK 0x00000002L |
|---|
| 13369 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 13370 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 13371 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 13372 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 13373 | #define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 13374 | //GDCSOC_RAS_LEAF4_STATUS |
|---|
| 13375 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 13376 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT 0x1 |
|---|
| 13377 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 13378 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 13379 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 13380 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 13381 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 13382 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 13383 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK 0x00000002L |
|---|
| 13384 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 13385 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 13386 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 13387 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 13388 | #define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 13389 | //GDCSOC_RAS_LEAF5_STATUS |
|---|
| 13390 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 13391 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET__SHIFT 0x1 |
|---|
| 13392 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 13393 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 13394 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 13395 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 13396 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 13397 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 13398 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET_MASK 0x00000002L |
|---|
| 13399 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 13400 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 13401 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 13402 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 13403 | #define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 13404 | //GDCSHUB_RAS_CENTRAL_STATUS |
|---|
| 13405 | #define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_EgStall_det__SHIFT 0x0 |
|---|
| 13406 | #define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_ErrEvent_det__SHIFT 0x1 |
|---|
| 13407 | #define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_EgStall_det__SHIFT 0x2 |
|---|
| 13408 | #define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_ErrEvent_det__SHIFT 0x3 |
|---|
| 13409 | #define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_EgStall_det_MASK 0x00000001L |
|---|
| 13410 | #define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_ErrEvent_det_MASK 0x00000002L |
|---|
| 13411 | #define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_EgStall_det_MASK 0x00000004L |
|---|
| 13412 | #define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_ErrEvent_det_MASK 0x00000008L |
|---|
| 13413 | |
|---|
| 13414 | |
|---|
| 13415 | // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp |
|---|
| 13416 | //BIF_CFG_DEV0_SWDS_VENDOR_ID |
|---|
| 13417 | #define BIF_CFG_DEV0_SWDS_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 13418 | #define BIF_CFG_DEV0_SWDS_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 13419 | //BIF_CFG_DEV0_SWDS_DEVICE_ID |
|---|
| 13420 | #define BIF_CFG_DEV0_SWDS_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 13421 | #define BIF_CFG_DEV0_SWDS_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 13422 | //BIF_CFG_DEV0_SWDS_COMMAND |
|---|
| 13423 | #define BIF_CFG_DEV0_SWDS_COMMAND__IOEN_DN__SHIFT 0x0 |
|---|
| 13424 | #define BIF_CFG_DEV0_SWDS_COMMAND__MEMEN_DN__SHIFT 0x1 |
|---|
| 13425 | #define BIF_CFG_DEV0_SWDS_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 13426 | #define BIF_CFG_DEV0_SWDS_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 13427 | #define BIF_CFG_DEV0_SWDS_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 13428 | #define BIF_CFG_DEV0_SWDS_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 13429 | #define BIF_CFG_DEV0_SWDS_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 13430 | #define BIF_CFG_DEV0_SWDS_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 13431 | #define BIF_CFG_DEV0_SWDS_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 13432 | #define BIF_CFG_DEV0_SWDS_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 13433 | #define BIF_CFG_DEV0_SWDS_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 13434 | #define BIF_CFG_DEV0_SWDS_COMMAND__IOEN_DN_MASK 0x0001L |
|---|
| 13435 | #define BIF_CFG_DEV0_SWDS_COMMAND__MEMEN_DN_MASK 0x0002L |
|---|
| 13436 | #define BIF_CFG_DEV0_SWDS_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 13437 | #define BIF_CFG_DEV0_SWDS_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 13438 | #define BIF_CFG_DEV0_SWDS_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 13439 | #define BIF_CFG_DEV0_SWDS_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 13440 | #define BIF_CFG_DEV0_SWDS_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 13441 | #define BIF_CFG_DEV0_SWDS_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 13442 | #define BIF_CFG_DEV0_SWDS_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 13443 | #define BIF_CFG_DEV0_SWDS_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 13444 | #define BIF_CFG_DEV0_SWDS_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 13445 | //BIF_CFG_DEV0_SWDS_STATUS |
|---|
| 13446 | #define BIF_CFG_DEV0_SWDS_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 13447 | #define BIF_CFG_DEV0_SWDS_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 13448 | #define BIF_CFG_DEV0_SWDS_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 13449 | #define BIF_CFG_DEV0_SWDS_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 13450 | #define BIF_CFG_DEV0_SWDS_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 13451 | #define BIF_CFG_DEV0_SWDS_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 13452 | #define BIF_CFG_DEV0_SWDS_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 13453 | #define BIF_CFG_DEV0_SWDS_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 13454 | #define BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 13455 | #define BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 13456 | #define BIF_CFG_DEV0_SWDS_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 13457 | #define BIF_CFG_DEV0_SWDS_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 13458 | #define BIF_CFG_DEV0_SWDS_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 13459 | #define BIF_CFG_DEV0_SWDS_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 13460 | #define BIF_CFG_DEV0_SWDS_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 13461 | #define BIF_CFG_DEV0_SWDS_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 13462 | #define BIF_CFG_DEV0_SWDS_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 13463 | #define BIF_CFG_DEV0_SWDS_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 13464 | #define BIF_CFG_DEV0_SWDS_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 13465 | #define BIF_CFG_DEV0_SWDS_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 13466 | #define BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 13467 | #define BIF_CFG_DEV0_SWDS_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 13468 | #define BIF_CFG_DEV0_SWDS_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 13469 | #define BIF_CFG_DEV0_SWDS_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 13470 | //BIF_CFG_DEV0_SWDS_REVISION_ID |
|---|
| 13471 | #define BIF_CFG_DEV0_SWDS_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 13472 | #define BIF_CFG_DEV0_SWDS_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 13473 | #define BIF_CFG_DEV0_SWDS_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 13474 | #define BIF_CFG_DEV0_SWDS_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 13475 | //BIF_CFG_DEV0_SWDS_PROG_INTERFACE |
|---|
| 13476 | #define BIF_CFG_DEV0_SWDS_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 13477 | #define BIF_CFG_DEV0_SWDS_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 13478 | //BIF_CFG_DEV0_SWDS_SUB_CLASS |
|---|
| 13479 | #define BIF_CFG_DEV0_SWDS_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 13480 | #define BIF_CFG_DEV0_SWDS_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 13481 | //BIF_CFG_DEV0_SWDS_BASE_CLASS |
|---|
| 13482 | #define BIF_CFG_DEV0_SWDS_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 13483 | #define BIF_CFG_DEV0_SWDS_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 13484 | //BIF_CFG_DEV0_SWDS_CACHE_LINE |
|---|
| 13485 | #define BIF_CFG_DEV0_SWDS_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 13486 | #define BIF_CFG_DEV0_SWDS_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 13487 | //BIF_CFG_DEV0_SWDS_LATENCY |
|---|
| 13488 | #define BIF_CFG_DEV0_SWDS_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 13489 | #define BIF_CFG_DEV0_SWDS_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 13490 | //BIF_CFG_DEV0_SWDS_HEADER |
|---|
| 13491 | #define 0x0 |
|---|
| 13492 | #define 0x7 |
|---|
| 13493 | #define 0x7FL |
|---|
| 13494 | #define 0x80L |
|---|
| 13495 | //BIF_CFG_DEV0_SWDS_BIST |
|---|
| 13496 | #define BIF_CFG_DEV0_SWDS_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 13497 | #define BIF_CFG_DEV0_SWDS_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 13498 | #define BIF_CFG_DEV0_SWDS_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 13499 | #define BIF_CFG_DEV0_SWDS_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 13500 | #define BIF_CFG_DEV0_SWDS_BIST__BIST_STRT_MASK 0x40L |
|---|
| 13501 | #define BIF_CFG_DEV0_SWDS_BIST__BIST_CAP_MASK 0x80L |
|---|
| 13502 | //BIF_CFG_DEV0_SWDS_BASE_ADDR_1 |
|---|
| 13503 | #define BIF_CFG_DEV0_SWDS_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 13504 | #define BIF_CFG_DEV0_SWDS_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 13505 | //BIF_CFG_DEV0_SWDS_BASE_ADDR_2 |
|---|
| 13506 | #define BIF_CFG_DEV0_SWDS_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 13507 | #define BIF_CFG_DEV0_SWDS_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 13508 | //SUB_BUS_NUMBER_LATENCY |
|---|
| 13509 | #define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
|---|
| 13510 | #define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
|---|
| 13511 | #define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
|---|
| 13512 | #define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
|---|
| 13513 | #define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
|---|
| 13514 | #define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
|---|
| 13515 | #define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
|---|
| 13516 | #define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
|---|
| 13517 | //IO_BASE_LIMIT |
|---|
| 13518 | #define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
|---|
| 13519 | #define IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
|---|
| 13520 | #define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
|---|
| 13521 | #define IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
|---|
| 13522 | #define IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
|---|
| 13523 | #define IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
|---|
| 13524 | #define IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
|---|
| 13525 | #define IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
|---|
| 13526 | //SECONDARY_STATUS |
|---|
| 13527 | #define SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 13528 | #define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 13529 | #define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 13530 | #define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 13531 | #define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 13532 | #define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 13533 | #define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 13534 | #define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 13535 | #define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 13536 | #define SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 13537 | #define SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 13538 | #define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 13539 | #define SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 13540 | #define SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 13541 | #define SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 13542 | #define SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 13543 | #define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 13544 | #define SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 13545 | //MEM_BASE_LIMIT |
|---|
| 13546 | #define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 13547 | #define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
|---|
| 13548 | #define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 13549 | #define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
|---|
| 13550 | #define MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 13551 | #define MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
|---|
| 13552 | #define MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 13553 | #define MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
|---|
| 13554 | //PREF_BASE_LIMIT |
|---|
| 13555 | #define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 13556 | #define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
|---|
| 13557 | #define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 13558 | #define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
|---|
| 13559 | #define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 13560 | #define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
|---|
| 13561 | #define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 13562 | #define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
|---|
| 13563 | //PREF_BASE_UPPER |
|---|
| 13564 | #define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
|---|
| 13565 | #define PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
|---|
| 13566 | //PREF_LIMIT_UPPER |
|---|
| 13567 | #define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
|---|
| 13568 | #define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
|---|
| 13569 | //IO_BASE_LIMIT_HI |
|---|
| 13570 | #define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
|---|
| 13571 | #define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
|---|
| 13572 | #define IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
|---|
| 13573 | #define IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
|---|
| 13574 | //BIF_CFG_DEV0_SWDS_CAP_PTR |
|---|
| 13575 | #define BIF_CFG_DEV0_SWDS_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 13576 | #define BIF_CFG_DEV0_SWDS_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 13577 | //BIF_CFG_DEV0_SWDS_ROM_BASE_ADDR |
|---|
| 13578 | #define BIF_CFG_DEV0_SWDS_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 13579 | #define BIF_CFG_DEV0_SWDS_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 13580 | //BIF_CFG_DEV0_SWDS_INTERRUPT_LINE |
|---|
| 13581 | #define BIF_CFG_DEV0_SWDS_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 13582 | #define BIF_CFG_DEV0_SWDS_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 13583 | //BIF_CFG_DEV0_SWDS_INTERRUPT_PIN |
|---|
| 13584 | #define BIF_CFG_DEV0_SWDS_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 13585 | #define BIF_CFG_DEV0_SWDS_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 13586 | //IRQ_BRIDGE_CNTL |
|---|
| 13587 | #define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
|---|
| 13588 | #define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
|---|
| 13589 | #define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
|---|
| 13590 | #define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
|---|
| 13591 | #define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
|---|
| 13592 | #define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
|---|
| 13593 | #define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
|---|
| 13594 | #define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
|---|
| 13595 | #define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
|---|
| 13596 | #define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
|---|
| 13597 | #define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
|---|
| 13598 | #define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
|---|
| 13599 | #define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
|---|
| 13600 | #define IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
|---|
| 13601 | #define IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
|---|
| 13602 | #define IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
|---|
| 13603 | #define IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
|---|
| 13604 | #define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
|---|
| 13605 | #define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
|---|
| 13606 | #define IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
|---|
| 13607 | #define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
|---|
| 13608 | #define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
|---|
| 13609 | #define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
|---|
| 13610 | #define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
|---|
| 13611 | //BIF_CFG_DEV0_SWDS_PMI_CAP_LIST |
|---|
| 13612 | #define BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 13613 | #define BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 13614 | #define BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 13615 | #define BIF_CFG_DEV0_SWDS_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 13616 | //BIF_CFG_DEV0_SWDS_PMI_CAP |
|---|
| 13617 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 13618 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 13619 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 13620 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 13621 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 13622 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 13623 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 13624 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 13625 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 13626 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 13627 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 13628 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 13629 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 13630 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 13631 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 13632 | #define BIF_CFG_DEV0_SWDS_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 13633 | //BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL |
|---|
| 13634 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 13635 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 13636 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 13637 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 13638 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 13639 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 13640 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 13641 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 13642 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 13643 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 13644 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 13645 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 13646 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 13647 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 13648 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 13649 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 13650 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 13651 | #define BIF_CFG_DEV0_SWDS_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 13652 | //BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST |
|---|
| 13653 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 13654 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 13655 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 13656 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 13657 | //BIF_CFG_DEV0_SWDS_PCIE_CAP |
|---|
| 13658 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 13659 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 13660 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 13661 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 13662 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 13663 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 13664 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 13665 | #define BIF_CFG_DEV0_SWDS_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 13666 | //BIF_CFG_DEV0_SWDS_DEVICE_CAP |
|---|
| 13667 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 13668 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 13669 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 13670 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 13671 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 13672 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 13673 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 13674 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 13675 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 13676 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 13677 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 13678 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 13679 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 13680 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 13681 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 13682 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 13683 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 13684 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 13685 | //BIF_CFG_DEV0_SWDS_DEVICE_CNTL |
|---|
| 13686 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 13687 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 13688 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 13689 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 13690 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 13691 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 13692 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 13693 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 13694 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 13695 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 13696 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 13697 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
|---|
| 13698 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 13699 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 13700 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 13701 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 13702 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 13703 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 13704 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 13705 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 13706 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 13707 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 13708 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 13709 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
|---|
| 13710 | //BIF_CFG_DEV0_SWDS_DEVICE_STATUS |
|---|
| 13711 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 13712 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 13713 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 13714 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 13715 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 13716 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 13717 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 13718 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 13719 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 13720 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 13721 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 13722 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 13723 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 13724 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 13725 | //BIF_CFG_DEV0_SWDS_LINK_CAP |
|---|
| 13726 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 13727 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 13728 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 13729 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 13730 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 13731 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 13732 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 13733 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 13734 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 13735 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 13736 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 13737 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 13738 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 13739 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 13740 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 13741 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 13742 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 13743 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 13744 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 13745 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 13746 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 13747 | #define BIF_CFG_DEV0_SWDS_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 13748 | //BIF_CFG_DEV0_SWDS_LINK_CNTL |
|---|
| 13749 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 13750 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 13751 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 13752 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 13753 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 13754 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 13755 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 13756 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 13757 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 13758 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 13759 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 13760 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 13761 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 13762 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 13763 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 13764 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 13765 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 13766 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 13767 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 13768 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 13769 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 13770 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 13771 | //BIF_CFG_DEV0_SWDS_LINK_STATUS |
|---|
| 13772 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 13773 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 13774 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 13775 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 13776 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 13777 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 13778 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 13779 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 13780 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 13781 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 13782 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 13783 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 13784 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 13785 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 13786 | //SLOT_CAP |
|---|
| 13787 | #define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
|---|
| 13788 | #define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
|---|
| 13789 | #define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
|---|
| 13790 | #define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
|---|
| 13791 | #define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
|---|
| 13792 | #define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
|---|
| 13793 | #define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
|---|
| 13794 | #define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
|---|
| 13795 | #define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
|---|
| 13796 | #define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
|---|
| 13797 | #define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
|---|
| 13798 | #define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
|---|
| 13799 | #define SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
|---|
| 13800 | #define SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
|---|
| 13801 | #define SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
|---|
| 13802 | #define SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
|---|
| 13803 | #define SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
|---|
| 13804 | #define SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
|---|
| 13805 | #define SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
|---|
| 13806 | #define SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
|---|
| 13807 | #define SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
|---|
| 13808 | #define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
|---|
| 13809 | #define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
|---|
| 13810 | #define SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
|---|
| 13811 | //SLOT_CNTL |
|---|
| 13812 | #define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
|---|
| 13813 | #define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
|---|
| 13814 | #define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
|---|
| 13815 | #define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
|---|
| 13816 | #define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
|---|
| 13817 | #define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
|---|
| 13818 | #define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
|---|
| 13819 | #define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
|---|
| 13820 | #define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
|---|
| 13821 | #define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
|---|
| 13822 | #define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
|---|
| 13823 | #define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
|---|
| 13824 | #define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
|---|
| 13825 | #define SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
|---|
| 13826 | #define SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
|---|
| 13827 | #define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
|---|
| 13828 | #define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
|---|
| 13829 | #define SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
|---|
| 13830 | #define SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
|---|
| 13831 | #define SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
|---|
| 13832 | #define SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
|---|
| 13833 | #define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
|---|
| 13834 | #define SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
|---|
| 13835 | #define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
|---|
| 13836 | //SLOT_STATUS |
|---|
| 13837 | #define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
|---|
| 13838 | #define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
|---|
| 13839 | #define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
|---|
| 13840 | #define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
|---|
| 13841 | #define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
|---|
| 13842 | #define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
|---|
| 13843 | #define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
|---|
| 13844 | #define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
|---|
| 13845 | #define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
|---|
| 13846 | #define SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
|---|
| 13847 | #define SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
|---|
| 13848 | #define SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
|---|
| 13849 | #define SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
|---|
| 13850 | #define SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
|---|
| 13851 | #define SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
|---|
| 13852 | #define SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
|---|
| 13853 | #define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
|---|
| 13854 | #define SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
|---|
| 13855 | //BIF_CFG_DEV0_SWDS_DEVICE_CAP2 |
|---|
| 13856 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 13857 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 13858 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 13859 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 13860 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 13861 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 13862 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 13863 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 13864 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 13865 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 13866 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 13867 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 13868 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 13869 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 13870 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 13871 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 13872 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 13873 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 13874 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 13875 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 13876 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 13877 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 13878 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 13879 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 13880 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 13881 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 13882 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 13883 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 13884 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 13885 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 13886 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 13887 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 13888 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 13889 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 13890 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 13891 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 13892 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 13893 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 13894 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 13895 | #define BIF_CFG_DEV0_SWDS_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 13896 | //BIF_CFG_DEV0_SWDS_DEVICE_CNTL2 |
|---|
| 13897 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 13898 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 13899 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 13900 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 13901 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 13902 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 13903 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 13904 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 13905 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 13906 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 13907 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 13908 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 13909 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 13910 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 13911 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 13912 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 13913 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 13914 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 13915 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 13916 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 13917 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 13918 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 13919 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 13920 | #define BIF_CFG_DEV0_SWDS_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 13921 | //BIF_CFG_DEV0_SWDS_DEVICE_STATUS2 |
|---|
| 13922 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 13923 | #define BIF_CFG_DEV0_SWDS_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 13924 | //BIF_CFG_DEV0_SWDS_LINK_CAP2 |
|---|
| 13925 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 13926 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 13927 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 13928 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 13929 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 13930 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 13931 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 13932 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 13933 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 13934 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 13935 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 13936 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 13937 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 13938 | #define BIF_CFG_DEV0_SWDS_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 13939 | //BIF_CFG_DEV0_SWDS_LINK_CNTL2 |
|---|
| 13940 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 13941 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 13942 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 13943 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 13944 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 13945 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 13946 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 13947 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 13948 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 13949 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 13950 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 13951 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 13952 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 13953 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 13954 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 13955 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 13956 | //BIF_CFG_DEV0_SWDS_LINK_STATUS2 |
|---|
| 13957 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 13958 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 13959 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 13960 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 13961 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 13962 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 13963 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 13964 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 13965 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 13966 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 13967 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 13968 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 13969 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 13970 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 13971 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 13972 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 13973 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 13974 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 13975 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 13976 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 13977 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 13978 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 13979 | //SLOT_CAP2 |
|---|
| 13980 | #define SLOT_CAP2__RESERVED__SHIFT 0x0 |
|---|
| 13981 | #define SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 13982 | //SLOT_CNTL2 |
|---|
| 13983 | #define SLOT_CNTL2__RESERVED__SHIFT 0x0 |
|---|
| 13984 | #define SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
|---|
| 13985 | //SLOT_STATUS2 |
|---|
| 13986 | #define SLOT_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 13987 | #define SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 13988 | //BIF_CFG_DEV0_SWDS_MSI_CAP_LIST |
|---|
| 13989 | #define BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 13990 | #define BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 13991 | #define BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 13992 | #define BIF_CFG_DEV0_SWDS_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 13993 | //BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL |
|---|
| 13994 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 13995 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 13996 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 13997 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 13998 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 13999 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 14000 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 14001 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 14002 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 14003 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 14004 | //BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO |
|---|
| 14005 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 14006 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 14007 | //BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI |
|---|
| 14008 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 14009 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 14010 | //BIF_CFG_DEV0_SWDS_MSI_MSG_DATA |
|---|
| 14011 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 14012 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 14013 | //BIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64 |
|---|
| 14014 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 14015 | #define BIF_CFG_DEV0_SWDS_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 14016 | //SSID_CAP_LIST |
|---|
| 14017 | #define SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 14018 | #define SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 14019 | #define SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 14020 | #define SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 14021 | //SSID_CAP |
|---|
| 14022 | #define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 14023 | #define SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 14024 | #define SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 14025 | #define SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 14026 | //BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 14027 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 14028 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 14029 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 14030 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 14031 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 14032 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 14033 | //BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 14034 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 14035 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 14036 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 14037 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 14038 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 14039 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 14040 | //BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1 |
|---|
| 14041 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 14042 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 14043 | //BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2 |
|---|
| 14044 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 14045 | #define BIF_CFG_DEV0_SWDS_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 14046 | //BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST |
|---|
| 14047 | #define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 14048 | #define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 14049 | #define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 14050 | #define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 14051 | #define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 14052 | #define BIF_CFG_DEV0_SWDS_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 14053 | //BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1 |
|---|
| 14054 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 14055 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 14056 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 14057 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 14058 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 14059 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 14060 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 14061 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 14062 | //BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2 |
|---|
| 14063 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 14064 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 14065 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 14066 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 14067 | //BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL |
|---|
| 14068 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 14069 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 14070 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 14071 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 14072 | //BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS |
|---|
| 14073 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 14074 | #define BIF_CFG_DEV0_SWDS_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 14075 | //BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP |
|---|
| 14076 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 14077 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 14078 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 14079 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 14080 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 14081 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 14082 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 14083 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 14084 | //BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL |
|---|
| 14085 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 14086 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 14087 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 14088 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 14089 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 14090 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 14091 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 14092 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 14093 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 14094 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 14095 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 14096 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 14097 | //BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS |
|---|
| 14098 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 14099 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 14100 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 14101 | #define BIF_CFG_DEV0_SWDS_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 14102 | //BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP |
|---|
| 14103 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 14104 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 14105 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 14106 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 14107 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 14108 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 14109 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 14110 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 14111 | //BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL |
|---|
| 14112 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 14113 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 14114 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 14115 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 14116 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 14117 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 14118 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 14119 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 14120 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 14121 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 14122 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 14123 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 14124 | //BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS |
|---|
| 14125 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 14126 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 14127 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 14128 | #define BIF_CFG_DEV0_SWDS_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 14129 | //BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 14130 | #define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 14131 | #define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 14132 | #define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 14133 | #define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 14134 | #define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 14135 | #define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 14136 | //BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 14137 | #define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 14138 | #define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 14139 | //BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 14140 | #define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 14141 | #define BIF_CFG_DEV0_SWDS_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 14142 | //BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 14143 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 14144 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 14145 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 14146 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 14147 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 14148 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 14149 | //BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS |
|---|
| 14150 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 14151 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 14152 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 14153 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 14154 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 14155 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 14156 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 14157 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 14158 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 14159 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 14160 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 14161 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 14162 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 14163 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 14164 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 14165 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 14166 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 14167 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 14168 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 14169 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 14170 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 14171 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 14172 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 14173 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 14174 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 14175 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 14176 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 14177 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 14178 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 14179 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 14180 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 14181 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 14182 | //BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK |
|---|
| 14183 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 14184 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 14185 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 14186 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 14187 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 14188 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 14189 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 14190 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 14191 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 14192 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 14193 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 14194 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 14195 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 14196 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 14197 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 14198 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 14199 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 14200 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 14201 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 14202 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 14203 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 14204 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 14205 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 14206 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 14207 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 14208 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 14209 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 14210 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 14211 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 14212 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 14213 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 14214 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 14215 | //BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 14216 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 14217 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 14218 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 14219 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 14220 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 14221 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 14222 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 14223 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 14224 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 14225 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 14226 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 14227 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 14228 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 14229 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 14230 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 14231 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 14232 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 14233 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 14234 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 14235 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 14236 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 14237 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 14238 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 14239 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 14240 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 14241 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 14242 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 14243 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 14244 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 14245 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 14246 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 14247 | #define BIF_CFG_DEV0_SWDS_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 14248 | //BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS |
|---|
| 14249 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 14250 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 14251 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 14252 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 14253 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 14254 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 14255 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 14256 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 14257 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 14258 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 14259 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 14260 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 14261 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 14262 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 14263 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 14264 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 14265 | //BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK |
|---|
| 14266 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 14267 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 14268 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 14269 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 14270 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 14271 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 14272 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 14273 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 14274 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 14275 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 14276 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 14277 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 14278 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 14279 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 14280 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 14281 | #define BIF_CFG_DEV0_SWDS_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 14282 | //BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 14283 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 14284 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 14285 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 14286 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 14287 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 14288 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 14289 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 14290 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 14291 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 14292 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 14293 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 14294 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 14295 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 14296 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 14297 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 14298 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 14299 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 14300 | #define BIF_CFG_DEV0_SWDS_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 14301 | //BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0 |
|---|
| 14302 | #define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 14303 | #define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 14304 | //BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1 |
|---|
| 14305 | #define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 14306 | #define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 14307 | //BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2 |
|---|
| 14308 | #define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 14309 | #define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 14310 | //BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3 |
|---|
| 14311 | #define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 14312 | #define BIF_CFG_DEV0_SWDS_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 14313 | //BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0 |
|---|
| 14314 | #define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 14315 | #define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 14316 | //BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1 |
|---|
| 14317 | #define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 14318 | #define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 14319 | //BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2 |
|---|
| 14320 | #define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 14321 | #define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 14322 | //BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3 |
|---|
| 14323 | #define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 14324 | #define BIF_CFG_DEV0_SWDS_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 14325 | //BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 14326 | #define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 14327 | #define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 14328 | #define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 14329 | #define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 14330 | #define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 14331 | #define BIF_CFG_DEV0_SWDS_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 14332 | //BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3 |
|---|
| 14333 | #define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 14334 | #define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
|---|
| 14335 | #define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
|---|
| 14336 | #define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 14337 | #define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 14338 | #define BIF_CFG_DEV0_SWDS_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
|---|
| 14339 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS |
|---|
| 14340 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 14341 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
|---|
| 14342 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 14343 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
|---|
| 14344 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 14345 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14346 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14347 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14348 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14349 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14350 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14351 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14352 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14353 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14354 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14355 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL |
|---|
| 14356 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14357 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14358 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14359 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14360 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14361 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14362 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14363 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14364 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14365 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14366 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL |
|---|
| 14367 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14368 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14369 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14370 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14371 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14372 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14373 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14374 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14375 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14376 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14377 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL |
|---|
| 14378 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14379 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14380 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14381 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14382 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14383 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14384 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14385 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14386 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14387 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14388 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL |
|---|
| 14389 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14390 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14391 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14392 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14393 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14394 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14395 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14396 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14397 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14398 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14399 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 14400 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14401 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14402 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14403 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14404 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14405 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14406 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14407 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14408 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14409 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14410 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 14411 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14412 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14413 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14414 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14415 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14416 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14417 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14418 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14419 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14420 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14421 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 14422 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14423 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14424 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14425 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14426 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14427 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14428 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14429 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14430 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14431 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14432 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 14433 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14434 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14435 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14436 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14437 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14438 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14439 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14440 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14441 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14442 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14443 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 14444 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14445 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14446 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14447 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14448 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14449 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14450 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14451 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14452 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14453 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14454 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 14455 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14456 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14457 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14458 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14459 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14460 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14461 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14462 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14463 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14464 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14465 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 14466 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14467 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14468 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14469 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14470 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14471 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14472 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14473 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14474 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14475 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14476 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 14477 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14478 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14479 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14480 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14481 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14482 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14483 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14484 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14485 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14486 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14487 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 14488 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14489 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14490 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14491 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14492 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14493 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14494 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14495 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14496 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14497 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14498 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 14499 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14500 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14501 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14502 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14503 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14504 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14505 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14506 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14507 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14508 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14509 | //BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 14510 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 14511 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 14512 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 14513 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 14514 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 14515 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 14516 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 14517 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 14518 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 14519 | #define BIF_CFG_DEV0_SWDS_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 14520 | //BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST |
|---|
| 14521 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 14522 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 14523 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 14524 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 14525 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 14526 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 14527 | //BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP |
|---|
| 14528 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 14529 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 14530 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 14531 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 14532 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 14533 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 14534 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 14535 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 14536 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 14537 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 14538 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 14539 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 14540 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 14541 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 14542 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 14543 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 14544 | //BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL |
|---|
| 14545 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 14546 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 14547 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 14548 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 14549 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 14550 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 14551 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 14552 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 14553 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 14554 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 14555 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 14556 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 14557 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 14558 | #define BIF_CFG_DEV0_SWDS_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 14559 | //BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST |
|---|
| 14560 | #define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 14561 | #define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 14562 | #define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 14563 | #define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 14564 | #define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 14565 | #define BIF_CFG_DEV0_SWDS_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 14566 | //BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP |
|---|
| 14567 | #define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 14568 | #define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
|---|
| 14569 | #define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 14570 | #define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
|---|
| 14571 | //BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS |
|---|
| 14572 | #define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 14573 | #define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
|---|
| 14574 | #define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 14575 | #define BIF_CFG_DEV0_SWDS_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
|---|
| 14576 | //BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST |
|---|
| 14577 | #define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 14578 | #define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 14579 | #define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 14580 | #define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 14581 | #define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 14582 | #define BIF_CFG_DEV0_SWDS_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 14583 | //BIF_CFG_DEV0_SWDS_LINK_CAP_16GT |
|---|
| 14584 | #define BIF_CFG_DEV0_SWDS_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
|---|
| 14585 | #define BIF_CFG_DEV0_SWDS_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 14586 | //BIF_CFG_DEV0_SWDS_LINK_CNTL_16GT |
|---|
| 14587 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
|---|
| 14588 | #define BIF_CFG_DEV0_SWDS_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 14589 | //BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT |
|---|
| 14590 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
|---|
| 14591 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
|---|
| 14592 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
|---|
| 14593 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
|---|
| 14594 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
|---|
| 14595 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
|---|
| 14596 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
|---|
| 14597 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
|---|
| 14598 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
|---|
| 14599 | #define BIF_CFG_DEV0_SWDS_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
|---|
| 14600 | //BIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT |
|---|
| 14601 | #define BIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 14602 | #define BIF_CFG_DEV0_SWDS_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 14603 | //BIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT |
|---|
| 14604 | #define BIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 14605 | #define BIF_CFG_DEV0_SWDS_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 14606 | //BIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT |
|---|
| 14607 | #define BIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 14608 | #define BIF_CFG_DEV0_SWDS_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 14609 | //BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT |
|---|
| 14610 | #define BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14611 | #define BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14612 | #define BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14613 | #define BIF_CFG_DEV0_SWDS_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14614 | //BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT |
|---|
| 14615 | #define BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14616 | #define BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14617 | #define BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14618 | #define BIF_CFG_DEV0_SWDS_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14619 | //BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT |
|---|
| 14620 | #define BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14621 | #define BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14622 | #define BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14623 | #define BIF_CFG_DEV0_SWDS_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14624 | //BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT |
|---|
| 14625 | #define BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14626 | #define BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14627 | #define BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14628 | #define BIF_CFG_DEV0_SWDS_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14629 | //BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT |
|---|
| 14630 | #define BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14631 | #define BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14632 | #define BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14633 | #define BIF_CFG_DEV0_SWDS_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14634 | //BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT |
|---|
| 14635 | #define BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14636 | #define BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14637 | #define BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14638 | #define BIF_CFG_DEV0_SWDS_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14639 | //BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT |
|---|
| 14640 | #define BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14641 | #define BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14642 | #define BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14643 | #define BIF_CFG_DEV0_SWDS_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14644 | //BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT |
|---|
| 14645 | #define BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14646 | #define BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14647 | #define BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14648 | #define BIF_CFG_DEV0_SWDS_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14649 | //BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT |
|---|
| 14650 | #define BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14651 | #define BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14652 | #define BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14653 | #define BIF_CFG_DEV0_SWDS_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14654 | //BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT |
|---|
| 14655 | #define BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14656 | #define BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14657 | #define BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14658 | #define BIF_CFG_DEV0_SWDS_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14659 | //BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT |
|---|
| 14660 | #define BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14661 | #define BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14662 | #define BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14663 | #define BIF_CFG_DEV0_SWDS_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14664 | //BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT |
|---|
| 14665 | #define BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14666 | #define BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14667 | #define BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14668 | #define BIF_CFG_DEV0_SWDS_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14669 | //BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT |
|---|
| 14670 | #define BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14671 | #define BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14672 | #define BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14673 | #define BIF_CFG_DEV0_SWDS_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14674 | //BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT |
|---|
| 14675 | #define BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14676 | #define BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14677 | #define BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14678 | #define BIF_CFG_DEV0_SWDS_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14679 | //BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 14680 | #define BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14681 | #define BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14682 | #define BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14683 | #define BIF_CFG_DEV0_SWDS_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14684 | //BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 14685 | #define BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 14686 | #define BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 14687 | #define BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 14688 | #define BIF_CFG_DEV0_SWDS_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 14689 | //BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 14690 | #define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 14691 | #define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 14692 | #define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 14693 | #define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 14694 | #define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 14695 | #define BIF_CFG_DEV0_SWDS_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 14696 | //BIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP |
|---|
| 14697 | #define BIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 14698 | #define BIF_CFG_DEV0_SWDS_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 14699 | //BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS |
|---|
| 14700 | #define BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
|---|
| 14701 | #define BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
|---|
| 14702 | #define BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
|---|
| 14703 | #define BIF_CFG_DEV0_SWDS_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
|---|
| 14704 | //BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL |
|---|
| 14705 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14706 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14707 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14708 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14709 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14710 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14711 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 14712 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14713 | //BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS |
|---|
| 14714 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14715 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14716 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14717 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14718 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14719 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14720 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14721 | #define BIF_CFG_DEV0_SWDS_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14722 | //BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL |
|---|
| 14723 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14724 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14725 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14726 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14727 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14728 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14729 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 14730 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14731 | //BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS |
|---|
| 14732 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14733 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14734 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14735 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14736 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14737 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14738 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14739 | #define BIF_CFG_DEV0_SWDS_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14740 | //BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL |
|---|
| 14741 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14742 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14743 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14744 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14745 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14746 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14747 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 14748 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14749 | //BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS |
|---|
| 14750 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14751 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14752 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14753 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14754 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14755 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14756 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14757 | #define BIF_CFG_DEV0_SWDS_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14758 | //BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL |
|---|
| 14759 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14760 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14761 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14762 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14763 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14764 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14765 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 14766 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14767 | //BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS |
|---|
| 14768 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14769 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14770 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14771 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14772 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14773 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14774 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14775 | #define BIF_CFG_DEV0_SWDS_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14776 | //BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL |
|---|
| 14777 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14778 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14779 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14780 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14781 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14782 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14783 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 14784 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14785 | //BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS |
|---|
| 14786 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14787 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14788 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14789 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14790 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14791 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14792 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14793 | #define BIF_CFG_DEV0_SWDS_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14794 | //BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL |
|---|
| 14795 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14796 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14797 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14798 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14799 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14800 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14801 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 14802 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14803 | //BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS |
|---|
| 14804 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14805 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14806 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14807 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14808 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14809 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14810 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14811 | #define BIF_CFG_DEV0_SWDS_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14812 | //BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL |
|---|
| 14813 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14814 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14815 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14816 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14817 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14818 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14819 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 14820 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14821 | //BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS |
|---|
| 14822 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14823 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14824 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14825 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14826 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14827 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14828 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14829 | #define BIF_CFG_DEV0_SWDS_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14830 | //BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL |
|---|
| 14831 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14832 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14833 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14834 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14835 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14836 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14837 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 14838 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14839 | //BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS |
|---|
| 14840 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14841 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14842 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14843 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14844 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14845 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14846 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14847 | #define BIF_CFG_DEV0_SWDS_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14848 | //BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL |
|---|
| 14849 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14850 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14851 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14852 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14853 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14854 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14855 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 14856 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14857 | //BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS |
|---|
| 14858 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14859 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14860 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14861 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14862 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14863 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14864 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14865 | #define BIF_CFG_DEV0_SWDS_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14866 | //BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL |
|---|
| 14867 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14868 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14869 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14870 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14871 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14872 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14873 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 14874 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14875 | //BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS |
|---|
| 14876 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14877 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14878 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14879 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14880 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14881 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14882 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14883 | #define BIF_CFG_DEV0_SWDS_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14884 | //BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL |
|---|
| 14885 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14886 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14887 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14888 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14889 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14890 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14891 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 14892 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14893 | //BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS |
|---|
| 14894 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14895 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14896 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14897 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14898 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14899 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14900 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14901 | #define BIF_CFG_DEV0_SWDS_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14902 | //BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL |
|---|
| 14903 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14904 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14905 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14906 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14907 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14908 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14909 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 14910 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14911 | //BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS |
|---|
| 14912 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14913 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14914 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14915 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14916 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14917 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14918 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14919 | #define BIF_CFG_DEV0_SWDS_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14920 | //BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL |
|---|
| 14921 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14922 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14923 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14924 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14925 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14926 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14927 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 14928 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14929 | //BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS |
|---|
| 14930 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14931 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14932 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14933 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14934 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14935 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14936 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14937 | #define BIF_CFG_DEV0_SWDS_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14938 | //BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL |
|---|
| 14939 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14940 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14941 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14942 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14943 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14944 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14945 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 14946 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14947 | //BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS |
|---|
| 14948 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14949 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14950 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14951 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14952 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14953 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14954 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14955 | #define BIF_CFG_DEV0_SWDS_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14956 | //BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL |
|---|
| 14957 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14958 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14959 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14960 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14961 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14962 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14963 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 14964 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14965 | //BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS |
|---|
| 14966 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14967 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14968 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14969 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14970 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14971 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14972 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14973 | #define BIF_CFG_DEV0_SWDS_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14974 | //BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL |
|---|
| 14975 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 14976 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 14977 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 14978 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 14979 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 14980 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 14981 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 14982 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 14983 | //BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS |
|---|
| 14984 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 14985 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 14986 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 14987 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 14988 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 14989 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 14990 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 14991 | #define BIF_CFG_DEV0_SWDS_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 14992 | |
|---|
| 14993 | |
|---|
| 14994 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
|---|
| 14995 | //MM_INDEX |
|---|
| 14996 | #define MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 14997 | #define MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 14998 | #define MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 14999 | #define MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 15000 | //MM_DATA |
|---|
| 15001 | #define MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 15002 | #define MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 15003 | //MM_INDEX_HI |
|---|
| 15004 | #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 15005 | #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 15006 | |
|---|
| 15007 | |
|---|
| 15008 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
|---|
| 15009 | //RCC_STRAP0_RCC_BIF_STRAP0 |
|---|
| 15010 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT 0x0 |
|---|
| 15011 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN__SHIFT 0x1 |
|---|
| 15012 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 |
|---|
| 15013 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 |
|---|
| 15014 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 |
|---|
| 15015 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 |
|---|
| 15016 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 |
|---|
| 15017 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 |
|---|
| 15018 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa |
|---|
| 15019 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb |
|---|
| 15020 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc |
|---|
| 15021 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd |
|---|
| 15022 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe |
|---|
| 15023 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf |
|---|
| 15024 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 |
|---|
| 15025 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 |
|---|
| 15026 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 |
|---|
| 15027 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 |
|---|
| 15028 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 |
|---|
| 15029 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a |
|---|
| 15030 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b |
|---|
| 15031 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d |
|---|
| 15032 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e |
|---|
| 15033 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f |
|---|
| 15034 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK 0x00000001L |
|---|
| 15035 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN_MASK 0x00000002L |
|---|
| 15036 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L |
|---|
| 15037 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L |
|---|
| 15038 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L |
|---|
| 15039 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L |
|---|
| 15040 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L |
|---|
| 15041 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L |
|---|
| 15042 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L |
|---|
| 15043 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L |
|---|
| 15044 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L |
|---|
| 15045 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L |
|---|
| 15046 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L |
|---|
| 15047 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L |
|---|
| 15048 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L |
|---|
| 15049 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L |
|---|
| 15050 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L |
|---|
| 15051 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L |
|---|
| 15052 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L |
|---|
| 15053 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L |
|---|
| 15054 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L |
|---|
| 15055 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L |
|---|
| 15056 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L |
|---|
| 15057 | #define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L |
|---|
| 15058 | //RCC_STRAP0_RCC_BIF_STRAP1 |
|---|
| 15059 | #define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 |
|---|
| 15060 | #define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 |
|---|
| 15061 | #define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 |
|---|
| 15062 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 |
|---|
| 15063 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN__SHIFT 0x4 |
|---|
| 15064 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 |
|---|
| 15065 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 |
|---|
| 15066 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 |
|---|
| 15067 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 |
|---|
| 15068 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 |
|---|
| 15069 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa |
|---|
| 15070 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc |
|---|
| 15071 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd |
|---|
| 15072 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf |
|---|
| 15073 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 |
|---|
| 15074 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 |
|---|
| 15075 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 |
|---|
| 15076 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 |
|---|
| 15077 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 |
|---|
| 15078 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 |
|---|
| 15079 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 |
|---|
| 15080 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 |
|---|
| 15081 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 |
|---|
| 15082 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a |
|---|
| 15083 | #define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L |
|---|
| 15084 | #define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L |
|---|
| 15085 | #define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L |
|---|
| 15086 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L |
|---|
| 15087 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN_MASK 0x00000010L |
|---|
| 15088 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L |
|---|
| 15089 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L |
|---|
| 15090 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L |
|---|
| 15091 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L |
|---|
| 15092 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L |
|---|
| 15093 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L |
|---|
| 15094 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L |
|---|
| 15095 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L |
|---|
| 15096 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L |
|---|
| 15097 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L |
|---|
| 15098 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L |
|---|
| 15099 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L |
|---|
| 15100 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L |
|---|
| 15101 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L |
|---|
| 15102 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L |
|---|
| 15103 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L |
|---|
| 15104 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L |
|---|
| 15105 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L |
|---|
| 15106 | #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L |
|---|
| 15107 | //RCC_STRAP0_RCC_BIF_STRAP2 |
|---|
| 15108 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 |
|---|
| 15109 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 |
|---|
| 15110 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 |
|---|
| 15111 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 |
|---|
| 15112 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 |
|---|
| 15113 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 |
|---|
| 15114 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 |
|---|
| 15115 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa |
|---|
| 15116 | #define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xc |
|---|
| 15117 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe |
|---|
| 15118 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf |
|---|
| 15119 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 |
|---|
| 15120 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 |
|---|
| 15121 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L |
|---|
| 15122 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L |
|---|
| 15123 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L |
|---|
| 15124 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L |
|---|
| 15125 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L |
|---|
| 15126 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L |
|---|
| 15127 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L |
|---|
| 15128 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L |
|---|
| 15129 | #define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00003000L |
|---|
| 15130 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L |
|---|
| 15131 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L |
|---|
| 15132 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L |
|---|
| 15133 | #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L |
|---|
| 15134 | //RCC_STRAP0_RCC_BIF_STRAP3 |
|---|
| 15135 | #define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 |
|---|
| 15136 | #define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 |
|---|
| 15137 | #define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL |
|---|
| 15138 | #define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L |
|---|
| 15139 | //RCC_STRAP0_RCC_BIF_STRAP4 |
|---|
| 15140 | #define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 |
|---|
| 15141 | #define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 |
|---|
| 15142 | #define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL |
|---|
| 15143 | #define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L |
|---|
| 15144 | //RCC_STRAP0_RCC_BIF_STRAP5 |
|---|
| 15145 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 |
|---|
| 15146 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 |
|---|
| 15147 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 |
|---|
| 15148 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 |
|---|
| 15149 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 |
|---|
| 15150 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 |
|---|
| 15151 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 |
|---|
| 15152 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 |
|---|
| 15153 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 |
|---|
| 15154 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b |
|---|
| 15155 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c |
|---|
| 15156 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL |
|---|
| 15157 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L |
|---|
| 15158 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L |
|---|
| 15159 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L |
|---|
| 15160 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L |
|---|
| 15161 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L |
|---|
| 15162 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L |
|---|
| 15163 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L |
|---|
| 15164 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L |
|---|
| 15165 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L |
|---|
| 15166 | #define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L |
|---|
| 15167 | //RCC_STRAP0_RCC_BIF_STRAP6 |
|---|
| 15168 | #define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3__SHIFT 0x0 |
|---|
| 15169 | #define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3_MASK 0xFFFFFFFFL |
|---|
| 15170 | //RCC_STRAP0_RCC_DEV0_PORT_STRAP0 |
|---|
| 15171 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 |
|---|
| 15172 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 |
|---|
| 15173 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 |
|---|
| 15174 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 |
|---|
| 15175 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 |
|---|
| 15176 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 |
|---|
| 15177 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 |
|---|
| 15178 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 |
|---|
| 15179 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c |
|---|
| 15180 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f |
|---|
| 15181 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L |
|---|
| 15182 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L |
|---|
| 15183 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L |
|---|
| 15184 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L |
|---|
| 15185 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001FFFE0L |
|---|
| 15186 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L |
|---|
| 15187 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L |
|---|
| 15188 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L |
|---|
| 15189 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L |
|---|
| 15190 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L |
|---|
| 15191 | //RCC_STRAP0_RCC_DEV0_PORT_STRAP1 |
|---|
| 15192 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 |
|---|
| 15193 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 |
|---|
| 15194 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL |
|---|
| 15195 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L |
|---|
| 15196 | //RCC_STRAP0_RCC_DEV0_PORT_STRAP2 |
|---|
| 15197 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 |
|---|
| 15198 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 |
|---|
| 15199 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 |
|---|
| 15200 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 |
|---|
| 15201 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 |
|---|
| 15202 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 |
|---|
| 15203 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 |
|---|
| 15204 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 |
|---|
| 15205 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 |
|---|
| 15206 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 |
|---|
| 15207 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc |
|---|
| 15208 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd |
|---|
| 15209 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe |
|---|
| 15210 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf |
|---|
| 15211 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 |
|---|
| 15212 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 |
|---|
| 15213 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x12 |
|---|
| 15214 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 |
|---|
| 15215 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 |
|---|
| 15216 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a |
|---|
| 15217 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d |
|---|
| 15218 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L |
|---|
| 15219 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L |
|---|
| 15220 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L |
|---|
| 15221 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L |
|---|
| 15222 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L |
|---|
| 15223 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L |
|---|
| 15224 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L |
|---|
| 15225 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L |
|---|
| 15226 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L |
|---|
| 15227 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L |
|---|
| 15228 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L |
|---|
| 15229 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L |
|---|
| 15230 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L |
|---|
| 15231 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L |
|---|
| 15232 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L |
|---|
| 15233 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L |
|---|
| 15234 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x000C0000L |
|---|
| 15235 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L |
|---|
| 15236 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L |
|---|
| 15237 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L |
|---|
| 15238 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L |
|---|
| 15239 | //RCC_STRAP0_RCC_DEV0_PORT_STRAP3 |
|---|
| 15240 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 |
|---|
| 15241 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 |
|---|
| 15242 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 |
|---|
| 15243 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 |
|---|
| 15244 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 |
|---|
| 15245 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 |
|---|
| 15246 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 |
|---|
| 15247 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 |
|---|
| 15248 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb |
|---|
| 15249 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe |
|---|
| 15250 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 |
|---|
| 15251 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 |
|---|
| 15252 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 |
|---|
| 15253 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b |
|---|
| 15254 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d |
|---|
| 15255 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e |
|---|
| 15256 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f |
|---|
| 15257 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L |
|---|
| 15258 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L |
|---|
| 15259 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L |
|---|
| 15260 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L |
|---|
| 15261 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L |
|---|
| 15262 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L |
|---|
| 15263 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L |
|---|
| 15264 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L |
|---|
| 15265 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L |
|---|
| 15266 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L |
|---|
| 15267 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L |
|---|
| 15268 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L |
|---|
| 15269 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L |
|---|
| 15270 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L |
|---|
| 15271 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L |
|---|
| 15272 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0_MASK 0x40000000L |
|---|
| 15273 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L |
|---|
| 15274 | //RCC_STRAP0_RCC_DEV0_PORT_STRAP4 |
|---|
| 15275 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 |
|---|
| 15276 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 |
|---|
| 15277 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 |
|---|
| 15278 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 |
|---|
| 15279 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL |
|---|
| 15280 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L |
|---|
| 15281 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L |
|---|
| 15282 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L |
|---|
| 15283 | //RCC_STRAP0_RCC_DEV0_PORT_STRAP5 |
|---|
| 15284 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 |
|---|
| 15285 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 |
|---|
| 15286 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 |
|---|
| 15287 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 |
|---|
| 15288 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 |
|---|
| 15289 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 |
|---|
| 15290 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 |
|---|
| 15291 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 |
|---|
| 15292 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 |
|---|
| 15293 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 |
|---|
| 15294 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 |
|---|
| 15295 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 |
|---|
| 15296 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a |
|---|
| 15297 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b |
|---|
| 15298 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c |
|---|
| 15299 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d |
|---|
| 15300 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e |
|---|
| 15301 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f |
|---|
| 15302 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL |
|---|
| 15303 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L |
|---|
| 15304 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L |
|---|
| 15305 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L |
|---|
| 15306 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L |
|---|
| 15307 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L |
|---|
| 15308 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L |
|---|
| 15309 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L |
|---|
| 15310 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L |
|---|
| 15311 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L |
|---|
| 15312 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L |
|---|
| 15313 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L |
|---|
| 15314 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L |
|---|
| 15315 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L |
|---|
| 15316 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L |
|---|
| 15317 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L |
|---|
| 15318 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L |
|---|
| 15319 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L |
|---|
| 15320 | //RCC_STRAP0_RCC_DEV0_PORT_STRAP6 |
|---|
| 15321 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 |
|---|
| 15322 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 |
|---|
| 15323 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 |
|---|
| 15324 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 |
|---|
| 15325 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 |
|---|
| 15326 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 |
|---|
| 15327 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 |
|---|
| 15328 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 |
|---|
| 15329 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 |
|---|
| 15330 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc |
|---|
| 15331 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 |
|---|
| 15332 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L |
|---|
| 15333 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L |
|---|
| 15334 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L |
|---|
| 15335 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L |
|---|
| 15336 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L |
|---|
| 15337 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L |
|---|
| 15338 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L |
|---|
| 15339 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L |
|---|
| 15340 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L |
|---|
| 15341 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L |
|---|
| 15342 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L |
|---|
| 15343 | //RCC_STRAP0_RCC_DEV0_PORT_STRAP7 |
|---|
| 15344 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 |
|---|
| 15345 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 |
|---|
| 15346 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc |
|---|
| 15347 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 |
|---|
| 15348 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 |
|---|
| 15349 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d |
|---|
| 15350 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL |
|---|
| 15351 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L |
|---|
| 15352 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L |
|---|
| 15353 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L |
|---|
| 15354 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L |
|---|
| 15355 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L |
|---|
| 15356 | //RCC_STRAP0_RCC_DEV0_PORT_STRAP8 |
|---|
| 15357 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 |
|---|
| 15358 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 |
|---|
| 15359 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 |
|---|
| 15360 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 |
|---|
| 15361 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL |
|---|
| 15362 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L |
|---|
| 15363 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L |
|---|
| 15364 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L |
|---|
| 15365 | //RCC_STRAP0_RCC_DEV0_PORT_STRAP9 |
|---|
| 15366 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 |
|---|
| 15367 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 |
|---|
| 15368 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL |
|---|
| 15369 | #define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L |
|---|
| 15370 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 |
|---|
| 15371 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
|---|
| 15372 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
|---|
| 15373 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
|---|
| 15374 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
|---|
| 15375 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
|---|
| 15376 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
|---|
| 15377 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
|---|
| 15378 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
|---|
| 15379 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 15380 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
|---|
| 15381 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
|---|
| 15382 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
|---|
| 15383 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
|---|
| 15384 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
|---|
| 15385 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
|---|
| 15386 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
|---|
| 15387 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP1 |
|---|
| 15388 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
|---|
| 15389 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 |
|---|
| 15390 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 15391 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L |
|---|
| 15392 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP13 |
|---|
| 15393 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 |
|---|
| 15394 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 |
|---|
| 15395 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 |
|---|
| 15396 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL |
|---|
| 15397 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L |
|---|
| 15398 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L |
|---|
| 15399 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP2 |
|---|
| 15400 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 |
|---|
| 15401 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 |
|---|
| 15402 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 |
|---|
| 15403 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 |
|---|
| 15404 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 |
|---|
| 15405 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 |
|---|
| 15406 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe |
|---|
| 15407 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf |
|---|
| 15408 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 |
|---|
| 15409 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 |
|---|
| 15410 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 |
|---|
| 15411 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 |
|---|
| 15412 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 |
|---|
| 15413 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 |
|---|
| 15414 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 |
|---|
| 15415 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 |
|---|
| 15416 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b |
|---|
| 15417 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c |
|---|
| 15418 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d |
|---|
| 15419 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e |
|---|
| 15420 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f |
|---|
| 15421 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L |
|---|
| 15422 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003EL |
|---|
| 15423 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L |
|---|
| 15424 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L |
|---|
| 15425 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L |
|---|
| 15426 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L |
|---|
| 15427 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L |
|---|
| 15428 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L |
|---|
| 15429 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L |
|---|
| 15430 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L |
|---|
| 15431 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L |
|---|
| 15432 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L |
|---|
| 15433 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L |
|---|
| 15434 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L |
|---|
| 15435 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L |
|---|
| 15436 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L |
|---|
| 15437 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L |
|---|
| 15438 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L |
|---|
| 15439 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L |
|---|
| 15440 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L |
|---|
| 15441 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L |
|---|
| 15442 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP3 |
|---|
| 15443 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 |
|---|
| 15444 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 |
|---|
| 15445 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 |
|---|
| 15446 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 |
|---|
| 15447 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 |
|---|
| 15448 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 |
|---|
| 15449 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 |
|---|
| 15450 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 |
|---|
| 15451 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 |
|---|
| 15452 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a |
|---|
| 15453 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b |
|---|
| 15454 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c |
|---|
| 15455 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L |
|---|
| 15456 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L |
|---|
| 15457 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003FFFCL |
|---|
| 15458 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L |
|---|
| 15459 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L |
|---|
| 15460 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L |
|---|
| 15461 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L |
|---|
| 15462 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L |
|---|
| 15463 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0_MASK 0x02000000L |
|---|
| 15464 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L |
|---|
| 15465 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L |
|---|
| 15466 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L |
|---|
| 15467 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP4 |
|---|
| 15468 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 |
|---|
| 15469 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 |
|---|
| 15470 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 |
|---|
| 15471 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 |
|---|
| 15472 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 |
|---|
| 15473 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c |
|---|
| 15474 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f |
|---|
| 15475 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL |
|---|
| 15476 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L |
|---|
| 15477 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L |
|---|
| 15478 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L |
|---|
| 15479 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L |
|---|
| 15480 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L |
|---|
| 15481 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L |
|---|
| 15482 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP5 |
|---|
| 15483 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 |
|---|
| 15484 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 15485 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP8 |
|---|
| 15486 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 |
|---|
| 15487 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 |
|---|
| 15488 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 |
|---|
| 15489 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 |
|---|
| 15490 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 |
|---|
| 15491 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 |
|---|
| 15492 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 |
|---|
| 15493 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd |
|---|
| 15494 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xf |
|---|
| 15495 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x11 |
|---|
| 15496 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x14 |
|---|
| 15497 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x18 |
|---|
| 15498 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a |
|---|
| 15499 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b |
|---|
| 15500 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e |
|---|
| 15501 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L |
|---|
| 15502 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L |
|---|
| 15503 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00000010L |
|---|
| 15504 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00000060L |
|---|
| 15505 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L |
|---|
| 15506 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L |
|---|
| 15507 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L |
|---|
| 15508 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x00006000L |
|---|
| 15509 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00018000L |
|---|
| 15510 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x000E0000L |
|---|
| 15511 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00F00000L |
|---|
| 15512 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03000000L |
|---|
| 15513 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L |
|---|
| 15514 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L |
|---|
| 15515 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L |
|---|
| 15516 | //RCC_STRAP0_RCC_DEV0_EPF0_STRAP9 |
|---|
| 15517 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 |
|---|
| 15518 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 |
|---|
| 15519 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 |
|---|
| 15520 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 |
|---|
| 15521 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 15522 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L |
|---|
| 15523 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L |
|---|
| 15524 | #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L |
|---|
| 15525 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP0 |
|---|
| 15526 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 |
|---|
| 15527 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 |
|---|
| 15528 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 |
|---|
| 15529 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c |
|---|
| 15530 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d |
|---|
| 15531 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e |
|---|
| 15532 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f |
|---|
| 15533 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL |
|---|
| 15534 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L |
|---|
| 15535 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L |
|---|
| 15536 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L |
|---|
| 15537 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L |
|---|
| 15538 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L |
|---|
| 15539 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L |
|---|
| 15540 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP10 |
|---|
| 15541 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 15542 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 |
|---|
| 15543 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 15544 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL |
|---|
| 15545 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP11 |
|---|
| 15546 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 15547 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 |
|---|
| 15548 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 15549 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL |
|---|
| 15550 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP12 |
|---|
| 15551 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 15552 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 |
|---|
| 15553 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 15554 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL |
|---|
| 15555 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP13 |
|---|
| 15556 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 |
|---|
| 15557 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 |
|---|
| 15558 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 |
|---|
| 15559 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL |
|---|
| 15560 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L |
|---|
| 15561 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L |
|---|
| 15562 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP2 |
|---|
| 15563 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 |
|---|
| 15564 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 |
|---|
| 15565 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 |
|---|
| 15566 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe |
|---|
| 15567 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 |
|---|
| 15568 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 |
|---|
| 15569 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 |
|---|
| 15570 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 |
|---|
| 15571 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 |
|---|
| 15572 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 |
|---|
| 15573 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 |
|---|
| 15574 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 |
|---|
| 15575 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c |
|---|
| 15576 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d |
|---|
| 15577 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e |
|---|
| 15578 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f |
|---|
| 15579 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L |
|---|
| 15580 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L |
|---|
| 15581 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L |
|---|
| 15582 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L |
|---|
| 15583 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L |
|---|
| 15584 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L |
|---|
| 15585 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L |
|---|
| 15586 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L |
|---|
| 15587 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L |
|---|
| 15588 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L |
|---|
| 15589 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L |
|---|
| 15590 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L |
|---|
| 15591 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L |
|---|
| 15592 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L |
|---|
| 15593 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L |
|---|
| 15594 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L |
|---|
| 15595 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP3 |
|---|
| 15596 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 |
|---|
| 15597 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 |
|---|
| 15598 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 |
|---|
| 15599 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 |
|---|
| 15600 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 |
|---|
| 15601 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 |
|---|
| 15602 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 |
|---|
| 15603 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 |
|---|
| 15604 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a |
|---|
| 15605 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b |
|---|
| 15606 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L |
|---|
| 15607 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L |
|---|
| 15608 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003FFFCL |
|---|
| 15609 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L |
|---|
| 15610 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L |
|---|
| 15611 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L |
|---|
| 15612 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L |
|---|
| 15613 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1_MASK 0x02000000L |
|---|
| 15614 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L |
|---|
| 15615 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L |
|---|
| 15616 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP4 |
|---|
| 15617 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 |
|---|
| 15618 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 |
|---|
| 15619 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 |
|---|
| 15620 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 |
|---|
| 15621 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c |
|---|
| 15622 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f |
|---|
| 15623 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L |
|---|
| 15624 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L |
|---|
| 15625 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L |
|---|
| 15626 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L |
|---|
| 15627 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L |
|---|
| 15628 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L |
|---|
| 15629 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP5 |
|---|
| 15630 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 |
|---|
| 15631 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL |
|---|
| 15632 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP6 |
|---|
| 15633 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 15634 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 |
|---|
| 15635 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 |
|---|
| 15636 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 |
|---|
| 15637 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 |
|---|
| 15638 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 |
|---|
| 15639 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 |
|---|
| 15640 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 |
|---|
| 15641 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 |
|---|
| 15642 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 |
|---|
| 15643 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 15644 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L |
|---|
| 15645 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L |
|---|
| 15646 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1_MASK 0x00000070L |
|---|
| 15647 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L |
|---|
| 15648 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L |
|---|
| 15649 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L |
|---|
| 15650 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L |
|---|
| 15651 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L |
|---|
| 15652 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L |
|---|
| 15653 | //RCC_STRAP0_RCC_DEV0_EPF1_STRAP7 |
|---|
| 15654 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 15655 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 |
|---|
| 15656 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1__SHIFT 0x14 |
|---|
| 15657 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1__SHIFT 0x16 |
|---|
| 15658 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1__SHIFT 0x17 |
|---|
| 15659 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1__SHIFT 0x18 |
|---|
| 15660 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1__SHIFT 0x1a |
|---|
| 15661 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 15662 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1_MASK 0x0000001EL |
|---|
| 15663 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1_MASK 0x00300000L |
|---|
| 15664 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1_MASK 0x00400000L |
|---|
| 15665 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1_MASK 0x00800000L |
|---|
| 15666 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1_MASK 0x03000000L |
|---|
| 15667 | #define RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1_MASK 0xFC000000L |
|---|
| 15668 | |
|---|
| 15669 | |
|---|
| 15670 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
|---|
| 15671 | //RCC_EP_DEV0_0_EP_PCIE_SCRATCH |
|---|
| 15672 | #define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
|---|
| 15673 | #define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 15674 | //RCC_EP_DEV0_0_EP_PCIE_CNTL |
|---|
| 15675 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
|---|
| 15676 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
|---|
| 15677 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
|---|
| 15678 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
|---|
| 15679 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
|---|
| 15680 | #define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
|---|
| 15681 | //RCC_EP_DEV0_0_EP_PCIE_INT_CNTL |
|---|
| 15682 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
|---|
| 15683 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
|---|
| 15684 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
|---|
| 15685 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
|---|
| 15686 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
|---|
| 15687 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
|---|
| 15688 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
|---|
| 15689 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
|---|
| 15690 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
|---|
| 15691 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
|---|
| 15692 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
|---|
| 15693 | #define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
|---|
| 15694 | //RCC_EP_DEV0_0_EP_PCIE_INT_STATUS |
|---|
| 15695 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
|---|
| 15696 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
|---|
| 15697 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
|---|
| 15698 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
|---|
| 15699 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
|---|
| 15700 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
|---|
| 15701 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
|---|
| 15702 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
|---|
| 15703 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
|---|
| 15704 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
|---|
| 15705 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
|---|
| 15706 | #define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
|---|
| 15707 | //RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 |
|---|
| 15708 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
|---|
| 15709 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
|---|
| 15710 | //RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL |
|---|
| 15711 | #define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
|---|
| 15712 | #define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
|---|
| 15713 | //RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL |
|---|
| 15714 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
|---|
| 15715 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
|---|
| 15716 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
|---|
| 15717 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
|---|
| 15718 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
|---|
| 15719 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
|---|
| 15720 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
|---|
| 15721 | #define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
|---|
| 15722 | //RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL |
|---|
| 15723 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
|---|
| 15724 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
|---|
| 15725 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
|---|
| 15726 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
|---|
| 15727 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
|---|
| 15728 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
|---|
| 15729 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
|---|
| 15730 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
|---|
| 15731 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
|---|
| 15732 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
|---|
| 15733 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
|---|
| 15734 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
|---|
| 15735 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
|---|
| 15736 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
|---|
| 15737 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
|---|
| 15738 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
|---|
| 15739 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
|---|
| 15740 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
|---|
| 15741 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
|---|
| 15742 | #define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
|---|
| 15743 | //RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC |
|---|
| 15744 | #define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d |
|---|
| 15745 | #define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L |
|---|
| 15746 | //RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 |
|---|
| 15747 | #define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 |
|---|
| 15748 | #define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L |
|---|
| 15749 | //RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP |
|---|
| 15750 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 15751 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 15752 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 15753 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 15754 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 15755 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 15756 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 15757 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 15758 | //RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
|---|
| 15759 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 15760 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
|---|
| 15761 | //RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL |
|---|
| 15762 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 15763 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
|---|
| 15764 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 15765 | #define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
|---|
| 15766 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 15767 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 15768 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 15769 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 15770 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 15771 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 15772 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 15773 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 15774 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 15775 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 15776 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 15777 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 15778 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 15779 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 15780 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 15781 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 15782 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 15783 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 15784 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 15785 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 15786 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 15787 | //RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 15788 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 15789 | #define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 15790 | //RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL |
|---|
| 15791 | #define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
|---|
| 15792 | #define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
|---|
| 15793 | //RCC_EP_DEV0_0_EP_PCIEP_RESERVED |
|---|
| 15794 | #define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
|---|
| 15795 | #define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 15796 | //RCC_EP_DEV0_0_EP_PCIE_TX_CNTL |
|---|
| 15797 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
|---|
| 15798 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
|---|
| 15799 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
|---|
| 15800 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
|---|
| 15801 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
|---|
| 15802 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
|---|
| 15803 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
|---|
| 15804 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
|---|
| 15805 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
|---|
| 15806 | #define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
|---|
| 15807 | //RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID |
|---|
| 15808 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
|---|
| 15809 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
|---|
| 15810 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
|---|
| 15811 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
|---|
| 15812 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
|---|
| 15813 | #define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
|---|
| 15814 | //RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL |
|---|
| 15815 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
|---|
| 15816 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
|---|
| 15817 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
|---|
| 15818 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
|---|
| 15819 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 |
|---|
| 15820 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 |
|---|
| 15821 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a |
|---|
| 15822 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b |
|---|
| 15823 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c |
|---|
| 15824 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d |
|---|
| 15825 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e |
|---|
| 15826 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f |
|---|
| 15827 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
|---|
| 15828 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
|---|
| 15829 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
|---|
| 15830 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
|---|
| 15831 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L |
|---|
| 15832 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L |
|---|
| 15833 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L |
|---|
| 15834 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L |
|---|
| 15835 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L |
|---|
| 15836 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L |
|---|
| 15837 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L |
|---|
| 15838 | #define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L |
|---|
| 15839 | //RCC_EP_DEV0_0_EP_PCIE_RX_CNTL |
|---|
| 15840 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
|---|
| 15841 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
|---|
| 15842 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
|---|
| 15843 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
|---|
| 15844 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
|---|
| 15845 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
|---|
| 15846 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
|---|
| 15847 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
|---|
| 15848 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
|---|
| 15849 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
|---|
| 15850 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
|---|
| 15851 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
|---|
| 15852 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
|---|
| 15853 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
|---|
| 15854 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
|---|
| 15855 | #define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
|---|
| 15856 | //RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL |
|---|
| 15857 | #define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
|---|
| 15858 | #define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
|---|
| 15859 | #define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 |
|---|
| 15860 | #define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
|---|
| 15861 | #define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
|---|
| 15862 | #define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L |
|---|
| 15863 | |
|---|
| 15864 | |
|---|
| 15865 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
|---|
| 15866 | //RCC_DWN_DEV0_0_DN_PCIE_RESERVED |
|---|
| 15867 | #define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
|---|
| 15868 | #define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 15869 | //RCC_DWN_DEV0_0_DN_PCIE_SCRATCH |
|---|
| 15870 | #define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
|---|
| 15871 | #define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 15872 | //RCC_DWN_DEV0_0_DN_PCIE_CNTL |
|---|
| 15873 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
|---|
| 15874 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
|---|
| 15875 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
|---|
| 15876 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
|---|
| 15877 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
|---|
| 15878 | #define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
|---|
| 15879 | //RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL |
|---|
| 15880 | #define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
|---|
| 15881 | #define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
|---|
| 15882 | //RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 |
|---|
| 15883 | #define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
|---|
| 15884 | #define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
|---|
| 15885 | //RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL |
|---|
| 15886 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
|---|
| 15887 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
|---|
| 15888 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
|---|
| 15889 | #define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
|---|
| 15890 | //RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL |
|---|
| 15891 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
|---|
| 15892 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
|---|
| 15893 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
|---|
| 15894 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
|---|
| 15895 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
|---|
| 15896 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
|---|
| 15897 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
|---|
| 15898 | #define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
|---|
| 15899 | //RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 |
|---|
| 15900 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 |
|---|
| 15901 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 |
|---|
| 15902 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 |
|---|
| 15903 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L |
|---|
| 15904 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L |
|---|
| 15905 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L |
|---|
| 15906 | //RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC |
|---|
| 15907 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 |
|---|
| 15908 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d |
|---|
| 15909 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L |
|---|
| 15910 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L |
|---|
| 15911 | //RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 |
|---|
| 15912 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 |
|---|
| 15913 | #define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L |
|---|
| 15914 | |
|---|
| 15915 | |
|---|
| 15916 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
|---|
| 15917 | //RCC_DWNP_DEV0_0_PCIE_ERR_CNTL |
|---|
| 15918 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
|---|
| 15919 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
|---|
| 15920 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
|---|
| 15921 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
|---|
| 15922 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
|---|
| 15923 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
|---|
| 15924 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
|---|
| 15925 | #define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
|---|
| 15926 | //RCC_DWNP_DEV0_0_PCIE_RX_CNTL |
|---|
| 15927 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
|---|
| 15928 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
|---|
| 15929 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
|---|
| 15930 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
|---|
| 15931 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
|---|
| 15932 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
|---|
| 15933 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
|---|
| 15934 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
|---|
| 15935 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
|---|
| 15936 | #define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
|---|
| 15937 | //RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL |
|---|
| 15938 | #define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
|---|
| 15939 | #define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
|---|
| 15940 | #define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 |
|---|
| 15941 | #define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
|---|
| 15942 | #define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
|---|
| 15943 | #define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L |
|---|
| 15944 | //RCC_DWNP_DEV0_0_PCIE_LC_CNTL2 |
|---|
| 15945 | #define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
|---|
| 15946 | #define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
|---|
| 15947 | //RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC |
|---|
| 15948 | #define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa |
|---|
| 15949 | #define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L |
|---|
| 15950 | //RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP |
|---|
| 15951 | #define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
|---|
| 15952 | #define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
|---|
| 15953 | //RCC_DEV0_0_RCC_VDM_SUPPORT |
|---|
| 15954 | #define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 |
|---|
| 15955 | #define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 |
|---|
| 15956 | #define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 |
|---|
| 15957 | #define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 |
|---|
| 15958 | #define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 |
|---|
| 15959 | #define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L |
|---|
| 15960 | #define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L |
|---|
| 15961 | #define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L |
|---|
| 15962 | #define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L |
|---|
| 15963 | #define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L |
|---|
| 15964 | //RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 |
|---|
| 15965 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 |
|---|
| 15966 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 |
|---|
| 15967 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 |
|---|
| 15968 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 |
|---|
| 15969 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 |
|---|
| 15970 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 |
|---|
| 15971 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb |
|---|
| 15972 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 |
|---|
| 15973 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 |
|---|
| 15974 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L |
|---|
| 15975 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L |
|---|
| 15976 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L |
|---|
| 15977 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L |
|---|
| 15978 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L |
|---|
| 15979 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L |
|---|
| 15980 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L |
|---|
| 15981 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L |
|---|
| 15982 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L |
|---|
| 15983 | //RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 |
|---|
| 15984 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 |
|---|
| 15985 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 |
|---|
| 15986 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc |
|---|
| 15987 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 |
|---|
| 15988 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL |
|---|
| 15989 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L |
|---|
| 15990 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L |
|---|
| 15991 | #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L |
|---|
| 15992 | //RCC_DEV0_0_RCC_BUS_CNTL |
|---|
| 15993 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 |
|---|
| 15994 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 |
|---|
| 15995 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 |
|---|
| 15996 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 |
|---|
| 15997 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 |
|---|
| 15998 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 |
|---|
| 15999 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 |
|---|
| 16000 | #define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc |
|---|
| 16001 | #define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd |
|---|
| 16002 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 |
|---|
| 16003 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 |
|---|
| 16004 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 |
|---|
| 16005 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 |
|---|
| 16006 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 |
|---|
| 16007 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 |
|---|
| 16008 | #define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 |
|---|
| 16009 | #define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 |
|---|
| 16010 | #define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c |
|---|
| 16011 | #define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d |
|---|
| 16012 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L |
|---|
| 16013 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L |
|---|
| 16014 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L |
|---|
| 16015 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L |
|---|
| 16016 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L |
|---|
| 16017 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L |
|---|
| 16018 | #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L |
|---|
| 16019 | #define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L |
|---|
| 16020 | #define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L |
|---|
| 16021 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L |
|---|
| 16022 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L |
|---|
| 16023 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L |
|---|
| 16024 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L |
|---|
| 16025 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L |
|---|
| 16026 | #define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L |
|---|
| 16027 | #define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L |
|---|
| 16028 | #define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L |
|---|
| 16029 | #define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L |
|---|
| 16030 | #define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L |
|---|
| 16031 | //RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC |
|---|
| 16032 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 |
|---|
| 16033 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 |
|---|
| 16034 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 |
|---|
| 16035 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 |
|---|
| 16036 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 |
|---|
| 16037 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 |
|---|
| 16038 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa |
|---|
| 16039 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb |
|---|
| 16040 | #define 0xc |
|---|
| 16041 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd |
|---|
| 16042 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe |
|---|
| 16043 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf |
|---|
| 16044 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 |
|---|
| 16045 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 |
|---|
| 16046 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 |
|---|
| 16047 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 |
|---|
| 16048 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L |
|---|
| 16049 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L |
|---|
| 16050 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L |
|---|
| 16051 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L |
|---|
| 16052 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L |
|---|
| 16053 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L |
|---|
| 16054 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L |
|---|
| 16055 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L |
|---|
| 16056 | #define 0x00001000L |
|---|
| 16057 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L |
|---|
| 16058 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L |
|---|
| 16059 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L |
|---|
| 16060 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L |
|---|
| 16061 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L |
|---|
| 16062 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L |
|---|
| 16063 | #define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L |
|---|
| 16064 | //RCC_DEV0_0_RCC_DEV0_LINK_CNTL |
|---|
| 16065 | #define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 |
|---|
| 16066 | #define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 |
|---|
| 16067 | #define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L |
|---|
| 16068 | #define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L |
|---|
| 16069 | //RCC_DEV0_0_RCC_CMN_LINK_CNTL |
|---|
| 16070 | #define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 |
|---|
| 16071 | #define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 |
|---|
| 16072 | #define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 |
|---|
| 16073 | #define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 |
|---|
| 16074 | #define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 |
|---|
| 16075 | #define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L |
|---|
| 16076 | #define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L |
|---|
| 16077 | #define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L |
|---|
| 16078 | #define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L |
|---|
| 16079 | #define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L |
|---|
| 16080 | //RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE |
|---|
| 16081 | #define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 |
|---|
| 16082 | #define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 |
|---|
| 16083 | #define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL |
|---|
| 16084 | #define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L |
|---|
| 16085 | //RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL |
|---|
| 16086 | #define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 16087 | #define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 16088 | //RCC_DEV0_0_RCC_MH_ARB_CNTL |
|---|
| 16089 | #define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 |
|---|
| 16090 | #define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 |
|---|
| 16091 | #define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L |
|---|
| 16092 | #define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL |
|---|
| 16093 | |
|---|
| 16094 | |
|---|
| 16095 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
|---|
| 16096 | //BIF_BME_STATUS |
|---|
| 16097 | #define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 16098 | #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 16099 | #define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 16100 | #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 16101 | //BIF_ATOMIC_ERR_LOG |
|---|
| 16102 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 16103 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 16104 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 16105 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 16106 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 16107 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 16108 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 16109 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 16110 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 16111 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 16112 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 16113 | #define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 16114 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 16115 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 16116 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 16117 | #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 16118 | //DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 16119 | #define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 16120 | #define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 16121 | //DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 16122 | #define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 16123 | #define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 16124 | //DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 16125 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 16126 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 16127 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 16128 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 16129 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 16130 | #define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 16131 | //HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 16132 | #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 16133 | #define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 16134 | //HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 16135 | #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 16136 | #define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 16137 | //GPU_HDP_FLUSH_REQ |
|---|
| 16138 | #define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 16139 | #define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 16140 | #define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 16141 | #define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 16142 | #define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 16143 | #define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 16144 | #define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 16145 | #define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 16146 | #define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 16147 | #define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 16148 | #define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 16149 | #define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 16150 | #define GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 16151 | #define GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 16152 | #define GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 16153 | #define GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 16154 | #define GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 16155 | #define GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 16156 | #define GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 16157 | #define GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 16158 | #define GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 16159 | #define GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 16160 | #define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 16161 | #define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 16162 | //GPU_HDP_FLUSH_DONE |
|---|
| 16163 | #define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 16164 | #define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 16165 | #define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 16166 | #define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 16167 | #define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 16168 | #define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 16169 | #define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 16170 | #define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 16171 | #define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 16172 | #define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 16173 | #define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 16174 | #define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 16175 | #define GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 16176 | #define GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 16177 | #define GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 16178 | #define GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 16179 | #define GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 16180 | #define GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 16181 | #define GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 16182 | #define GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 16183 | #define GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 16184 | #define GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 16185 | #define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 16186 | #define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 16187 | //BIF_TRANS_PENDING |
|---|
| 16188 | #define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 16189 | #define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 16190 | #define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 16191 | #define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 16192 | //NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 16193 | #define NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 16194 | #define NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 16195 | //MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 16196 | #define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 16197 | #define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 16198 | //MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 16199 | #define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 16200 | #define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 16201 | //MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 16202 | #define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 16203 | #define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 16204 | //MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 16205 | #define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 16206 | #define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 16207 | //MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 16208 | #define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 16209 | #define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 16210 | //MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 16211 | #define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 16212 | #define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 16213 | //MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 16214 | #define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 16215 | #define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 16216 | //MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 16217 | #define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 16218 | #define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 16219 | //MAILBOX_CONTROL |
|---|
| 16220 | #define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 16221 | #define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 16222 | #define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 16223 | #define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 16224 | #define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 16225 | #define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 16226 | #define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 16227 | #define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 16228 | //MAILBOX_INT_CNTL |
|---|
| 16229 | #define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 16230 | #define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 16231 | #define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 16232 | #define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 16233 | //BIF_VMHV_MAILBOX |
|---|
| 16234 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 16235 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 16236 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 16237 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 16238 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 16239 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 16240 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 16241 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 16242 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 16243 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 16244 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 16245 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 16246 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 16247 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 16248 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 16249 | #define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 16250 | |
|---|
| 16251 | |
|---|
| 16252 | // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec |
|---|
| 16253 | //SHADOW_COMMAND |
|---|
| 16254 | #define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0 |
|---|
| 16255 | #define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1 |
|---|
| 16256 | #define SHADOW_COMMAND__IOEN_UP_MASK 0x0001L |
|---|
| 16257 | #define SHADOW_COMMAND__MEMEN_UP_MASK 0x0002L |
|---|
| 16258 | //SHADOW_BASE_ADDR_1 |
|---|
| 16259 | #define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0 |
|---|
| 16260 | #define SHADOW_BASE_ADDR_1__BAR1_UP_MASK 0xFFFFFFFFL |
|---|
| 16261 | //SHADOW_BASE_ADDR_2 |
|---|
| 16262 | #define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0 |
|---|
| 16263 | #define SHADOW_BASE_ADDR_2__BAR2_UP_MASK 0xFFFFFFFFL |
|---|
| 16264 | //SHADOW_SUB_BUS_NUMBER_LATENCY |
|---|
| 16265 | #define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8 |
|---|
| 16266 | #define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10 |
|---|
| 16267 | #define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK 0x0000FF00L |
|---|
| 16268 | #define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK 0x00FF0000L |
|---|
| 16269 | //SHADOW_IO_BASE_LIMIT |
|---|
| 16270 | #define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4 |
|---|
| 16271 | #define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc |
|---|
| 16272 | #define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK 0x00F0L |
|---|
| 16273 | #define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK 0xF000L |
|---|
| 16274 | //SHADOW_MEM_BASE_LIMIT |
|---|
| 16275 | #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 16276 | #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4 |
|---|
| 16277 | #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 16278 | #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14 |
|---|
| 16279 | #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 16280 | #define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK 0x0000FFF0L |
|---|
| 16281 | #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 16282 | #define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK 0xFFF00000L |
|---|
| 16283 | //SHADOW_PREF_BASE_LIMIT |
|---|
| 16284 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 16285 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4 |
|---|
| 16286 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 16287 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14 |
|---|
| 16288 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 16289 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK 0x0000FFF0L |
|---|
| 16290 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 16291 | #define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK 0xFFF00000L |
|---|
| 16292 | //SHADOW_PREF_BASE_UPPER |
|---|
| 16293 | #define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0 |
|---|
| 16294 | #define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK 0xFFFFFFFFL |
|---|
| 16295 | //SHADOW_PREF_LIMIT_UPPER |
|---|
| 16296 | #define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0 |
|---|
| 16297 | #define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK 0xFFFFFFFFL |
|---|
| 16298 | //SHADOW_IO_BASE_LIMIT_HI |
|---|
| 16299 | #define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0 |
|---|
| 16300 | #define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10 |
|---|
| 16301 | #define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK 0x0000FFFFL |
|---|
| 16302 | #define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK 0xFFFF0000L |
|---|
| 16303 | //SHADOW_IRQ_BRIDGE_CNTL |
|---|
| 16304 | #define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2 |
|---|
| 16305 | #define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3 |
|---|
| 16306 | #define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4 |
|---|
| 16307 | #define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6 |
|---|
| 16308 | #define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK 0x0004L |
|---|
| 16309 | #define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK 0x0008L |
|---|
| 16310 | #define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK 0x0010L |
|---|
| 16311 | #define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK 0x0040L |
|---|
| 16312 | //SUC_INDEX |
|---|
| 16313 | #define SUC_INDEX__SUC_INDEX__SHIFT 0x0 |
|---|
| 16314 | #define SUC_INDEX__SUC_INDEX_MASK 0xFFFFFFFFL |
|---|
| 16315 | //SUC_DATA |
|---|
| 16316 | #define SUC_DATA__SUC_DATA__SHIFT 0x0 |
|---|
| 16317 | #define SUC_DATA__SUC_DATA_MASK 0xFFFFFFFFL |
|---|
| 16318 | |
|---|
| 16319 | |
|---|
| 16320 | // addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal |
|---|
| 16321 | //RCC_STRAP1_RCC_DEV0_PORT_STRAP0 |
|---|
| 16322 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 |
|---|
| 16323 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 |
|---|
| 16324 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 |
|---|
| 16325 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 |
|---|
| 16326 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 |
|---|
| 16327 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 |
|---|
| 16328 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 |
|---|
| 16329 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 |
|---|
| 16330 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c |
|---|
| 16331 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f |
|---|
| 16332 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L |
|---|
| 16333 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L |
|---|
| 16334 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L |
|---|
| 16335 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L |
|---|
| 16336 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001FFFE0L |
|---|
| 16337 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L |
|---|
| 16338 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L |
|---|
| 16339 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L |
|---|
| 16340 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L |
|---|
| 16341 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L |
|---|
| 16342 | //RCC_STRAP1_RCC_DEV0_PORT_STRAP1 |
|---|
| 16343 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 |
|---|
| 16344 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 |
|---|
| 16345 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL |
|---|
| 16346 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L |
|---|
| 16347 | //RCC_STRAP1_RCC_DEV0_PORT_STRAP2 |
|---|
| 16348 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 |
|---|
| 16349 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 |
|---|
| 16350 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 |
|---|
| 16351 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 |
|---|
| 16352 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 |
|---|
| 16353 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 |
|---|
| 16354 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 |
|---|
| 16355 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 |
|---|
| 16356 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 |
|---|
| 16357 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 |
|---|
| 16358 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc |
|---|
| 16359 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd |
|---|
| 16360 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe |
|---|
| 16361 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf |
|---|
| 16362 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 |
|---|
| 16363 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 |
|---|
| 16364 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x12 |
|---|
| 16365 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 |
|---|
| 16366 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 |
|---|
| 16367 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a |
|---|
| 16368 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d |
|---|
| 16369 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L |
|---|
| 16370 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L |
|---|
| 16371 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L |
|---|
| 16372 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L |
|---|
| 16373 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L |
|---|
| 16374 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L |
|---|
| 16375 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L |
|---|
| 16376 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L |
|---|
| 16377 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L |
|---|
| 16378 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L |
|---|
| 16379 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L |
|---|
| 16380 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L |
|---|
| 16381 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L |
|---|
| 16382 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L |
|---|
| 16383 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L |
|---|
| 16384 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L |
|---|
| 16385 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x000C0000L |
|---|
| 16386 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L |
|---|
| 16387 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L |
|---|
| 16388 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L |
|---|
| 16389 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L |
|---|
| 16390 | //RCC_STRAP1_RCC_DEV0_PORT_STRAP3 |
|---|
| 16391 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 |
|---|
| 16392 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 |
|---|
| 16393 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 |
|---|
| 16394 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 |
|---|
| 16395 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 |
|---|
| 16396 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 |
|---|
| 16397 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 |
|---|
| 16398 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 |
|---|
| 16399 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb |
|---|
| 16400 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe |
|---|
| 16401 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 |
|---|
| 16402 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 |
|---|
| 16403 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 |
|---|
| 16404 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b |
|---|
| 16405 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d |
|---|
| 16406 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e |
|---|
| 16407 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f |
|---|
| 16408 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L |
|---|
| 16409 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L |
|---|
| 16410 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L |
|---|
| 16411 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L |
|---|
| 16412 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L |
|---|
| 16413 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L |
|---|
| 16414 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L |
|---|
| 16415 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L |
|---|
| 16416 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L |
|---|
| 16417 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L |
|---|
| 16418 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L |
|---|
| 16419 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L |
|---|
| 16420 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L |
|---|
| 16421 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L |
|---|
| 16422 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L |
|---|
| 16423 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0_MASK 0x40000000L |
|---|
| 16424 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L |
|---|
| 16425 | //RCC_STRAP1_RCC_DEV0_PORT_STRAP4 |
|---|
| 16426 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 |
|---|
| 16427 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 |
|---|
| 16428 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 |
|---|
| 16429 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 |
|---|
| 16430 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL |
|---|
| 16431 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L |
|---|
| 16432 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L |
|---|
| 16433 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L |
|---|
| 16434 | //RCC_STRAP1_RCC_DEV0_PORT_STRAP5 |
|---|
| 16435 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 |
|---|
| 16436 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 |
|---|
| 16437 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 |
|---|
| 16438 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 |
|---|
| 16439 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 |
|---|
| 16440 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 |
|---|
| 16441 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 |
|---|
| 16442 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 |
|---|
| 16443 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 |
|---|
| 16444 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 |
|---|
| 16445 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 |
|---|
| 16446 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 |
|---|
| 16447 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a |
|---|
| 16448 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b |
|---|
| 16449 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c |
|---|
| 16450 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d |
|---|
| 16451 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e |
|---|
| 16452 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f |
|---|
| 16453 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL |
|---|
| 16454 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L |
|---|
| 16455 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L |
|---|
| 16456 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L |
|---|
| 16457 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L |
|---|
| 16458 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L |
|---|
| 16459 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L |
|---|
| 16460 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L |
|---|
| 16461 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L |
|---|
| 16462 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L |
|---|
| 16463 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L |
|---|
| 16464 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L |
|---|
| 16465 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L |
|---|
| 16466 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L |
|---|
| 16467 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L |
|---|
| 16468 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L |
|---|
| 16469 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L |
|---|
| 16470 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L |
|---|
| 16471 | //RCC_STRAP1_RCC_DEV0_PORT_STRAP6 |
|---|
| 16472 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 |
|---|
| 16473 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 |
|---|
| 16474 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 |
|---|
| 16475 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 |
|---|
| 16476 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 |
|---|
| 16477 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 |
|---|
| 16478 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 |
|---|
| 16479 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 |
|---|
| 16480 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 |
|---|
| 16481 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc |
|---|
| 16482 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 |
|---|
| 16483 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L |
|---|
| 16484 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L |
|---|
| 16485 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L |
|---|
| 16486 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L |
|---|
| 16487 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L |
|---|
| 16488 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L |
|---|
| 16489 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L |
|---|
| 16490 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L |
|---|
| 16491 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L |
|---|
| 16492 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L |
|---|
| 16493 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L |
|---|
| 16494 | //RCC_STRAP1_RCC_DEV0_PORT_STRAP7 |
|---|
| 16495 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 |
|---|
| 16496 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 |
|---|
| 16497 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc |
|---|
| 16498 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 |
|---|
| 16499 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 |
|---|
| 16500 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d |
|---|
| 16501 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL |
|---|
| 16502 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L |
|---|
| 16503 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L |
|---|
| 16504 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L |
|---|
| 16505 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L |
|---|
| 16506 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L |
|---|
| 16507 | //RCC_STRAP1_RCC_DEV0_PORT_STRAP8 |
|---|
| 16508 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 |
|---|
| 16509 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 |
|---|
| 16510 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 |
|---|
| 16511 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 |
|---|
| 16512 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL |
|---|
| 16513 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L |
|---|
| 16514 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L |
|---|
| 16515 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L |
|---|
| 16516 | //RCC_STRAP1_RCC_DEV0_PORT_STRAP9 |
|---|
| 16517 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 |
|---|
| 16518 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 |
|---|
| 16519 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL |
|---|
| 16520 | #define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L |
|---|
| 16521 | //RCC_DEV1_PORT_STRAP0 |
|---|
| 16522 | #define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT 0x1 |
|---|
| 16523 | #define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT 0x2 |
|---|
| 16524 | #define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT 0x3 |
|---|
| 16525 | #define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT 0x4 |
|---|
| 16526 | #define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT 0x5 |
|---|
| 16527 | #define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT 0x18 |
|---|
| 16528 | #define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT 0x19 |
|---|
| 16529 | #define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT 0x1c |
|---|
| 16530 | #define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT 0x1f |
|---|
| 16531 | #define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1_MASK 0x00000002L |
|---|
| 16532 | #define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1_MASK 0x00000004L |
|---|
| 16533 | #define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1_MASK 0x00000008L |
|---|
| 16534 | #define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1_MASK 0x00000010L |
|---|
| 16535 | #define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1_MASK 0x001FFFE0L |
|---|
| 16536 | #define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1_MASK 0x01000000L |
|---|
| 16537 | #define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1_MASK 0x0E000000L |
|---|
| 16538 | #define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1_MASK 0x70000000L |
|---|
| 16539 | #define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1_MASK 0x80000000L |
|---|
| 16540 | //RCC_DEV1_PORT_STRAP1 |
|---|
| 16541 | #define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT 0x0 |
|---|
| 16542 | #define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT 0x10 |
|---|
| 16543 | #define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1_MASK 0x0000FFFFL |
|---|
| 16544 | #define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1_MASK 0xFFFF0000L |
|---|
| 16545 | //RCC_DEV1_PORT_STRAP2 |
|---|
| 16546 | #define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT 0x0 |
|---|
| 16547 | #define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT 0x1 |
|---|
| 16548 | #define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT 0x2 |
|---|
| 16549 | #define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT 0x3 |
|---|
| 16550 | #define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT 0x4 |
|---|
| 16551 | #define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__SHIFT 0x5 |
|---|
| 16552 | #define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT 0x6 |
|---|
| 16553 | #define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT 0x7 |
|---|
| 16554 | #define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT 0x8 |
|---|
| 16555 | #define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT 0x9 |
|---|
| 16556 | #define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT 0xc |
|---|
| 16557 | #define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT 0xd |
|---|
| 16558 | #define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT 0xe |
|---|
| 16559 | #define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT 0xf |
|---|
| 16560 | #define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT 0x10 |
|---|
| 16561 | #define RCC_DEV1_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV1__SHIFT 0x11 |
|---|
| 16562 | #define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT 0x12 |
|---|
| 16563 | #define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x14 |
|---|
| 16564 | #define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT 0x17 |
|---|
| 16565 | #define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x1a |
|---|
| 16566 | #define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT 0x1d |
|---|
| 16567 | #define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1_MASK 0x00000001L |
|---|
| 16568 | #define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1_MASK 0x00000002L |
|---|
| 16569 | #define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1_MASK 0x00000004L |
|---|
| 16570 | #define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1_MASK 0x00000008L |
|---|
| 16571 | #define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1_MASK 0x00000010L |
|---|
| 16572 | #define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1_MASK 0x00000020L |
|---|
| 16573 | #define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1_MASK 0x00000040L |
|---|
| 16574 | #define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1_MASK 0x00000080L |
|---|
| 16575 | #define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1_MASK 0x00000100L |
|---|
| 16576 | #define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1_MASK 0x00000E00L |
|---|
| 16577 | #define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1_MASK 0x00001000L |
|---|
| 16578 | #define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1_MASK 0x00002000L |
|---|
| 16579 | #define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1_MASK 0x00004000L |
|---|
| 16580 | #define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1_MASK 0x00008000L |
|---|
| 16581 | #define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1_MASK 0x00010000L |
|---|
| 16582 | #define RCC_DEV1_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV1_MASK 0x00020000L |
|---|
| 16583 | #define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1_MASK 0x000C0000L |
|---|
| 16584 | #define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1_MASK 0x00700000L |
|---|
| 16585 | #define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1_MASK 0x03800000L |
|---|
| 16586 | #define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1_MASK 0x1C000000L |
|---|
| 16587 | #define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1_MASK 0xE0000000L |
|---|
| 16588 | //RCC_DEV1_PORT_STRAP3 |
|---|
| 16589 | #define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT 0x0 |
|---|
| 16590 | #define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT 0x1 |
|---|
| 16591 | #define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT 0x2 |
|---|
| 16592 | #define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT 0x3 |
|---|
| 16593 | #define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT 0x6 |
|---|
| 16594 | #define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT 0x7 |
|---|
| 16595 | #define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT 0x8 |
|---|
| 16596 | #define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT 0x9 |
|---|
| 16597 | #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0xb |
|---|
| 16598 | #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0xe |
|---|
| 16599 | #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0x12 |
|---|
| 16600 | #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0x15 |
|---|
| 16601 | #define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT 0x19 |
|---|
| 16602 | #define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT 0x1b |
|---|
| 16603 | #define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT 0x1d |
|---|
| 16604 | #define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__SHIFT 0x1e |
|---|
| 16605 | #define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT 0x1f |
|---|
| 16606 | #define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1_MASK 0x00000001L |
|---|
| 16607 | #define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1_MASK 0x00000002L |
|---|
| 16608 | #define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1_MASK 0x00000004L |
|---|
| 16609 | #define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1_MASK 0x00000038L |
|---|
| 16610 | #define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1_MASK 0x00000040L |
|---|
| 16611 | #define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1_MASK 0x00000080L |
|---|
| 16612 | #define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1_MASK 0x00000100L |
|---|
| 16613 | #define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1_MASK 0x00000600L |
|---|
| 16614 | #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK 0x00003800L |
|---|
| 16615 | #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1_MASK 0x0003C000L |
|---|
| 16616 | #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK 0x001C0000L |
|---|
| 16617 | #define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1_MASK 0x01E00000L |
|---|
| 16618 | #define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1_MASK 0x06000000L |
|---|
| 16619 | #define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1_MASK 0x18000000L |
|---|
| 16620 | #define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1_MASK 0x20000000L |
|---|
| 16621 | #define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1_MASK 0x40000000L |
|---|
| 16622 | #define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1_MASK 0x80000000L |
|---|
| 16623 | //RCC_DEV1_PORT_STRAP4 |
|---|
| 16624 | #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT 0x0 |
|---|
| 16625 | #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT 0x8 |
|---|
| 16626 | #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT 0x10 |
|---|
| 16627 | #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT 0x18 |
|---|
| 16628 | #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1_MASK 0x000000FFL |
|---|
| 16629 | #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1_MASK 0x0000FF00L |
|---|
| 16630 | #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1_MASK 0x00FF0000L |
|---|
| 16631 | #define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1_MASK 0xFF000000L |
|---|
| 16632 | //RCC_DEV1_PORT_STRAP5 |
|---|
| 16633 | #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT 0x0 |
|---|
| 16634 | #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT 0x8 |
|---|
| 16635 | #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT 0x10 |
|---|
| 16636 | #define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT 0x11 |
|---|
| 16637 | #define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT 0x12 |
|---|
| 16638 | #define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT 0x13 |
|---|
| 16639 | #define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT 0x14 |
|---|
| 16640 | #define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT 0x15 |
|---|
| 16641 | #define RCC_DEV1_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV1__SHIFT 0x16 |
|---|
| 16642 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT 0x17 |
|---|
| 16643 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT 0x18 |
|---|
| 16644 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT 0x19 |
|---|
| 16645 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT 0x1a |
|---|
| 16646 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT 0x1b |
|---|
| 16647 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT 0x1c |
|---|
| 16648 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT 0x1d |
|---|
| 16649 | #define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT 0x1e |
|---|
| 16650 | #define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT 0x1f |
|---|
| 16651 | #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1_MASK 0x000000FFL |
|---|
| 16652 | #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1_MASK 0x0000FF00L |
|---|
| 16653 | #define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1_MASK 0x00010000L |
|---|
| 16654 | #define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1_MASK 0x00020000L |
|---|
| 16655 | #define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1_MASK 0x00040000L |
|---|
| 16656 | #define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1_MASK 0x00080000L |
|---|
| 16657 | #define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1_MASK 0x00100000L |
|---|
| 16658 | #define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1_MASK 0x00200000L |
|---|
| 16659 | #define RCC_DEV1_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV1_MASK 0x00400000L |
|---|
| 16660 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1_MASK 0x00800000L |
|---|
| 16661 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1_MASK 0x01000000L |
|---|
| 16662 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1_MASK 0x02000000L |
|---|
| 16663 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1_MASK 0x04000000L |
|---|
| 16664 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1_MASK 0x08000000L |
|---|
| 16665 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1_MASK 0x10000000L |
|---|
| 16666 | #define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1_MASK 0x20000000L |
|---|
| 16667 | #define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1_MASK 0x40000000L |
|---|
| 16668 | #define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1_MASK 0x80000000L |
|---|
| 16669 | //RCC_DEV1_PORT_STRAP6 |
|---|
| 16670 | #define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT 0x0 |
|---|
| 16671 | #define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT 0x1 |
|---|
| 16672 | #define RCC_DEV1_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT 0x2 |
|---|
| 16673 | #define RCC_DEV1_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1__SHIFT 0x3 |
|---|
| 16674 | #define RCC_DEV1_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1__SHIFT 0x4 |
|---|
| 16675 | #define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1__SHIFT 0x5 |
|---|
| 16676 | #define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1__SHIFT 0x6 |
|---|
| 16677 | #define RCC_DEV1_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1__SHIFT 0x7 |
|---|
| 16678 | #define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1__SHIFT 0x8 |
|---|
| 16679 | #define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1__SHIFT 0xc |
|---|
| 16680 | #define RCC_DEV1_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV1__SHIFT 0x10 |
|---|
| 16681 | #define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1_MASK 0x00000001L |
|---|
| 16682 | #define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1_MASK 0x00000002L |
|---|
| 16683 | #define RCC_DEV1_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV1_MASK 0x00000004L |
|---|
| 16684 | #define RCC_DEV1_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1_MASK 0x00000008L |
|---|
| 16685 | #define RCC_DEV1_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1_MASK 0x00000010L |
|---|
| 16686 | #define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1_MASK 0x00000020L |
|---|
| 16687 | #define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1_MASK 0x00000040L |
|---|
| 16688 | #define RCC_DEV1_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1_MASK 0x00000080L |
|---|
| 16689 | #define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1_MASK 0x00000F00L |
|---|
| 16690 | #define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1_MASK 0x0000F000L |
|---|
| 16691 | #define RCC_DEV1_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV1_MASK 0x00030000L |
|---|
| 16692 | //RCC_DEV1_PORT_STRAP7 |
|---|
| 16693 | #define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT 0x0 |
|---|
| 16694 | #define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT 0x8 |
|---|
| 16695 | #define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT 0xc |
|---|
| 16696 | #define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT 0x10 |
|---|
| 16697 | #define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT 0x18 |
|---|
| 16698 | #define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT 0x1d |
|---|
| 16699 | #define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1_MASK 0x000000FFL |
|---|
| 16700 | #define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1_MASK 0x00000F00L |
|---|
| 16701 | #define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1_MASK 0x0000F000L |
|---|
| 16702 | #define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1_MASK 0x00FF0000L |
|---|
| 16703 | #define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1_MASK 0x1F000000L |
|---|
| 16704 | #define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1_MASK 0xE0000000L |
|---|
| 16705 | //RCC_DEV1_PORT_STRAP8 |
|---|
| 16706 | #define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV1__SHIFT 0x0 |
|---|
| 16707 | #define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV1__SHIFT 0x8 |
|---|
| 16708 | #define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV1__SHIFT 0x10 |
|---|
| 16709 | #define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV1__SHIFT 0x18 |
|---|
| 16710 | #define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV1_MASK 0x000000FFL |
|---|
| 16711 | #define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV1_MASK 0x0000FF00L |
|---|
| 16712 | #define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV1_MASK 0x00FF0000L |
|---|
| 16713 | #define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV1_MASK 0xFF000000L |
|---|
| 16714 | //RCC_DEV1_PORT_STRAP9 |
|---|
| 16715 | #define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV1__SHIFT 0x0 |
|---|
| 16716 | #define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV1__SHIFT 0x8 |
|---|
| 16717 | #define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV1_MASK 0x000000FFL |
|---|
| 16718 | #define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV1_MASK 0x0000FF00L |
|---|
| 16719 | //RCC_DEV2_PORT_STRAP0 |
|---|
| 16720 | #define RCC_DEV2_PORT_STRAP0__STRAP_ARI_EN_DN_DEV2__SHIFT 0x1 |
|---|
| 16721 | #define RCC_DEV2_PORT_STRAP0__STRAP_ACS_EN_DN_DEV2__SHIFT 0x2 |
|---|
| 16722 | #define RCC_DEV2_PORT_STRAP0__STRAP_AER_EN_DN_DEV2__SHIFT 0x3 |
|---|
| 16723 | #define RCC_DEV2_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV2__SHIFT 0x4 |
|---|
| 16724 | #define RCC_DEV2_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV2__SHIFT 0x5 |
|---|
| 16725 | #define RCC_DEV2_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2__SHIFT 0x18 |
|---|
| 16726 | #define RCC_DEV2_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2__SHIFT 0x19 |
|---|
| 16727 | #define RCC_DEV2_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2__SHIFT 0x1c |
|---|
| 16728 | #define RCC_DEV2_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV2__SHIFT 0x1f |
|---|
| 16729 | #define RCC_DEV2_PORT_STRAP0__STRAP_ARI_EN_DN_DEV2_MASK 0x00000002L |
|---|
| 16730 | #define RCC_DEV2_PORT_STRAP0__STRAP_ACS_EN_DN_DEV2_MASK 0x00000004L |
|---|
| 16731 | #define RCC_DEV2_PORT_STRAP0__STRAP_AER_EN_DN_DEV2_MASK 0x00000008L |
|---|
| 16732 | #define RCC_DEV2_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV2_MASK 0x00000010L |
|---|
| 16733 | #define RCC_DEV2_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV2_MASK 0x001FFFE0L |
|---|
| 16734 | #define RCC_DEV2_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2_MASK 0x01000000L |
|---|
| 16735 | #define RCC_DEV2_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2_MASK 0x0E000000L |
|---|
| 16736 | #define RCC_DEV2_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2_MASK 0x70000000L |
|---|
| 16737 | #define RCC_DEV2_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV2_MASK 0x80000000L |
|---|
| 16738 | //RCC_DEV2_PORT_STRAP1 |
|---|
| 16739 | #define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV2__SHIFT 0x0 |
|---|
| 16740 | #define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV2__SHIFT 0x10 |
|---|
| 16741 | #define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV2_MASK 0x0000FFFFL |
|---|
| 16742 | #define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV2_MASK 0xFFFF0000L |
|---|
| 16743 | //RCC_DEV2_PORT_STRAP2 |
|---|
| 16744 | #define RCC_DEV2_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV2__SHIFT 0x0 |
|---|
| 16745 | #define RCC_DEV2_PORT_STRAP2__STRAP_DSN_EN_DN_DEV2__SHIFT 0x1 |
|---|
| 16746 | #define RCC_DEV2_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV2__SHIFT 0x2 |
|---|
| 16747 | #define RCC_DEV2_PORT_STRAP2__STRAP_ECN1P1_EN_DEV2__SHIFT 0x3 |
|---|
| 16748 | #define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV2__SHIFT 0x4 |
|---|
| 16749 | #define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV2__SHIFT 0x5 |
|---|
| 16750 | #define RCC_DEV2_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV2__SHIFT 0x6 |
|---|
| 16751 | #define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV2__SHIFT 0x7 |
|---|
| 16752 | #define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV2__SHIFT 0x8 |
|---|
| 16753 | #define RCC_DEV2_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV2__SHIFT 0x9 |
|---|
| 16754 | #define RCC_DEV2_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2__SHIFT 0xc |
|---|
| 16755 | #define RCC_DEV2_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2__SHIFT 0xd |
|---|
| 16756 | #define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV2__SHIFT 0xe |
|---|
| 16757 | #define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_EN_DEV2__SHIFT 0xf |
|---|
| 16758 | #define RCC_DEV2_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV2__SHIFT 0x10 |
|---|
| 16759 | #define RCC_DEV2_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV2__SHIFT 0x11 |
|---|
| 16760 | #define RCC_DEV2_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV2__SHIFT 0x12 |
|---|
| 16761 | #define RCC_DEV2_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV2__SHIFT 0x14 |
|---|
| 16762 | #define RCC_DEV2_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV2__SHIFT 0x17 |
|---|
| 16763 | #define RCC_DEV2_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV2__SHIFT 0x1a |
|---|
| 16764 | #define RCC_DEV2_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV2__SHIFT 0x1d |
|---|
| 16765 | #define RCC_DEV2_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV2_MASK 0x00000001L |
|---|
| 16766 | #define RCC_DEV2_PORT_STRAP2__STRAP_DSN_EN_DN_DEV2_MASK 0x00000002L |
|---|
| 16767 | #define RCC_DEV2_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV2_MASK 0x00000004L |
|---|
| 16768 | #define RCC_DEV2_PORT_STRAP2__STRAP_ECN1P1_EN_DEV2_MASK 0x00000008L |
|---|
| 16769 | #define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV2_MASK 0x00000010L |
|---|
| 16770 | #define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV2_MASK 0x00000020L |
|---|
| 16771 | #define RCC_DEV2_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV2_MASK 0x00000040L |
|---|
| 16772 | #define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV2_MASK 0x00000080L |
|---|
| 16773 | #define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV2_MASK 0x00000100L |
|---|
| 16774 | #define RCC_DEV2_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV2_MASK 0x00000E00L |
|---|
| 16775 | #define RCC_DEV2_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2_MASK 0x00001000L |
|---|
| 16776 | #define RCC_DEV2_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2_MASK 0x00002000L |
|---|
| 16777 | #define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV2_MASK 0x00004000L |
|---|
| 16778 | #define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_EN_DEV2_MASK 0x00008000L |
|---|
| 16779 | #define RCC_DEV2_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV2_MASK 0x00010000L |
|---|
| 16780 | #define RCC_DEV2_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV2_MASK 0x00020000L |
|---|
| 16781 | #define RCC_DEV2_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV2_MASK 0x000C0000L |
|---|
| 16782 | #define RCC_DEV2_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV2_MASK 0x00700000L |
|---|
| 16783 | #define RCC_DEV2_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV2_MASK 0x03800000L |
|---|
| 16784 | #define RCC_DEV2_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV2_MASK 0x1C000000L |
|---|
| 16785 | #define RCC_DEV2_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV2_MASK 0xE0000000L |
|---|
| 16786 | //RCC_DEV2_PORT_STRAP3 |
|---|
| 16787 | #define RCC_DEV2_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2__SHIFT 0x0 |
|---|
| 16788 | #define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DEV2__SHIFT 0x1 |
|---|
| 16789 | #define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DN_DEV2__SHIFT 0x2 |
|---|
| 16790 | #define RCC_DEV2_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV2__SHIFT 0x3 |
|---|
| 16791 | #define RCC_DEV2_PORT_STRAP3__STRAP_MSI_EN_DN_DEV2__SHIFT 0x6 |
|---|
| 16792 | #define RCC_DEV2_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV2__SHIFT 0x7 |
|---|
| 16793 | #define RCC_DEV2_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV2__SHIFT 0x8 |
|---|
| 16794 | #define RCC_DEV2_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV2__SHIFT 0x9 |
|---|
| 16795 | #define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2__SHIFT 0xb |
|---|
| 16796 | #define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2__SHIFT 0xe |
|---|
| 16797 | #define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2__SHIFT 0x12 |
|---|
| 16798 | #define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2__SHIFT 0x15 |
|---|
| 16799 | #define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DEV2__SHIFT 0x19 |
|---|
| 16800 | #define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV2__SHIFT 0x1b |
|---|
| 16801 | #define RCC_DEV2_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV2__SHIFT 0x1d |
|---|
| 16802 | #define RCC_DEV2_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV2__SHIFT 0x1e |
|---|
| 16803 | #define RCC_DEV2_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV2__SHIFT 0x1f |
|---|
| 16804 | #define RCC_DEV2_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2_MASK 0x00000001L |
|---|
| 16805 | #define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DEV2_MASK 0x00000002L |
|---|
| 16806 | #define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DN_DEV2_MASK 0x00000004L |
|---|
| 16807 | #define RCC_DEV2_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV2_MASK 0x00000038L |
|---|
| 16808 | #define RCC_DEV2_PORT_STRAP3__STRAP_MSI_EN_DN_DEV2_MASK 0x00000040L |
|---|
| 16809 | #define RCC_DEV2_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV2_MASK 0x00000080L |
|---|
| 16810 | #define RCC_DEV2_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV2_MASK 0x00000100L |
|---|
| 16811 | #define RCC_DEV2_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV2_MASK 0x00000600L |
|---|
| 16812 | #define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2_MASK 0x00003800L |
|---|
| 16813 | #define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2_MASK 0x0003C000L |
|---|
| 16814 | #define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2_MASK 0x001C0000L |
|---|
| 16815 | #define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2_MASK 0x01E00000L |
|---|
| 16816 | #define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DEV2_MASK 0x06000000L |
|---|
| 16817 | #define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV2_MASK 0x18000000L |
|---|
| 16818 | #define RCC_DEV2_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV2_MASK 0x20000000L |
|---|
| 16819 | #define RCC_DEV2_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV2_MASK 0x40000000L |
|---|
| 16820 | #define RCC_DEV2_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV2_MASK 0x80000000L |
|---|
| 16821 | //RCC_DEV2_PORT_STRAP4 |
|---|
| 16822 | #define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV2__SHIFT 0x0 |
|---|
| 16823 | #define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV2__SHIFT 0x8 |
|---|
| 16824 | #define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV2__SHIFT 0x10 |
|---|
| 16825 | #define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV2__SHIFT 0x18 |
|---|
| 16826 | #define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV2_MASK 0x000000FFL |
|---|
| 16827 | #define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV2_MASK 0x0000FF00L |
|---|
| 16828 | #define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV2_MASK 0x00FF0000L |
|---|
| 16829 | #define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV2_MASK 0xFF000000L |
|---|
| 16830 | //RCC_DEV2_PORT_STRAP5 |
|---|
| 16831 | #define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV2__SHIFT 0x0 |
|---|
| 16832 | #define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV2__SHIFT 0x8 |
|---|
| 16833 | #define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2__SHIFT 0x10 |
|---|
| 16834 | #define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV2__SHIFT 0x11 |
|---|
| 16835 | #define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV2__SHIFT 0x12 |
|---|
| 16836 | #define RCC_DEV2_PORT_STRAP5__STRAP_VC_EN_DN_DEV2__SHIFT 0x13 |
|---|
| 16837 | #define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DEV2__SHIFT 0x14 |
|---|
| 16838 | #define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV2__SHIFT 0x15 |
|---|
| 16839 | #define RCC_DEV2_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV2__SHIFT 0x16 |
|---|
| 16840 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV2__SHIFT 0x17 |
|---|
| 16841 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2__SHIFT 0x18 |
|---|
| 16842 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2__SHIFT 0x19 |
|---|
| 16843 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2__SHIFT 0x1a |
|---|
| 16844 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2__SHIFT 0x1b |
|---|
| 16845 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2__SHIFT 0x1c |
|---|
| 16846 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2__SHIFT 0x1d |
|---|
| 16847 | #define RCC_DEV2_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV2__SHIFT 0x1e |
|---|
| 16848 | #define RCC_DEV2_PORT_STRAP5__STRAP_SSID_EN_DEV2__SHIFT 0x1f |
|---|
| 16849 | #define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV2_MASK 0x000000FFL |
|---|
| 16850 | #define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV2_MASK 0x0000FF00L |
|---|
| 16851 | #define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2_MASK 0x00010000L |
|---|
| 16852 | #define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV2_MASK 0x00020000L |
|---|
| 16853 | #define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV2_MASK 0x00040000L |
|---|
| 16854 | #define RCC_DEV2_PORT_STRAP5__STRAP_VC_EN_DN_DEV2_MASK 0x00080000L |
|---|
| 16855 | #define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DEV2_MASK 0x00100000L |
|---|
| 16856 | #define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV2_MASK 0x00200000L |
|---|
| 16857 | #define RCC_DEV2_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV2_MASK 0x00400000L |
|---|
| 16858 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV2_MASK 0x00800000L |
|---|
| 16859 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2_MASK 0x01000000L |
|---|
| 16860 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2_MASK 0x02000000L |
|---|
| 16861 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2_MASK 0x04000000L |
|---|
| 16862 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2_MASK 0x08000000L |
|---|
| 16863 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2_MASK 0x10000000L |
|---|
| 16864 | #define RCC_DEV2_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2_MASK 0x20000000L |
|---|
| 16865 | #define RCC_DEV2_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV2_MASK 0x40000000L |
|---|
| 16866 | #define RCC_DEV2_PORT_STRAP5__STRAP_SSID_EN_DEV2_MASK 0x80000000L |
|---|
| 16867 | //RCC_DEV2_PORT_STRAP6 |
|---|
| 16868 | #define RCC_DEV2_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV2__SHIFT 0x0 |
|---|
| 16869 | #define RCC_DEV2_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2__SHIFT 0x1 |
|---|
| 16870 | #define RCC_DEV2_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV2__SHIFT 0x2 |
|---|
| 16871 | #define RCC_DEV2_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2__SHIFT 0x3 |
|---|
| 16872 | #define RCC_DEV2_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2__SHIFT 0x4 |
|---|
| 16873 | #define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2__SHIFT 0x5 |
|---|
| 16874 | #define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2__SHIFT 0x6 |
|---|
| 16875 | #define RCC_DEV2_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2__SHIFT 0x7 |
|---|
| 16876 | #define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2__SHIFT 0x8 |
|---|
| 16877 | #define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2__SHIFT 0xc |
|---|
| 16878 | #define RCC_DEV2_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV2__SHIFT 0x10 |
|---|
| 16879 | #define RCC_DEV2_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV2_MASK 0x00000001L |
|---|
| 16880 | #define RCC_DEV2_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2_MASK 0x00000002L |
|---|
| 16881 | #define RCC_DEV2_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV2_MASK 0x00000004L |
|---|
| 16882 | #define RCC_DEV2_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2_MASK 0x00000008L |
|---|
| 16883 | #define RCC_DEV2_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2_MASK 0x00000010L |
|---|
| 16884 | #define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2_MASK 0x00000020L |
|---|
| 16885 | #define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2_MASK 0x00000040L |
|---|
| 16886 | #define RCC_DEV2_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2_MASK 0x00000080L |
|---|
| 16887 | #define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2_MASK 0x00000F00L |
|---|
| 16888 | #define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2_MASK 0x0000F000L |
|---|
| 16889 | #define RCC_DEV2_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV2_MASK 0x00030000L |
|---|
| 16890 | //RCC_DEV2_PORT_STRAP7 |
|---|
| 16891 | #define RCC_DEV2_PORT_STRAP7__STRAP_PORT_NUMBER_DEV2__SHIFT 0x0 |
|---|
| 16892 | #define RCC_DEV2_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV2__SHIFT 0x8 |
|---|
| 16893 | #define RCC_DEV2_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV2__SHIFT 0xc |
|---|
| 16894 | #define RCC_DEV2_PORT_STRAP7__STRAP_RP_BUSNUM_DEV2__SHIFT 0x10 |
|---|
| 16895 | #define RCC_DEV2_PORT_STRAP7__STRAP_DN_DEVNUM_DEV2__SHIFT 0x18 |
|---|
| 16896 | #define RCC_DEV2_PORT_STRAP7__STRAP_DN_FUNCID_DEV2__SHIFT 0x1d |
|---|
| 16897 | #define RCC_DEV2_PORT_STRAP7__STRAP_PORT_NUMBER_DEV2_MASK 0x000000FFL |
|---|
| 16898 | #define RCC_DEV2_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV2_MASK 0x00000F00L |
|---|
| 16899 | #define RCC_DEV2_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV2_MASK 0x0000F000L |
|---|
| 16900 | #define RCC_DEV2_PORT_STRAP7__STRAP_RP_BUSNUM_DEV2_MASK 0x00FF0000L |
|---|
| 16901 | #define RCC_DEV2_PORT_STRAP7__STRAP_DN_DEVNUM_DEV2_MASK 0x1F000000L |
|---|
| 16902 | #define RCC_DEV2_PORT_STRAP7__STRAP_DN_FUNCID_DEV2_MASK 0xE0000000L |
|---|
| 16903 | //RCC_DEV2_PORT_STRAP8 |
|---|
| 16904 | #define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV2__SHIFT 0x0 |
|---|
| 16905 | #define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV2__SHIFT 0x8 |
|---|
| 16906 | #define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV2__SHIFT 0x10 |
|---|
| 16907 | #define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV2__SHIFT 0x18 |
|---|
| 16908 | #define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV2_MASK 0x000000FFL |
|---|
| 16909 | #define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV2_MASK 0x0000FF00L |
|---|
| 16910 | #define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV2_MASK 0x00FF0000L |
|---|
| 16911 | #define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV2_MASK 0xFF000000L |
|---|
| 16912 | //RCC_DEV2_PORT_STRAP9 |
|---|
| 16913 | #define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV2__SHIFT 0x0 |
|---|
| 16914 | #define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV2__SHIFT 0x8 |
|---|
| 16915 | #define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV2_MASK 0x000000FFL |
|---|
| 16916 | #define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV2_MASK 0x0000FF00L |
|---|
| 16917 | //RCC_STRAP1_RCC_BIF_STRAP0 |
|---|
| 16918 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT 0x0 |
|---|
| 16919 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN__SHIFT 0x1 |
|---|
| 16920 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 |
|---|
| 16921 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 |
|---|
| 16922 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 |
|---|
| 16923 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 |
|---|
| 16924 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 |
|---|
| 16925 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 |
|---|
| 16926 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa |
|---|
| 16927 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb |
|---|
| 16928 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc |
|---|
| 16929 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd |
|---|
| 16930 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe |
|---|
| 16931 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf |
|---|
| 16932 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 |
|---|
| 16933 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 |
|---|
| 16934 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 |
|---|
| 16935 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 |
|---|
| 16936 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 |
|---|
| 16937 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a |
|---|
| 16938 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b |
|---|
| 16939 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d |
|---|
| 16940 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e |
|---|
| 16941 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f |
|---|
| 16942 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK 0x00000001L |
|---|
| 16943 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN_MASK 0x00000002L |
|---|
| 16944 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L |
|---|
| 16945 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L |
|---|
| 16946 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L |
|---|
| 16947 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L |
|---|
| 16948 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L |
|---|
| 16949 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L |
|---|
| 16950 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L |
|---|
| 16951 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L |
|---|
| 16952 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L |
|---|
| 16953 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L |
|---|
| 16954 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L |
|---|
| 16955 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L |
|---|
| 16956 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L |
|---|
| 16957 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L |
|---|
| 16958 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L |
|---|
| 16959 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L |
|---|
| 16960 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L |
|---|
| 16961 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L |
|---|
| 16962 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L |
|---|
| 16963 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L |
|---|
| 16964 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L |
|---|
| 16965 | #define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L |
|---|
| 16966 | //RCC_STRAP1_RCC_BIF_STRAP1 |
|---|
| 16967 | #define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 |
|---|
| 16968 | #define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 |
|---|
| 16969 | #define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 |
|---|
| 16970 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 |
|---|
| 16971 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN__SHIFT 0x4 |
|---|
| 16972 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 |
|---|
| 16973 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 |
|---|
| 16974 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 |
|---|
| 16975 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 |
|---|
| 16976 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 |
|---|
| 16977 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa |
|---|
| 16978 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc |
|---|
| 16979 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd |
|---|
| 16980 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf |
|---|
| 16981 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 |
|---|
| 16982 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 |
|---|
| 16983 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 |
|---|
| 16984 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 |
|---|
| 16985 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 |
|---|
| 16986 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 |
|---|
| 16987 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 |
|---|
| 16988 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 |
|---|
| 16989 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 |
|---|
| 16990 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a |
|---|
| 16991 | #define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L |
|---|
| 16992 | #define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L |
|---|
| 16993 | #define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L |
|---|
| 16994 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L |
|---|
| 16995 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN_MASK 0x00000010L |
|---|
| 16996 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L |
|---|
| 16997 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L |
|---|
| 16998 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L |
|---|
| 16999 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L |
|---|
| 17000 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L |
|---|
| 17001 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L |
|---|
| 17002 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L |
|---|
| 17003 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L |
|---|
| 17004 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L |
|---|
| 17005 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L |
|---|
| 17006 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L |
|---|
| 17007 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L |
|---|
| 17008 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L |
|---|
| 17009 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L |
|---|
| 17010 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L |
|---|
| 17011 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L |
|---|
| 17012 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L |
|---|
| 17013 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L |
|---|
| 17014 | #define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L |
|---|
| 17015 | //RCC_STRAP1_RCC_BIF_STRAP2 |
|---|
| 17016 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 |
|---|
| 17017 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 |
|---|
| 17018 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 |
|---|
| 17019 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 |
|---|
| 17020 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 |
|---|
| 17021 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 |
|---|
| 17022 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 |
|---|
| 17023 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa |
|---|
| 17024 | #define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xc |
|---|
| 17025 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe |
|---|
| 17026 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf |
|---|
| 17027 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 |
|---|
| 17028 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 |
|---|
| 17029 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L |
|---|
| 17030 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L |
|---|
| 17031 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L |
|---|
| 17032 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L |
|---|
| 17033 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L |
|---|
| 17034 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L |
|---|
| 17035 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L |
|---|
| 17036 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L |
|---|
| 17037 | #define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00003000L |
|---|
| 17038 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L |
|---|
| 17039 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L |
|---|
| 17040 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L |
|---|
| 17041 | #define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L |
|---|
| 17042 | //RCC_STRAP1_RCC_BIF_STRAP3 |
|---|
| 17043 | #define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 |
|---|
| 17044 | #define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 |
|---|
| 17045 | #define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL |
|---|
| 17046 | #define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L |
|---|
| 17047 | //RCC_STRAP1_RCC_BIF_STRAP4 |
|---|
| 17048 | #define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 |
|---|
| 17049 | #define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 |
|---|
| 17050 | #define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL |
|---|
| 17051 | #define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L |
|---|
| 17052 | //RCC_STRAP1_RCC_BIF_STRAP5 |
|---|
| 17053 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 |
|---|
| 17054 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 |
|---|
| 17055 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 |
|---|
| 17056 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 |
|---|
| 17057 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 |
|---|
| 17058 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 |
|---|
| 17059 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 |
|---|
| 17060 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 |
|---|
| 17061 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 |
|---|
| 17062 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b |
|---|
| 17063 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c |
|---|
| 17064 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL |
|---|
| 17065 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L |
|---|
| 17066 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L |
|---|
| 17067 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L |
|---|
| 17068 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L |
|---|
| 17069 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L |
|---|
| 17070 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L |
|---|
| 17071 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L |
|---|
| 17072 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L |
|---|
| 17073 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L |
|---|
| 17074 | #define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L |
|---|
| 17075 | //RCC_STRAP1_RCC_BIF_STRAP6 |
|---|
| 17076 | #define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3__SHIFT 0x0 |
|---|
| 17077 | #define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3_MASK 0xFFFFFFFFL |
|---|
| 17078 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP0 |
|---|
| 17079 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
|---|
| 17080 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 |
|---|
| 17081 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 |
|---|
| 17082 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 |
|---|
| 17083 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c |
|---|
| 17084 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d |
|---|
| 17085 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e |
|---|
| 17086 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f |
|---|
| 17087 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 17088 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L |
|---|
| 17089 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L |
|---|
| 17090 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L |
|---|
| 17091 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L |
|---|
| 17092 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L |
|---|
| 17093 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L |
|---|
| 17094 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L |
|---|
| 17095 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP1 |
|---|
| 17096 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 |
|---|
| 17097 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 |
|---|
| 17098 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 17099 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L |
|---|
| 17100 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP2 |
|---|
| 17101 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 |
|---|
| 17102 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 |
|---|
| 17103 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 |
|---|
| 17104 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 |
|---|
| 17105 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 |
|---|
| 17106 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 |
|---|
| 17107 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe |
|---|
| 17108 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf |
|---|
| 17109 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 |
|---|
| 17110 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 |
|---|
| 17111 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 |
|---|
| 17112 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 |
|---|
| 17113 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 |
|---|
| 17114 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 |
|---|
| 17115 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 |
|---|
| 17116 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 |
|---|
| 17117 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b |
|---|
| 17118 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c |
|---|
| 17119 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d |
|---|
| 17120 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e |
|---|
| 17121 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f |
|---|
| 17122 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L |
|---|
| 17123 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003EL |
|---|
| 17124 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L |
|---|
| 17125 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L |
|---|
| 17126 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L |
|---|
| 17127 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L |
|---|
| 17128 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L |
|---|
| 17129 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L |
|---|
| 17130 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L |
|---|
| 17131 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L |
|---|
| 17132 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L |
|---|
| 17133 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L |
|---|
| 17134 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L |
|---|
| 17135 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L |
|---|
| 17136 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L |
|---|
| 17137 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L |
|---|
| 17138 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L |
|---|
| 17139 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L |
|---|
| 17140 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L |
|---|
| 17141 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L |
|---|
| 17142 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L |
|---|
| 17143 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP3 |
|---|
| 17144 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 |
|---|
| 17145 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 |
|---|
| 17146 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 |
|---|
| 17147 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 |
|---|
| 17148 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 |
|---|
| 17149 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 |
|---|
| 17150 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 |
|---|
| 17151 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 |
|---|
| 17152 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 |
|---|
| 17153 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a |
|---|
| 17154 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b |
|---|
| 17155 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c |
|---|
| 17156 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L |
|---|
| 17157 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L |
|---|
| 17158 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003FFFCL |
|---|
| 17159 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L |
|---|
| 17160 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L |
|---|
| 17161 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L |
|---|
| 17162 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L |
|---|
| 17163 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L |
|---|
| 17164 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0_MASK 0x02000000L |
|---|
| 17165 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L |
|---|
| 17166 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L |
|---|
| 17167 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L |
|---|
| 17168 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP4 |
|---|
| 17169 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 |
|---|
| 17170 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 |
|---|
| 17171 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 |
|---|
| 17172 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 |
|---|
| 17173 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 |
|---|
| 17174 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c |
|---|
| 17175 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f |
|---|
| 17176 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL |
|---|
| 17177 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L |
|---|
| 17178 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L |
|---|
| 17179 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L |
|---|
| 17180 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L |
|---|
| 17181 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L |
|---|
| 17182 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L |
|---|
| 17183 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP5 |
|---|
| 17184 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 |
|---|
| 17185 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 17186 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP8 |
|---|
| 17187 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 |
|---|
| 17188 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 |
|---|
| 17189 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 |
|---|
| 17190 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 |
|---|
| 17191 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 |
|---|
| 17192 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 |
|---|
| 17193 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 |
|---|
| 17194 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd |
|---|
| 17195 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xf |
|---|
| 17196 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x11 |
|---|
| 17197 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x14 |
|---|
| 17198 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x18 |
|---|
| 17199 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a |
|---|
| 17200 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b |
|---|
| 17201 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e |
|---|
| 17202 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L |
|---|
| 17203 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L |
|---|
| 17204 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00000010L |
|---|
| 17205 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00000060L |
|---|
| 17206 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L |
|---|
| 17207 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L |
|---|
| 17208 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L |
|---|
| 17209 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x00006000L |
|---|
| 17210 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00018000L |
|---|
| 17211 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x000E0000L |
|---|
| 17212 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00F00000L |
|---|
| 17213 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03000000L |
|---|
| 17214 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L |
|---|
| 17215 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L |
|---|
| 17216 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L |
|---|
| 17217 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP9 |
|---|
| 17218 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 |
|---|
| 17219 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 |
|---|
| 17220 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 |
|---|
| 17221 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 |
|---|
| 17222 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL |
|---|
| 17223 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L |
|---|
| 17224 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L |
|---|
| 17225 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L |
|---|
| 17226 | //RCC_STRAP1_RCC_DEV0_EPF0_STRAP13 |
|---|
| 17227 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 |
|---|
| 17228 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 |
|---|
| 17229 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 |
|---|
| 17230 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL |
|---|
| 17231 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L |
|---|
| 17232 | #define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L |
|---|
| 17233 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP0 |
|---|
| 17234 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 |
|---|
| 17235 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 |
|---|
| 17236 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 |
|---|
| 17237 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c |
|---|
| 17238 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d |
|---|
| 17239 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e |
|---|
| 17240 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f |
|---|
| 17241 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL |
|---|
| 17242 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L |
|---|
| 17243 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L |
|---|
| 17244 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L |
|---|
| 17245 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L |
|---|
| 17246 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L |
|---|
| 17247 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L |
|---|
| 17248 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP2 |
|---|
| 17249 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 |
|---|
| 17250 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 |
|---|
| 17251 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 |
|---|
| 17252 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe |
|---|
| 17253 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 |
|---|
| 17254 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 |
|---|
| 17255 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 |
|---|
| 17256 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 |
|---|
| 17257 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 |
|---|
| 17258 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 |
|---|
| 17259 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 |
|---|
| 17260 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 |
|---|
| 17261 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c |
|---|
| 17262 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d |
|---|
| 17263 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e |
|---|
| 17264 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f |
|---|
| 17265 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L |
|---|
| 17266 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L |
|---|
| 17267 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L |
|---|
| 17268 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L |
|---|
| 17269 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L |
|---|
| 17270 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L |
|---|
| 17271 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L |
|---|
| 17272 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L |
|---|
| 17273 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L |
|---|
| 17274 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L |
|---|
| 17275 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L |
|---|
| 17276 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L |
|---|
| 17277 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L |
|---|
| 17278 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L |
|---|
| 17279 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L |
|---|
| 17280 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L |
|---|
| 17281 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP3 |
|---|
| 17282 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 |
|---|
| 17283 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 |
|---|
| 17284 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 |
|---|
| 17285 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 |
|---|
| 17286 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 |
|---|
| 17287 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 |
|---|
| 17288 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 |
|---|
| 17289 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 |
|---|
| 17290 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a |
|---|
| 17291 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b |
|---|
| 17292 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L |
|---|
| 17293 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L |
|---|
| 17294 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003FFFCL |
|---|
| 17295 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L |
|---|
| 17296 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L |
|---|
| 17297 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L |
|---|
| 17298 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L |
|---|
| 17299 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1_MASK 0x02000000L |
|---|
| 17300 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L |
|---|
| 17301 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L |
|---|
| 17302 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP4 |
|---|
| 17303 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 |
|---|
| 17304 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 |
|---|
| 17305 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 |
|---|
| 17306 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 |
|---|
| 17307 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c |
|---|
| 17308 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f |
|---|
| 17309 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L |
|---|
| 17310 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L |
|---|
| 17311 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L |
|---|
| 17312 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L |
|---|
| 17313 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L |
|---|
| 17314 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L |
|---|
| 17315 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP5 |
|---|
| 17316 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 |
|---|
| 17317 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL |
|---|
| 17318 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP6 |
|---|
| 17319 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 17320 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 |
|---|
| 17321 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 |
|---|
| 17322 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 |
|---|
| 17323 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 |
|---|
| 17324 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 |
|---|
| 17325 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 |
|---|
| 17326 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 |
|---|
| 17327 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 |
|---|
| 17328 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 |
|---|
| 17329 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 17330 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L |
|---|
| 17331 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L |
|---|
| 17332 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1_MASK 0x00000070L |
|---|
| 17333 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK 0x00000100L |
|---|
| 17334 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000200L |
|---|
| 17335 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK 0x00010000L |
|---|
| 17336 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK 0x00020000L |
|---|
| 17337 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK 0x01000000L |
|---|
| 17338 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK 0x02000000L |
|---|
| 17339 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP7 |
|---|
| 17340 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 17341 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 |
|---|
| 17342 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1__SHIFT 0x14 |
|---|
| 17343 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1__SHIFT 0x16 |
|---|
| 17344 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1__SHIFT 0x17 |
|---|
| 17345 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1__SHIFT 0x18 |
|---|
| 17346 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1__SHIFT 0x1a |
|---|
| 17347 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 17348 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1_MASK 0x0000001EL |
|---|
| 17349 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1_MASK 0x00300000L |
|---|
| 17350 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1_MASK 0x00400000L |
|---|
| 17351 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1_MASK 0x00800000L |
|---|
| 17352 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1_MASK 0x03000000L |
|---|
| 17353 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1_MASK 0xFC000000L |
|---|
| 17354 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP10 |
|---|
| 17355 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 17356 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 |
|---|
| 17357 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 17358 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL |
|---|
| 17359 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP11 |
|---|
| 17360 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 17361 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 |
|---|
| 17362 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 17363 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL |
|---|
| 17364 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP12 |
|---|
| 17365 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 |
|---|
| 17366 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 |
|---|
| 17367 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1_MASK 0x00000001L |
|---|
| 17368 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_MASK 0x1FFFFFFEL |
|---|
| 17369 | //RCC_STRAP1_RCC_DEV0_EPF1_STRAP13 |
|---|
| 17370 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 |
|---|
| 17371 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 |
|---|
| 17372 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 |
|---|
| 17373 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL |
|---|
| 17374 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L |
|---|
| 17375 | #define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L |
|---|
| 17376 | //RCC_DEV0_EPF2_STRAP0 |
|---|
| 17377 | #define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0 |
|---|
| 17378 | #define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10 |
|---|
| 17379 | #define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14 |
|---|
| 17380 | #define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c |
|---|
| 17381 | #define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d |
|---|
| 17382 | #define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e |
|---|
| 17383 | #define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f |
|---|
| 17384 | #define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2_MASK 0x0000FFFFL |
|---|
| 17385 | #define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2_MASK 0x000F0000L |
|---|
| 17386 | #define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2_MASK 0x00F00000L |
|---|
| 17387 | #define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2_MASK 0x10000000L |
|---|
| 17388 | #define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_MASK 0x20000000L |
|---|
| 17389 | #define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2_MASK 0x40000000L |
|---|
| 17390 | #define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2_MASK 0x80000000L |
|---|
| 17391 | //RCC_DEV0_EPF2_STRAP2 |
|---|
| 17392 | #define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7 |
|---|
| 17393 | #define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8 |
|---|
| 17394 | #define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2__SHIFT 0x9 |
|---|
| 17395 | #define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe |
|---|
| 17396 | #define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10 |
|---|
| 17397 | #define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11 |
|---|
| 17398 | #define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14 |
|---|
| 17399 | #define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15 |
|---|
| 17400 | #define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x17 |
|---|
| 17401 | #define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18 |
|---|
| 17402 | #define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2__SHIFT 0x1c |
|---|
| 17403 | #define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2__SHIFT 0x1d |
|---|
| 17404 | #define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2__SHIFT 0x1e |
|---|
| 17405 | #define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2__SHIFT 0x1f |
|---|
| 17406 | #define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK 0x00000080L |
|---|
| 17407 | #define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK 0x00000100L |
|---|
| 17408 | #define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2_MASK 0x00003E00L |
|---|
| 17409 | #define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK 0x00004000L |
|---|
| 17410 | #define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK 0x00010000L |
|---|
| 17411 | #define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK 0x00020000L |
|---|
| 17412 | #define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK 0x00100000L |
|---|
| 17413 | #define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK 0x00200000L |
|---|
| 17414 | #define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2_MASK 0x00800000L |
|---|
| 17415 | #define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK 0x07000000L |
|---|
| 17416 | #define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2_MASK 0x10000000L |
|---|
| 17417 | #define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2_MASK 0x20000000L |
|---|
| 17418 | #define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2_MASK 0x40000000L |
|---|
| 17419 | #define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2_MASK 0x80000000L |
|---|
| 17420 | //RCC_DEV0_EPF2_STRAP3 |
|---|
| 17421 | #define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x0 |
|---|
| 17422 | #define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x1 |
|---|
| 17423 | #define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x2 |
|---|
| 17424 | #define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12 |
|---|
| 17425 | #define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13 |
|---|
| 17426 | #define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14 |
|---|
| 17427 | #define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18 |
|---|
| 17428 | #define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__SHIFT 0x19 |
|---|
| 17429 | #define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a |
|---|
| 17430 | #define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b |
|---|
| 17431 | #define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_MASK 0x00000001L |
|---|
| 17432 | #define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2_MASK 0x00000002L |
|---|
| 17433 | #define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2_MASK 0x0003FFFCL |
|---|
| 17434 | #define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2_MASK 0x00040000L |
|---|
| 17435 | #define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2_MASK 0x00080000L |
|---|
| 17436 | #define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2_MASK 0x00100000L |
|---|
| 17437 | #define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2_MASK 0x01000000L |
|---|
| 17438 | #define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2_MASK 0x02000000L |
|---|
| 17439 | #define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_MASK 0x04000000L |
|---|
| 17440 | #define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_MASK 0x08000000L |
|---|
| 17441 | //RCC_DEV0_EPF2_STRAP4 |
|---|
| 17442 | #define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14 |
|---|
| 17443 | #define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15 |
|---|
| 17444 | #define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16 |
|---|
| 17445 | #define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17 |
|---|
| 17446 | #define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c |
|---|
| 17447 | #define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f |
|---|
| 17448 | #define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2_MASK 0x00100000L |
|---|
| 17449 | #define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2_MASK 0x00200000L |
|---|
| 17450 | #define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2_MASK 0x00400000L |
|---|
| 17451 | #define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2_MASK 0x0F800000L |
|---|
| 17452 | #define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2_MASK 0x70000000L |
|---|
| 17453 | #define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2_MASK 0x80000000L |
|---|
| 17454 | //RCC_DEV0_EPF2_STRAP5 |
|---|
| 17455 | #define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0 |
|---|
| 17456 | #define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESEL_DEV0_F2__SHIFT 0x10 |
|---|
| 17457 | #define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESELD_DEV0_F2__SHIFT 0x14 |
|---|
| 17458 | #define RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2__SHIFT 0x1b |
|---|
| 17459 | #define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2_MASK 0x0000FFFFL |
|---|
| 17460 | #define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESEL_DEV0_F2_MASK 0x000F0000L |
|---|
| 17461 | #define RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESELD_DEV0_F2_MASK 0x00F00000L |
|---|
| 17462 | #define RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2_MASK 0x38000000L |
|---|
| 17463 | //RCC_DEV0_EPF2_STRAP6 |
|---|
| 17464 | #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0 |
|---|
| 17465 | #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x1 |
|---|
| 17466 | #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__SHIFT 0x4 |
|---|
| 17467 | #define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT 0x8 |
|---|
| 17468 | #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2_MASK 0x00000001L |
|---|
| 17469 | #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2_MASK 0x00000002L |
|---|
| 17470 | #define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2_MASK 0x00000070L |
|---|
| 17471 | #define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2_MASK 0x00000100L |
|---|
| 17472 | //RCC_DEV0_EPF2_STRAP7 |
|---|
| 17473 | #define RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_EN_DEV0_F2__SHIFT 0x0 |
|---|
| 17474 | #define RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F2__SHIFT 0x1 |
|---|
| 17475 | #define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F2__SHIFT 0x14 |
|---|
| 17476 | #define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_EN_DEV0_F2__SHIFT 0x16 |
|---|
| 17477 | #define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F2__SHIFT 0x17 |
|---|
| 17478 | #define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F2__SHIFT 0x18 |
|---|
| 17479 | #define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F2__SHIFT 0x1a |
|---|
| 17480 | #define RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_EN_DEV0_F2_MASK 0x00000001L |
|---|
| 17481 | #define RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F2_MASK 0x0000001EL |
|---|
| 17482 | #define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F2_MASK 0x00300000L |
|---|
| 17483 | #define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_EN_DEV0_F2_MASK 0x00400000L |
|---|
| 17484 | #define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F2_MASK 0x00800000L |
|---|
| 17485 | #define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F2_MASK 0x03000000L |
|---|
| 17486 | #define RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F2_MASK 0xFC000000L |
|---|
| 17487 | //RCC_DEV0_EPF2_STRAP13 |
|---|
| 17488 | #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0 |
|---|
| 17489 | #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8 |
|---|
| 17490 | #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10 |
|---|
| 17491 | #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2_MASK 0x000000FFL |
|---|
| 17492 | #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2_MASK 0x0000FF00L |
|---|
| 17493 | #define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2_MASK 0x00FF0000L |
|---|
| 17494 | //RCC_DEV0_EPF3_STRAP0 |
|---|
| 17495 | #define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0 |
|---|
| 17496 | #define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10 |
|---|
| 17497 | #define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14 |
|---|
| 17498 | #define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c |
|---|
| 17499 | #define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d |
|---|
| 17500 | #define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e |
|---|
| 17501 | #define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f |
|---|
| 17502 | #define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3_MASK 0x0000FFFFL |
|---|
| 17503 | #define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3_MASK 0x000F0000L |
|---|
| 17504 | #define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3_MASK 0x00F00000L |
|---|
| 17505 | #define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3_MASK 0x10000000L |
|---|
| 17506 | #define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_MASK 0x20000000L |
|---|
| 17507 | #define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3_MASK 0x40000000L |
|---|
| 17508 | #define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3_MASK 0x80000000L |
|---|
| 17509 | //RCC_DEV0_EPF3_STRAP2 |
|---|
| 17510 | #define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7 |
|---|
| 17511 | #define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8 |
|---|
| 17512 | #define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3__SHIFT 0x9 |
|---|
| 17513 | #define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe |
|---|
| 17514 | #define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10 |
|---|
| 17515 | #define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11 |
|---|
| 17516 | #define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14 |
|---|
| 17517 | #define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15 |
|---|
| 17518 | #define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x17 |
|---|
| 17519 | #define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18 |
|---|
| 17520 | #define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3__SHIFT 0x1c |
|---|
| 17521 | #define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3__SHIFT 0x1d |
|---|
| 17522 | #define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3__SHIFT 0x1e |
|---|
| 17523 | #define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3__SHIFT 0x1f |
|---|
| 17524 | #define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3_MASK 0x00000080L |
|---|
| 17525 | #define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3_MASK 0x00000100L |
|---|
| 17526 | #define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3_MASK 0x00003E00L |
|---|
| 17527 | #define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_MASK 0x00004000L |
|---|
| 17528 | #define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3_MASK 0x00010000L |
|---|
| 17529 | #define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3_MASK 0x00020000L |
|---|
| 17530 | #define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3_MASK 0x00100000L |
|---|
| 17531 | #define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3_MASK 0x00200000L |
|---|
| 17532 | #define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3_MASK 0x00800000L |
|---|
| 17533 | #define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3_MASK 0x07000000L |
|---|
| 17534 | #define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3_MASK 0x10000000L |
|---|
| 17535 | #define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3_MASK 0x20000000L |
|---|
| 17536 | #define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3_MASK 0x40000000L |
|---|
| 17537 | #define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3_MASK 0x80000000L |
|---|
| 17538 | //RCC_DEV0_EPF3_STRAP3 |
|---|
| 17539 | #define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x0 |
|---|
| 17540 | #define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x1 |
|---|
| 17541 | #define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x2 |
|---|
| 17542 | #define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12 |
|---|
| 17543 | #define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13 |
|---|
| 17544 | #define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14 |
|---|
| 17545 | #define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18 |
|---|
| 17546 | #define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__SHIFT 0x19 |
|---|
| 17547 | #define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a |
|---|
| 17548 | #define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b |
|---|
| 17549 | #define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_MASK 0x00000001L |
|---|
| 17550 | #define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3_MASK 0x00000002L |
|---|
| 17551 | #define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3_MASK 0x0003FFFCL |
|---|
| 17552 | #define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3_MASK 0x00040000L |
|---|
| 17553 | #define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3_MASK 0x00080000L |
|---|
| 17554 | #define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3_MASK 0x00100000L |
|---|
| 17555 | #define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3_MASK 0x01000000L |
|---|
| 17556 | #define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3_MASK 0x02000000L |
|---|
| 17557 | #define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_MASK 0x04000000L |
|---|
| 17558 | #define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_MASK 0x08000000L |
|---|
| 17559 | //RCC_DEV0_EPF3_STRAP4 |
|---|
| 17560 | #define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14 |
|---|
| 17561 | #define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15 |
|---|
| 17562 | #define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16 |
|---|
| 17563 | #define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17 |
|---|
| 17564 | #define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c |
|---|
| 17565 | #define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x1f |
|---|
| 17566 | #define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3_MASK 0x00100000L |
|---|
| 17567 | #define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3_MASK 0x00200000L |
|---|
| 17568 | #define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3_MASK 0x00400000L |
|---|
| 17569 | #define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3_MASK 0x0F800000L |
|---|
| 17570 | #define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3_MASK 0x70000000L |
|---|
| 17571 | #define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3_MASK 0x80000000L |
|---|
| 17572 | //RCC_DEV0_EPF3_STRAP5 |
|---|
| 17573 | #define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0 |
|---|
| 17574 | #define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__SHIFT 0x10 |
|---|
| 17575 | #define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__SHIFT 0x14 |
|---|
| 17576 | #define RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3__SHIFT 0x1b |
|---|
| 17577 | #define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3_MASK 0x0000FFFFL |
|---|
| 17578 | #define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3_MASK 0x000F0000L |
|---|
| 17579 | #define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3_MASK 0x00F00000L |
|---|
| 17580 | #define RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3_MASK 0x38000000L |
|---|
| 17581 | //RCC_DEV0_EPF3_STRAP6 |
|---|
| 17582 | #define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0 |
|---|
| 17583 | #define RCC_DEV0_EPF3_STRAP6__STRAP_APER1_EN_DEV0_F3__SHIFT 0x8 |
|---|
| 17584 | #define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3_MASK 0x00000001L |
|---|
| 17585 | #define RCC_DEV0_EPF3_STRAP6__STRAP_APER1_EN_DEV0_F3_MASK 0x00000100L |
|---|
| 17586 | //RCC_DEV0_EPF3_STRAP7 |
|---|
| 17587 | #define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F3__SHIFT 0x14 |
|---|
| 17588 | #define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_EN_DEV0_F3__SHIFT 0x16 |
|---|
| 17589 | #define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F3__SHIFT 0x17 |
|---|
| 17590 | #define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F3__SHIFT 0x18 |
|---|
| 17591 | #define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F3__SHIFT 0x1a |
|---|
| 17592 | #define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F3_MASK 0x00300000L |
|---|
| 17593 | #define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_EN_DEV0_F3_MASK 0x00400000L |
|---|
| 17594 | #define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F3_MASK 0x00800000L |
|---|
| 17595 | #define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F3_MASK 0x03000000L |
|---|
| 17596 | #define RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F3_MASK 0xFC000000L |
|---|
| 17597 | //RCC_DEV0_EPF3_STRAP13 |
|---|
| 17598 | #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0 |
|---|
| 17599 | #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8 |
|---|
| 17600 | #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10 |
|---|
| 17601 | #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3_MASK 0x000000FFL |
|---|
| 17602 | #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3_MASK 0x0000FF00L |
|---|
| 17603 | #define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3_MASK 0x00FF0000L |
|---|
| 17604 | //RCC_DEV0_EPF4_STRAP0 |
|---|
| 17605 | #define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT 0x0 |
|---|
| 17606 | #define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT 0x10 |
|---|
| 17607 | #define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT 0x14 |
|---|
| 17608 | #define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x1c |
|---|
| 17609 | #define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT 0x1d |
|---|
| 17610 | #define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x1e |
|---|
| 17611 | #define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x1f |
|---|
| 17612 | #define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4_MASK 0x0000FFFFL |
|---|
| 17613 | #define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4_MASK 0x000F0000L |
|---|
| 17614 | #define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4_MASK 0x00F00000L |
|---|
| 17615 | #define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4_MASK 0x10000000L |
|---|
| 17616 | #define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4_MASK 0x20000000L |
|---|
| 17617 | #define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4_MASK 0x40000000L |
|---|
| 17618 | #define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4_MASK 0x80000000L |
|---|
| 17619 | //RCC_DEV0_EPF4_STRAP2 |
|---|
| 17620 | #define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT 0x7 |
|---|
| 17621 | #define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT 0x8 |
|---|
| 17622 | #define RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4__SHIFT 0x9 |
|---|
| 17623 | #define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT 0xe |
|---|
| 17624 | #define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x10 |
|---|
| 17625 | #define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x11 |
|---|
| 17626 | #define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x14 |
|---|
| 17627 | #define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x15 |
|---|
| 17628 | #define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT 0x17 |
|---|
| 17629 | #define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT 0x18 |
|---|
| 17630 | #define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4__SHIFT 0x1c |
|---|
| 17631 | #define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4__SHIFT 0x1d |
|---|
| 17632 | #define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4__SHIFT 0x1e |
|---|
| 17633 | #define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4__SHIFT 0x1f |
|---|
| 17634 | #define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4_MASK 0x00000080L |
|---|
| 17635 | #define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4_MASK 0x00000100L |
|---|
| 17636 | #define RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4_MASK 0x00003E00L |
|---|
| 17637 | #define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4_MASK 0x00004000L |
|---|
| 17638 | #define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4_MASK 0x00010000L |
|---|
| 17639 | #define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4_MASK 0x00020000L |
|---|
| 17640 | #define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4_MASK 0x00100000L |
|---|
| 17641 | #define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4_MASK 0x00200000L |
|---|
| 17642 | #define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4_MASK 0x00800000L |
|---|
| 17643 | #define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4_MASK 0x07000000L |
|---|
| 17644 | #define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4_MASK 0x10000000L |
|---|
| 17645 | #define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4_MASK 0x20000000L |
|---|
| 17646 | #define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4_MASK 0x40000000L |
|---|
| 17647 | #define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4_MASK 0x80000000L |
|---|
| 17648 | //RCC_DEV0_EPF4_STRAP3 |
|---|
| 17649 | #define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x0 |
|---|
| 17650 | #define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x1 |
|---|
| 17651 | #define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT 0x2 |
|---|
| 17652 | #define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT 0x12 |
|---|
| 17653 | #define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT 0x13 |
|---|
| 17654 | #define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT 0x14 |
|---|
| 17655 | #define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x18 |
|---|
| 17656 | #define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__SHIFT 0x19 |
|---|
| 17657 | #define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x1a |
|---|
| 17658 | #define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x1b |
|---|
| 17659 | #define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4_MASK 0x00000001L |
|---|
| 17660 | #define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4_MASK 0x00000002L |
|---|
| 17661 | #define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4_MASK 0x0003FFFCL |
|---|
| 17662 | #define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4_MASK 0x00040000L |
|---|
| 17663 | #define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4_MASK 0x00080000L |
|---|
| 17664 | #define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4_MASK 0x00100000L |
|---|
| 17665 | #define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4_MASK 0x01000000L |
|---|
| 17666 | #define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4_MASK 0x02000000L |
|---|
| 17667 | #define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4_MASK 0x04000000L |
|---|
| 17668 | #define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4_MASK 0x08000000L |
|---|
| 17669 | //RCC_DEV0_EPF4_STRAP4 |
|---|
| 17670 | #define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT 0x14 |
|---|
| 17671 | #define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT 0x15 |
|---|
| 17672 | #define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT 0x16 |
|---|
| 17673 | #define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT 0x17 |
|---|
| 17674 | #define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT 0x1c |
|---|
| 17675 | #define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x1f |
|---|
| 17676 | #define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4_MASK 0x00100000L |
|---|
| 17677 | #define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4_MASK 0x00200000L |
|---|
| 17678 | #define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4_MASK 0x00400000L |
|---|
| 17679 | #define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4_MASK 0x0F800000L |
|---|
| 17680 | #define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4_MASK 0x70000000L |
|---|
| 17681 | #define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4_MASK 0x80000000L |
|---|
| 17682 | //RCC_DEV0_EPF4_STRAP5 |
|---|
| 17683 | #define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT 0x0 |
|---|
| 17684 | #define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__SHIFT 0x10 |
|---|
| 17685 | #define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__SHIFT 0x14 |
|---|
| 17686 | #define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4_MASK 0x0000FFFFL |
|---|
| 17687 | #define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4_MASK 0x000F0000L |
|---|
| 17688 | #define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4_MASK 0x00F00000L |
|---|
| 17689 | //RCC_DEV0_EPF4_STRAP6 |
|---|
| 17690 | #define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT 0x0 |
|---|
| 17691 | #define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4_MASK 0x00000001L |
|---|
| 17692 | //RCC_DEV0_EPF4_STRAP7 |
|---|
| 17693 | #define RCC_DEV0_EPF4_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F4__SHIFT 0x5 |
|---|
| 17694 | #define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F4__SHIFT 0x14 |
|---|
| 17695 | #define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_EN_DEV0_F4__SHIFT 0x16 |
|---|
| 17696 | #define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F4__SHIFT 0x17 |
|---|
| 17697 | #define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F4__SHIFT 0x18 |
|---|
| 17698 | #define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F4__SHIFT 0x1a |
|---|
| 17699 | #define RCC_DEV0_EPF4_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F4_MASK 0x0000FFE0L |
|---|
| 17700 | #define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F4_MASK 0x00300000L |
|---|
| 17701 | #define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_EN_DEV0_F4_MASK 0x00400000L |
|---|
| 17702 | #define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F4_MASK 0x00800000L |
|---|
| 17703 | #define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F4_MASK 0x03000000L |
|---|
| 17704 | #define RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F4_MASK 0xFC000000L |
|---|
| 17705 | //RCC_DEV0_EPF4_STRAP13 |
|---|
| 17706 | #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT 0x0 |
|---|
| 17707 | #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT 0x8 |
|---|
| 17708 | #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT 0x10 |
|---|
| 17709 | #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4_MASK 0x000000FFL |
|---|
| 17710 | #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4_MASK 0x0000FF00L |
|---|
| 17711 | #define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4_MASK 0x00FF0000L |
|---|
| 17712 | //RCC_DEV0_EPF5_STRAP0 |
|---|
| 17713 | #define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT 0x0 |
|---|
| 17714 | #define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT 0x10 |
|---|
| 17715 | #define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT 0x14 |
|---|
| 17716 | #define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x1c |
|---|
| 17717 | #define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT 0x1d |
|---|
| 17718 | #define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x1e |
|---|
| 17719 | #define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x1f |
|---|
| 17720 | #define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5_MASK 0x0000FFFFL |
|---|
| 17721 | #define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5_MASK 0x000F0000L |
|---|
| 17722 | #define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5_MASK 0x00F00000L |
|---|
| 17723 | #define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5_MASK 0x10000000L |
|---|
| 17724 | #define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5_MASK 0x20000000L |
|---|
| 17725 | #define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5_MASK 0x40000000L |
|---|
| 17726 | #define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5_MASK 0x80000000L |
|---|
| 17727 | //RCC_DEV0_EPF5_STRAP2 |
|---|
| 17728 | #define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT 0x7 |
|---|
| 17729 | #define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT 0x8 |
|---|
| 17730 | #define RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5__SHIFT 0x9 |
|---|
| 17731 | #define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT 0xe |
|---|
| 17732 | #define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x10 |
|---|
| 17733 | #define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x11 |
|---|
| 17734 | #define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x14 |
|---|
| 17735 | #define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x15 |
|---|
| 17736 | #define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT 0x17 |
|---|
| 17737 | #define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT 0x18 |
|---|
| 17738 | #define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5__SHIFT 0x1c |
|---|
| 17739 | #define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5__SHIFT 0x1d |
|---|
| 17740 | #define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5__SHIFT 0x1e |
|---|
| 17741 | #define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5__SHIFT 0x1f |
|---|
| 17742 | #define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5_MASK 0x00000080L |
|---|
| 17743 | #define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5_MASK 0x00000100L |
|---|
| 17744 | #define RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5_MASK 0x00003E00L |
|---|
| 17745 | #define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5_MASK 0x00004000L |
|---|
| 17746 | #define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5_MASK 0x00010000L |
|---|
| 17747 | #define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5_MASK 0x00020000L |
|---|
| 17748 | #define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5_MASK 0x00100000L |
|---|
| 17749 | #define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5_MASK 0x00200000L |
|---|
| 17750 | #define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5_MASK 0x00800000L |
|---|
| 17751 | #define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5_MASK 0x07000000L |
|---|
| 17752 | #define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5_MASK 0x10000000L |
|---|
| 17753 | #define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5_MASK 0x20000000L |
|---|
| 17754 | #define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5_MASK 0x40000000L |
|---|
| 17755 | #define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5_MASK 0x80000000L |
|---|
| 17756 | //RCC_DEV0_EPF5_STRAP3 |
|---|
| 17757 | #define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x0 |
|---|
| 17758 | #define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x1 |
|---|
| 17759 | #define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT 0x2 |
|---|
| 17760 | #define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT 0x12 |
|---|
| 17761 | #define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT 0x13 |
|---|
| 17762 | #define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT 0x14 |
|---|
| 17763 | #define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x18 |
|---|
| 17764 | #define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__SHIFT 0x19 |
|---|
| 17765 | #define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x1a |
|---|
| 17766 | #define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x1b |
|---|
| 17767 | #define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5_MASK 0x00000001L |
|---|
| 17768 | #define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5_MASK 0x00000002L |
|---|
| 17769 | #define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5_MASK 0x0003FFFCL |
|---|
| 17770 | #define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5_MASK 0x00040000L |
|---|
| 17771 | #define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5_MASK 0x00080000L |
|---|
| 17772 | #define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5_MASK 0x00100000L |
|---|
| 17773 | #define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5_MASK 0x01000000L |
|---|
| 17774 | #define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5_MASK 0x02000000L |
|---|
| 17775 | #define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5_MASK 0x04000000L |
|---|
| 17776 | #define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5_MASK 0x08000000L |
|---|
| 17777 | //RCC_DEV0_EPF5_STRAP4 |
|---|
| 17778 | #define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x14 |
|---|
| 17779 | #define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x15 |
|---|
| 17780 | #define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x16 |
|---|
| 17781 | #define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x17 |
|---|
| 17782 | #define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x1c |
|---|
| 17783 | #define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f |
|---|
| 17784 | #define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5_MASK 0x00100000L |
|---|
| 17785 | #define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5_MASK 0x00200000L |
|---|
| 17786 | #define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5_MASK 0x00400000L |
|---|
| 17787 | #define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5_MASK 0x0F800000L |
|---|
| 17788 | #define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5_MASK 0x70000000L |
|---|
| 17789 | #define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5_MASK 0x80000000L |
|---|
| 17790 | //RCC_DEV0_EPF5_STRAP5 |
|---|
| 17791 | #define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT 0x0 |
|---|
| 17792 | #define RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESEL_DEV0_F5__SHIFT 0x10 |
|---|
| 17793 | #define RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESELD_DEV0_F5__SHIFT 0x14 |
|---|
| 17794 | #define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5_MASK 0x0000FFFFL |
|---|
| 17795 | #define RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESEL_DEV0_F5_MASK 0x000F0000L |
|---|
| 17796 | #define RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESELD_DEV0_F5_MASK 0x00F00000L |
|---|
| 17797 | //RCC_DEV0_EPF5_STRAP6 |
|---|
| 17798 | #define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT 0x0 |
|---|
| 17799 | #define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5_MASK 0x00000001L |
|---|
| 17800 | //RCC_DEV0_EPF5_STRAP7 |
|---|
| 17801 | #define RCC_DEV0_EPF5_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F5__SHIFT 0x5 |
|---|
| 17802 | #define RCC_DEV0_EPF5_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F5_MASK 0x0000FFE0L |
|---|
| 17803 | //RCC_DEV0_EPF5_STRAP13 |
|---|
| 17804 | #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT 0x0 |
|---|
| 17805 | #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT 0x8 |
|---|
| 17806 | #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT 0x10 |
|---|
| 17807 | #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5_MASK 0x000000FFL |
|---|
| 17808 | #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5_MASK 0x0000FF00L |
|---|
| 17809 | #define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5_MASK 0x00FF0000L |
|---|
| 17810 | //RCC_DEV0_EPF6_STRAP0 |
|---|
| 17811 | #define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT 0x0 |
|---|
| 17812 | #define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT 0x10 |
|---|
| 17813 | #define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT 0x14 |
|---|
| 17814 | #define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x1c |
|---|
| 17815 | #define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT 0x1d |
|---|
| 17816 | #define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x1e |
|---|
| 17817 | #define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x1f |
|---|
| 17818 | #define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6_MASK 0x0000FFFFL |
|---|
| 17819 | #define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6_MASK 0x000F0000L |
|---|
| 17820 | #define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6_MASK 0x00F00000L |
|---|
| 17821 | #define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6_MASK 0x10000000L |
|---|
| 17822 | #define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6_MASK 0x20000000L |
|---|
| 17823 | #define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6_MASK 0x40000000L |
|---|
| 17824 | #define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6_MASK 0x80000000L |
|---|
| 17825 | //RCC_DEV0_EPF6_STRAP2 |
|---|
| 17826 | #define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT 0x7 |
|---|
| 17827 | #define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT 0x8 |
|---|
| 17828 | #define RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6__SHIFT 0x9 |
|---|
| 17829 | #define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT 0xe |
|---|
| 17830 | #define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x10 |
|---|
| 17831 | #define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x11 |
|---|
| 17832 | #define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x14 |
|---|
| 17833 | #define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x15 |
|---|
| 17834 | #define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT 0x17 |
|---|
| 17835 | #define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT 0x18 |
|---|
| 17836 | #define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6__SHIFT 0x1c |
|---|
| 17837 | #define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6__SHIFT 0x1d |
|---|
| 17838 | #define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6__SHIFT 0x1e |
|---|
| 17839 | #define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6__SHIFT 0x1f |
|---|
| 17840 | #define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6_MASK 0x00000080L |
|---|
| 17841 | #define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6_MASK 0x00000100L |
|---|
| 17842 | #define RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6_MASK 0x00003E00L |
|---|
| 17843 | #define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6_MASK 0x00004000L |
|---|
| 17844 | #define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6_MASK 0x00010000L |
|---|
| 17845 | #define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6_MASK 0x00020000L |
|---|
| 17846 | #define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6_MASK 0x00100000L |
|---|
| 17847 | #define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6_MASK 0x00200000L |
|---|
| 17848 | #define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6_MASK 0x00800000L |
|---|
| 17849 | #define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6_MASK 0x07000000L |
|---|
| 17850 | #define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6_MASK 0x10000000L |
|---|
| 17851 | #define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6_MASK 0x20000000L |
|---|
| 17852 | #define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6_MASK 0x40000000L |
|---|
| 17853 | #define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6_MASK 0x80000000L |
|---|
| 17854 | //RCC_DEV0_EPF6_STRAP3 |
|---|
| 17855 | #define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x0 |
|---|
| 17856 | #define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x1 |
|---|
| 17857 | #define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT 0x2 |
|---|
| 17858 | #define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT 0x12 |
|---|
| 17859 | #define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT 0x13 |
|---|
| 17860 | #define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT 0x14 |
|---|
| 17861 | #define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x18 |
|---|
| 17862 | #define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__SHIFT 0x19 |
|---|
| 17863 | #define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x1a |
|---|
| 17864 | #define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x1b |
|---|
| 17865 | #define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6_MASK 0x00000001L |
|---|
| 17866 | #define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6_MASK 0x00000002L |
|---|
| 17867 | #define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6_MASK 0x0003FFFCL |
|---|
| 17868 | #define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6_MASK 0x00040000L |
|---|
| 17869 | #define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6_MASK 0x00080000L |
|---|
| 17870 | #define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6_MASK 0x00100000L |
|---|
| 17871 | #define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6_MASK 0x01000000L |
|---|
| 17872 | #define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6_MASK 0x02000000L |
|---|
| 17873 | #define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6_MASK 0x04000000L |
|---|
| 17874 | #define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6_MASK 0x08000000L |
|---|
| 17875 | //RCC_DEV0_EPF6_STRAP4 |
|---|
| 17876 | #define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT 0x14 |
|---|
| 17877 | #define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT 0x15 |
|---|
| 17878 | #define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT 0x16 |
|---|
| 17879 | #define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT 0x17 |
|---|
| 17880 | #define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT 0x1c |
|---|
| 17881 | #define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x1f |
|---|
| 17882 | #define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6_MASK 0x00100000L |
|---|
| 17883 | #define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6_MASK 0x00200000L |
|---|
| 17884 | #define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6_MASK 0x00400000L |
|---|
| 17885 | #define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6_MASK 0x0F800000L |
|---|
| 17886 | #define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6_MASK 0x70000000L |
|---|
| 17887 | #define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6_MASK 0x80000000L |
|---|
| 17888 | //RCC_DEV0_EPF6_STRAP5 |
|---|
| 17889 | #define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT 0x0 |
|---|
| 17890 | #define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6_MASK 0x0000FFFFL |
|---|
| 17891 | //RCC_DEV0_EPF6_STRAP6 |
|---|
| 17892 | #define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT 0x0 |
|---|
| 17893 | #define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6_MASK 0x00000001L |
|---|
| 17894 | //RCC_DEV0_EPF6_STRAP13 |
|---|
| 17895 | #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT 0x0 |
|---|
| 17896 | #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT 0x8 |
|---|
| 17897 | #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT 0x10 |
|---|
| 17898 | #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6_MASK 0x000000FFL |
|---|
| 17899 | #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6_MASK 0x0000FF00L |
|---|
| 17900 | #define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6_MASK 0x00FF0000L |
|---|
| 17901 | //RCC_DEV1_EPF0_STRAP0 |
|---|
| 17902 | #define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT 0x0 |
|---|
| 17903 | #define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT 0x10 |
|---|
| 17904 | #define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT 0x14 |
|---|
| 17905 | #define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT 0x1c |
|---|
| 17906 | #define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT 0x1d |
|---|
| 17907 | #define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT 0x1e |
|---|
| 17908 | #define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT 0x1f |
|---|
| 17909 | #define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0_MASK 0x0000FFFFL |
|---|
| 17910 | #define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0_MASK 0x000F0000L |
|---|
| 17911 | #define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0_MASK 0x00F00000L |
|---|
| 17912 | #define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0_MASK 0x10000000L |
|---|
| 17913 | #define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0_MASK 0x20000000L |
|---|
| 17914 | #define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0_MASK 0x40000000L |
|---|
| 17915 | #define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0_MASK 0x80000000L |
|---|
| 17916 | //RCC_DEV1_EPF0_STRAP2 |
|---|
| 17917 | #define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT 0x7 |
|---|
| 17918 | #define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT 0x8 |
|---|
| 17919 | #define RCC_DEV1_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F0__SHIFT 0x9 |
|---|
| 17920 | #define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT 0xe |
|---|
| 17921 | #define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT 0xf |
|---|
| 17922 | #define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT 0x10 |
|---|
| 17923 | #define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT 0x11 |
|---|
| 17924 | #define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT 0x14 |
|---|
| 17925 | #define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT 0x15 |
|---|
| 17926 | #define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT 0x17 |
|---|
| 17927 | #define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT 0x18 |
|---|
| 17928 | #define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EN_DEV1_F0__SHIFT 0x1c |
|---|
| 17929 | #define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0__SHIFT 0x1d |
|---|
| 17930 | #define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0__SHIFT 0x1e |
|---|
| 17931 | #define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0__SHIFT 0x1f |
|---|
| 17932 | #define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0_MASK 0x00000080L |
|---|
| 17933 | #define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0_MASK 0x00000100L |
|---|
| 17934 | #define RCC_DEV1_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F0_MASK 0x00003E00L |
|---|
| 17935 | #define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0_MASK 0x00004000L |
|---|
| 17936 | #define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0_MASK 0x00008000L |
|---|
| 17937 | #define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0_MASK 0x00010000L |
|---|
| 17938 | #define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0_MASK 0x00020000L |
|---|
| 17939 | #define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0_MASK 0x00100000L |
|---|
| 17940 | #define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0_MASK 0x00200000L |
|---|
| 17941 | #define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0_MASK 0x00800000L |
|---|
| 17942 | #define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0_MASK 0x07000000L |
|---|
| 17943 | #define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EN_DEV1_F0_MASK 0x10000000L |
|---|
| 17944 | #define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0_MASK 0x20000000L |
|---|
| 17945 | #define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0_MASK 0x40000000L |
|---|
| 17946 | #define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0_MASK 0x80000000L |
|---|
| 17947 | //RCC_DEV1_EPF0_STRAP3 |
|---|
| 17948 | #define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT 0x0 |
|---|
| 17949 | #define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT 0x1 |
|---|
| 17950 | #define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT 0x2 |
|---|
| 17951 | #define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT 0x12 |
|---|
| 17952 | #define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT 0x13 |
|---|
| 17953 | #define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT 0x14 |
|---|
| 17954 | #define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT 0x18 |
|---|
| 17955 | #define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__SHIFT 0x19 |
|---|
| 17956 | #define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT 0x1a |
|---|
| 17957 | #define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT 0x1b |
|---|
| 17958 | #define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0_MASK 0x00000001L |
|---|
| 17959 | #define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0_MASK 0x00000002L |
|---|
| 17960 | #define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0_MASK 0x0003FFFCL |
|---|
| 17961 | #define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0_MASK 0x00040000L |
|---|
| 17962 | #define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0_MASK 0x00080000L |
|---|
| 17963 | #define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0_MASK 0x00100000L |
|---|
| 17964 | #define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0_MASK 0x01000000L |
|---|
| 17965 | #define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0_MASK 0x02000000L |
|---|
| 17966 | #define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0_MASK 0x04000000L |
|---|
| 17967 | #define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0_MASK 0x08000000L |
|---|
| 17968 | //RCC_DEV1_EPF0_STRAP4 |
|---|
| 17969 | #define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT 0x14 |
|---|
| 17970 | #define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT 0x15 |
|---|
| 17971 | #define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT 0x16 |
|---|
| 17972 | #define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT 0x17 |
|---|
| 17973 | #define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT 0x1c |
|---|
| 17974 | #define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0_MASK 0x00100000L |
|---|
| 17975 | #define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0_MASK 0x00200000L |
|---|
| 17976 | #define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0_MASK 0x00400000L |
|---|
| 17977 | #define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0_MASK 0x0F800000L |
|---|
| 17978 | #define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0_MASK 0x70000000L |
|---|
| 17979 | //RCC_DEV1_EPF0_STRAP5 |
|---|
| 17980 | #define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT 0x0 |
|---|
| 17981 | #define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__SHIFT 0x18 |
|---|
| 17982 | #define RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV1_F0__SHIFT 0x19 |
|---|
| 17983 | #define RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV1_F0__SHIFT 0x1a |
|---|
| 17984 | #define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0_MASK 0x0000FFFFL |
|---|
| 17985 | #define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0_MASK 0x01000000L |
|---|
| 17986 | #define RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV1_F0_MASK 0x02000000L |
|---|
| 17987 | #define RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV1_F0_MASK 0x04000000L |
|---|
| 17988 | //RCC_DEV1_EPF0_STRAP6 |
|---|
| 17989 | #define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT 0x0 |
|---|
| 17990 | #define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0_MASK 0x00000001L |
|---|
| 17991 | //RCC_DEV1_EPF0_STRAP7 |
|---|
| 17992 | #define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV1_F0__SHIFT 0x14 |
|---|
| 17993 | #define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_EN_DEV1_F0__SHIFT 0x16 |
|---|
| 17994 | #define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV1_F0__SHIFT 0x17 |
|---|
| 17995 | #define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV1_F0__SHIFT 0x18 |
|---|
| 17996 | #define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV1_F0__SHIFT 0x1a |
|---|
| 17997 | #define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV1_F0_MASK 0x00300000L |
|---|
| 17998 | #define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_EN_DEV1_F0_MASK 0x00400000L |
|---|
| 17999 | #define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV1_F0_MASK 0x00800000L |
|---|
| 18000 | #define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV1_F0_MASK 0x03000000L |
|---|
| 18001 | #define RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV1_F0_MASK 0xFC000000L |
|---|
| 18002 | //RCC_DEV1_EPF0_STRAP13 |
|---|
| 18003 | #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT 0x0 |
|---|
| 18004 | #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT 0x8 |
|---|
| 18005 | #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT 0x10 |
|---|
| 18006 | #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0_MASK 0x000000FFL |
|---|
| 18007 | #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0_MASK 0x0000FF00L |
|---|
| 18008 | #define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0_MASK 0x00FF0000L |
|---|
| 18009 | //RCC_DEV2_EPF0_STRAP0 |
|---|
| 18010 | #define RCC_DEV2_EPF0_STRAP0__STRAP_DEVICE_ID_DEV2_F0__SHIFT 0x0 |
|---|
| 18011 | #define RCC_DEV2_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F0__SHIFT 0x10 |
|---|
| 18012 | #define RCC_DEV2_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV2_F0__SHIFT 0x14 |
|---|
| 18013 | #define RCC_DEV2_EPF0_STRAP0__STRAP_FUNC_EN_DEV2_F0__SHIFT 0x1c |
|---|
| 18014 | #define RCC_DEV2_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0__SHIFT 0x1d |
|---|
| 18015 | #define RCC_DEV2_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV2_F0__SHIFT 0x1e |
|---|
| 18016 | #define RCC_DEV2_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV2_F0__SHIFT 0x1f |
|---|
| 18017 | #define RCC_DEV2_EPF0_STRAP0__STRAP_DEVICE_ID_DEV2_F0_MASK 0x0000FFFFL |
|---|
| 18018 | #define RCC_DEV2_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F0_MASK 0x000F0000L |
|---|
| 18019 | #define RCC_DEV2_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV2_F0_MASK 0x00F00000L |
|---|
| 18020 | #define RCC_DEV2_EPF0_STRAP0__STRAP_FUNC_EN_DEV2_F0_MASK 0x10000000L |
|---|
| 18021 | #define RCC_DEV2_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0_MASK 0x20000000L |
|---|
| 18022 | #define RCC_DEV2_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV2_F0_MASK 0x40000000L |
|---|
| 18023 | #define RCC_DEV2_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV2_F0_MASK 0x80000000L |
|---|
| 18024 | //RCC_DEV2_EPF0_STRAP2 |
|---|
| 18025 | #define RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0__SHIFT 0x7 |
|---|
| 18026 | #define RCC_DEV2_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F0__SHIFT 0x8 |
|---|
| 18027 | #define RCC_DEV2_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F0__SHIFT 0x9 |
|---|
| 18028 | #define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0__SHIFT 0xe |
|---|
| 18029 | #define RCC_DEV2_EPF0_STRAP2__STRAP_ARI_EN_DEV2_F0__SHIFT 0xf |
|---|
| 18030 | #define RCC_DEV2_EPF0_STRAP2__STRAP_AER_EN_DEV2_F0__SHIFT 0x10 |
|---|
| 18031 | #define RCC_DEV2_EPF0_STRAP2__STRAP_ACS_EN_DEV2_F0__SHIFT 0x11 |
|---|
| 18032 | #define RCC_DEV2_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F0__SHIFT 0x14 |
|---|
| 18033 | #define RCC_DEV2_EPF0_STRAP2__STRAP_DPA_EN_DEV2_F0__SHIFT 0x15 |
|---|
| 18034 | #define RCC_DEV2_EPF0_STRAP2__STRAP_VC_EN_DEV2_F0__SHIFT 0x17 |
|---|
| 18035 | #define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F0__SHIFT 0x18 |
|---|
| 18036 | #define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EN_DEV2_F0__SHIFT 0x1c |
|---|
| 18037 | #define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0__SHIFT 0x1d |
|---|
| 18038 | #define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0__SHIFT 0x1e |
|---|
| 18039 | #define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0__SHIFT 0x1f |
|---|
| 18040 | #define RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK 0x00000080L |
|---|
| 18041 | #define RCC_DEV2_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F0_MASK 0x00000100L |
|---|
| 18042 | #define RCC_DEV2_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F0_MASK 0x00003E00L |
|---|
| 18043 | #define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0_MASK 0x00004000L |
|---|
| 18044 | #define RCC_DEV2_EPF0_STRAP2__STRAP_ARI_EN_DEV2_F0_MASK 0x00008000L |
|---|
| 18045 | #define RCC_DEV2_EPF0_STRAP2__STRAP_AER_EN_DEV2_F0_MASK 0x00010000L |
|---|
| 18046 | #define RCC_DEV2_EPF0_STRAP2__STRAP_ACS_EN_DEV2_F0_MASK 0x00020000L |
|---|
| 18047 | #define RCC_DEV2_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F0_MASK 0x00100000L |
|---|
| 18048 | #define RCC_DEV2_EPF0_STRAP2__STRAP_DPA_EN_DEV2_F0_MASK 0x00200000L |
|---|
| 18049 | #define RCC_DEV2_EPF0_STRAP2__STRAP_VC_EN_DEV2_F0_MASK 0x00800000L |
|---|
| 18050 | #define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F0_MASK 0x07000000L |
|---|
| 18051 | #define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EN_DEV2_F0_MASK 0x10000000L |
|---|
| 18052 | #define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0_MASK 0x20000000L |
|---|
| 18053 | #define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0_MASK 0x40000000L |
|---|
| 18054 | #define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0_MASK 0x80000000L |
|---|
| 18055 | //RCC_DEV2_EPF0_STRAP3 |
|---|
| 18056 | #define RCC_DEV2_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0__SHIFT 0x0 |
|---|
| 18057 | #define RCC_DEV2_EPF0_STRAP3__STRAP_PWR_EN_DEV2_F0__SHIFT 0x1 |
|---|
| 18058 | #define RCC_DEV2_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV2_F0__SHIFT 0x2 |
|---|
| 18059 | #define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_EN_DEV2_F0__SHIFT 0x12 |
|---|
| 18060 | #define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F0__SHIFT 0x13 |
|---|
| 18061 | #define RCC_DEV2_EPF0_STRAP3__STRAP_MSIX_EN_DEV2_F0__SHIFT 0x14 |
|---|
| 18062 | #define RCC_DEV2_EPF0_STRAP3__STRAP_PMC_DSI_DEV2_F0__SHIFT 0x18 |
|---|
| 18063 | #define RCC_DEV2_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV2_F0__SHIFT 0x19 |
|---|
| 18064 | #define RCC_DEV2_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0__SHIFT 0x1a |
|---|
| 18065 | #define RCC_DEV2_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0__SHIFT 0x1b |
|---|
| 18066 | #define RCC_DEV2_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0_MASK 0x00000001L |
|---|
| 18067 | #define RCC_DEV2_EPF0_STRAP3__STRAP_PWR_EN_DEV2_F0_MASK 0x00000002L |
|---|
| 18068 | #define RCC_DEV2_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV2_F0_MASK 0x0003FFFCL |
|---|
| 18069 | #define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_EN_DEV2_F0_MASK 0x00040000L |
|---|
| 18070 | #define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F0_MASK 0x00080000L |
|---|
| 18071 | #define RCC_DEV2_EPF0_STRAP3__STRAP_MSIX_EN_DEV2_F0_MASK 0x00100000L |
|---|
| 18072 | #define RCC_DEV2_EPF0_STRAP3__STRAP_PMC_DSI_DEV2_F0_MASK 0x01000000L |
|---|
| 18073 | #define RCC_DEV2_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV2_F0_MASK 0x02000000L |
|---|
| 18074 | #define RCC_DEV2_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0_MASK 0x04000000L |
|---|
| 18075 | #define RCC_DEV2_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0_MASK 0x08000000L |
|---|
| 18076 | //RCC_DEV2_EPF0_STRAP4 |
|---|
| 18077 | #define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F0__SHIFT 0x14 |
|---|
| 18078 | #define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV2_F0__SHIFT 0x15 |
|---|
| 18079 | #define RCC_DEV2_EPF0_STRAP4__STRAP_FLR_EN_DEV2_F0__SHIFT 0x16 |
|---|
| 18080 | #define RCC_DEV2_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV2_F0__SHIFT 0x17 |
|---|
| 18081 | #define RCC_DEV2_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F0__SHIFT 0x1c |
|---|
| 18082 | #define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F0_MASK 0x00100000L |
|---|
| 18083 | #define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV2_F0_MASK 0x00200000L |
|---|
| 18084 | #define RCC_DEV2_EPF0_STRAP4__STRAP_FLR_EN_DEV2_F0_MASK 0x00400000L |
|---|
| 18085 | #define RCC_DEV2_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV2_F0_MASK 0x0F800000L |
|---|
| 18086 | #define RCC_DEV2_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F0_MASK 0x70000000L |
|---|
| 18087 | //RCC_DEV2_EPF0_STRAP5 |
|---|
| 18088 | #define RCC_DEV2_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F0__SHIFT 0x0 |
|---|
| 18089 | #define RCC_DEV2_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV2_F0__SHIFT 0x18 |
|---|
| 18090 | #define RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV2_F0__SHIFT 0x19 |
|---|
| 18091 | #define RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV2_F0__SHIFT 0x1a |
|---|
| 18092 | #define RCC_DEV2_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F0_MASK 0x0000FFFFL |
|---|
| 18093 | #define RCC_DEV2_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV2_F0_MASK 0x01000000L |
|---|
| 18094 | #define RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV2_F0_MASK 0x02000000L |
|---|
| 18095 | #define RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV2_F0_MASK 0x04000000L |
|---|
| 18096 | //RCC_DEV2_EPF0_STRAP6 |
|---|
| 18097 | #define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_EN_DEV2_F0__SHIFT 0x0 |
|---|
| 18098 | #define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_EN_DEV2_F0_MASK 0x00000001L |
|---|
| 18099 | //RCC_DEV2_EPF0_STRAP7 |
|---|
| 18100 | #define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV2_F0__SHIFT 0x14 |
|---|
| 18101 | #define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_EN_DEV2_F0__SHIFT 0x16 |
|---|
| 18102 | #define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV2_F0__SHIFT 0x17 |
|---|
| 18103 | #define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV2_F0__SHIFT 0x18 |
|---|
| 18104 | #define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV2_F0__SHIFT 0x1a |
|---|
| 18105 | #define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV2_F0_MASK 0x00300000L |
|---|
| 18106 | #define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_EN_DEV2_F0_MASK 0x00400000L |
|---|
| 18107 | #define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV2_F0_MASK 0x00800000L |
|---|
| 18108 | #define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV2_F0_MASK 0x03000000L |
|---|
| 18109 | #define RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV2_F0_MASK 0xFC000000L |
|---|
| 18110 | //RCC_DEV2_EPF0_STRAP13 |
|---|
| 18111 | #define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F0__SHIFT 0x0 |
|---|
| 18112 | #define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F0__SHIFT 0x8 |
|---|
| 18113 | #define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F0__SHIFT 0x10 |
|---|
| 18114 | #define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F0_MASK 0x000000FFL |
|---|
| 18115 | #define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F0_MASK 0x0000FF00L |
|---|
| 18116 | #define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F0_MASK 0x00FF0000L |
|---|
| 18117 | |
|---|
| 18118 | |
|---|
| 18119 | // addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC |
|---|
| 18120 | //RCC_DEV0_1_RCC_VDM_SUPPORT |
|---|
| 18121 | #define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 |
|---|
| 18122 | #define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 |
|---|
| 18123 | #define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 |
|---|
| 18124 | #define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 |
|---|
| 18125 | #define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 |
|---|
| 18126 | #define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L |
|---|
| 18127 | #define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L |
|---|
| 18128 | #define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L |
|---|
| 18129 | #define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L |
|---|
| 18130 | #define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L |
|---|
| 18131 | //RCC_DEV0_1_RCC_BUS_CNTL |
|---|
| 18132 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 |
|---|
| 18133 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 |
|---|
| 18134 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 |
|---|
| 18135 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 |
|---|
| 18136 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 |
|---|
| 18137 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 |
|---|
| 18138 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 |
|---|
| 18139 | #define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc |
|---|
| 18140 | #define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd |
|---|
| 18141 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 |
|---|
| 18142 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 |
|---|
| 18143 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 |
|---|
| 18144 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 |
|---|
| 18145 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 |
|---|
| 18146 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 |
|---|
| 18147 | #define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 |
|---|
| 18148 | #define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 |
|---|
| 18149 | #define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c |
|---|
| 18150 | #define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d |
|---|
| 18151 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L |
|---|
| 18152 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L |
|---|
| 18153 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L |
|---|
| 18154 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L |
|---|
| 18155 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L |
|---|
| 18156 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L |
|---|
| 18157 | #define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L |
|---|
| 18158 | #define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L |
|---|
| 18159 | #define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L |
|---|
| 18160 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L |
|---|
| 18161 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L |
|---|
| 18162 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L |
|---|
| 18163 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L |
|---|
| 18164 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L |
|---|
| 18165 | #define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L |
|---|
| 18166 | #define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L |
|---|
| 18167 | #define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L |
|---|
| 18168 | #define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L |
|---|
| 18169 | #define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L |
|---|
| 18170 | //RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC |
|---|
| 18171 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 |
|---|
| 18172 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 |
|---|
| 18173 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 |
|---|
| 18174 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 |
|---|
| 18175 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 |
|---|
| 18176 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 |
|---|
| 18177 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa |
|---|
| 18178 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb |
|---|
| 18179 | #define 0xc |
|---|
| 18180 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd |
|---|
| 18181 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe |
|---|
| 18182 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf |
|---|
| 18183 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 |
|---|
| 18184 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 |
|---|
| 18185 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 |
|---|
| 18186 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 |
|---|
| 18187 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x00000010L |
|---|
| 18188 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x00000020L |
|---|
| 18189 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x00000040L |
|---|
| 18190 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L |
|---|
| 18191 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L |
|---|
| 18192 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L |
|---|
| 18193 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L |
|---|
| 18194 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L |
|---|
| 18195 | #define 0x00001000L |
|---|
| 18196 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L |
|---|
| 18197 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L |
|---|
| 18198 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L |
|---|
| 18199 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L |
|---|
| 18200 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L |
|---|
| 18201 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L |
|---|
| 18202 | #define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L |
|---|
| 18203 | //RCC_DEV0_1_RCC_DEV0_LINK_CNTL |
|---|
| 18204 | #define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 |
|---|
| 18205 | #define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 |
|---|
| 18206 | #define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L |
|---|
| 18207 | #define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L |
|---|
| 18208 | //RCC_DEV0_1_RCC_CMN_LINK_CNTL |
|---|
| 18209 | #define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 |
|---|
| 18210 | #define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 |
|---|
| 18211 | #define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 |
|---|
| 18212 | #define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 |
|---|
| 18213 | #define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 |
|---|
| 18214 | #define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L |
|---|
| 18215 | #define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L |
|---|
| 18216 | #define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L |
|---|
| 18217 | #define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L |
|---|
| 18218 | #define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L |
|---|
| 18219 | //RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE |
|---|
| 18220 | #define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 |
|---|
| 18221 | #define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 |
|---|
| 18222 | #define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL |
|---|
| 18223 | #define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L |
|---|
| 18224 | //RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL |
|---|
| 18225 | #define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 18226 | #define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 18227 | //RCC_DEV0_1_RCC_MH_ARB_CNTL |
|---|
| 18228 | #define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 |
|---|
| 18229 | #define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 |
|---|
| 18230 | #define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L |
|---|
| 18231 | #define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL |
|---|
| 18232 | //RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 |
|---|
| 18233 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 |
|---|
| 18234 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 |
|---|
| 18235 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 |
|---|
| 18236 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 |
|---|
| 18237 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 |
|---|
| 18238 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 |
|---|
| 18239 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb |
|---|
| 18240 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 |
|---|
| 18241 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 |
|---|
| 18242 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L |
|---|
| 18243 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L |
|---|
| 18244 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L |
|---|
| 18245 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L |
|---|
| 18246 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L |
|---|
| 18247 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L |
|---|
| 18248 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L |
|---|
| 18249 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L |
|---|
| 18250 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L |
|---|
| 18251 | //RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 |
|---|
| 18252 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 |
|---|
| 18253 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 |
|---|
| 18254 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc |
|---|
| 18255 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 |
|---|
| 18256 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL |
|---|
| 18257 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L |
|---|
| 18258 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L |
|---|
| 18259 | #define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L |
|---|
| 18260 | |
|---|
| 18261 | |
|---|
| 18262 | // addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC |
|---|
| 18263 | //RCC_EP_DEV0_1_EP_PCIE_SCRATCH |
|---|
| 18264 | #define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
|---|
| 18265 | #define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 18266 | //RCC_EP_DEV0_1_EP_PCIE_CNTL |
|---|
| 18267 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
|---|
| 18268 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
|---|
| 18269 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
|---|
| 18270 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
|---|
| 18271 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
|---|
| 18272 | #define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
|---|
| 18273 | //RCC_EP_DEV0_1_EP_PCIE_INT_CNTL |
|---|
| 18274 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 |
|---|
| 18275 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 |
|---|
| 18276 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 |
|---|
| 18277 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 |
|---|
| 18278 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 |
|---|
| 18279 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 |
|---|
| 18280 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L |
|---|
| 18281 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L |
|---|
| 18282 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L |
|---|
| 18283 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L |
|---|
| 18284 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L |
|---|
| 18285 | #define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L |
|---|
| 18286 | //RCC_EP_DEV0_1_EP_PCIE_INT_STATUS |
|---|
| 18287 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 |
|---|
| 18288 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 |
|---|
| 18289 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 |
|---|
| 18290 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 |
|---|
| 18291 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 |
|---|
| 18292 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 |
|---|
| 18293 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L |
|---|
| 18294 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L |
|---|
| 18295 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L |
|---|
| 18296 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L |
|---|
| 18297 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L |
|---|
| 18298 | #define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L |
|---|
| 18299 | //RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 |
|---|
| 18300 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
|---|
| 18301 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
|---|
| 18302 | //RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL |
|---|
| 18303 | #define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
|---|
| 18304 | #define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
|---|
| 18305 | //RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL |
|---|
| 18306 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
|---|
| 18307 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
|---|
| 18308 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
|---|
| 18309 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
|---|
| 18310 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
|---|
| 18311 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
|---|
| 18312 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
|---|
| 18313 | #define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
|---|
| 18314 | //RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL |
|---|
| 18315 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 |
|---|
| 18316 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 |
|---|
| 18317 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 |
|---|
| 18318 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 |
|---|
| 18319 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa |
|---|
| 18320 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd |
|---|
| 18321 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe |
|---|
| 18322 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf |
|---|
| 18323 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 |
|---|
| 18324 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 |
|---|
| 18325 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L |
|---|
| 18326 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L |
|---|
| 18327 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L |
|---|
| 18328 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L |
|---|
| 18329 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L |
|---|
| 18330 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L |
|---|
| 18331 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L |
|---|
| 18332 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L |
|---|
| 18333 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L |
|---|
| 18334 | #define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L |
|---|
| 18335 | //RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC |
|---|
| 18336 | #define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d |
|---|
| 18337 | #define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L |
|---|
| 18338 | //RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 |
|---|
| 18339 | #define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 |
|---|
| 18340 | #define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L |
|---|
| 18341 | //RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP |
|---|
| 18342 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 18343 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 18344 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 18345 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 18346 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 18347 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 18348 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 18349 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 18350 | //RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR |
|---|
| 18351 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 18352 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
|---|
| 18353 | //RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL |
|---|
| 18354 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 18355 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 |
|---|
| 18356 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 18357 | #define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L |
|---|
| 18358 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 18359 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 18360 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 18361 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 18362 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 18363 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 18364 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 18365 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 18366 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 18367 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 18368 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 18369 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 18370 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 18371 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 18372 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 18373 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 18374 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 18375 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 18376 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 18377 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 18378 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 18379 | //RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 18380 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 18381 | #define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 18382 | //RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL |
|---|
| 18383 | #define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 |
|---|
| 18384 | #define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL |
|---|
| 18385 | //RCC_EP_DEV0_1_EP_PCIEP_RESERVED |
|---|
| 18386 | #define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 |
|---|
| 18387 | #define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 18388 | //RCC_EP_DEV0_1_EP_PCIE_TX_CNTL |
|---|
| 18389 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
|---|
| 18390 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
|---|
| 18391 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
|---|
| 18392 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
|---|
| 18393 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
|---|
| 18394 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
|---|
| 18395 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
|---|
| 18396 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
|---|
| 18397 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
|---|
| 18398 | #define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
|---|
| 18399 | //RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID |
|---|
| 18400 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
|---|
| 18401 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
|---|
| 18402 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
|---|
| 18403 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
|---|
| 18404 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
|---|
| 18405 | #define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
|---|
| 18406 | //RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL |
|---|
| 18407 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
|---|
| 18408 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
|---|
| 18409 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
|---|
| 18410 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
|---|
| 18411 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 |
|---|
| 18412 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 |
|---|
| 18413 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a |
|---|
| 18414 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b |
|---|
| 18415 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c |
|---|
| 18416 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d |
|---|
| 18417 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e |
|---|
| 18418 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f |
|---|
| 18419 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
|---|
| 18420 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
|---|
| 18421 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
|---|
| 18422 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
|---|
| 18423 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L |
|---|
| 18424 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L |
|---|
| 18425 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L |
|---|
| 18426 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L |
|---|
| 18427 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L |
|---|
| 18428 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L |
|---|
| 18429 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L |
|---|
| 18430 | #define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L |
|---|
| 18431 | //RCC_EP_DEV0_1_EP_PCIE_RX_CNTL |
|---|
| 18432 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
|---|
| 18433 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
|---|
| 18434 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
|---|
| 18435 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
|---|
| 18436 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
|---|
| 18437 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
|---|
| 18438 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
|---|
| 18439 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
|---|
| 18440 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
|---|
| 18441 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
|---|
| 18442 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
|---|
| 18443 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
|---|
| 18444 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
|---|
| 18445 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
|---|
| 18446 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
|---|
| 18447 | #define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
|---|
| 18448 | //RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL |
|---|
| 18449 | #define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
|---|
| 18450 | #define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
|---|
| 18451 | #define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 |
|---|
| 18452 | #define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
|---|
| 18453 | #define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
|---|
| 18454 | #define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L |
|---|
| 18455 | |
|---|
| 18456 | |
|---|
| 18457 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC |
|---|
| 18458 | //RCC_DWN_DEV0_1_DN_PCIE_RESERVED |
|---|
| 18459 | #define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 |
|---|
| 18460 | #define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 18461 | //RCC_DWN_DEV0_1_DN_PCIE_SCRATCH |
|---|
| 18462 | #define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
|---|
| 18463 | #define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 18464 | //RCC_DWN_DEV0_1_DN_PCIE_CNTL |
|---|
| 18465 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
|---|
| 18466 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 |
|---|
| 18467 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
|---|
| 18468 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
|---|
| 18469 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L |
|---|
| 18470 | #define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
|---|
| 18471 | //RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL |
|---|
| 18472 | #define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
|---|
| 18473 | #define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
|---|
| 18474 | //RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 |
|---|
| 18475 | #define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
|---|
| 18476 | #define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
|---|
| 18477 | //RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL |
|---|
| 18478 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
|---|
| 18479 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 |
|---|
| 18480 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
|---|
| 18481 | #define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L |
|---|
| 18482 | //RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL |
|---|
| 18483 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
|---|
| 18484 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
|---|
| 18485 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
|---|
| 18486 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 |
|---|
| 18487 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
|---|
| 18488 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
|---|
| 18489 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
|---|
| 18490 | #define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L |
|---|
| 18491 | //RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 |
|---|
| 18492 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 |
|---|
| 18493 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 |
|---|
| 18494 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 |
|---|
| 18495 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L |
|---|
| 18496 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L |
|---|
| 18497 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L |
|---|
| 18498 | //RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC |
|---|
| 18499 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 |
|---|
| 18500 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d |
|---|
| 18501 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L |
|---|
| 18502 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L |
|---|
| 18503 | //RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 |
|---|
| 18504 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 |
|---|
| 18505 | #define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L |
|---|
| 18506 | |
|---|
| 18507 | |
|---|
| 18508 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC |
|---|
| 18509 | //RCC_DWNP_DEV0_1_PCIE_ERR_CNTL |
|---|
| 18510 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
|---|
| 18511 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
|---|
| 18512 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
|---|
| 18513 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
|---|
| 18514 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
|---|
| 18515 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
|---|
| 18516 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
|---|
| 18517 | #define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
|---|
| 18518 | //RCC_DWNP_DEV0_1_PCIE_RX_CNTL |
|---|
| 18519 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
|---|
| 18520 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 |
|---|
| 18521 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
|---|
| 18522 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 |
|---|
| 18523 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
|---|
| 18524 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
|---|
| 18525 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L |
|---|
| 18526 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
|---|
| 18527 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L |
|---|
| 18528 | #define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
|---|
| 18529 | //RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL |
|---|
| 18530 | #define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
|---|
| 18531 | #define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
|---|
| 18532 | #define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 |
|---|
| 18533 | #define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
|---|
| 18534 | #define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
|---|
| 18535 | #define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L |
|---|
| 18536 | //RCC_DWNP_DEV0_1_PCIE_LC_CNTL2 |
|---|
| 18537 | #define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
|---|
| 18538 | #define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
|---|
| 18539 | //RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC |
|---|
| 18540 | #define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa |
|---|
| 18541 | #define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L |
|---|
| 18542 | //RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP |
|---|
| 18543 | #define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 |
|---|
| 18544 | #define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL |
|---|
| 18545 | |
|---|
| 18546 | |
|---|
| 18547 | // addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk |
|---|
| 18548 | //MISC_SCRATCH |
|---|
| 18549 | #define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 |
|---|
| 18550 | #define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL |
|---|
| 18551 | //INTR_LINE_POLARITY |
|---|
| 18552 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 |
|---|
| 18553 | #define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL |
|---|
| 18554 | //INTR_LINE_ENABLE |
|---|
| 18555 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 |
|---|
| 18556 | #define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL |
|---|
| 18557 | //OUTSTANDING_VC_ALLOC |
|---|
| 18558 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 |
|---|
| 18559 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 |
|---|
| 18560 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 |
|---|
| 18561 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 |
|---|
| 18562 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 |
|---|
| 18563 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa |
|---|
| 18564 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc |
|---|
| 18565 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe |
|---|
| 18566 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 |
|---|
| 18567 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 |
|---|
| 18568 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a |
|---|
| 18569 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c |
|---|
| 18570 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L |
|---|
| 18571 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL |
|---|
| 18572 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L |
|---|
| 18573 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L |
|---|
| 18574 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L |
|---|
| 18575 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L |
|---|
| 18576 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L |
|---|
| 18577 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L |
|---|
| 18578 | #define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L |
|---|
| 18579 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L |
|---|
| 18580 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L |
|---|
| 18581 | #define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L |
|---|
| 18582 | //BIFC_MISC_CTRL0 |
|---|
| 18583 | #define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 |
|---|
| 18584 | #define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 |
|---|
| 18585 | #define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT 0x4 |
|---|
| 18586 | #define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 |
|---|
| 18587 | #define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9 |
|---|
| 18588 | #define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa |
|---|
| 18589 | #define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0xb |
|---|
| 18590 | #define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0xc |
|---|
| 18591 | #define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT 0xd |
|---|
| 18592 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 |
|---|
| 18593 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 |
|---|
| 18594 | #define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12 |
|---|
| 18595 | #define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13 |
|---|
| 18596 | #define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14 |
|---|
| 18597 | #define BIFC_MISC_CTRL0__VC5_DMA_IOCFG_DIS__SHIFT 0x17 |
|---|
| 18598 | #define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 |
|---|
| 18599 | #define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19 |
|---|
| 18600 | #define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a |
|---|
| 18601 | #define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b |
|---|
| 18602 | #define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c |
|---|
| 18603 | #define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f |
|---|
| 18604 | #define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L |
|---|
| 18605 | #define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L |
|---|
| 18606 | #define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK 0x000000F0L |
|---|
| 18607 | #define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L |
|---|
| 18608 | #define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK 0x00000200L |
|---|
| 18609 | #define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L |
|---|
| 18610 | #define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x00000800L |
|---|
| 18611 | #define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x00001000L |
|---|
| 18612 | #define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK 0x00002000L |
|---|
| 18613 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L |
|---|
| 18614 | #define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L |
|---|
| 18615 | #define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L |
|---|
| 18616 | #define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L |
|---|
| 18617 | #define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L |
|---|
| 18618 | #define BIFC_MISC_CTRL0__VC5_DMA_IOCFG_DIS_MASK 0x00800000L |
|---|
| 18619 | #define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L |
|---|
| 18620 | #define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK 0x02000000L |
|---|
| 18621 | #define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L |
|---|
| 18622 | #define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L |
|---|
| 18623 | #define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L |
|---|
| 18624 | #define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L |
|---|
| 18625 | //BIFC_MISC_CTRL1 |
|---|
| 18626 | #define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 |
|---|
| 18627 | #define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 |
|---|
| 18628 | #define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 |
|---|
| 18629 | #define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 |
|---|
| 18630 | #define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 |
|---|
| 18631 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 |
|---|
| 18632 | #define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 |
|---|
| 18633 | #define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x7 |
|---|
| 18634 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 |
|---|
| 18635 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa |
|---|
| 18636 | #define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc |
|---|
| 18637 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd |
|---|
| 18638 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe |
|---|
| 18639 | #define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf |
|---|
| 18640 | #define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 |
|---|
| 18641 | #define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 |
|---|
| 18642 | #define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 |
|---|
| 18643 | #define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 |
|---|
| 18644 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14 |
|---|
| 18645 | #define BIFC_MISC_CTRL1__GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x15 |
|---|
| 18646 | #define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18 |
|---|
| 18647 | #define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19 |
|---|
| 18648 | #define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a |
|---|
| 18649 | #define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b |
|---|
| 18650 | #define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c |
|---|
| 18651 | #define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d |
|---|
| 18652 | #define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x1e |
|---|
| 18653 | #define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L |
|---|
| 18654 | #define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L |
|---|
| 18655 | #define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L |
|---|
| 18656 | #define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L |
|---|
| 18657 | #define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L |
|---|
| 18658 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L |
|---|
| 18659 | #define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L |
|---|
| 18660 | #define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x00000080L |
|---|
| 18661 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L |
|---|
| 18662 | #define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L |
|---|
| 18663 | #define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L |
|---|
| 18664 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L |
|---|
| 18665 | #define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L |
|---|
| 18666 | #define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L |
|---|
| 18667 | #define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L |
|---|
| 18668 | #define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L |
|---|
| 18669 | #define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L |
|---|
| 18670 | #define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L |
|---|
| 18671 | #define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L |
|---|
| 18672 | #define BIFC_MISC_CTRL1__GSI_SMN_POSTWR_MULTI_EN_MASK 0x00200000L |
|---|
| 18673 | #define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L |
|---|
| 18674 | #define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L |
|---|
| 18675 | #define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L |
|---|
| 18676 | #define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L |
|---|
| 18677 | #define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L |
|---|
| 18678 | #define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L |
|---|
| 18679 | #define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0xC0000000L |
|---|
| 18680 | //BIFC_BME_ERR_LOG |
|---|
| 18681 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 |
|---|
| 18682 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 |
|---|
| 18683 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2 |
|---|
| 18684 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3 |
|---|
| 18685 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4 |
|---|
| 18686 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5 |
|---|
| 18687 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6 |
|---|
| 18688 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7 |
|---|
| 18689 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 |
|---|
| 18690 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 |
|---|
| 18691 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12 |
|---|
| 18692 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13 |
|---|
| 18693 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14 |
|---|
| 18694 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15 |
|---|
| 18695 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16 |
|---|
| 18696 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17 |
|---|
| 18697 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L |
|---|
| 18698 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L |
|---|
| 18699 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2_MASK 0x00000004L |
|---|
| 18700 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3_MASK 0x00000008L |
|---|
| 18701 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4_MASK 0x00000010L |
|---|
| 18702 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5_MASK 0x00000020L |
|---|
| 18703 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6_MASK 0x00000040L |
|---|
| 18704 | #define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7_MASK 0x00000080L |
|---|
| 18705 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L |
|---|
| 18706 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L |
|---|
| 18707 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK 0x00040000L |
|---|
| 18708 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK 0x00080000L |
|---|
| 18709 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK 0x00100000L |
|---|
| 18710 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK 0x00200000L |
|---|
| 18711 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK 0x00400000L |
|---|
| 18712 | #define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7_MASK 0x00800000L |
|---|
| 18713 | //BIFC_RCCBIH_BME_ERR_LOG0 |
|---|
| 18714 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 |
|---|
| 18715 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 |
|---|
| 18716 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2 |
|---|
| 18717 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3 |
|---|
| 18718 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4 |
|---|
| 18719 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5 |
|---|
| 18720 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6 |
|---|
| 18721 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7 |
|---|
| 18722 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 |
|---|
| 18723 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 |
|---|
| 18724 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12 |
|---|
| 18725 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13 |
|---|
| 18726 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14 |
|---|
| 18727 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15 |
|---|
| 18728 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16 |
|---|
| 18729 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17 |
|---|
| 18730 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L |
|---|
| 18731 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L |
|---|
| 18732 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L |
|---|
| 18733 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L |
|---|
| 18734 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00000010L |
|---|
| 18735 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00000020L |
|---|
| 18736 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00000040L |
|---|
| 18737 | #define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00000080L |
|---|
| 18738 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L |
|---|
| 18739 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L |
|---|
| 18740 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L |
|---|
| 18741 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L |
|---|
| 18742 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00100000L |
|---|
| 18743 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00200000L |
|---|
| 18744 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00400000L |
|---|
| 18745 | #define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00800000L |
|---|
| 18746 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 |
|---|
| 18747 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 |
|---|
| 18748 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 |
|---|
| 18749 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT 0x4 |
|---|
| 18750 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 |
|---|
| 18751 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 |
|---|
| 18752 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa |
|---|
| 18753 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc |
|---|
| 18754 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT 0xe |
|---|
| 18755 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 |
|---|
| 18756 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 |
|---|
| 18757 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT 0x14 |
|---|
| 18758 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 |
|---|
| 18759 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 |
|---|
| 18760 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a |
|---|
| 18761 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c |
|---|
| 18762 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT 0x1e |
|---|
| 18763 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L |
|---|
| 18764 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL |
|---|
| 18765 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK 0x00000030L |
|---|
| 18766 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L |
|---|
| 18767 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L |
|---|
| 18768 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L |
|---|
| 18769 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L |
|---|
| 18770 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK 0x0000C000L |
|---|
| 18771 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L |
|---|
| 18772 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L |
|---|
| 18773 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK 0x00300000L |
|---|
| 18774 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L |
|---|
| 18775 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L |
|---|
| 18776 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L |
|---|
| 18777 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L |
|---|
| 18778 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK 0xC0000000L |
|---|
| 18779 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 |
|---|
| 18780 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 |
|---|
| 18781 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 |
|---|
| 18782 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT 0x4 |
|---|
| 18783 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 |
|---|
| 18784 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 |
|---|
| 18785 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa |
|---|
| 18786 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc |
|---|
| 18787 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT 0xe |
|---|
| 18788 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 |
|---|
| 18789 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 |
|---|
| 18790 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT 0x14 |
|---|
| 18791 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 |
|---|
| 18792 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 |
|---|
| 18793 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a |
|---|
| 18794 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c |
|---|
| 18795 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT 0x1e |
|---|
| 18796 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L |
|---|
| 18797 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL |
|---|
| 18798 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK 0x00000030L |
|---|
| 18799 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L |
|---|
| 18800 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L |
|---|
| 18801 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L |
|---|
| 18802 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L |
|---|
| 18803 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK 0x0000C000L |
|---|
| 18804 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L |
|---|
| 18805 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L |
|---|
| 18806 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK 0x00300000L |
|---|
| 18807 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L |
|---|
| 18808 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L |
|---|
| 18809 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L |
|---|
| 18810 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L |
|---|
| 18811 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK 0xC0000000L |
|---|
| 18812 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 |
|---|
| 18813 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 |
|---|
| 18814 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 |
|---|
| 18815 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT 0x4 |
|---|
| 18816 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 |
|---|
| 18817 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 |
|---|
| 18818 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa |
|---|
| 18819 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc |
|---|
| 18820 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT 0xe |
|---|
| 18821 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 |
|---|
| 18822 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 |
|---|
| 18823 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT 0x14 |
|---|
| 18824 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 |
|---|
| 18825 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 |
|---|
| 18826 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a |
|---|
| 18827 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c |
|---|
| 18828 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT 0x1e |
|---|
| 18829 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L |
|---|
| 18830 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL |
|---|
| 18831 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK 0x00000030L |
|---|
| 18832 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L |
|---|
| 18833 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L |
|---|
| 18834 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L |
|---|
| 18835 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L |
|---|
| 18836 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK 0x0000C000L |
|---|
| 18837 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L |
|---|
| 18838 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L |
|---|
| 18839 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK 0x00300000L |
|---|
| 18840 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L |
|---|
| 18841 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L |
|---|
| 18842 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L |
|---|
| 18843 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L |
|---|
| 18844 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK 0xC0000000L |
|---|
| 18845 | //BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 |
|---|
| 18846 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 |
|---|
| 18847 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 |
|---|
| 18848 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT 0x4 |
|---|
| 18849 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 |
|---|
| 18850 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 |
|---|
| 18851 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa |
|---|
| 18852 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc |
|---|
| 18853 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT 0xe |
|---|
| 18854 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 |
|---|
| 18855 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 |
|---|
| 18856 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT 0x14 |
|---|
| 18857 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 |
|---|
| 18858 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 |
|---|
| 18859 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a |
|---|
| 18860 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c |
|---|
| 18861 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT 0x1e |
|---|
| 18862 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L |
|---|
| 18863 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL |
|---|
| 18864 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK 0x00000030L |
|---|
| 18865 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L |
|---|
| 18866 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L |
|---|
| 18867 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L |
|---|
| 18868 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L |
|---|
| 18869 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK 0x0000C000L |
|---|
| 18870 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L |
|---|
| 18871 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L |
|---|
| 18872 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK 0x00300000L |
|---|
| 18873 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L |
|---|
| 18874 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L |
|---|
| 18875 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L |
|---|
| 18876 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L |
|---|
| 18877 | #define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK 0xC0000000L |
|---|
| 18878 | //BIFC_DMA_ATTR_CNTL2_DEV0 |
|---|
| 18879 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT 0x0 |
|---|
| 18880 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT 0x4 |
|---|
| 18881 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT 0x8 |
|---|
| 18882 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT 0xc |
|---|
| 18883 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT 0x10 |
|---|
| 18884 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT 0x14 |
|---|
| 18885 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT 0x18 |
|---|
| 18886 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT 0x1c |
|---|
| 18887 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK 0x00000001L |
|---|
| 18888 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK 0x00000010L |
|---|
| 18889 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK 0x00000100L |
|---|
| 18890 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK 0x00001000L |
|---|
| 18891 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK 0x00010000L |
|---|
| 18892 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK 0x00100000L |
|---|
| 18893 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK 0x01000000L |
|---|
| 18894 | #define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK 0x10000000L |
|---|
| 18895 | //BME_DUMMY_CNTL_0 |
|---|
| 18896 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 |
|---|
| 18897 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 |
|---|
| 18898 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 |
|---|
| 18899 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 |
|---|
| 18900 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 |
|---|
| 18901 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa |
|---|
| 18902 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc |
|---|
| 18903 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe |
|---|
| 18904 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L |
|---|
| 18905 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL |
|---|
| 18906 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L |
|---|
| 18907 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L |
|---|
| 18908 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L |
|---|
| 18909 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L |
|---|
| 18910 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L |
|---|
| 18911 | #define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L |
|---|
| 18912 | //BIFC_THT_CNTL |
|---|
| 18913 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 |
|---|
| 18914 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 |
|---|
| 18915 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 |
|---|
| 18916 | #define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x10 |
|---|
| 18917 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL |
|---|
| 18918 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L |
|---|
| 18919 | #define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L |
|---|
| 18920 | #define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x00010000L |
|---|
| 18921 | //BIFC_HSTARB_CNTL |
|---|
| 18922 | #define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 |
|---|
| 18923 | #define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L |
|---|
| 18924 | //BIFC_GSI_CNTL |
|---|
| 18925 | #define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 |
|---|
| 18926 | #define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 |
|---|
| 18927 | #define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 |
|---|
| 18928 | #define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 |
|---|
| 18929 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 |
|---|
| 18930 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 |
|---|
| 18931 | #define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9 |
|---|
| 18932 | #define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa |
|---|
| 18933 | #define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc |
|---|
| 18934 | #define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT 0xe |
|---|
| 18935 | #define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L |
|---|
| 18936 | #define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL |
|---|
| 18937 | #define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L |
|---|
| 18938 | #define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L |
|---|
| 18939 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L |
|---|
| 18940 | #define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L |
|---|
| 18941 | #define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000200L |
|---|
| 18942 | #define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L |
|---|
| 18943 | #define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L |
|---|
| 18944 | #define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK 0x00004000L |
|---|
| 18945 | //BIFC_PCIEFUNC_CNTL |
|---|
| 18946 | #define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 |
|---|
| 18947 | #define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 |
|---|
| 18948 | #define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL |
|---|
| 18949 | #define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L |
|---|
| 18950 | //BIFC_PASID_CHECK_DIS |
|---|
| 18951 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT 0x0 |
|---|
| 18952 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT 0x1 |
|---|
| 18953 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT 0x2 |
|---|
| 18954 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT 0x3 |
|---|
| 18955 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK 0x00000001L |
|---|
| 18956 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK 0x00000002L |
|---|
| 18957 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK 0x00000004L |
|---|
| 18958 | #define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK 0x00000008L |
|---|
| 18959 | //BIFC_SDP_CNTL_0 |
|---|
| 18960 | #define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 |
|---|
| 18961 | #define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8 |
|---|
| 18962 | #define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10 |
|---|
| 18963 | #define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18 |
|---|
| 18964 | #define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL |
|---|
| 18965 | #define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L |
|---|
| 18966 | #define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L |
|---|
| 18967 | #define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L |
|---|
| 18968 | //BIFC_SDP_CNTL_1 |
|---|
| 18969 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0 |
|---|
| 18970 | #define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1 |
|---|
| 18971 | #define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2 |
|---|
| 18972 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3 |
|---|
| 18973 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4 |
|---|
| 18974 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7 |
|---|
| 18975 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L |
|---|
| 18976 | #define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L |
|---|
| 18977 | #define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L |
|---|
| 18978 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L |
|---|
| 18979 | #define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L |
|---|
| 18980 | #define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L |
|---|
| 18981 | //BIFC_PASID_STS |
|---|
| 18982 | #define BIFC_PASID_STS__PASID_STS__SHIFT 0x0 |
|---|
| 18983 | #define BIFC_PASID_STS__PASID_STS_MASK 0x0000000FL |
|---|
| 18984 | //BIFC_ATHUB_ACT_CNTL |
|---|
| 18985 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT 0x0 |
|---|
| 18986 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT 0x8 |
|---|
| 18987 | #define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS__SHIFT 0x9 |
|---|
| 18988 | #define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS__SHIFT 0xa |
|---|
| 18989 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT 0xb |
|---|
| 18990 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK 0x00000007L |
|---|
| 18991 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK 0x00000100L |
|---|
| 18992 | #define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS_MASK 0x00000200L |
|---|
| 18993 | #define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS_MASK 0x00000400L |
|---|
| 18994 | #define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK 0x00000800L |
|---|
| 18995 | //BIFC_PERF_CNTL_0 |
|---|
| 18996 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 |
|---|
| 18997 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 |
|---|
| 18998 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 |
|---|
| 18999 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 |
|---|
| 19000 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 |
|---|
| 19001 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 |
|---|
| 19002 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L |
|---|
| 19003 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L |
|---|
| 19004 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L |
|---|
| 19005 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L |
|---|
| 19006 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x003F0000L |
|---|
| 19007 | #define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x3F000000L |
|---|
| 19008 | //BIFC_PERF_CNTL_1 |
|---|
| 19009 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 |
|---|
| 19010 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 |
|---|
| 19011 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8 |
|---|
| 19012 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9 |
|---|
| 19013 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10 |
|---|
| 19014 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18 |
|---|
| 19015 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L |
|---|
| 19016 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L |
|---|
| 19017 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000100L |
|---|
| 19018 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000200L |
|---|
| 19019 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x003F0000L |
|---|
| 19020 | #define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x7F000000L |
|---|
| 19021 | //BIFC_PERF_CNT_MMIO_RD |
|---|
| 19022 | #define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0 |
|---|
| 19023 | #define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK 0xFFFFFFFFL |
|---|
| 19024 | //BIFC_PERF_CNT_MMIO_WR |
|---|
| 19025 | #define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0 |
|---|
| 19026 | #define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK 0xFFFFFFFFL |
|---|
| 19027 | //BIFC_PERF_CNT_DMA_RD |
|---|
| 19028 | #define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0 |
|---|
| 19029 | #define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK 0xFFFFFFFFL |
|---|
| 19030 | //BIFC_PERF_CNT_DMA_WR |
|---|
| 19031 | #define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0 |
|---|
| 19032 | #define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK 0xFFFFFFFFL |
|---|
| 19033 | //NBIF_REGIF_ERRSET_CTRL |
|---|
| 19034 | #define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 |
|---|
| 19035 | #define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L |
|---|
| 19036 | //NBIF_PGMST_CTRL |
|---|
| 19037 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0 |
|---|
| 19038 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8 |
|---|
| 19039 | #define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa |
|---|
| 19040 | #define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe |
|---|
| 19041 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL |
|---|
| 19042 | #define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L |
|---|
| 19043 | #define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L |
|---|
| 19044 | #define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L |
|---|
| 19045 | //NBIF_PGSLV_CTRL |
|---|
| 19046 | #define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0 |
|---|
| 19047 | #define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL |
|---|
| 19048 | //NBIF_PG_MISC_CTRL |
|---|
| 19049 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 |
|---|
| 19050 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 |
|---|
| 19051 | #define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa |
|---|
| 19052 | #define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0xb |
|---|
| 19053 | #define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0xc |
|---|
| 19054 | #define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM__SHIFT 0xd |
|---|
| 19055 | #define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe |
|---|
| 19056 | #define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0xf |
|---|
| 19057 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 |
|---|
| 19058 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f |
|---|
| 19059 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL |
|---|
| 19060 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L |
|---|
| 19061 | #define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L |
|---|
| 19062 | #define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000800L |
|---|
| 19063 | #define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00001000L |
|---|
| 19064 | #define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM_MASK 0x00002000L |
|---|
| 19065 | #define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L |
|---|
| 19066 | #define NBIF_PG_MISC_CTRL__NBIF_PG_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00008000L |
|---|
| 19067 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L |
|---|
| 19068 | #define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L |
|---|
| 19069 | //SMN_MST_EP_CNTL3 |
|---|
| 19070 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 |
|---|
| 19071 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 |
|---|
| 19072 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 |
|---|
| 19073 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 |
|---|
| 19074 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 |
|---|
| 19075 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 |
|---|
| 19076 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 |
|---|
| 19077 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 |
|---|
| 19078 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L |
|---|
| 19079 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L |
|---|
| 19080 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L |
|---|
| 19081 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L |
|---|
| 19082 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L |
|---|
| 19083 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L |
|---|
| 19084 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L |
|---|
| 19085 | #define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L |
|---|
| 19086 | //SMN_MST_EP_CNTL4 |
|---|
| 19087 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 |
|---|
| 19088 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 |
|---|
| 19089 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 |
|---|
| 19090 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 |
|---|
| 19091 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 |
|---|
| 19092 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 |
|---|
| 19093 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 |
|---|
| 19094 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 |
|---|
| 19095 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L |
|---|
| 19096 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L |
|---|
| 19097 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L |
|---|
| 19098 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L |
|---|
| 19099 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L |
|---|
| 19100 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L |
|---|
| 19101 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L |
|---|
| 19102 | #define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L |
|---|
| 19103 | //SMN_MST_CNTL1 |
|---|
| 19104 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0 |
|---|
| 19105 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10 |
|---|
| 19106 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L |
|---|
| 19107 | #define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L |
|---|
| 19108 | //SMN_MST_EP_CNTL5 |
|---|
| 19109 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0 |
|---|
| 19110 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1 |
|---|
| 19111 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2 |
|---|
| 19112 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3 |
|---|
| 19113 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4 |
|---|
| 19114 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5 |
|---|
| 19115 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6 |
|---|
| 19116 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7 |
|---|
| 19117 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L |
|---|
| 19118 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L |
|---|
| 19119 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L |
|---|
| 19120 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L |
|---|
| 19121 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L |
|---|
| 19122 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L |
|---|
| 19123 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L |
|---|
| 19124 | #define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L |
|---|
| 19125 | //BIF_SELFRING_BUFFER_VID |
|---|
| 19126 | #define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 |
|---|
| 19127 | #define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT 0x8 |
|---|
| 19128 | #define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT 0x10 |
|---|
| 19129 | #define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL |
|---|
| 19130 | #define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK 0x0000FF00L |
|---|
| 19131 | #define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK 0x00FF0000L |
|---|
| 19132 | //BIF_SELFRING_VECTOR_CNTL |
|---|
| 19133 | #define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 |
|---|
| 19134 | #define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1 |
|---|
| 19135 | #define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L |
|---|
| 19136 | #define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L |
|---|
| 19137 | //NBIF_STRAP_WRITE_CTRL |
|---|
| 19138 | #define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0 |
|---|
| 19139 | #define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK 0x00000001L |
|---|
| 19140 | //NBIF_INTX_DSTATE_MISC_CNTL |
|---|
| 19141 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x0 |
|---|
| 19142 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x1 |
|---|
| 19143 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x2 |
|---|
| 19144 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x3 |
|---|
| 19145 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x4 |
|---|
| 19146 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT 0x5 |
|---|
| 19147 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT 0x6 |
|---|
| 19148 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x7 |
|---|
| 19149 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00000001L |
|---|
| 19150 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00000002L |
|---|
| 19151 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00000004L |
|---|
| 19152 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00000008L |
|---|
| 19153 | #define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00000010L |
|---|
| 19154 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK 0x00000020L |
|---|
| 19155 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK 0x00000040L |
|---|
| 19156 | #define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000080L |
|---|
| 19157 | //NBIF_PENDING_MISC_CNTL |
|---|
| 19158 | #define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT 0x0 |
|---|
| 19159 | #define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT 0x1 |
|---|
| 19160 | #define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK 0x00000001L |
|---|
| 19161 | #define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK 0x00000002L |
|---|
| 19162 | //BIF_GMI_WRR_WEIGHT |
|---|
| 19163 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE__SHIFT 0x1f |
|---|
| 19164 | #define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE_MASK 0x80000000L |
|---|
| 19165 | //BIF_GMI_WRR_WEIGHT2 |
|---|
| 19166 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT 0x0 |
|---|
| 19167 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT 0x8 |
|---|
| 19168 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT 0x10 |
|---|
| 19169 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT 0x18 |
|---|
| 19170 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK 0x000000FFL |
|---|
| 19171 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK 0x0000FF00L |
|---|
| 19172 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK 0x00FF0000L |
|---|
| 19173 | #define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK 0xFF000000L |
|---|
| 19174 | //BIF_GMI_WRR_WEIGHT3 |
|---|
| 19175 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT 0x0 |
|---|
| 19176 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT 0x8 |
|---|
| 19177 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT 0x10 |
|---|
| 19178 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT 0x18 |
|---|
| 19179 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK 0x000000FFL |
|---|
| 19180 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK 0x0000FF00L |
|---|
| 19181 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK 0x00FF0000L |
|---|
| 19182 | #define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK 0xFF000000L |
|---|
| 19183 | //NBIF_PWRBRK_REQUEST |
|---|
| 19184 | #define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT 0x0 |
|---|
| 19185 | #define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK 0x00000001L |
|---|
| 19186 | //BIF_ATOMIC_ERR_LOG_DEV0_F0 |
|---|
| 19187 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0 |
|---|
| 19188 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1 |
|---|
| 19189 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2 |
|---|
| 19190 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3 |
|---|
| 19191 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10 |
|---|
| 19192 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11 |
|---|
| 19193 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12 |
|---|
| 19194 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13 |
|---|
| 19195 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L |
|---|
| 19196 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L |
|---|
| 19197 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L |
|---|
| 19198 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L |
|---|
| 19199 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L |
|---|
| 19200 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L |
|---|
| 19201 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L |
|---|
| 19202 | #define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L |
|---|
| 19203 | //BIF_ATOMIC_ERR_LOG_DEV0_F1 |
|---|
| 19204 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x0 |
|---|
| 19205 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x1 |
|---|
| 19206 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x2 |
|---|
| 19207 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT 0x3 |
|---|
| 19208 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x10 |
|---|
| 19209 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x11 |
|---|
| 19210 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x12 |
|---|
| 19211 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT 0x13 |
|---|
| 19212 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00000001L |
|---|
| 19213 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00000002L |
|---|
| 19214 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00000004L |
|---|
| 19215 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK 0x00000008L |
|---|
| 19216 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00010000L |
|---|
| 19217 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00020000L |
|---|
| 19218 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00040000L |
|---|
| 19219 | #define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK 0x00080000L |
|---|
| 19220 | //BIF_ATOMIC_ERR_LOG_DEV0_F2 |
|---|
| 19221 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2__SHIFT 0x0 |
|---|
| 19222 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT 0x1 |
|---|
| 19223 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2__SHIFT 0x2 |
|---|
| 19224 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2__SHIFT 0x3 |
|---|
| 19225 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2__SHIFT 0x10 |
|---|
| 19226 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT 0x11 |
|---|
| 19227 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2__SHIFT 0x12 |
|---|
| 19228 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2__SHIFT 0x13 |
|---|
| 19229 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2_MASK 0x00000001L |
|---|
| 19230 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK 0x00000002L |
|---|
| 19231 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2_MASK 0x00000004L |
|---|
| 19232 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2_MASK 0x00000008L |
|---|
| 19233 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2_MASK 0x00010000L |
|---|
| 19234 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK 0x00020000L |
|---|
| 19235 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2_MASK 0x00040000L |
|---|
| 19236 | #define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2_MASK 0x00080000L |
|---|
| 19237 | //BIF_ATOMIC_ERR_LOG_DEV0_F3 |
|---|
| 19238 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3__SHIFT 0x0 |
|---|
| 19239 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT 0x1 |
|---|
| 19240 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3__SHIFT 0x2 |
|---|
| 19241 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3__SHIFT 0x3 |
|---|
| 19242 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3__SHIFT 0x10 |
|---|
| 19243 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT 0x11 |
|---|
| 19244 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3__SHIFT 0x12 |
|---|
| 19245 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3__SHIFT 0x13 |
|---|
| 19246 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3_MASK 0x00000001L |
|---|
| 19247 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK 0x00000002L |
|---|
| 19248 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3_MASK 0x00000004L |
|---|
| 19249 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3_MASK 0x00000008L |
|---|
| 19250 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3_MASK 0x00010000L |
|---|
| 19251 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK 0x00020000L |
|---|
| 19252 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3_MASK 0x00040000L |
|---|
| 19253 | #define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3_MASK 0x00080000L |
|---|
| 19254 | //BIF_ATOMIC_ERR_LOG_DEV0_F4 |
|---|
| 19255 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4__SHIFT 0x0 |
|---|
| 19256 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT 0x1 |
|---|
| 19257 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4__SHIFT 0x2 |
|---|
| 19258 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4__SHIFT 0x3 |
|---|
| 19259 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4__SHIFT 0x10 |
|---|
| 19260 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT 0x11 |
|---|
| 19261 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4__SHIFT 0x12 |
|---|
| 19262 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4__SHIFT 0x13 |
|---|
| 19263 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4_MASK 0x00000001L |
|---|
| 19264 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK 0x00000002L |
|---|
| 19265 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4_MASK 0x00000004L |
|---|
| 19266 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4_MASK 0x00000008L |
|---|
| 19267 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4_MASK 0x00010000L |
|---|
| 19268 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK 0x00020000L |
|---|
| 19269 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4_MASK 0x00040000L |
|---|
| 19270 | #define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4_MASK 0x00080000L |
|---|
| 19271 | //BIF_ATOMIC_ERR_LOG_DEV0_F5 |
|---|
| 19272 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5__SHIFT 0x0 |
|---|
| 19273 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT 0x1 |
|---|
| 19274 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5__SHIFT 0x2 |
|---|
| 19275 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5__SHIFT 0x3 |
|---|
| 19276 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5__SHIFT 0x10 |
|---|
| 19277 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT 0x11 |
|---|
| 19278 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5__SHIFT 0x12 |
|---|
| 19279 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5__SHIFT 0x13 |
|---|
| 19280 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5_MASK 0x00000001L |
|---|
| 19281 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK 0x00000002L |
|---|
| 19282 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5_MASK 0x00000004L |
|---|
| 19283 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5_MASK 0x00000008L |
|---|
| 19284 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5_MASK 0x00010000L |
|---|
| 19285 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK 0x00020000L |
|---|
| 19286 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5_MASK 0x00040000L |
|---|
| 19287 | #define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5_MASK 0x00080000L |
|---|
| 19288 | //BIF_ATOMIC_ERR_LOG_DEV0_F6 |
|---|
| 19289 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6__SHIFT 0x0 |
|---|
| 19290 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT 0x1 |
|---|
| 19291 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6__SHIFT 0x2 |
|---|
| 19292 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6__SHIFT 0x3 |
|---|
| 19293 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6__SHIFT 0x10 |
|---|
| 19294 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT 0x11 |
|---|
| 19295 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6__SHIFT 0x12 |
|---|
| 19296 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6__SHIFT 0x13 |
|---|
| 19297 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6_MASK 0x00000001L |
|---|
| 19298 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK 0x00000002L |
|---|
| 19299 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6_MASK 0x00000004L |
|---|
| 19300 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6_MASK 0x00000008L |
|---|
| 19301 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6_MASK 0x00010000L |
|---|
| 19302 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK 0x00020000L |
|---|
| 19303 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6_MASK 0x00040000L |
|---|
| 19304 | #define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6_MASK 0x00080000L |
|---|
| 19305 | //BIF_ATOMIC_ERR_LOG_DEV0_F7 |
|---|
| 19306 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_OPCODE_DEV0_F7__SHIFT 0x0 |
|---|
| 19307 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_REQEN_LOW_DEV0_F7__SHIFT 0x1 |
|---|
| 19308 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_LENGTH_DEV0_F7__SHIFT 0x2 |
|---|
| 19309 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_NR_DEV0_F7__SHIFT 0x3 |
|---|
| 19310 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F7__SHIFT 0x10 |
|---|
| 19311 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7__SHIFT 0x11 |
|---|
| 19312 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F7__SHIFT 0x12 |
|---|
| 19313 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_NR_DEV0_F7__SHIFT 0x13 |
|---|
| 19314 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_OPCODE_DEV0_F7_MASK 0x00000001L |
|---|
| 19315 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_REQEN_LOW_DEV0_F7_MASK 0x00000002L |
|---|
| 19316 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_LENGTH_DEV0_F7_MASK 0x00000004L |
|---|
| 19317 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_NR_DEV0_F7_MASK 0x00000008L |
|---|
| 19318 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F7_MASK 0x00010000L |
|---|
| 19319 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7_MASK 0x00020000L |
|---|
| 19320 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F7_MASK 0x00040000L |
|---|
| 19321 | #define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_NR_DEV0_F7_MASK 0x00080000L |
|---|
| 19322 | //BIF_DMA_MP4_ERR_LOG |
|---|
| 19323 | #define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x0 |
|---|
| 19324 | #define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x1 |
|---|
| 19325 | #define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x10 |
|---|
| 19326 | #define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x11 |
|---|
| 19327 | #define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK 0x00000001L |
|---|
| 19328 | #define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00000002L |
|---|
| 19329 | #define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK 0x00010000L |
|---|
| 19330 | #define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00020000L |
|---|
| 19331 | //BIF_PASID_ERR_LOG |
|---|
| 19332 | #define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT 0x0 |
|---|
| 19333 | #define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT 0x1 |
|---|
| 19334 | #define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2__SHIFT 0x2 |
|---|
| 19335 | #define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3__SHIFT 0x3 |
|---|
| 19336 | #define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK 0x00000001L |
|---|
| 19337 | #define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK 0x00000002L |
|---|
| 19338 | #define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2_MASK 0x00000004L |
|---|
| 19339 | #define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3_MASK 0x00000008L |
|---|
| 19340 | //BIF_PASID_ERR_CLR |
|---|
| 19341 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT 0x0 |
|---|
| 19342 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT 0x1 |
|---|
| 19343 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT 0x2 |
|---|
| 19344 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT 0x3 |
|---|
| 19345 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK 0x00000001L |
|---|
| 19346 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK 0x00000002L |
|---|
| 19347 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK 0x00000004L |
|---|
| 19348 | #define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK 0x00000008L |
|---|
| 19349 | //NBIF_VWIRE_CTRL |
|---|
| 19350 | #define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT 0x0 |
|---|
| 19351 | #define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 |
|---|
| 19352 | #define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 |
|---|
| 19353 | #define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT 0x10 |
|---|
| 19354 | #define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 |
|---|
| 19355 | #define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a |
|---|
| 19356 | #define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK 0x00000001L |
|---|
| 19357 | #define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L |
|---|
| 19358 | #define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L |
|---|
| 19359 | #define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK 0x00010000L |
|---|
| 19360 | #define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L |
|---|
| 19361 | #define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L |
|---|
| 19362 | //NBIF_SMN_VWR_VCHG_DIS_CTRL |
|---|
| 19363 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0 |
|---|
| 19364 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1 |
|---|
| 19365 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2 |
|---|
| 19366 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3 |
|---|
| 19367 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4 |
|---|
| 19368 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5 |
|---|
| 19369 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6 |
|---|
| 19370 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT 0x7 |
|---|
| 19371 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT 0x8 |
|---|
| 19372 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT 0x9 |
|---|
| 19373 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L |
|---|
| 19374 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L |
|---|
| 19375 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L |
|---|
| 19376 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L |
|---|
| 19377 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L |
|---|
| 19378 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L |
|---|
| 19379 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L |
|---|
| 19380 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK 0x00000080L |
|---|
| 19381 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK 0x00000100L |
|---|
| 19382 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK 0x00000200L |
|---|
| 19383 | //NBIF_SMN_VWR_VCHG_RST_CTRL0 |
|---|
| 19384 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0 |
|---|
| 19385 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1 |
|---|
| 19386 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2 |
|---|
| 19387 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3 |
|---|
| 19388 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4 |
|---|
| 19389 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5 |
|---|
| 19390 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6 |
|---|
| 19391 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT 0x7 |
|---|
| 19392 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT 0x8 |
|---|
| 19393 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT 0x9 |
|---|
| 19394 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L |
|---|
| 19395 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L |
|---|
| 19396 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L |
|---|
| 19397 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L |
|---|
| 19398 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L |
|---|
| 19399 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L |
|---|
| 19400 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L |
|---|
| 19401 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK 0x00000080L |
|---|
| 19402 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK 0x00000100L |
|---|
| 19403 | #define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK 0x00000200L |
|---|
| 19404 | //NBIF_SMN_VWR_VCHG_TRIG |
|---|
| 19405 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0 |
|---|
| 19406 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1 |
|---|
| 19407 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2 |
|---|
| 19408 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3 |
|---|
| 19409 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4 |
|---|
| 19410 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5 |
|---|
| 19411 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6 |
|---|
| 19412 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT 0x7 |
|---|
| 19413 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT 0x8 |
|---|
| 19414 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT 0x9 |
|---|
| 19415 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L |
|---|
| 19416 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L |
|---|
| 19417 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L |
|---|
| 19418 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L |
|---|
| 19419 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L |
|---|
| 19420 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L |
|---|
| 19421 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L |
|---|
| 19422 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK 0x00000080L |
|---|
| 19423 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK 0x00000100L |
|---|
| 19424 | #define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK 0x00000200L |
|---|
| 19425 | //NBIF_SMN_VWR_WTRIG_CNTL |
|---|
| 19426 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0 |
|---|
| 19427 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1 |
|---|
| 19428 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2 |
|---|
| 19429 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3 |
|---|
| 19430 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4 |
|---|
| 19431 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5 |
|---|
| 19432 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6 |
|---|
| 19433 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT 0x7 |
|---|
| 19434 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT 0x8 |
|---|
| 19435 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT 0x9 |
|---|
| 19436 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L |
|---|
| 19437 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L |
|---|
| 19438 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L |
|---|
| 19439 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L |
|---|
| 19440 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L |
|---|
| 19441 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L |
|---|
| 19442 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L |
|---|
| 19443 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK 0x00000080L |
|---|
| 19444 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK 0x00000100L |
|---|
| 19445 | #define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK 0x00000200L |
|---|
| 19446 | //NBIF_SMN_VWR_VCHG_DIS_CTRL_1 |
|---|
| 19447 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0 |
|---|
| 19448 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1 |
|---|
| 19449 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2 |
|---|
| 19450 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3 |
|---|
| 19451 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4 |
|---|
| 19452 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5 |
|---|
| 19453 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6 |
|---|
| 19454 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT 0x7 |
|---|
| 19455 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT 0x8 |
|---|
| 19456 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT 0x9 |
|---|
| 19457 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L |
|---|
| 19458 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L |
|---|
| 19459 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L |
|---|
| 19460 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L |
|---|
| 19461 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L |
|---|
| 19462 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L |
|---|
| 19463 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L |
|---|
| 19464 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK 0x00000080L |
|---|
| 19465 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK 0x00000100L |
|---|
| 19466 | #define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK 0x00000200L |
|---|
| 19467 | //NBIF_MGCG_CTRL_LCLK |
|---|
| 19468 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0 |
|---|
| 19469 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1 |
|---|
| 19470 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2 |
|---|
| 19471 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa |
|---|
| 19472 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb |
|---|
| 19473 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT 0xc |
|---|
| 19474 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd |
|---|
| 19475 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L |
|---|
| 19476 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L |
|---|
| 19477 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL |
|---|
| 19478 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L |
|---|
| 19479 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L |
|---|
| 19480 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L |
|---|
| 19481 | #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L |
|---|
| 19482 | //NBIF_DS_CTRL_LCLK |
|---|
| 19483 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 |
|---|
| 19484 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 |
|---|
| 19485 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L |
|---|
| 19486 | #define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L |
|---|
| 19487 | //SMN_MST_CNTL0 |
|---|
| 19488 | #define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 |
|---|
| 19489 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 |
|---|
| 19490 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 |
|---|
| 19491 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa |
|---|
| 19492 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb |
|---|
| 19493 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 |
|---|
| 19494 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 |
|---|
| 19495 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 |
|---|
| 19496 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c |
|---|
| 19497 | #define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L |
|---|
| 19498 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L |
|---|
| 19499 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L |
|---|
| 19500 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L |
|---|
| 19501 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L |
|---|
| 19502 | #define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L |
|---|
| 19503 | #define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L |
|---|
| 19504 | #define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L |
|---|
| 19505 | #define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L |
|---|
| 19506 | //SMN_MST_EP_CNTL1 |
|---|
| 19507 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 |
|---|
| 19508 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 |
|---|
| 19509 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 |
|---|
| 19510 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 |
|---|
| 19511 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 |
|---|
| 19512 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 |
|---|
| 19513 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 |
|---|
| 19514 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 |
|---|
| 19515 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L |
|---|
| 19516 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L |
|---|
| 19517 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L |
|---|
| 19518 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L |
|---|
| 19519 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L |
|---|
| 19520 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L |
|---|
| 19521 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L |
|---|
| 19522 | #define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L |
|---|
| 19523 | //SMN_MST_EP_CNTL2 |
|---|
| 19524 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 |
|---|
| 19525 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 |
|---|
| 19526 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 |
|---|
| 19527 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 |
|---|
| 19528 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 |
|---|
| 19529 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 |
|---|
| 19530 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 |
|---|
| 19531 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 |
|---|
| 19532 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L |
|---|
| 19533 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L |
|---|
| 19534 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L |
|---|
| 19535 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L |
|---|
| 19536 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L |
|---|
| 19537 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L |
|---|
| 19538 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L |
|---|
| 19539 | #define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L |
|---|
| 19540 | //NBIF_SDP_VWR_VCHG_DIS_CTRL |
|---|
| 19541 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 |
|---|
| 19542 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 |
|---|
| 19543 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 |
|---|
| 19544 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 |
|---|
| 19545 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 |
|---|
| 19546 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 |
|---|
| 19547 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 |
|---|
| 19548 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 |
|---|
| 19549 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 |
|---|
| 19550 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L |
|---|
| 19551 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L |
|---|
| 19552 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L |
|---|
| 19553 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L |
|---|
| 19554 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L |
|---|
| 19555 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L |
|---|
| 19556 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L |
|---|
| 19557 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L |
|---|
| 19558 | #define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L |
|---|
| 19559 | //NBIF_SDP_VWR_VCHG_RST_CTRL0 |
|---|
| 19560 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 |
|---|
| 19561 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 |
|---|
| 19562 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 |
|---|
| 19563 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 |
|---|
| 19564 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 |
|---|
| 19565 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 |
|---|
| 19566 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 |
|---|
| 19567 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 |
|---|
| 19568 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 |
|---|
| 19569 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L |
|---|
| 19570 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L |
|---|
| 19571 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L |
|---|
| 19572 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L |
|---|
| 19573 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L |
|---|
| 19574 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L |
|---|
| 19575 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L |
|---|
| 19576 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L |
|---|
| 19577 | #define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L |
|---|
| 19578 | //NBIF_SDP_VWR_VCHG_RST_CTRL1 |
|---|
| 19579 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 |
|---|
| 19580 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 |
|---|
| 19581 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 |
|---|
| 19582 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 |
|---|
| 19583 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 |
|---|
| 19584 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 |
|---|
| 19585 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 |
|---|
| 19586 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 |
|---|
| 19587 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 |
|---|
| 19588 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L |
|---|
| 19589 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L |
|---|
| 19590 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L |
|---|
| 19591 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L |
|---|
| 19592 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L |
|---|
| 19593 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L |
|---|
| 19594 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L |
|---|
| 19595 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L |
|---|
| 19596 | #define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L |
|---|
| 19597 | //NBIF_SDP_VWR_VCHG_TRIG |
|---|
| 19598 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 |
|---|
| 19599 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 |
|---|
| 19600 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 |
|---|
| 19601 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 |
|---|
| 19602 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 |
|---|
| 19603 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 |
|---|
| 19604 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 |
|---|
| 19605 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 |
|---|
| 19606 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 |
|---|
| 19607 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L |
|---|
| 19608 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L |
|---|
| 19609 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L |
|---|
| 19610 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L |
|---|
| 19611 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L |
|---|
| 19612 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L |
|---|
| 19613 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L |
|---|
| 19614 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L |
|---|
| 19615 | #define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L |
|---|
| 19616 | //BIFC_A2S_SDP_PORT_CTRL |
|---|
| 19617 | #define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 |
|---|
| 19618 | #define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL |
|---|
| 19619 | //BIFC_A2S_CNTL_SW0 |
|---|
| 19620 | #define BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP__SHIFT 0x0 |
|---|
| 19621 | #define BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE__SHIFT 0x2 |
|---|
| 19622 | #define BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 |
|---|
| 19623 | #define BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 |
|---|
| 19624 | #define BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 |
|---|
| 19625 | #define BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP_MASK 0x00000003L |
|---|
| 19626 | #define BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE_MASK 0x0000001CL |
|---|
| 19627 | #define BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L |
|---|
| 19628 | #define BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L |
|---|
| 19629 | #define BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L |
|---|
| 19630 | //BIFC_A2S_MISC_CNTL |
|---|
| 19631 | #define BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 |
|---|
| 19632 | #define BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 |
|---|
| 19633 | #define BIFC_A2S_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x3 |
|---|
| 19634 | #define BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4 |
|---|
| 19635 | #define BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5 |
|---|
| 19636 | #define BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6 |
|---|
| 19637 | #define BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7 |
|---|
| 19638 | #define BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8 |
|---|
| 19639 | #define BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9 |
|---|
| 19640 | #define BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa |
|---|
| 19641 | #define BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10 |
|---|
| 19642 | #define BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15 |
|---|
| 19643 | #define BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L |
|---|
| 19644 | #define BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L |
|---|
| 19645 | #define BIFC_A2S_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000008L |
|---|
| 19646 | #define BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L |
|---|
| 19647 | #define BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L |
|---|
| 19648 | #define BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L |
|---|
| 19649 | #define BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L |
|---|
| 19650 | #define BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L |
|---|
| 19651 | #define BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L |
|---|
| 19652 | #define BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L |
|---|
| 19653 | #define BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L |
|---|
| 19654 | #define BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L |
|---|
| 19655 | //BIFC_A2S_TAG_ALLOC_0 |
|---|
| 19656 | #define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0 |
|---|
| 19657 | #define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8 |
|---|
| 19658 | #define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10 |
|---|
| 19659 | #define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL |
|---|
| 19660 | #define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L |
|---|
| 19661 | #define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L |
|---|
| 19662 | //BIFC_A2S_TAG_ALLOC_1 |
|---|
| 19663 | #define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0 |
|---|
| 19664 | #define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10 |
|---|
| 19665 | #define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18 |
|---|
| 19666 | #define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL |
|---|
| 19667 | #define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L |
|---|
| 19668 | #define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L |
|---|
| 19669 | //BIFC_A2S_CNTL_CL0 |
|---|
| 19670 | #define BIFC_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 |
|---|
| 19671 | #define BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 |
|---|
| 19672 | #define BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 |
|---|
| 19673 | #define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 |
|---|
| 19674 | #define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 |
|---|
| 19675 | #define BIFC_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa |
|---|
| 19676 | #define BIFC_A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc |
|---|
| 19677 | #define BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe |
|---|
| 19678 | #define BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 |
|---|
| 19679 | #define BIFC_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 |
|---|
| 19680 | #define BIFC_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 |
|---|
| 19681 | #define BIFC_A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L |
|---|
| 19682 | #define BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000CL |
|---|
| 19683 | #define BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L |
|---|
| 19684 | #define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L |
|---|
| 19685 | #define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L |
|---|
| 19686 | #define BIFC_A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000C00L |
|---|
| 19687 | #define BIFC_A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L |
|---|
| 19688 | #define BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000C000L |
|---|
| 19689 | #define BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L |
|---|
| 19690 | #define BIFC_A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000C0000L |
|---|
| 19691 | #define BIFC_A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L |
|---|
| 19692 | //BIFC_A2S_CPLBUF_ALLOC_CNTL |
|---|
| 19693 | #define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD__SHIFT 0x0 |
|---|
| 19694 | #define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD__SHIFT 0x14 |
|---|
| 19695 | #define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD__SHIFT 0x18 |
|---|
| 19696 | #define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD__SHIFT 0x1c |
|---|
| 19697 | #define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC0_RD_MASK 0x0000000FL |
|---|
| 19698 | #define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC5_RD_MASK 0x00F00000L |
|---|
| 19699 | #define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC6_RD_MASK 0x0F000000L |
|---|
| 19700 | #define BIFC_A2S_CPLBUF_ALLOC_CNTL__CPLBUF_RSVD_FOR_VC7_RD_MASK 0xF0000000L |
|---|
| 19701 | |
|---|
| 19702 | |
|---|
| 19703 | // addressBlock: nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC |
|---|
| 19704 | //RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL |
|---|
| 19705 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 19706 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
|---|
| 19707 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
|---|
| 19708 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 19709 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 19710 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
|---|
| 19711 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 19712 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 19713 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
|---|
| 19714 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 19715 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 19716 | #define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
|---|
| 19717 | //RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE |
|---|
| 19718 | #define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
|---|
| 19719 | #define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
|---|
| 19720 | #define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
|---|
| 19721 | #define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
|---|
| 19722 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 |
|---|
| 19723 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
|---|
| 19724 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
|---|
| 19725 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
|---|
| 19726 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
|---|
| 19727 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
|---|
| 19728 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
|---|
| 19729 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
|---|
| 19730 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
|---|
| 19731 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
|---|
| 19732 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
|---|
| 19733 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
|---|
| 19734 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
|---|
| 19735 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
|---|
| 19736 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
|---|
| 19737 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
|---|
| 19738 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
|---|
| 19739 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 |
|---|
| 19740 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
|---|
| 19741 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
|---|
| 19742 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 |
|---|
| 19743 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
|---|
| 19744 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
|---|
| 19745 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 |
|---|
| 19746 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
|---|
| 19747 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
|---|
| 19748 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 |
|---|
| 19749 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
|---|
| 19750 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
|---|
| 19751 | //RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 |
|---|
| 19752 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
|---|
| 19753 | #define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 19754 | //RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL |
|---|
| 19755 | #define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
|---|
| 19756 | #define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
|---|
| 19757 | #define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
|---|
| 19758 | #define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
|---|
| 19759 | |
|---|
| 19760 | |
|---|
| 19761 | // addressBlock: nbio_nbif0_rcc_pfc_amdgfxaz_RCCPFCDEC |
|---|
| 19762 | //RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL |
|---|
| 19763 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 19764 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
|---|
| 19765 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
|---|
| 19766 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 19767 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 19768 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
|---|
| 19769 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 19770 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 19771 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
|---|
| 19772 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 19773 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 19774 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
|---|
| 19775 | //RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE |
|---|
| 19776 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
|---|
| 19777 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
|---|
| 19778 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
|---|
| 19779 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
|---|
| 19780 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 |
|---|
| 19781 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
|---|
| 19782 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
|---|
| 19783 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
|---|
| 19784 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
|---|
| 19785 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
|---|
| 19786 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
|---|
| 19787 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
|---|
| 19788 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
|---|
| 19789 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
|---|
| 19790 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
|---|
| 19791 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
|---|
| 19792 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
|---|
| 19793 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
|---|
| 19794 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
|---|
| 19795 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
|---|
| 19796 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
|---|
| 19797 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 |
|---|
| 19798 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
|---|
| 19799 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
|---|
| 19800 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 |
|---|
| 19801 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
|---|
| 19802 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
|---|
| 19803 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 |
|---|
| 19804 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
|---|
| 19805 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
|---|
| 19806 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 |
|---|
| 19807 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
|---|
| 19808 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
|---|
| 19809 | //RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 |
|---|
| 19810 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
|---|
| 19811 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 19812 | //RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL |
|---|
| 19813 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
|---|
| 19814 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
|---|
| 19815 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
|---|
| 19816 | #define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
|---|
| 19817 | |
|---|
| 19818 | |
|---|
| 19819 | // addressBlock: nbio_nbif0_rcc_pfc_usb_RCCPFCDEC |
|---|
| 19820 | //RCC_PFC_USB_RCC_PFC_LTR_CNTL |
|---|
| 19821 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 19822 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
|---|
| 19823 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
|---|
| 19824 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 19825 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 19826 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
|---|
| 19827 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 19828 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 19829 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
|---|
| 19830 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 19831 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 19832 | #define RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
|---|
| 19833 | //RCC_PFC_USB_RCC_PFC_PME_RESTORE |
|---|
| 19834 | #define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
|---|
| 19835 | #define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
|---|
| 19836 | #define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
|---|
| 19837 | #define RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
|---|
| 19838 | //RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0 |
|---|
| 19839 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
|---|
| 19840 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
|---|
| 19841 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
|---|
| 19842 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
|---|
| 19843 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
|---|
| 19844 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
|---|
| 19845 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
|---|
| 19846 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
|---|
| 19847 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
|---|
| 19848 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
|---|
| 19849 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
|---|
| 19850 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
|---|
| 19851 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
|---|
| 19852 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
|---|
| 19853 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
|---|
| 19854 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
|---|
| 19855 | //RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1 |
|---|
| 19856 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
|---|
| 19857 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
|---|
| 19858 | //RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2 |
|---|
| 19859 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
|---|
| 19860 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
|---|
| 19861 | //RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3 |
|---|
| 19862 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
|---|
| 19863 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
|---|
| 19864 | //RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4 |
|---|
| 19865 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
|---|
| 19866 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
|---|
| 19867 | //RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5 |
|---|
| 19868 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
|---|
| 19869 | #define RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 19870 | //RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL |
|---|
| 19871 | #define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
|---|
| 19872 | #define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
|---|
| 19873 | #define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
|---|
| 19874 | #define RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
|---|
| 19875 | |
|---|
| 19876 | |
|---|
| 19877 | // addressBlock: nbio_nbif0_rcc_pfc_pd_controller_RCCPFCDEC |
|---|
| 19878 | //RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL |
|---|
| 19879 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 19880 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa |
|---|
| 19881 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf |
|---|
| 19882 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 19883 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 19884 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f |
|---|
| 19885 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 19886 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 19887 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L |
|---|
| 19888 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 19889 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 19890 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L |
|---|
| 19891 | //RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE |
|---|
| 19892 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 |
|---|
| 19893 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 |
|---|
| 19894 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L |
|---|
| 19895 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L |
|---|
| 19896 | //RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0 |
|---|
| 19897 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 |
|---|
| 19898 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 |
|---|
| 19899 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 |
|---|
| 19900 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 |
|---|
| 19901 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 |
|---|
| 19902 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 |
|---|
| 19903 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 |
|---|
| 19904 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 |
|---|
| 19905 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L |
|---|
| 19906 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L |
|---|
| 19907 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L |
|---|
| 19908 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L |
|---|
| 19909 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L |
|---|
| 19910 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L |
|---|
| 19911 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L |
|---|
| 19912 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L |
|---|
| 19913 | //RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1 |
|---|
| 19914 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 |
|---|
| 19915 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL |
|---|
| 19916 | //RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2 |
|---|
| 19917 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 |
|---|
| 19918 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL |
|---|
| 19919 | //RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3 |
|---|
| 19920 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 |
|---|
| 19921 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL |
|---|
| 19922 | //RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4 |
|---|
| 19923 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 |
|---|
| 19924 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL |
|---|
| 19925 | //RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5 |
|---|
| 19926 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 |
|---|
| 19927 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 19928 | //RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL |
|---|
| 19929 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 |
|---|
| 19930 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 |
|---|
| 19931 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L |
|---|
| 19932 | #define RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L |
|---|
| 19933 | |
|---|
| 19934 | |
|---|
| 19935 | // addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk |
|---|
| 19936 | //HARD_RST_CTRL |
|---|
| 19937 | #define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 |
|---|
| 19938 | #define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 |
|---|
| 19939 | #define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 |
|---|
| 19940 | #define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 |
|---|
| 19941 | #define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 |
|---|
| 19942 | #define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 |
|---|
| 19943 | #define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 |
|---|
| 19944 | #define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 |
|---|
| 19945 | #define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c |
|---|
| 19946 | #define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d |
|---|
| 19947 | #define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e |
|---|
| 19948 | #define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f |
|---|
| 19949 | #define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L |
|---|
| 19950 | #define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L |
|---|
| 19951 | #define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L |
|---|
| 19952 | #define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L |
|---|
| 19953 | #define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L |
|---|
| 19954 | #define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L |
|---|
| 19955 | #define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L |
|---|
| 19956 | #define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L |
|---|
| 19957 | #define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L |
|---|
| 19958 | #define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L |
|---|
| 19959 | #define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L |
|---|
| 19960 | #define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L |
|---|
| 19961 | //SELF_SOFT_RST |
|---|
| 19962 | #define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 |
|---|
| 19963 | #define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 |
|---|
| 19964 | #define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 |
|---|
| 19965 | #define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 |
|---|
| 19966 | #define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 |
|---|
| 19967 | #define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 |
|---|
| 19968 | #define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 |
|---|
| 19969 | #define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 |
|---|
| 19970 | #define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18 |
|---|
| 19971 | #define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19 |
|---|
| 19972 | #define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a |
|---|
| 19973 | #define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b |
|---|
| 19974 | #define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c |
|---|
| 19975 | #define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d |
|---|
| 19976 | #define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e |
|---|
| 19977 | #define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f |
|---|
| 19978 | #define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L |
|---|
| 19979 | #define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L |
|---|
| 19980 | #define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L |
|---|
| 19981 | #define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L |
|---|
| 19982 | #define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L |
|---|
| 19983 | #define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L |
|---|
| 19984 | #define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L |
|---|
| 19985 | #define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L |
|---|
| 19986 | #define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L |
|---|
| 19987 | #define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L |
|---|
| 19988 | #define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L |
|---|
| 19989 | #define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L |
|---|
| 19990 | #define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L |
|---|
| 19991 | #define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L |
|---|
| 19992 | #define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L |
|---|
| 19993 | #define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L |
|---|
| 19994 | //BIF_GFX_DRV_VPU_RST |
|---|
| 19995 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 |
|---|
| 19996 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 |
|---|
| 19997 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 |
|---|
| 19998 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 |
|---|
| 19999 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 |
|---|
| 20000 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 |
|---|
| 20001 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 |
|---|
| 20002 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 |
|---|
| 20003 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L |
|---|
| 20004 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L |
|---|
| 20005 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L |
|---|
| 20006 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L |
|---|
| 20007 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L |
|---|
| 20008 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L |
|---|
| 20009 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L |
|---|
| 20010 | #define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L |
|---|
| 20011 | //BIF_RST_MISC_CTRL |
|---|
| 20012 | #define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 |
|---|
| 20013 | #define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 |
|---|
| 20014 | #define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 |
|---|
| 20015 | #define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 |
|---|
| 20016 | #define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 |
|---|
| 20017 | #define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 |
|---|
| 20018 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 |
|---|
| 20019 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa |
|---|
| 20020 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd |
|---|
| 20021 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf |
|---|
| 20022 | #define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 |
|---|
| 20023 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 |
|---|
| 20024 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 |
|---|
| 20025 | #define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L |
|---|
| 20026 | #define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL |
|---|
| 20027 | #define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L |
|---|
| 20028 | #define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L |
|---|
| 20029 | #define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L |
|---|
| 20030 | #define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L |
|---|
| 20031 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L |
|---|
| 20032 | #define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L |
|---|
| 20033 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L |
|---|
| 20034 | #define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L |
|---|
| 20035 | #define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L |
|---|
| 20036 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L |
|---|
| 20037 | #define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L |
|---|
| 20038 | //BIF_RST_MISC_CTRL2 |
|---|
| 20039 | #define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 |
|---|
| 20040 | #define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 |
|---|
| 20041 | #define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 |
|---|
| 20042 | #define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f |
|---|
| 20043 | #define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L |
|---|
| 20044 | #define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L |
|---|
| 20045 | #define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L |
|---|
| 20046 | #define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L |
|---|
| 20047 | //BIF_RST_MISC_CTRL3 |
|---|
| 20048 | #define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 |
|---|
| 20049 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 |
|---|
| 20050 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 |
|---|
| 20051 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 |
|---|
| 20052 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa |
|---|
| 20053 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd |
|---|
| 20054 | #define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL |
|---|
| 20055 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L |
|---|
| 20056 | #define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L |
|---|
| 20057 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L |
|---|
| 20058 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L |
|---|
| 20059 | #define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L |
|---|
| 20060 | //BIF_RST_GFXVF_FLR_IDLE |
|---|
| 20061 | #define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT 0x0 |
|---|
| 20062 | #define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT 0x1 |
|---|
| 20063 | #define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT 0x2 |
|---|
| 20064 | #define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT 0x3 |
|---|
| 20065 | #define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT 0x4 |
|---|
| 20066 | #define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT 0x5 |
|---|
| 20067 | #define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT 0x6 |
|---|
| 20068 | #define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT 0x7 |
|---|
| 20069 | #define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT 0x8 |
|---|
| 20070 | #define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT 0x9 |
|---|
| 20071 | #define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT 0xa |
|---|
| 20072 | #define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT 0xb |
|---|
| 20073 | #define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT 0xc |
|---|
| 20074 | #define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT 0xd |
|---|
| 20075 | #define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT 0xe |
|---|
| 20076 | #define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT 0xf |
|---|
| 20077 | #define BIF_RST_GFXVF_FLR_IDLE__VF16_TRANS_IDLE__SHIFT 0x10 |
|---|
| 20078 | #define BIF_RST_GFXVF_FLR_IDLE__VF17_TRANS_IDLE__SHIFT 0x11 |
|---|
| 20079 | #define BIF_RST_GFXVF_FLR_IDLE__VF18_TRANS_IDLE__SHIFT 0x12 |
|---|
| 20080 | #define BIF_RST_GFXVF_FLR_IDLE__VF19_TRANS_IDLE__SHIFT 0x13 |
|---|
| 20081 | #define BIF_RST_GFXVF_FLR_IDLE__VF20_TRANS_IDLE__SHIFT 0x14 |
|---|
| 20082 | #define BIF_RST_GFXVF_FLR_IDLE__VF21_TRANS_IDLE__SHIFT 0x15 |
|---|
| 20083 | #define BIF_RST_GFXVF_FLR_IDLE__VF22_TRANS_IDLE__SHIFT 0x16 |
|---|
| 20084 | #define BIF_RST_GFXVF_FLR_IDLE__VF23_TRANS_IDLE__SHIFT 0x17 |
|---|
| 20085 | #define BIF_RST_GFXVF_FLR_IDLE__VF24_TRANS_IDLE__SHIFT 0x18 |
|---|
| 20086 | #define BIF_RST_GFXVF_FLR_IDLE__VF25_TRANS_IDLE__SHIFT 0x19 |
|---|
| 20087 | #define BIF_RST_GFXVF_FLR_IDLE__VF26_TRANS_IDLE__SHIFT 0x1a |
|---|
| 20088 | #define BIF_RST_GFXVF_FLR_IDLE__VF27_TRANS_IDLE__SHIFT 0x1b |
|---|
| 20089 | #define BIF_RST_GFXVF_FLR_IDLE__VF28_TRANS_IDLE__SHIFT 0x1c |
|---|
| 20090 | #define BIF_RST_GFXVF_FLR_IDLE__VF29_TRANS_IDLE__SHIFT 0x1d |
|---|
| 20091 | #define BIF_RST_GFXVF_FLR_IDLE__VF30_TRANS_IDLE__SHIFT 0x1e |
|---|
| 20092 | #define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f |
|---|
| 20093 | #define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE_MASK 0x00000001L |
|---|
| 20094 | #define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE_MASK 0x00000002L |
|---|
| 20095 | #define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE_MASK 0x00000004L |
|---|
| 20096 | #define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE_MASK 0x00000008L |
|---|
| 20097 | #define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE_MASK 0x00000010L |
|---|
| 20098 | #define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE_MASK 0x00000020L |
|---|
| 20099 | #define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE_MASK 0x00000040L |
|---|
| 20100 | #define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE_MASK 0x00000080L |
|---|
| 20101 | #define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE_MASK 0x00000100L |
|---|
| 20102 | #define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE_MASK 0x00000200L |
|---|
| 20103 | #define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE_MASK 0x00000400L |
|---|
| 20104 | #define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE_MASK 0x00000800L |
|---|
| 20105 | #define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE_MASK 0x00001000L |
|---|
| 20106 | #define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE_MASK 0x00002000L |
|---|
| 20107 | #define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE_MASK 0x00004000L |
|---|
| 20108 | #define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE_MASK 0x00008000L |
|---|
| 20109 | #define BIF_RST_GFXVF_FLR_IDLE__VF16_TRANS_IDLE_MASK 0x00010000L |
|---|
| 20110 | #define BIF_RST_GFXVF_FLR_IDLE__VF17_TRANS_IDLE_MASK 0x00020000L |
|---|
| 20111 | #define BIF_RST_GFXVF_FLR_IDLE__VF18_TRANS_IDLE_MASK 0x00040000L |
|---|
| 20112 | #define BIF_RST_GFXVF_FLR_IDLE__VF19_TRANS_IDLE_MASK 0x00080000L |
|---|
| 20113 | #define BIF_RST_GFXVF_FLR_IDLE__VF20_TRANS_IDLE_MASK 0x00100000L |
|---|
| 20114 | #define BIF_RST_GFXVF_FLR_IDLE__VF21_TRANS_IDLE_MASK 0x00200000L |
|---|
| 20115 | #define BIF_RST_GFXVF_FLR_IDLE__VF22_TRANS_IDLE_MASK 0x00400000L |
|---|
| 20116 | #define BIF_RST_GFXVF_FLR_IDLE__VF23_TRANS_IDLE_MASK 0x00800000L |
|---|
| 20117 | #define BIF_RST_GFXVF_FLR_IDLE__VF24_TRANS_IDLE_MASK 0x01000000L |
|---|
| 20118 | #define BIF_RST_GFXVF_FLR_IDLE__VF25_TRANS_IDLE_MASK 0x02000000L |
|---|
| 20119 | #define BIF_RST_GFXVF_FLR_IDLE__VF26_TRANS_IDLE_MASK 0x04000000L |
|---|
| 20120 | #define BIF_RST_GFXVF_FLR_IDLE__VF27_TRANS_IDLE_MASK 0x08000000L |
|---|
| 20121 | #define BIF_RST_GFXVF_FLR_IDLE__VF28_TRANS_IDLE_MASK 0x10000000L |
|---|
| 20122 | #define BIF_RST_GFXVF_FLR_IDLE__VF29_TRANS_IDLE_MASK 0x20000000L |
|---|
| 20123 | #define BIF_RST_GFXVF_FLR_IDLE__VF30_TRANS_IDLE_MASK 0x40000000L |
|---|
| 20124 | #define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE_MASK 0x80000000L |
|---|
| 20125 | //DEV0_PF0_FLR_RST_CTRL |
|---|
| 20126 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20127 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20128 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20129 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20130 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20131 | #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 |
|---|
| 20132 | #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 |
|---|
| 20133 | #define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 |
|---|
| 20134 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 |
|---|
| 20135 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 |
|---|
| 20136 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa |
|---|
| 20137 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb |
|---|
| 20138 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc |
|---|
| 20139 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd |
|---|
| 20140 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe |
|---|
| 20141 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf |
|---|
| 20142 | #define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 |
|---|
| 20143 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
|---|
| 20144 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
|---|
| 20145 | #define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
|---|
| 20146 | #define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
|---|
| 20147 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f |
|---|
| 20148 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20149 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20150 | #define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20151 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20152 | #define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20153 | #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L |
|---|
| 20154 | #define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L |
|---|
| 20155 | #define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L |
|---|
| 20156 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L |
|---|
| 20157 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L |
|---|
| 20158 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L |
|---|
| 20159 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L |
|---|
| 20160 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L |
|---|
| 20161 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L |
|---|
| 20162 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L |
|---|
| 20163 | #define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L |
|---|
| 20164 | #define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L |
|---|
| 20165 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
|---|
| 20166 | #define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
|---|
| 20167 | #define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
|---|
| 20168 | #define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
|---|
| 20169 | #define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L |
|---|
| 20170 | //DEV0_PF1_FLR_RST_CTRL |
|---|
| 20171 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20172 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20173 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20174 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20175 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20176 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
|---|
| 20177 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
|---|
| 20178 | #define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
|---|
| 20179 | #define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
|---|
| 20180 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20181 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20182 | #define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20183 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20184 | #define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20185 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
|---|
| 20186 | #define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
|---|
| 20187 | #define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
|---|
| 20188 | #define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
|---|
| 20189 | //DEV0_PF2_FLR_RST_CTRL |
|---|
| 20190 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20191 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20192 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20193 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20194 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20195 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
|---|
| 20196 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
|---|
| 20197 | #define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
|---|
| 20198 | #define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
|---|
| 20199 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20200 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20201 | #define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20202 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20203 | #define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20204 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
|---|
| 20205 | #define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
|---|
| 20206 | #define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
|---|
| 20207 | #define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
|---|
| 20208 | //DEV0_PF3_FLR_RST_CTRL |
|---|
| 20209 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20210 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20211 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20212 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20213 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20214 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
|---|
| 20215 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
|---|
| 20216 | #define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
|---|
| 20217 | #define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
|---|
| 20218 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20219 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20220 | #define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20221 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20222 | #define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20223 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
|---|
| 20224 | #define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
|---|
| 20225 | #define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
|---|
| 20226 | #define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
|---|
| 20227 | //DEV0_PF4_FLR_RST_CTRL |
|---|
| 20228 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20229 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20230 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20231 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20232 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20233 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
|---|
| 20234 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
|---|
| 20235 | #define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
|---|
| 20236 | #define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
|---|
| 20237 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20238 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20239 | #define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20240 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20241 | #define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20242 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
|---|
| 20243 | #define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
|---|
| 20244 | #define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
|---|
| 20245 | #define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
|---|
| 20246 | //DEV0_PF5_FLR_RST_CTRL |
|---|
| 20247 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20248 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20249 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20250 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20251 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20252 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
|---|
| 20253 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
|---|
| 20254 | #define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
|---|
| 20255 | #define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
|---|
| 20256 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20257 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20258 | #define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20259 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20260 | #define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20261 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
|---|
| 20262 | #define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
|---|
| 20263 | #define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
|---|
| 20264 | #define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
|---|
| 20265 | //DEV0_PF6_FLR_RST_CTRL |
|---|
| 20266 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20267 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20268 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20269 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20270 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20271 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
|---|
| 20272 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
|---|
| 20273 | #define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
|---|
| 20274 | #define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
|---|
| 20275 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20276 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20277 | #define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20278 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20279 | #define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20280 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
|---|
| 20281 | #define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
|---|
| 20282 | #define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
|---|
| 20283 | #define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
|---|
| 20284 | //DEV0_PF7_FLR_RST_CTRL |
|---|
| 20285 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20286 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20287 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20288 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20289 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20290 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 |
|---|
| 20291 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 |
|---|
| 20292 | #define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 |
|---|
| 20293 | #define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 |
|---|
| 20294 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20295 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20296 | #define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20297 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20298 | #define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20299 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L |
|---|
| 20300 | #define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L |
|---|
| 20301 | #define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L |
|---|
| 20302 | #define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L |
|---|
| 20303 | //BIF_INST_RESET_INTR_STS |
|---|
| 20304 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 |
|---|
| 20305 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 |
|---|
| 20306 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 |
|---|
| 20307 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 |
|---|
| 20308 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 |
|---|
| 20309 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L |
|---|
| 20310 | #define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L |
|---|
| 20311 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L |
|---|
| 20312 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L |
|---|
| 20313 | #define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L |
|---|
| 20314 | //BIF_PF_FLR_INTR_STS |
|---|
| 20315 | #define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 |
|---|
| 20316 | #define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 |
|---|
| 20317 | #define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2 |
|---|
| 20318 | #define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3 |
|---|
| 20319 | #define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4 |
|---|
| 20320 | #define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5 |
|---|
| 20321 | #define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6 |
|---|
| 20322 | #define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7 |
|---|
| 20323 | #define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L |
|---|
| 20324 | #define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L |
|---|
| 20325 | #define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L |
|---|
| 20326 | #define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L |
|---|
| 20327 | #define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK 0x00000010L |
|---|
| 20328 | #define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK 0x00000020L |
|---|
| 20329 | #define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK 0x00000040L |
|---|
| 20330 | #define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK 0x00000080L |
|---|
| 20331 | //BIF_D3HOTD0_INTR_STS |
|---|
| 20332 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 |
|---|
| 20333 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 |
|---|
| 20334 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2 |
|---|
| 20335 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3 |
|---|
| 20336 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4 |
|---|
| 20337 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5 |
|---|
| 20338 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6 |
|---|
| 20339 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7 |
|---|
| 20340 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L |
|---|
| 20341 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L |
|---|
| 20342 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L |
|---|
| 20343 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L |
|---|
| 20344 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK 0x00000010L |
|---|
| 20345 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK 0x00000020L |
|---|
| 20346 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK 0x00000040L |
|---|
| 20347 | #define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK 0x00000080L |
|---|
| 20348 | //BIF_POWER_INTR_STS |
|---|
| 20349 | #define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 |
|---|
| 20350 | #define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 |
|---|
| 20351 | #define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L |
|---|
| 20352 | #define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L |
|---|
| 20353 | //BIF_PF_DSTATE_INTR_STS |
|---|
| 20354 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 |
|---|
| 20355 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 |
|---|
| 20356 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 |
|---|
| 20357 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 |
|---|
| 20358 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 |
|---|
| 20359 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 |
|---|
| 20360 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 |
|---|
| 20361 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 |
|---|
| 20362 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L |
|---|
| 20363 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L |
|---|
| 20364 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L |
|---|
| 20365 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L |
|---|
| 20366 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L |
|---|
| 20367 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L |
|---|
| 20368 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L |
|---|
| 20369 | #define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L |
|---|
| 20370 | //SELF_SOFT_RST_2 |
|---|
| 20371 | #define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT 0x0 |
|---|
| 20372 | #define SELF_SOFT_RST_2__NBIF_S5_RST__SHIFT 0x1e |
|---|
| 20373 | #define SELF_SOFT_RST_2__NBIF_S5_CDC_RST__SHIFT 0x1f |
|---|
| 20374 | #define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK 0x00000001L |
|---|
| 20375 | #define SELF_SOFT_RST_2__NBIF_S5_RST_MASK 0x40000000L |
|---|
| 20376 | #define SELF_SOFT_RST_2__NBIF_S5_CDC_RST_MASK 0x80000000L |
|---|
| 20377 | //BIF_PF0_VF_FLR_INTR_STS |
|---|
| 20378 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT 0x0 |
|---|
| 20379 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT 0x1 |
|---|
| 20380 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT 0x2 |
|---|
| 20381 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT 0x3 |
|---|
| 20382 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT 0x4 |
|---|
| 20383 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT 0x5 |
|---|
| 20384 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT 0x6 |
|---|
| 20385 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT 0x7 |
|---|
| 20386 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT 0x8 |
|---|
| 20387 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT 0x9 |
|---|
| 20388 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT 0xa |
|---|
| 20389 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT 0xb |
|---|
| 20390 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT 0xc |
|---|
| 20391 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT 0xd |
|---|
| 20392 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT 0xe |
|---|
| 20393 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT 0xf |
|---|
| 20394 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF16_FLR_INTR_STS__SHIFT 0x10 |
|---|
| 20395 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF17_FLR_INTR_STS__SHIFT 0x11 |
|---|
| 20396 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF18_FLR_INTR_STS__SHIFT 0x12 |
|---|
| 20397 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF19_FLR_INTR_STS__SHIFT 0x13 |
|---|
| 20398 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF20_FLR_INTR_STS__SHIFT 0x14 |
|---|
| 20399 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF21_FLR_INTR_STS__SHIFT 0x15 |
|---|
| 20400 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF22_FLR_INTR_STS__SHIFT 0x16 |
|---|
| 20401 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF23_FLR_INTR_STS__SHIFT 0x17 |
|---|
| 20402 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF24_FLR_INTR_STS__SHIFT 0x18 |
|---|
| 20403 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF25_FLR_INTR_STS__SHIFT 0x19 |
|---|
| 20404 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF26_FLR_INTR_STS__SHIFT 0x1a |
|---|
| 20405 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF27_FLR_INTR_STS__SHIFT 0x1b |
|---|
| 20406 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF28_FLR_INTR_STS__SHIFT 0x1c |
|---|
| 20407 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF29_FLR_INTR_STS__SHIFT 0x1d |
|---|
| 20408 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF30_FLR_INTR_STS__SHIFT 0x1e |
|---|
| 20409 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f |
|---|
| 20410 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS_MASK 0x00000001L |
|---|
| 20411 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS_MASK 0x00000002L |
|---|
| 20412 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS_MASK 0x00000004L |
|---|
| 20413 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS_MASK 0x00000008L |
|---|
| 20414 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS_MASK 0x00000010L |
|---|
| 20415 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS_MASK 0x00000020L |
|---|
| 20416 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS_MASK 0x00000040L |
|---|
| 20417 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS_MASK 0x00000080L |
|---|
| 20418 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS_MASK 0x00000100L |
|---|
| 20419 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS_MASK 0x00000200L |
|---|
| 20420 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS_MASK 0x00000400L |
|---|
| 20421 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS_MASK 0x00000800L |
|---|
| 20422 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS_MASK 0x00001000L |
|---|
| 20423 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS_MASK 0x00002000L |
|---|
| 20424 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS_MASK 0x00004000L |
|---|
| 20425 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS_MASK 0x00008000L |
|---|
| 20426 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF16_FLR_INTR_STS_MASK 0x00010000L |
|---|
| 20427 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF17_FLR_INTR_STS_MASK 0x00020000L |
|---|
| 20428 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF18_FLR_INTR_STS_MASK 0x00040000L |
|---|
| 20429 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF19_FLR_INTR_STS_MASK 0x00080000L |
|---|
| 20430 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF20_FLR_INTR_STS_MASK 0x00100000L |
|---|
| 20431 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF21_FLR_INTR_STS_MASK 0x00200000L |
|---|
| 20432 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF22_FLR_INTR_STS_MASK 0x00400000L |
|---|
| 20433 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF23_FLR_INTR_STS_MASK 0x00800000L |
|---|
| 20434 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF24_FLR_INTR_STS_MASK 0x01000000L |
|---|
| 20435 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF25_FLR_INTR_STS_MASK 0x02000000L |
|---|
| 20436 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF26_FLR_INTR_STS_MASK 0x04000000L |
|---|
| 20437 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF27_FLR_INTR_STS_MASK 0x08000000L |
|---|
| 20438 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF28_FLR_INTR_STS_MASK 0x10000000L |
|---|
| 20439 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF29_FLR_INTR_STS_MASK 0x20000000L |
|---|
| 20440 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_VF30_FLR_INTR_STS_MASK 0x40000000L |
|---|
| 20441 | #define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS_MASK 0x80000000L |
|---|
| 20442 | //BIF_INST_RESET_INTR_MASK |
|---|
| 20443 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 |
|---|
| 20444 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 |
|---|
| 20445 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 |
|---|
| 20446 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 |
|---|
| 20447 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 |
|---|
| 20448 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L |
|---|
| 20449 | #define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L |
|---|
| 20450 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L |
|---|
| 20451 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L |
|---|
| 20452 | #define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L |
|---|
| 20453 | //BIF_PF_FLR_INTR_MASK |
|---|
| 20454 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 |
|---|
| 20455 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 |
|---|
| 20456 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2 |
|---|
| 20457 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3 |
|---|
| 20458 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4 |
|---|
| 20459 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5 |
|---|
| 20460 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6 |
|---|
| 20461 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7 |
|---|
| 20462 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L |
|---|
| 20463 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L |
|---|
| 20464 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L |
|---|
| 20465 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L |
|---|
| 20466 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK 0x00000010L |
|---|
| 20467 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK 0x00000020L |
|---|
| 20468 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK 0x00000040L |
|---|
| 20469 | #define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK 0x00000080L |
|---|
| 20470 | //BIF_D3HOTD0_INTR_MASK |
|---|
| 20471 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 |
|---|
| 20472 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 |
|---|
| 20473 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2 |
|---|
| 20474 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3 |
|---|
| 20475 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4 |
|---|
| 20476 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5 |
|---|
| 20477 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6 |
|---|
| 20478 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7 |
|---|
| 20479 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L |
|---|
| 20480 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L |
|---|
| 20481 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L |
|---|
| 20482 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L |
|---|
| 20483 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK 0x00000010L |
|---|
| 20484 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK 0x00000020L |
|---|
| 20485 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK 0x00000040L |
|---|
| 20486 | #define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK 0x00000080L |
|---|
| 20487 | //BIF_POWER_INTR_MASK |
|---|
| 20488 | #define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 |
|---|
| 20489 | #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 |
|---|
| 20490 | #define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L |
|---|
| 20491 | #define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L |
|---|
| 20492 | //BIF_PF_DSTATE_INTR_MASK |
|---|
| 20493 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 |
|---|
| 20494 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 |
|---|
| 20495 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 |
|---|
| 20496 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 |
|---|
| 20497 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 |
|---|
| 20498 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 |
|---|
| 20499 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 |
|---|
| 20500 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 |
|---|
| 20501 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L |
|---|
| 20502 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L |
|---|
| 20503 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L |
|---|
| 20504 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L |
|---|
| 20505 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L |
|---|
| 20506 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L |
|---|
| 20507 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L |
|---|
| 20508 | #define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L |
|---|
| 20509 | //BIF_PF0_VF_FLR_INTR_MASK |
|---|
| 20510 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT 0x0 |
|---|
| 20511 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT 0x1 |
|---|
| 20512 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT 0x2 |
|---|
| 20513 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT 0x3 |
|---|
| 20514 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT 0x4 |
|---|
| 20515 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT 0x5 |
|---|
| 20516 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT 0x6 |
|---|
| 20517 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT 0x7 |
|---|
| 20518 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT 0x8 |
|---|
| 20519 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT 0x9 |
|---|
| 20520 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT 0xa |
|---|
| 20521 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT 0xb |
|---|
| 20522 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT 0xc |
|---|
| 20523 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT 0xd |
|---|
| 20524 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT 0xe |
|---|
| 20525 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT 0xf |
|---|
| 20526 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF16_FLR_INTR_MASK__SHIFT 0x10 |
|---|
| 20527 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF17_FLR_INTR_MASK__SHIFT 0x11 |
|---|
| 20528 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF18_FLR_INTR_MASK__SHIFT 0x12 |
|---|
| 20529 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF19_FLR_INTR_MASK__SHIFT 0x13 |
|---|
| 20530 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF20_FLR_INTR_MASK__SHIFT 0x14 |
|---|
| 20531 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF21_FLR_INTR_MASK__SHIFT 0x15 |
|---|
| 20532 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF22_FLR_INTR_MASK__SHIFT 0x16 |
|---|
| 20533 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF23_FLR_INTR_MASK__SHIFT 0x17 |
|---|
| 20534 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF24_FLR_INTR_MASK__SHIFT 0x18 |
|---|
| 20535 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF25_FLR_INTR_MASK__SHIFT 0x19 |
|---|
| 20536 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF26_FLR_INTR_MASK__SHIFT 0x1a |
|---|
| 20537 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF27_FLR_INTR_MASK__SHIFT 0x1b |
|---|
| 20538 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF28_FLR_INTR_MASK__SHIFT 0x1c |
|---|
| 20539 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF29_FLR_INTR_MASK__SHIFT 0x1d |
|---|
| 20540 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF30_FLR_INTR_MASK__SHIFT 0x1e |
|---|
| 20541 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f |
|---|
| 20542 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK_MASK 0x00000001L |
|---|
| 20543 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK_MASK 0x00000002L |
|---|
| 20544 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK_MASK 0x00000004L |
|---|
| 20545 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK_MASK 0x00000008L |
|---|
| 20546 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK_MASK 0x00000010L |
|---|
| 20547 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK_MASK 0x00000020L |
|---|
| 20548 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK_MASK 0x00000040L |
|---|
| 20549 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK_MASK 0x00000080L |
|---|
| 20550 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK_MASK 0x00000100L |
|---|
| 20551 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK_MASK 0x00000200L |
|---|
| 20552 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK_MASK 0x00000400L |
|---|
| 20553 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK_MASK 0x00000800L |
|---|
| 20554 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK_MASK 0x00001000L |
|---|
| 20555 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK_MASK 0x00002000L |
|---|
| 20556 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK_MASK 0x00004000L |
|---|
| 20557 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK_MASK 0x00008000L |
|---|
| 20558 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF16_FLR_INTR_MASK_MASK 0x00010000L |
|---|
| 20559 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF17_FLR_INTR_MASK_MASK 0x00020000L |
|---|
| 20560 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF18_FLR_INTR_MASK_MASK 0x00040000L |
|---|
| 20561 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF19_FLR_INTR_MASK_MASK 0x00080000L |
|---|
| 20562 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF20_FLR_INTR_MASK_MASK 0x00100000L |
|---|
| 20563 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF21_FLR_INTR_MASK_MASK 0x00200000L |
|---|
| 20564 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF22_FLR_INTR_MASK_MASK 0x00400000L |
|---|
| 20565 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF23_FLR_INTR_MASK_MASK 0x00800000L |
|---|
| 20566 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF24_FLR_INTR_MASK_MASK 0x01000000L |
|---|
| 20567 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF25_FLR_INTR_MASK_MASK 0x02000000L |
|---|
| 20568 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF26_FLR_INTR_MASK_MASK 0x04000000L |
|---|
| 20569 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF27_FLR_INTR_MASK_MASK 0x08000000L |
|---|
| 20570 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF28_FLR_INTR_MASK_MASK 0x10000000L |
|---|
| 20571 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF29_FLR_INTR_MASK_MASK 0x20000000L |
|---|
| 20572 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF30_FLR_INTR_MASK_MASK 0x40000000L |
|---|
| 20573 | #define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK_MASK 0x80000000L |
|---|
| 20574 | //BIF_PF_FLR_RST |
|---|
| 20575 | #define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 |
|---|
| 20576 | #define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 |
|---|
| 20577 | #define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 |
|---|
| 20578 | #define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 |
|---|
| 20579 | #define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4 |
|---|
| 20580 | #define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5 |
|---|
| 20581 | #define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6 |
|---|
| 20582 | #define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7 |
|---|
| 20583 | #define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L |
|---|
| 20584 | #define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L |
|---|
| 20585 | #define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L |
|---|
| 20586 | #define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L |
|---|
| 20587 | #define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L |
|---|
| 20588 | #define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L |
|---|
| 20589 | #define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L |
|---|
| 20590 | #define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L |
|---|
| 20591 | //BIF_PF0_VF_FLR_RST |
|---|
| 20592 | #define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 |
|---|
| 20593 | #define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 |
|---|
| 20594 | #define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 |
|---|
| 20595 | #define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 |
|---|
| 20596 | #define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 |
|---|
| 20597 | #define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 |
|---|
| 20598 | #define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 |
|---|
| 20599 | #define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 |
|---|
| 20600 | #define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 |
|---|
| 20601 | #define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 |
|---|
| 20602 | #define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa |
|---|
| 20603 | #define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb |
|---|
| 20604 | #define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc |
|---|
| 20605 | #define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd |
|---|
| 20606 | #define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe |
|---|
| 20607 | #define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf |
|---|
| 20608 | #define BIF_PF0_VF_FLR_RST__PF0_VF16_FLR_RST__SHIFT 0x10 |
|---|
| 20609 | #define BIF_PF0_VF_FLR_RST__PF0_VF17_FLR_RST__SHIFT 0x11 |
|---|
| 20610 | #define BIF_PF0_VF_FLR_RST__PF0_VF18_FLR_RST__SHIFT 0x12 |
|---|
| 20611 | #define BIF_PF0_VF_FLR_RST__PF0_VF19_FLR_RST__SHIFT 0x13 |
|---|
| 20612 | #define BIF_PF0_VF_FLR_RST__PF0_VF20_FLR_RST__SHIFT 0x14 |
|---|
| 20613 | #define BIF_PF0_VF_FLR_RST__PF0_VF21_FLR_RST__SHIFT 0x15 |
|---|
| 20614 | #define BIF_PF0_VF_FLR_RST__PF0_VF22_FLR_RST__SHIFT 0x16 |
|---|
| 20615 | #define BIF_PF0_VF_FLR_RST__PF0_VF23_FLR_RST__SHIFT 0x17 |
|---|
| 20616 | #define BIF_PF0_VF_FLR_RST__PF0_VF24_FLR_RST__SHIFT 0x18 |
|---|
| 20617 | #define BIF_PF0_VF_FLR_RST__PF0_VF25_FLR_RST__SHIFT 0x19 |
|---|
| 20618 | #define BIF_PF0_VF_FLR_RST__PF0_VF26_FLR_RST__SHIFT 0x1a |
|---|
| 20619 | #define BIF_PF0_VF_FLR_RST__PF0_VF27_FLR_RST__SHIFT 0x1b |
|---|
| 20620 | #define BIF_PF0_VF_FLR_RST__PF0_VF28_FLR_RST__SHIFT 0x1c |
|---|
| 20621 | #define BIF_PF0_VF_FLR_RST__PF0_VF29_FLR_RST__SHIFT 0x1d |
|---|
| 20622 | #define BIF_PF0_VF_FLR_RST__PF0_VF30_FLR_RST__SHIFT 0x1e |
|---|
| 20623 | #define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f |
|---|
| 20624 | #define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK 0x00000001L |
|---|
| 20625 | #define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK 0x00000002L |
|---|
| 20626 | #define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK 0x00000004L |
|---|
| 20627 | #define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK 0x00000008L |
|---|
| 20628 | #define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK 0x00000010L |
|---|
| 20629 | #define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK 0x00000020L |
|---|
| 20630 | #define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK 0x00000040L |
|---|
| 20631 | #define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK 0x00000080L |
|---|
| 20632 | #define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK 0x00000100L |
|---|
| 20633 | #define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK 0x00000200L |
|---|
| 20634 | #define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK 0x00000400L |
|---|
| 20635 | #define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK 0x00000800L |
|---|
| 20636 | #define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK 0x00001000L |
|---|
| 20637 | #define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK 0x00002000L |
|---|
| 20638 | #define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK 0x00004000L |
|---|
| 20639 | #define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK 0x00008000L |
|---|
| 20640 | #define BIF_PF0_VF_FLR_RST__PF0_VF16_FLR_RST_MASK 0x00010000L |
|---|
| 20641 | #define BIF_PF0_VF_FLR_RST__PF0_VF17_FLR_RST_MASK 0x00020000L |
|---|
| 20642 | #define BIF_PF0_VF_FLR_RST__PF0_VF18_FLR_RST_MASK 0x00040000L |
|---|
| 20643 | #define BIF_PF0_VF_FLR_RST__PF0_VF19_FLR_RST_MASK 0x00080000L |
|---|
| 20644 | #define BIF_PF0_VF_FLR_RST__PF0_VF20_FLR_RST_MASK 0x00100000L |
|---|
| 20645 | #define BIF_PF0_VF_FLR_RST__PF0_VF21_FLR_RST_MASK 0x00200000L |
|---|
| 20646 | #define BIF_PF0_VF_FLR_RST__PF0_VF22_FLR_RST_MASK 0x00400000L |
|---|
| 20647 | #define BIF_PF0_VF_FLR_RST__PF0_VF23_FLR_RST_MASK 0x00800000L |
|---|
| 20648 | #define BIF_PF0_VF_FLR_RST__PF0_VF24_FLR_RST_MASK 0x01000000L |
|---|
| 20649 | #define BIF_PF0_VF_FLR_RST__PF0_VF25_FLR_RST_MASK 0x02000000L |
|---|
| 20650 | #define BIF_PF0_VF_FLR_RST__PF0_VF26_FLR_RST_MASK 0x04000000L |
|---|
| 20651 | #define BIF_PF0_VF_FLR_RST__PF0_VF27_FLR_RST_MASK 0x08000000L |
|---|
| 20652 | #define BIF_PF0_VF_FLR_RST__PF0_VF28_FLR_RST_MASK 0x10000000L |
|---|
| 20653 | #define BIF_PF0_VF_FLR_RST__PF0_VF29_FLR_RST_MASK 0x20000000L |
|---|
| 20654 | #define BIF_PF0_VF_FLR_RST__PF0_VF30_FLR_RST_MASK 0x40000000L |
|---|
| 20655 | #define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK 0x80000000L |
|---|
| 20656 | //BIF_DEV0_PF0_DSTATE_VALUE |
|---|
| 20657 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 |
|---|
| 20658 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
|---|
| 20659 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 |
|---|
| 20660 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L |
|---|
| 20661 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
|---|
| 20662 | #define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L |
|---|
| 20663 | //BIF_DEV0_PF1_DSTATE_VALUE |
|---|
| 20664 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 |
|---|
| 20665 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
|---|
| 20666 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 |
|---|
| 20667 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L |
|---|
| 20668 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
|---|
| 20669 | #define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L |
|---|
| 20670 | //BIF_DEV0_PF2_DSTATE_VALUE |
|---|
| 20671 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 |
|---|
| 20672 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
|---|
| 20673 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 |
|---|
| 20674 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L |
|---|
| 20675 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
|---|
| 20676 | #define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L |
|---|
| 20677 | //BIF_DEV0_PF3_DSTATE_VALUE |
|---|
| 20678 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 |
|---|
| 20679 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
|---|
| 20680 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 |
|---|
| 20681 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L |
|---|
| 20682 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
|---|
| 20683 | #define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L |
|---|
| 20684 | //BIF_DEV0_PF4_DSTATE_VALUE |
|---|
| 20685 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 |
|---|
| 20686 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
|---|
| 20687 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 |
|---|
| 20688 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L |
|---|
| 20689 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
|---|
| 20690 | #define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L |
|---|
| 20691 | //BIF_DEV0_PF5_DSTATE_VALUE |
|---|
| 20692 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 |
|---|
| 20693 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
|---|
| 20694 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 |
|---|
| 20695 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L |
|---|
| 20696 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
|---|
| 20697 | #define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L |
|---|
| 20698 | //BIF_DEV0_PF6_DSTATE_VALUE |
|---|
| 20699 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 |
|---|
| 20700 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
|---|
| 20701 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 |
|---|
| 20702 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L |
|---|
| 20703 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
|---|
| 20704 | #define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L |
|---|
| 20705 | //BIF_DEV0_PF7_DSTATE_VALUE |
|---|
| 20706 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0 |
|---|
| 20707 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 |
|---|
| 20708 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10 |
|---|
| 20709 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L |
|---|
| 20710 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L |
|---|
| 20711 | #define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L |
|---|
| 20712 | //DEV0_PF0_D3HOTD0_RST_CTRL |
|---|
| 20713 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20714 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20715 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20716 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20717 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20718 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20719 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20720 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20721 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20722 | #define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20723 | //DEV0_PF1_D3HOTD0_RST_CTRL |
|---|
| 20724 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20725 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20726 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20727 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20728 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20729 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20730 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20731 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20732 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20733 | #define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20734 | //DEV0_PF2_D3HOTD0_RST_CTRL |
|---|
| 20735 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20736 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20737 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20738 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20739 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20740 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20741 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20742 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20743 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20744 | #define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20745 | //DEV0_PF3_D3HOTD0_RST_CTRL |
|---|
| 20746 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20747 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20748 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20749 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20750 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20751 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20752 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20753 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20754 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20755 | #define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20756 | //DEV0_PF4_D3HOTD0_RST_CTRL |
|---|
| 20757 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20758 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20759 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20760 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20761 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20762 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20763 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20764 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20765 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20766 | #define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20767 | //DEV0_PF5_D3HOTD0_RST_CTRL |
|---|
| 20768 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20769 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20770 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20771 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20772 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20773 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20774 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20775 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20776 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20777 | #define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20778 | //DEV0_PF6_D3HOTD0_RST_CTRL |
|---|
| 20779 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20780 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20781 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20782 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20783 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20784 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20785 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20786 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20787 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20788 | #define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20789 | //DEV0_PF7_D3HOTD0_RST_CTRL |
|---|
| 20790 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 |
|---|
| 20791 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 |
|---|
| 20792 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 |
|---|
| 20793 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 |
|---|
| 20794 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 |
|---|
| 20795 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L |
|---|
| 20796 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L |
|---|
| 20797 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L |
|---|
| 20798 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L |
|---|
| 20799 | #define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L |
|---|
| 20800 | //BIF_PORT0_DSTATE_VALUE |
|---|
| 20801 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 |
|---|
| 20802 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 |
|---|
| 20803 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L |
|---|
| 20804 | #define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L |
|---|
| 20805 | //BIF_USB_SHUB_RS_RESET_CNTL |
|---|
| 20806 | #define BIF_USB_SHUB_RS_RESET_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 |
|---|
| 20807 | #define BIF_USB_SHUB_RS_RESET_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 |
|---|
| 20808 | #define BIF_USB_SHUB_RS_RESET_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L |
|---|
| 20809 | #define BIF_USB_SHUB_RS_RESET_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L |
|---|
| 20810 | |
|---|
| 20811 | |
|---|
| 20812 | // addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk |
|---|
| 20813 | //BIFL_RAS_CENTRAL_CNTL |
|---|
| 20814 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT 0x1d |
|---|
| 20815 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT 0x1e |
|---|
| 20816 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT 0x1f |
|---|
| 20817 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK 0x20000000L |
|---|
| 20818 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK 0x40000000L |
|---|
| 20819 | #define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK 0x80000000L |
|---|
| 20820 | //BIFL_RAS_CENTRAL_STATUS |
|---|
| 20821 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT 0x0 |
|---|
| 20822 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT 0x1 |
|---|
| 20823 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT 0x2 |
|---|
| 20824 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT 0x3 |
|---|
| 20825 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT 0x1d |
|---|
| 20826 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT 0x1e |
|---|
| 20827 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT 0x1f |
|---|
| 20828 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK 0x00000001L |
|---|
| 20829 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK 0x00000002L |
|---|
| 20830 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK 0x00000004L |
|---|
| 20831 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK 0x00000008L |
|---|
| 20832 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK 0x20000000L |
|---|
| 20833 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK 0x40000000L |
|---|
| 20834 | #define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK 0x80000000L |
|---|
| 20835 | //BIFL_RAS_LEAF0_CTRL |
|---|
| 20836 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 20837 | #define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 20838 | #define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 |
|---|
| 20839 | #define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 20840 | #define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 20841 | #define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 20842 | #define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 20843 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 20844 | #define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 20845 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 20846 | #define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 20847 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 |
|---|
| 20848 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 20849 | #define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 20850 | #define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L |
|---|
| 20851 | #define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 20852 | #define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 20853 | #define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 20854 | #define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 20855 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 20856 | #define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 20857 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 20858 | #define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 20859 | #define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L |
|---|
| 20860 | //BIFL_RAS_LEAF1_CTRL |
|---|
| 20861 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 20862 | #define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 20863 | #define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 |
|---|
| 20864 | #define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 20865 | #define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 20866 | #define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 20867 | #define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 20868 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 20869 | #define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 20870 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 20871 | #define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 20872 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 |
|---|
| 20873 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 20874 | #define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 20875 | #define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L |
|---|
| 20876 | #define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 20877 | #define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 20878 | #define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 20879 | #define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 20880 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 20881 | #define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 20882 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 20883 | #define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 20884 | #define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L |
|---|
| 20885 | //BIFL_RAS_LEAF2_CTRL |
|---|
| 20886 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 20887 | #define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 20888 | #define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 |
|---|
| 20889 | #define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 20890 | #define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 20891 | #define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 20892 | #define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 20893 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 20894 | #define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 20895 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 20896 | #define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 20897 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 |
|---|
| 20898 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 20899 | #define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 20900 | #define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L |
|---|
| 20901 | #define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 20902 | #define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 20903 | #define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 20904 | #define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 20905 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 20906 | #define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 20907 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 20908 | #define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 20909 | #define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L |
|---|
| 20910 | //BIFL_RAS_LEAF3_CTRL |
|---|
| 20911 | #define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 20912 | #define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 20913 | #define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2 |
|---|
| 20914 | #define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 20915 | #define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 20916 | #define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 20917 | #define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 20918 | #define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 20919 | #define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 20920 | #define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 20921 | #define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 20922 | #define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 |
|---|
| 20923 | #define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 20924 | #define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 20925 | #define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L |
|---|
| 20926 | #define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 20927 | #define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 20928 | #define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 20929 | #define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 20930 | #define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 20931 | #define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 20932 | #define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 20933 | #define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 20934 | #define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L |
|---|
| 20935 | //BIFL_RAS_LEAF4_CTRL |
|---|
| 20936 | #define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0 |
|---|
| 20937 | #define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 |
|---|
| 20938 | #define BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2 |
|---|
| 20939 | #define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3 |
|---|
| 20940 | #define BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x4 |
|---|
| 20941 | #define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5 |
|---|
| 20942 | #define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6 |
|---|
| 20943 | #define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN__SHIFT 0x8 |
|---|
| 20944 | #define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN__SHIFT 0x9 |
|---|
| 20945 | #define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa |
|---|
| 20946 | #define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb |
|---|
| 20947 | #define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10 |
|---|
| 20948 | #define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L |
|---|
| 20949 | #define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L |
|---|
| 20950 | #define BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK 0x00000004L |
|---|
| 20951 | #define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L |
|---|
| 20952 | #define BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK 0x00000010L |
|---|
| 20953 | #define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L |
|---|
| 20954 | #define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L |
|---|
| 20955 | #define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN_MASK 0x00000100L |
|---|
| 20956 | #define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN_MASK 0x00000200L |
|---|
| 20957 | #define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L |
|---|
| 20958 | #define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L |
|---|
| 20959 | #define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L |
|---|
| 20960 | //BIFL_RAS_LEAF0_STATUS |
|---|
| 20961 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 20962 | #define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT 0x1 |
|---|
| 20963 | #define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 20964 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 20965 | #define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 20966 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 20967 | #define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 20968 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 20969 | #define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK 0x00000002L |
|---|
| 20970 | #define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 20971 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 20972 | #define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 20973 | #define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 20974 | #define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 20975 | //BIFL_RAS_LEAF1_STATUS |
|---|
| 20976 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 20977 | #define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT 0x1 |
|---|
| 20978 | #define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 20979 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 20980 | #define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 20981 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 20982 | #define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 20983 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 20984 | #define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK 0x00000002L |
|---|
| 20985 | #define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 20986 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 20987 | #define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 20988 | #define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 20989 | #define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 20990 | //BIFL_RAS_LEAF2_STATUS |
|---|
| 20991 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 20992 | #define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT 0x1 |
|---|
| 20993 | #define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 20994 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 20995 | #define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 20996 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 20997 | #define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 20998 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 20999 | #define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK 0x00000002L |
|---|
| 21000 | #define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 21001 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 21002 | #define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 21003 | #define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 21004 | #define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 21005 | //BIFL_RAS_LEAF3_STATUS |
|---|
| 21006 | #define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 21007 | #define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT 0x1 |
|---|
| 21008 | #define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 21009 | #define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 21010 | #define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 21011 | #define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 21012 | #define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 21013 | #define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 21014 | #define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK 0x00000002L |
|---|
| 21015 | #define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 21016 | #define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 21017 | #define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 21018 | #define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 21019 | #define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 21020 | //BIFL_RAS_LEAF4_STATUS |
|---|
| 21021 | #define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV__SHIFT 0x0 |
|---|
| 21022 | #define BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET__SHIFT 0x1 |
|---|
| 21023 | #define BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET__SHIFT 0x2 |
|---|
| 21024 | #define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8 |
|---|
| 21025 | #define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9 |
|---|
| 21026 | #define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa |
|---|
| 21027 | #define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb |
|---|
| 21028 | #define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV_MASK 0x00000001L |
|---|
| 21029 | #define BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET_MASK 0x00000002L |
|---|
| 21030 | #define BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET_MASK 0x00000004L |
|---|
| 21031 | #define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L |
|---|
| 21032 | #define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L |
|---|
| 21033 | #define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L |
|---|
| 21034 | #define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L |
|---|
| 21035 | //BIFL_IOHUB_RAS_IH_CNTL |
|---|
| 21036 | #define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT 0x0 |
|---|
| 21037 | #define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK 0x00000001L |
|---|
| 21038 | //BIFL_RAS_VWR_FROM_IOHUB |
|---|
| 21039 | #define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT 0x0 |
|---|
| 21040 | #define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK 0x00000001L |
|---|
| 21041 | |
|---|
| 21042 | |
|---|
| 21043 | // addressBlock: nbio_nbif0_bif_swus_SUMDEC |
|---|
| 21044 | //SUM_INDEX |
|---|
| 21045 | #define SUM_INDEX__SUM_INDEX__SHIFT 0x0 |
|---|
| 21046 | #define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL |
|---|
| 21047 | //SUM_DATA |
|---|
| 21048 | #define SUM_DATA__SUM_DATA__SHIFT 0x0 |
|---|
| 21049 | #define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL |
|---|
| 21050 | |
|---|
| 21051 | |
|---|
| 21052 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
|---|
| 21053 | //BIF_CFG_DEV0_EPF0_VENDOR_ID |
|---|
| 21054 | #define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 21055 | #define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 21056 | //BIF_CFG_DEV0_EPF0_DEVICE_ID |
|---|
| 21057 | #define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 21058 | #define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 21059 | //BIF_CFG_DEV0_EPF0_COMMAND |
|---|
| 21060 | #define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 21061 | #define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 21062 | #define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 21063 | #define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 21064 | #define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 21065 | #define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 21066 | #define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 21067 | #define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 21068 | #define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 21069 | #define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 21070 | #define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 21071 | #define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 21072 | #define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 21073 | #define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 21074 | #define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 21075 | #define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 21076 | #define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 21077 | #define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 21078 | #define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 21079 | #define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 21080 | #define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 21081 | #define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 21082 | //BIF_CFG_DEV0_EPF0_STATUS |
|---|
| 21083 | #define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 21084 | #define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 21085 | #define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 21086 | #define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 21087 | #define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 21088 | #define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 21089 | #define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 21090 | #define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 21091 | #define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 21092 | #define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 21093 | #define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 21094 | #define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 21095 | #define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 21096 | #define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 21097 | #define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 21098 | #define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 21099 | #define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 21100 | #define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 21101 | #define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 21102 | #define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 21103 | #define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 21104 | #define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 21105 | #define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 21106 | #define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 21107 | //BIF_CFG_DEV0_EPF0_REVISION_ID |
|---|
| 21108 | #define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 21109 | #define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 21110 | #define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 21111 | #define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 21112 | //BIF_CFG_DEV0_EPF0_PROG_INTERFACE |
|---|
| 21113 | #define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 21114 | #define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 21115 | //BIF_CFG_DEV0_EPF0_SUB_CLASS |
|---|
| 21116 | #define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 21117 | #define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 21118 | //BIF_CFG_DEV0_EPF0_BASE_CLASS |
|---|
| 21119 | #define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 21120 | #define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 21121 | //BIF_CFG_DEV0_EPF0_CACHE_LINE |
|---|
| 21122 | #define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 21123 | #define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 21124 | //BIF_CFG_DEV0_EPF0_LATENCY |
|---|
| 21125 | #define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 21126 | #define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 21127 | //BIF_CFG_DEV0_EPF0_HEADER |
|---|
| 21128 | #define 0x0 |
|---|
| 21129 | #define 0x7 |
|---|
| 21130 | #define 0x7FL |
|---|
| 21131 | #define 0x80L |
|---|
| 21132 | //BIF_CFG_DEV0_EPF0_BIST |
|---|
| 21133 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 21134 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 21135 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 21136 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 21137 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 21138 | #define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 21139 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_1 |
|---|
| 21140 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 21141 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 21142 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_2 |
|---|
| 21143 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 21144 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 21145 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_3 |
|---|
| 21146 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 21147 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 21148 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_4 |
|---|
| 21149 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 21150 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 21151 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_5 |
|---|
| 21152 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 21153 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 21154 | //BIF_CFG_DEV0_EPF0_BASE_ADDR_6 |
|---|
| 21155 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 21156 | #define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 21157 | //BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR |
|---|
| 21158 | #define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 21159 | #define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 21160 | //BIF_CFG_DEV0_EPF0_ADAPTER_ID |
|---|
| 21161 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 21162 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 21163 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 21164 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 21165 | //BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR |
|---|
| 21166 | #define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 21167 | #define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 21168 | //BIF_CFG_DEV0_EPF0_CAP_PTR |
|---|
| 21169 | #define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 21170 | #define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 21171 | //BIF_CFG_DEV0_EPF0_INTERRUPT_LINE |
|---|
| 21172 | #define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 21173 | #define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 21174 | //BIF_CFG_DEV0_EPF0_INTERRUPT_PIN |
|---|
| 21175 | #define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 21176 | #define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 21177 | //BIF_CFG_DEV0_EPF0_MIN_GRANT |
|---|
| 21178 | #define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 21179 | #define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 21180 | //BIF_CFG_DEV0_EPF0_MAX_LATENCY |
|---|
| 21181 | #define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 21182 | #define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 21183 | //BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST |
|---|
| 21184 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21185 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 21186 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 21187 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 21188 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 21189 | #define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 21190 | //BIF_CFG_DEV0_EPF0_ADAPTER_ID_W |
|---|
| 21191 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 21192 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 21193 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 21194 | #define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 21195 | //BIF_CFG_DEV0_EPF0_PMI_CAP_LIST |
|---|
| 21196 | #define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21197 | #define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 21198 | #define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 21199 | #define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 21200 | //BIF_CFG_DEV0_EPF0_PMI_CAP |
|---|
| 21201 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 21202 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 21203 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 21204 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 21205 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 21206 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 21207 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 21208 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 21209 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 21210 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 21211 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 21212 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 21213 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 21214 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 21215 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 21216 | #define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 21217 | //BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL |
|---|
| 21218 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 21219 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 21220 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 21221 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 21222 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 21223 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 21224 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 21225 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 21226 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 21227 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 21228 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 21229 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 21230 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 21231 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 21232 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 21233 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 21234 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 21235 | #define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 21236 | //BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST |
|---|
| 21237 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21238 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 21239 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 21240 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 21241 | //BIF_CFG_DEV0_EPF0_PCIE_CAP |
|---|
| 21242 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 21243 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 21244 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 21245 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 21246 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 21247 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 21248 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 21249 | #define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 21250 | //BIF_CFG_DEV0_EPF0_DEVICE_CAP |
|---|
| 21251 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 21252 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 21253 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 21254 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 21255 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 21256 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 21257 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 21258 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 21259 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 21260 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 21261 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 21262 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 21263 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 21264 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 21265 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 21266 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 21267 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 21268 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 21269 | //BIF_CFG_DEV0_EPF0_DEVICE_CNTL |
|---|
| 21270 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 21271 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 21272 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 21273 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 21274 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 21275 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 21276 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 21277 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 21278 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 21279 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 21280 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 21281 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 21282 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 21283 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 21284 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 21285 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 21286 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 21287 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 21288 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 21289 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 21290 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 21291 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 21292 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 21293 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 21294 | //BIF_CFG_DEV0_EPF0_DEVICE_STATUS |
|---|
| 21295 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 21296 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 21297 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 21298 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 21299 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 21300 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 21301 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 21302 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 21303 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 21304 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 21305 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 21306 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 21307 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 21308 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 21309 | //BIF_CFG_DEV0_EPF0_LINK_CAP |
|---|
| 21310 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 21311 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 21312 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 21313 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 21314 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 21315 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 21316 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 21317 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 21318 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 21319 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 21320 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 21321 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 21322 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 21323 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 21324 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 21325 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 21326 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 21327 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 21328 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 21329 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 21330 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 21331 | #define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 21332 | //BIF_CFG_DEV0_EPF0_LINK_CNTL |
|---|
| 21333 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 21334 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 21335 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 21336 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 21337 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 21338 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 21339 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 21340 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 21341 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 21342 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 21343 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 21344 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 21345 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 21346 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 21347 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 21348 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 21349 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 21350 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 21351 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 21352 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 21353 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 21354 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 21355 | //BIF_CFG_DEV0_EPF0_LINK_STATUS |
|---|
| 21356 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 21357 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 21358 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 21359 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 21360 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 21361 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 21362 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 21363 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 21364 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 21365 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 21366 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 21367 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 21368 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 21369 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 21370 | //BIF_CFG_DEV0_EPF0_DEVICE_CAP2 |
|---|
| 21371 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 21372 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 21373 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 21374 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 21375 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 21376 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 21377 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 21378 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 21379 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 21380 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 21381 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 21382 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 21383 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 21384 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 21385 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 21386 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 21387 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 21388 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 21389 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 21390 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 21391 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 21392 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 21393 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 21394 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 21395 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 21396 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 21397 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 21398 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 21399 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 21400 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 21401 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 21402 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 21403 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 21404 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 21405 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 21406 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 21407 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 21408 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 21409 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 21410 | #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 21411 | //BIF_CFG_DEV0_EPF0_DEVICE_CNTL2 |
|---|
| 21412 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 21413 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 21414 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 21415 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 21416 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 21417 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 21418 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 21419 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 21420 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 21421 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 21422 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 21423 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 21424 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 21425 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 21426 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 21427 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 21428 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 21429 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 21430 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 21431 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 21432 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 21433 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 21434 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 21435 | #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 21436 | //BIF_CFG_DEV0_EPF0_DEVICE_STATUS2 |
|---|
| 21437 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 21438 | #define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 21439 | //BIF_CFG_DEV0_EPF0_LINK_CAP2 |
|---|
| 21440 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 21441 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 21442 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 21443 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 21444 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 21445 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 21446 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 21447 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 21448 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 21449 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 21450 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 21451 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 21452 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 21453 | #define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 21454 | //BIF_CFG_DEV0_EPF0_LINK_CNTL2 |
|---|
| 21455 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 21456 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 21457 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 21458 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 21459 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 21460 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 21461 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 21462 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 21463 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 21464 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 21465 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 21466 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 21467 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 21468 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 21469 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 21470 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 21471 | //BIF_CFG_DEV0_EPF0_LINK_STATUS2 |
|---|
| 21472 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 21473 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 21474 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 21475 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 21476 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 21477 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 21478 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 21479 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 21480 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 21481 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 21482 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 21483 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 21484 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 21485 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 21486 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 21487 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 21488 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 21489 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 21490 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 21491 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 21492 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 21493 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 21494 | //BIF_CFG_DEV0_EPF0_MSI_CAP_LIST |
|---|
| 21495 | #define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21496 | #define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 21497 | #define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 21498 | #define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 21499 | //BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL |
|---|
| 21500 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 21501 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 21502 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 21503 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 21504 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 21505 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 21506 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 21507 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 21508 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 21509 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 21510 | //BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO |
|---|
| 21511 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 21512 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 21513 | //BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI |
|---|
| 21514 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 21515 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 21516 | //BIF_CFG_DEV0_EPF0_MSI_MSG_DATA |
|---|
| 21517 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 21518 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 21519 | //BIF_CFG_DEV0_EPF0_MSI_MASK |
|---|
| 21520 | #define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 21521 | #define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 21522 | //BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 |
|---|
| 21523 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 21524 | #define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 21525 | //BIF_CFG_DEV0_EPF0_MSI_MASK_64 |
|---|
| 21526 | #define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 21527 | #define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 21528 | //BIF_CFG_DEV0_EPF0_MSI_PENDING |
|---|
| 21529 | #define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 21530 | #define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 21531 | //BIF_CFG_DEV0_EPF0_MSI_PENDING_64 |
|---|
| 21532 | #define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 21533 | #define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 21534 | //BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST |
|---|
| 21535 | #define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21536 | #define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 21537 | #define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 21538 | #define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 21539 | //BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL |
|---|
| 21540 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 21541 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 21542 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 21543 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 21544 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 21545 | #define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 21546 | //BIF_CFG_DEV0_EPF0_MSIX_TABLE |
|---|
| 21547 | #define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 21548 | #define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 21549 | #define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 21550 | #define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 21551 | //BIF_CFG_DEV0_EPF0_MSIX_PBA |
|---|
| 21552 | #define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 21553 | #define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 21554 | #define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 21555 | #define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 21556 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 21557 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21558 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 21559 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 21560 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 21561 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 21562 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 21563 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 21564 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 21565 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 21566 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 21567 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 21568 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 21569 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 21570 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 21571 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 21572 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 21573 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 21574 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 21575 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 21576 | //BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST |
|---|
| 21577 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21578 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 21579 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 21580 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 21581 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 21582 | #define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 21583 | //BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 |
|---|
| 21584 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 21585 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 21586 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 21587 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 21588 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 21589 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 21590 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 21591 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 21592 | //BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 |
|---|
| 21593 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 21594 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 21595 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 21596 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 21597 | //BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL |
|---|
| 21598 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 21599 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 21600 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 21601 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 21602 | //BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS |
|---|
| 21603 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 21604 | #define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 21605 | //BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP |
|---|
| 21606 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 21607 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 21608 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 21609 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 21610 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 21611 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 21612 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 21613 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 21614 | //BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL |
|---|
| 21615 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 21616 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 21617 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 21618 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 21619 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 21620 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 21621 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 21622 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 21623 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 21624 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 21625 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 21626 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 21627 | //BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS |
|---|
| 21628 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 21629 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 21630 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 21631 | #define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 21632 | //BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP |
|---|
| 21633 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 21634 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 21635 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 21636 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 21637 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 21638 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 21639 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 21640 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 21641 | //BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL |
|---|
| 21642 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 21643 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 21644 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 21645 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 21646 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 21647 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 21648 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 21649 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 21650 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 21651 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 21652 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 21653 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 21654 | //BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS |
|---|
| 21655 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 21656 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 21657 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 21658 | #define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 21659 | //BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 21660 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21661 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 21662 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 21663 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 21664 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 21665 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 21666 | //BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 21667 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 21668 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 21669 | //BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 21670 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 21671 | #define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 21672 | //BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 21673 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21674 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 21675 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 21676 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 21677 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 21678 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 21679 | //BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS |
|---|
| 21680 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 21681 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 21682 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 21683 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 21684 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 21685 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 21686 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 21687 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 21688 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 21689 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 21690 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 21691 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 21692 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 21693 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 21694 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 21695 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 21696 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 21697 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 21698 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 21699 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 21700 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 21701 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 21702 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 21703 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 21704 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 21705 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 21706 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 21707 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 21708 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 21709 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 21710 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 21711 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 21712 | //BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK |
|---|
| 21713 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 21714 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 21715 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 21716 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 21717 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 21718 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 21719 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 21720 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 21721 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 21722 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 21723 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 21724 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 21725 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 21726 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 21727 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 21728 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 21729 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 21730 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 21731 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 21732 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 21733 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 21734 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 21735 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 21736 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 21737 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 21738 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 21739 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 21740 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 21741 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 21742 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 21743 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 21744 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 21745 | //BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 21746 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 21747 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 21748 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 21749 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 21750 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 21751 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 21752 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 21753 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 21754 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 21755 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 21756 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 21757 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 21758 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 21759 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 21760 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 21761 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 21762 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 21763 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 21764 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 21765 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 21766 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 21767 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 21768 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 21769 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 21770 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 21771 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 21772 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 21773 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 21774 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 21775 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 21776 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 21777 | #define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 21778 | //BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS |
|---|
| 21779 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 21780 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 21781 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 21782 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 21783 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 21784 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 21785 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 21786 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 21787 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 21788 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 21789 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 21790 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 21791 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 21792 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 21793 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 21794 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 21795 | //BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK |
|---|
| 21796 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 21797 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 21798 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 21799 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 21800 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 21801 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 21802 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 21803 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 21804 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 21805 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 21806 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 21807 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 21808 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 21809 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 21810 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 21811 | #define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 21812 | //BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 21813 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 21814 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 21815 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 21816 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 21817 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 21818 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 21819 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 21820 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 21821 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 21822 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 21823 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 21824 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 21825 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 21826 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 21827 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 21828 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 21829 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 21830 | #define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 21831 | //BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 |
|---|
| 21832 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 21833 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 21834 | //BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 |
|---|
| 21835 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 21836 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 21837 | //BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 |
|---|
| 21838 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 21839 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 21840 | //BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 |
|---|
| 21841 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 21842 | #define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 21843 | //BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 21844 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 21845 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 21846 | //BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 21847 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 21848 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 21849 | //BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 21850 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 21851 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 21852 | //BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 21853 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 21854 | #define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 21855 | //BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST |
|---|
| 21856 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21857 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 21858 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 21859 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 21860 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 21861 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 21862 | //BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP |
|---|
| 21863 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 21864 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 21865 | //BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL |
|---|
| 21866 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 21867 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 21868 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 21869 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 21870 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 21871 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 21872 | //BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP |
|---|
| 21873 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 21874 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 21875 | //BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL |
|---|
| 21876 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 21877 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 21878 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 21879 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 21880 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 21881 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 21882 | //BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP |
|---|
| 21883 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 21884 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 21885 | //BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL |
|---|
| 21886 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 21887 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 21888 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 21889 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 21890 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 21891 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 21892 | //BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP |
|---|
| 21893 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 21894 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 21895 | //BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL |
|---|
| 21896 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 21897 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 21898 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 21899 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 21900 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 21901 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 21902 | //BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP |
|---|
| 21903 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 21904 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 21905 | //BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL |
|---|
| 21906 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 21907 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 21908 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 21909 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 21910 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 21911 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 21912 | //BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP |
|---|
| 21913 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 21914 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 21915 | //BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL |
|---|
| 21916 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 21917 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 21918 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 21919 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 21920 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 21921 | #define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 21922 | //BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 21923 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21924 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 21925 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 21926 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 21927 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 21928 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 21929 | //BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 21930 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 21931 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 21932 | //BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA |
|---|
| 21933 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 21934 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 21935 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 21936 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 21937 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 21938 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 21939 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 21940 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 21941 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 21942 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 21943 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 21944 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 21945 | //BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP |
|---|
| 21946 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 21947 | #define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 21948 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST |
|---|
| 21949 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 21950 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 21951 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 21952 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 21953 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 21954 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 21955 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP |
|---|
| 21956 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 21957 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 21958 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 21959 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 21960 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 21961 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 21962 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 21963 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 21964 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 21965 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 21966 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 21967 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 21968 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 21969 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS |
|---|
| 21970 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 21971 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 21972 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 21973 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 21974 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL |
|---|
| 21975 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 21976 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 21977 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 21978 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 21979 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 21980 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 21981 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 21982 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 21983 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 21984 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 21985 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 21986 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 21987 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 21988 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 21989 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 21990 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 21991 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 21992 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 21993 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 21994 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 21995 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 21996 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 21997 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 21998 | //BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 21999 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 22000 | #define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 22001 | //BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 22002 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22003 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22004 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22005 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22006 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22007 | #define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22008 | //BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 |
|---|
| 22009 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 22010 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
|---|
| 22011 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
|---|
| 22012 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 22013 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 22014 | #define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
|---|
| 22015 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS |
|---|
| 22016 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 22017 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
|---|
| 22018 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 22019 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
|---|
| 22020 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 22021 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22022 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22023 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22024 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22025 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22026 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22027 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22028 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22029 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22030 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22031 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL |
|---|
| 22032 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22033 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22034 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22035 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22036 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22037 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22038 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22039 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22040 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22041 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22042 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL |
|---|
| 22043 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22044 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22045 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22046 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22047 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22048 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22049 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22050 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22051 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22052 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22053 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL |
|---|
| 22054 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22055 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22056 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22057 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22058 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22059 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22060 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22061 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22062 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22063 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22064 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL |
|---|
| 22065 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22066 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22067 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22068 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22069 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22070 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22071 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22072 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22073 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22074 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22075 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 22076 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22077 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22078 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22079 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22080 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22081 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22082 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22083 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22084 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22085 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22086 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 22087 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22088 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22089 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22090 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22091 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22092 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22093 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22094 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22095 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22096 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22097 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 22098 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22099 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22100 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22101 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22102 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22103 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22104 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22105 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22106 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22107 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22108 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 22109 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22110 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22111 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22112 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22113 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22114 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22115 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22116 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22117 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22118 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22119 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 22120 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22121 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22122 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22123 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22124 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22125 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22126 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22127 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22128 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22129 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22130 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 22131 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22132 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22133 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22134 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22135 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22136 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22137 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22138 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22139 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22140 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22141 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 22142 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22143 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22144 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22145 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22146 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22147 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22148 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22149 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22150 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22151 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22152 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 22153 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22154 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22155 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22156 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22157 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22158 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22159 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22160 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22161 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22162 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22163 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 22164 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22165 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22166 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22167 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22168 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22169 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22170 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22171 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22172 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22173 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22174 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 22175 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22176 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22177 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22178 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22179 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22180 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22181 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22182 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22183 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22184 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22185 | //BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 22186 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 22187 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 22188 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 22189 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 22190 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 22191 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 22192 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 22193 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 22194 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 22195 | #define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 22196 | //BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST |
|---|
| 22197 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22198 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22199 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22200 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22201 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22202 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22203 | //BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP |
|---|
| 22204 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 22205 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 22206 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 22207 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 22208 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 22209 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 22210 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 22211 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 22212 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 22213 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 22214 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 22215 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 22216 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 22217 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 22218 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 22219 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 22220 | //BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL |
|---|
| 22221 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 22222 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 22223 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 22224 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 22225 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 22226 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 22227 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 22228 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 22229 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 22230 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 22231 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 22232 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 22233 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 22234 | #define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 22235 | //BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 22236 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22237 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22238 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22239 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22240 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22241 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22242 | //BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP |
|---|
| 22243 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 22244 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 22245 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 22246 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 22247 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 22248 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 22249 | //BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL |
|---|
| 22250 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 22251 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 22252 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 22253 | #define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 22254 | //BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST |
|---|
| 22255 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22256 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22257 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22258 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22259 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22260 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22261 | //BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL |
|---|
| 22262 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
|---|
| 22263 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
|---|
| 22264 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
|---|
| 22265 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
|---|
| 22266 | //BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS |
|---|
| 22267 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
|---|
| 22268 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
|---|
| 22269 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
|---|
| 22270 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
|---|
| 22271 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
|---|
| 22272 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
|---|
| 22273 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
|---|
| 22274 | #define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
|---|
| 22275 | //BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
|---|
| 22276 | #define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
|---|
| 22277 | #define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
|---|
| 22278 | //BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
|---|
| 22279 | #define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
|---|
| 22280 | #define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
|---|
| 22281 | //BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST |
|---|
| 22282 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22283 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22284 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22285 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22286 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22287 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22288 | //BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP |
|---|
| 22289 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 22290 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 22291 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 22292 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 22293 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 22294 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 22295 | //BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL |
|---|
| 22296 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 22297 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 22298 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 22299 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 22300 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 22301 | #define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 22302 | //BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST |
|---|
| 22303 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22304 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22305 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22306 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22307 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22308 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22309 | //BIF_CFG_DEV0_EPF0_PCIE_MC_CAP |
|---|
| 22310 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
|---|
| 22311 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
|---|
| 22312 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
|---|
| 22313 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
|---|
| 22314 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
|---|
| 22315 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
|---|
| 22316 | //BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL |
|---|
| 22317 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
|---|
| 22318 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
|---|
| 22319 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
|---|
| 22320 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
|---|
| 22321 | //BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 |
|---|
| 22322 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
|---|
| 22323 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
|---|
| 22324 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
|---|
| 22325 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
|---|
| 22326 | //BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 |
|---|
| 22327 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
|---|
| 22328 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
|---|
| 22329 | //BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 |
|---|
| 22330 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
|---|
| 22331 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
|---|
| 22332 | //BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 |
|---|
| 22333 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
|---|
| 22334 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
|---|
| 22335 | //BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 |
|---|
| 22336 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
|---|
| 22337 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
|---|
| 22338 | //BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 |
|---|
| 22339 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
|---|
| 22340 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
|---|
| 22341 | //BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
|---|
| 22342 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
|---|
| 22343 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
|---|
| 22344 | //BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
|---|
| 22345 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
|---|
| 22346 | #define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
|---|
| 22347 | //BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST |
|---|
| 22348 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22349 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22350 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22351 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22352 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22353 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22354 | //BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP |
|---|
| 22355 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 22356 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
|---|
| 22357 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 22358 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 22359 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 22360 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 22361 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 22362 | #define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 22363 | //BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 22364 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22365 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22366 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22367 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22368 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22369 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22370 | //BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP |
|---|
| 22371 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 22372 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 22373 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 22374 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 22375 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 22376 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 22377 | //BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL |
|---|
| 22378 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 22379 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 22380 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 22381 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 22382 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 22383 | #define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 22384 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST |
|---|
| 22385 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22386 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22387 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22388 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22389 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22390 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22391 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP |
|---|
| 22392 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
|---|
| 22393 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
|---|
| 22394 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
|---|
| 22395 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
|---|
| 22396 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
|---|
| 22397 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
|---|
| 22398 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
|---|
| 22399 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
|---|
| 22400 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL |
|---|
| 22401 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
|---|
| 22402 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
|---|
| 22403 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
|---|
| 22404 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
|---|
| 22405 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
|---|
| 22406 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
|---|
| 22407 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
|---|
| 22408 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
|---|
| 22409 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
|---|
| 22410 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
|---|
| 22411 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
|---|
| 22412 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
|---|
| 22413 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS |
|---|
| 22414 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
|---|
| 22415 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
|---|
| 22416 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS |
|---|
| 22417 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
|---|
| 22418 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
|---|
| 22419 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS |
|---|
| 22420 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
|---|
| 22421 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
|---|
| 22422 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS |
|---|
| 22423 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
|---|
| 22424 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
|---|
| 22425 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK |
|---|
| 22426 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
|---|
| 22427 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
|---|
| 22428 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET |
|---|
| 22429 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
|---|
| 22430 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
|---|
| 22431 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE |
|---|
| 22432 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
|---|
| 22433 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
|---|
| 22434 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID |
|---|
| 22435 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
|---|
| 22436 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
|---|
| 22437 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
|---|
| 22438 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
|---|
| 22439 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 22440 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
|---|
| 22441 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
|---|
| 22442 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 22443 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 |
|---|
| 22444 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 22445 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 22446 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 |
|---|
| 22447 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 22448 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 22449 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 |
|---|
| 22450 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 22451 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 22452 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 |
|---|
| 22453 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 22454 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 22455 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 |
|---|
| 22456 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 22457 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 22458 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 |
|---|
| 22459 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 22460 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 22461 | //BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
|---|
| 22462 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 |
|---|
| 22463 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
|---|
| 22464 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L |
|---|
| 22465 | #define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 22466 | //BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 22467 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22468 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22469 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22470 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22471 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22472 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22473 | //BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP |
|---|
| 22474 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 22475 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 22476 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 22477 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 22478 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 22479 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 22480 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 22481 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 22482 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 22483 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 22484 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 22485 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 22486 | //BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL |
|---|
| 22487 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 22488 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 22489 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 22490 | #define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 22491 | //BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST |
|---|
| 22492 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22493 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22494 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22495 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22496 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22497 | #define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22498 | //BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP |
|---|
| 22499 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 22500 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
|---|
| 22501 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 22502 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
|---|
| 22503 | //BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS |
|---|
| 22504 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 22505 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
|---|
| 22506 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 22507 | #define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
|---|
| 22508 | //BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST |
|---|
| 22509 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22510 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22511 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22512 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22513 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22514 | #define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22515 | //BIF_CFG_DEV0_EPF0_LINK_CAP_16GT |
|---|
| 22516 | #define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
|---|
| 22517 | #define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 22518 | //BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT |
|---|
| 22519 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
|---|
| 22520 | #define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 22521 | //BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT |
|---|
| 22522 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
|---|
| 22523 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
|---|
| 22524 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
|---|
| 22525 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
|---|
| 22526 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
|---|
| 22527 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
|---|
| 22528 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
|---|
| 22529 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
|---|
| 22530 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
|---|
| 22531 | #define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
|---|
| 22532 | //BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
|---|
| 22533 | #define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 22534 | #define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 22535 | //BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT |
|---|
| 22536 | #define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 22537 | #define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 22538 | //BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT |
|---|
| 22539 | #define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 22540 | #define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 22541 | //BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT |
|---|
| 22542 | #define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22543 | #define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22544 | #define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22545 | #define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22546 | //BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT |
|---|
| 22547 | #define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22548 | #define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22549 | #define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22550 | #define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22551 | //BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT |
|---|
| 22552 | #define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22553 | #define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22554 | #define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22555 | #define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22556 | //BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT |
|---|
| 22557 | #define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22558 | #define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22559 | #define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22560 | #define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22561 | //BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT |
|---|
| 22562 | #define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22563 | #define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22564 | #define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22565 | #define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22566 | //BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT |
|---|
| 22567 | #define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22568 | #define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22569 | #define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22570 | #define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22571 | //BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT |
|---|
| 22572 | #define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22573 | #define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22574 | #define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22575 | #define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22576 | //BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT |
|---|
| 22577 | #define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22578 | #define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22579 | #define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22580 | #define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22581 | //BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT |
|---|
| 22582 | #define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22583 | #define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22584 | #define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22585 | #define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22586 | //BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT |
|---|
| 22587 | #define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22588 | #define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22589 | #define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22590 | #define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22591 | //BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT |
|---|
| 22592 | #define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22593 | #define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22594 | #define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22595 | #define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22596 | //BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT |
|---|
| 22597 | #define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22598 | #define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22599 | #define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22600 | #define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22601 | //BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT |
|---|
| 22602 | #define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22603 | #define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22604 | #define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22605 | #define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22606 | //BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT |
|---|
| 22607 | #define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22608 | #define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22609 | #define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22610 | #define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22611 | //BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 22612 | #define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22613 | #define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22614 | #define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22615 | #define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22616 | //BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 22617 | #define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 22618 | #define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 22619 | #define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 22620 | #define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 22621 | //BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 22622 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22623 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22624 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22625 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22626 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22627 | #define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22628 | //BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP |
|---|
| 22629 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 22630 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 22631 | //BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS |
|---|
| 22632 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
|---|
| 22633 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
|---|
| 22634 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
|---|
| 22635 | #define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
|---|
| 22636 | //BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL |
|---|
| 22637 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22638 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22639 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22640 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22641 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22642 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22643 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 22644 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22645 | //BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS |
|---|
| 22646 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22647 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22648 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22649 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22650 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22651 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22652 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22653 | #define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22654 | //BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL |
|---|
| 22655 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22656 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22657 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22658 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22659 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22660 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22661 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 22662 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22663 | //BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS |
|---|
| 22664 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22665 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22666 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22667 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22668 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22669 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22670 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22671 | #define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22672 | //BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL |
|---|
| 22673 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22674 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22675 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22676 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22677 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22678 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22679 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 22680 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22681 | //BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS |
|---|
| 22682 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22683 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22684 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22685 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22686 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22687 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22688 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22689 | #define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22690 | //BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL |
|---|
| 22691 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22692 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22693 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22694 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22695 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22696 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22697 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 22698 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22699 | //BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS |
|---|
| 22700 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22701 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22702 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22703 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22704 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22705 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22706 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22707 | #define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22708 | //BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL |
|---|
| 22709 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22710 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22711 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22712 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22713 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22714 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22715 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 22716 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22717 | //BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS |
|---|
| 22718 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22719 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22720 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22721 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22722 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22723 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22724 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22725 | #define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22726 | //BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL |
|---|
| 22727 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22728 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22729 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22730 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22731 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22732 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22733 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 22734 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22735 | //BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS |
|---|
| 22736 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22737 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22738 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22739 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22740 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22741 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22742 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22743 | #define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22744 | //BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL |
|---|
| 22745 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22746 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22747 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22748 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22749 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22750 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22751 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 22752 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22753 | //BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS |
|---|
| 22754 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22755 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22756 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22757 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22758 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22759 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22760 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22761 | #define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22762 | //BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL |
|---|
| 22763 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22764 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22765 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22766 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22767 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22768 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22769 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 22770 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22771 | //BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS |
|---|
| 22772 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22773 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22774 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22775 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22776 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22777 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22778 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22779 | #define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22780 | //BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL |
|---|
| 22781 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22782 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22783 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22784 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22785 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22786 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22787 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 22788 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22789 | //BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS |
|---|
| 22790 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22791 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22792 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22793 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22794 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22795 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22796 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22797 | #define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22798 | //BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL |
|---|
| 22799 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22800 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22801 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22802 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22803 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22804 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22805 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 22806 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22807 | //BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS |
|---|
| 22808 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22809 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22810 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22811 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22812 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22813 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22814 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22815 | #define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22816 | //BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL |
|---|
| 22817 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22818 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22819 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22820 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22821 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22822 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22823 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 22824 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22825 | //BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS |
|---|
| 22826 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22827 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22828 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22829 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22830 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22831 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22832 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22833 | #define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22834 | //BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL |
|---|
| 22835 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22836 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22837 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22838 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22839 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22840 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22841 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 22842 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22843 | //BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS |
|---|
| 22844 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22845 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22846 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22847 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22848 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22849 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22850 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22851 | #define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22852 | //BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL |
|---|
| 22853 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22854 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22855 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22856 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22857 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22858 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22859 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 22860 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22861 | //BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS |
|---|
| 22862 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22863 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22864 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22865 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22866 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22867 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22868 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22869 | #define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22870 | //BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL |
|---|
| 22871 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22872 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22873 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22874 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22875 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22876 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22877 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 22878 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22879 | //BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS |
|---|
| 22880 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22881 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22882 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22883 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22884 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22885 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22886 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22887 | #define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22888 | //BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL |
|---|
| 22889 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22890 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22891 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22892 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22893 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22894 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22895 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 22896 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22897 | //BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS |
|---|
| 22898 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22899 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22900 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22901 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22902 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22903 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22904 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22905 | #define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22906 | //BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL |
|---|
| 22907 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 22908 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 22909 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 22910 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 22911 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 22912 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 22913 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 22914 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 22915 | //BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS |
|---|
| 22916 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 22917 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 22918 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 22919 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 22920 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 22921 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 22922 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 22923 | #define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 22924 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
|---|
| 22925 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 22926 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 22927 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 22928 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22929 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 22930 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22931 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP |
|---|
| 22932 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 22933 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 22934 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL |
|---|
| 22935 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 22936 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 22937 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 22938 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 22939 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 22940 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 22941 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP |
|---|
| 22942 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 22943 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 22944 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL |
|---|
| 22945 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 22946 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 22947 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 22948 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 22949 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 22950 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 22951 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP |
|---|
| 22952 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 22953 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 22954 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL |
|---|
| 22955 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 22956 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 22957 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 22958 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 22959 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 22960 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 22961 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP |
|---|
| 22962 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 22963 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 22964 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL |
|---|
| 22965 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 22966 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 22967 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 22968 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 22969 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 22970 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 22971 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP |
|---|
| 22972 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 22973 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 22974 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL |
|---|
| 22975 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 22976 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 22977 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 22978 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 22979 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 22980 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 22981 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP |
|---|
| 22982 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 22983 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 22984 | //BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL |
|---|
| 22985 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 22986 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 22987 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 22988 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 22989 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 22990 | #define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 22991 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
|---|
| 22992 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
|---|
| 22993 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
|---|
| 22994 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
|---|
| 22995 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
|---|
| 22996 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
|---|
| 22997 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 22998 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
|---|
| 22999 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
|---|
| 23000 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
|---|
| 23001 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 23002 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 23003 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
|---|
| 23004 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 23005 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
|---|
| 23006 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
|---|
| 23007 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
|---|
| 23008 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
|---|
| 23009 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
|---|
| 23010 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
|---|
| 23011 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
|---|
| 23012 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
|---|
| 23013 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
|---|
| 23014 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
|---|
| 23015 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
|---|
| 23016 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
|---|
| 23017 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
|---|
| 23018 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
|---|
| 23019 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc |
|---|
| 23020 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd |
|---|
| 23021 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe |
|---|
| 23022 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf |
|---|
| 23023 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
|---|
| 23024 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
|---|
| 23025 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
|---|
| 23026 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
|---|
| 23027 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
|---|
| 23028 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
|---|
| 23029 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
|---|
| 23030 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
|---|
| 23031 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
|---|
| 23032 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
|---|
| 23033 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
|---|
| 23034 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
|---|
| 23035 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
|---|
| 23036 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
|---|
| 23037 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L |
|---|
| 23038 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L |
|---|
| 23039 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L |
|---|
| 23040 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L |
|---|
| 23041 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
|---|
| 23042 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
|---|
| 23043 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
|---|
| 23044 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
|---|
| 23045 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
|---|
| 23046 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
|---|
| 23047 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
|---|
| 23048 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
|---|
| 23049 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
|---|
| 23050 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
|---|
| 23051 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
|---|
| 23052 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
|---|
| 23053 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
|---|
| 23054 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
|---|
| 23055 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
|---|
| 23056 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc |
|---|
| 23057 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd |
|---|
| 23058 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe |
|---|
| 23059 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf |
|---|
| 23060 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
|---|
| 23061 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
|---|
| 23062 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
|---|
| 23063 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
|---|
| 23064 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
|---|
| 23065 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
|---|
| 23066 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
|---|
| 23067 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
|---|
| 23068 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
|---|
| 23069 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
|---|
| 23070 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
|---|
| 23071 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
|---|
| 23072 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
|---|
| 23073 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
|---|
| 23074 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L |
|---|
| 23075 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L |
|---|
| 23076 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L |
|---|
| 23077 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L |
|---|
| 23078 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
|---|
| 23079 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
|---|
| 23080 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
|---|
| 23081 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
|---|
| 23082 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
|---|
| 23083 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
|---|
| 23084 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
|---|
| 23085 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
|---|
| 23086 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
|---|
| 23087 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
|---|
| 23088 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
|---|
| 23089 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 23090 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
|---|
| 23091 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 23092 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
|---|
| 23093 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
|---|
| 23094 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 23095 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 23096 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 23097 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
|---|
| 23098 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
|---|
| 23099 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
|---|
| 23100 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
|---|
| 23101 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
|---|
| 23102 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
|---|
| 23103 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
|---|
| 23104 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
|---|
| 23105 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
|---|
| 23106 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
|---|
| 23107 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
|---|
| 23108 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
|---|
| 23109 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
|---|
| 23110 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
|---|
| 23111 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
|---|
| 23112 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
|---|
| 23113 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
|---|
| 23114 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
|---|
| 23115 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
|---|
| 23116 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
|---|
| 23117 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
|---|
| 23118 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
|---|
| 23119 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
|---|
| 23120 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
|---|
| 23121 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
|---|
| 23122 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
|---|
| 23123 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
|---|
| 23124 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
|---|
| 23125 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
|---|
| 23126 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
|---|
| 23127 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
|---|
| 23128 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
|---|
| 23129 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
|---|
| 23130 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
|---|
| 23131 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
|---|
| 23132 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
|---|
| 23133 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
|---|
| 23134 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
|---|
| 23135 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
|---|
| 23136 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
|---|
| 23137 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
|---|
| 23138 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
|---|
| 23139 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
|---|
| 23140 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
|---|
| 23141 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
|---|
| 23142 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
|---|
| 23143 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
|---|
| 23144 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
|---|
| 23145 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
|---|
| 23146 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
|---|
| 23147 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
|---|
| 23148 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
|---|
| 23149 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
|---|
| 23150 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
|---|
| 23151 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
|---|
| 23152 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
|---|
| 23153 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
|---|
| 23154 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
|---|
| 23155 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
|---|
| 23156 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
|---|
| 23157 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
|---|
| 23158 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
|---|
| 23159 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
|---|
| 23160 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
|---|
| 23161 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
|---|
| 23162 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
|---|
| 23163 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
|---|
| 23164 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 |
|---|
| 23165 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 |
|---|
| 23166 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 |
|---|
| 23167 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 |
|---|
| 23168 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 |
|---|
| 23169 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 |
|---|
| 23170 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 |
|---|
| 23171 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 |
|---|
| 23172 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 |
|---|
| 23173 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 |
|---|
| 23174 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa |
|---|
| 23175 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb |
|---|
| 23176 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc |
|---|
| 23177 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd |
|---|
| 23178 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe |
|---|
| 23179 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf |
|---|
| 23180 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 |
|---|
| 23181 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 |
|---|
| 23182 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 |
|---|
| 23183 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 |
|---|
| 23184 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 |
|---|
| 23185 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 |
|---|
| 23186 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 |
|---|
| 23187 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 |
|---|
| 23188 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 |
|---|
| 23189 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 |
|---|
| 23190 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a |
|---|
| 23191 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b |
|---|
| 23192 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c |
|---|
| 23193 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d |
|---|
| 23194 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e |
|---|
| 23195 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f |
|---|
| 23196 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L |
|---|
| 23197 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L |
|---|
| 23198 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L |
|---|
| 23199 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L |
|---|
| 23200 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L |
|---|
| 23201 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L |
|---|
| 23202 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L |
|---|
| 23203 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L |
|---|
| 23204 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L |
|---|
| 23205 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L |
|---|
| 23206 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L |
|---|
| 23207 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L |
|---|
| 23208 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L |
|---|
| 23209 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L |
|---|
| 23210 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L |
|---|
| 23211 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L |
|---|
| 23212 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L |
|---|
| 23213 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L |
|---|
| 23214 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L |
|---|
| 23215 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L |
|---|
| 23216 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L |
|---|
| 23217 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L |
|---|
| 23218 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L |
|---|
| 23219 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L |
|---|
| 23220 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L |
|---|
| 23221 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L |
|---|
| 23222 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L |
|---|
| 23223 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L |
|---|
| 23224 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L |
|---|
| 23225 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L |
|---|
| 23226 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L |
|---|
| 23227 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L |
|---|
| 23228 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
|---|
| 23229 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
|---|
| 23230 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
|---|
| 23231 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
|---|
| 23232 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
|---|
| 23233 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
|---|
| 23234 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
|---|
| 23235 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
|---|
| 23236 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
|---|
| 23237 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
|---|
| 23238 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
|---|
| 23239 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
|---|
| 23240 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
|---|
| 23241 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
|---|
| 23242 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
|---|
| 23243 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
|---|
| 23244 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18 |
|---|
| 23245 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
|---|
| 23246 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
|---|
| 23247 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
|---|
| 23248 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L |
|---|
| 23249 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION |
|---|
| 23250 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 |
|---|
| 23251 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 |
|---|
| 23252 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L |
|---|
| 23253 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L |
|---|
| 23254 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE |
|---|
| 23255 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 |
|---|
| 23256 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f |
|---|
| 23257 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL |
|---|
| 23258 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L |
|---|
| 23259 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
|---|
| 23260 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
|---|
| 23261 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
|---|
| 23262 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23263 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23264 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
|---|
| 23265 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
|---|
| 23266 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
|---|
| 23267 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23268 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23269 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
|---|
| 23270 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
|---|
| 23271 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
|---|
| 23272 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23273 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23274 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
|---|
| 23275 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
|---|
| 23276 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
|---|
| 23277 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23278 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23279 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
|---|
| 23280 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
|---|
| 23281 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
|---|
| 23282 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23283 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23284 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
|---|
| 23285 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
|---|
| 23286 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
|---|
| 23287 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23288 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23289 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
|---|
| 23290 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
|---|
| 23291 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
|---|
| 23292 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23293 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23294 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
|---|
| 23295 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
|---|
| 23296 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
|---|
| 23297 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23298 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23299 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
|---|
| 23300 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
|---|
| 23301 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
|---|
| 23302 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23303 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23304 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
|---|
| 23305 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
|---|
| 23306 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
|---|
| 23307 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23308 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23309 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
|---|
| 23310 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
|---|
| 23311 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
|---|
| 23312 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23313 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23314 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
|---|
| 23315 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
|---|
| 23316 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
|---|
| 23317 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23318 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23319 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
|---|
| 23320 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
|---|
| 23321 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
|---|
| 23322 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23323 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23324 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
|---|
| 23325 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
|---|
| 23326 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
|---|
| 23327 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23328 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23329 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
|---|
| 23330 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
|---|
| 23331 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
|---|
| 23332 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23333 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23334 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
|---|
| 23335 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
|---|
| 23336 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
|---|
| 23337 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23338 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23339 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB |
|---|
| 23340 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0 |
|---|
| 23341 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10 |
|---|
| 23342 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23343 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23344 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB |
|---|
| 23345 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0 |
|---|
| 23346 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10 |
|---|
| 23347 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23348 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23349 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB |
|---|
| 23350 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0 |
|---|
| 23351 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10 |
|---|
| 23352 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23353 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23354 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB |
|---|
| 23355 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0 |
|---|
| 23356 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10 |
|---|
| 23357 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23358 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23359 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB |
|---|
| 23360 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0 |
|---|
| 23361 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10 |
|---|
| 23362 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23363 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23364 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB |
|---|
| 23365 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0 |
|---|
| 23366 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10 |
|---|
| 23367 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23368 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23369 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB |
|---|
| 23370 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0 |
|---|
| 23371 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10 |
|---|
| 23372 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23373 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23374 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB |
|---|
| 23375 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0 |
|---|
| 23376 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10 |
|---|
| 23377 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23378 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23379 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB |
|---|
| 23380 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0 |
|---|
| 23381 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10 |
|---|
| 23382 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23383 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23384 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB |
|---|
| 23385 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0 |
|---|
| 23386 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10 |
|---|
| 23387 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23388 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23389 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB |
|---|
| 23390 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0 |
|---|
| 23391 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10 |
|---|
| 23392 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23393 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23394 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB |
|---|
| 23395 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0 |
|---|
| 23396 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10 |
|---|
| 23397 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23398 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23399 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB |
|---|
| 23400 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0 |
|---|
| 23401 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10 |
|---|
| 23402 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23403 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23404 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB |
|---|
| 23405 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0 |
|---|
| 23406 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10 |
|---|
| 23407 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23408 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23409 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB |
|---|
| 23410 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0 |
|---|
| 23411 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10 |
|---|
| 23412 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 23413 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 23414 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
|---|
| 23415 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 23416 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 23417 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
|---|
| 23418 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 23419 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 23420 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
|---|
| 23421 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 23422 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 23423 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
|---|
| 23424 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 23425 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 23426 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
|---|
| 23427 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 23428 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 23429 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
|---|
| 23430 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 23431 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 23432 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
|---|
| 23433 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 23434 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 23435 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
|---|
| 23436 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 23437 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 23438 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
|---|
| 23439 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 23440 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 23441 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
|---|
| 23442 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
|---|
| 23443 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 23444 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
|---|
| 23445 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
|---|
| 23446 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 23447 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
|---|
| 23448 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
|---|
| 23449 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 23450 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
|---|
| 23451 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
|---|
| 23452 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 23453 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
|---|
| 23454 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
|---|
| 23455 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 23456 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
|---|
| 23457 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
|---|
| 23458 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 23459 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
|---|
| 23460 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
|---|
| 23461 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 23462 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
|---|
| 23463 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
|---|
| 23464 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 23465 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
|---|
| 23466 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
|---|
| 23467 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 23468 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
|---|
| 23469 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 23470 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 23471 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
|---|
| 23472 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 23473 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 23474 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
|---|
| 23475 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 23476 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 23477 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
|---|
| 23478 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 23479 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 23480 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
|---|
| 23481 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 23482 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 23483 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
|---|
| 23484 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 23485 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 23486 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
|---|
| 23487 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 23488 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 23489 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
|---|
| 23490 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 23491 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 23492 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
|---|
| 23493 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 23494 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 23495 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 |
|---|
| 23496 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0 |
|---|
| 23497 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 23498 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 |
|---|
| 23499 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0 |
|---|
| 23500 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 23501 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 |
|---|
| 23502 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0 |
|---|
| 23503 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 23504 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 |
|---|
| 23505 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0 |
|---|
| 23506 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 23507 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 |
|---|
| 23508 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0 |
|---|
| 23509 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 23510 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 |
|---|
| 23511 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0 |
|---|
| 23512 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 23513 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 |
|---|
| 23514 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0 |
|---|
| 23515 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 23516 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 |
|---|
| 23517 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0 |
|---|
| 23518 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 23519 | //BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 |
|---|
| 23520 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0 |
|---|
| 23521 | #define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 23522 | |
|---|
| 23523 | |
|---|
| 23524 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
|---|
| 23525 | //BIF_CFG_DEV0_EPF1_VENDOR_ID |
|---|
| 23526 | #define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 23527 | #define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 23528 | //BIF_CFG_DEV0_EPF1_DEVICE_ID |
|---|
| 23529 | #define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 23530 | #define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 23531 | //BIF_CFG_DEV0_EPF1_COMMAND |
|---|
| 23532 | #define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 23533 | #define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 23534 | #define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 23535 | #define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 23536 | #define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 23537 | #define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 23538 | #define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 23539 | #define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 23540 | #define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 23541 | #define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 23542 | #define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 23543 | #define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 23544 | #define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 23545 | #define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 23546 | #define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 23547 | #define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 23548 | #define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 23549 | #define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 23550 | #define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 23551 | #define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 23552 | #define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 23553 | #define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 23554 | //BIF_CFG_DEV0_EPF1_STATUS |
|---|
| 23555 | #define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 23556 | #define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 23557 | #define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 23558 | #define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 23559 | #define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 23560 | #define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 23561 | #define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 23562 | #define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 23563 | #define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 23564 | #define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 23565 | #define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 23566 | #define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 23567 | #define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 23568 | #define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 23569 | #define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 23570 | #define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 23571 | #define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 23572 | #define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 23573 | #define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 23574 | #define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 23575 | #define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 23576 | #define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 23577 | #define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 23578 | #define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 23579 | //BIF_CFG_DEV0_EPF1_REVISION_ID |
|---|
| 23580 | #define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 23581 | #define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 23582 | #define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 23583 | #define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 23584 | //BIF_CFG_DEV0_EPF1_PROG_INTERFACE |
|---|
| 23585 | #define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 23586 | #define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 23587 | //BIF_CFG_DEV0_EPF1_SUB_CLASS |
|---|
| 23588 | #define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 23589 | #define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 23590 | //BIF_CFG_DEV0_EPF1_BASE_CLASS |
|---|
| 23591 | #define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 23592 | #define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 23593 | //BIF_CFG_DEV0_EPF1_CACHE_LINE |
|---|
| 23594 | #define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 23595 | #define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 23596 | //BIF_CFG_DEV0_EPF1_LATENCY |
|---|
| 23597 | #define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 23598 | #define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 23599 | //BIF_CFG_DEV0_EPF1_HEADER |
|---|
| 23600 | #define 0x0 |
|---|
| 23601 | #define 0x7 |
|---|
| 23602 | #define 0x7FL |
|---|
| 23603 | #define 0x80L |
|---|
| 23604 | //BIF_CFG_DEV0_EPF1_BIST |
|---|
| 23605 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 23606 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 23607 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 23608 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 23609 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 23610 | #define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 23611 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_1 |
|---|
| 23612 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 23613 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 23614 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_2 |
|---|
| 23615 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 23616 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 23617 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_3 |
|---|
| 23618 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 23619 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 23620 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_4 |
|---|
| 23621 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 23622 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 23623 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_5 |
|---|
| 23624 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 23625 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 23626 | //BIF_CFG_DEV0_EPF1_BASE_ADDR_6 |
|---|
| 23627 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 23628 | #define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 23629 | //BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR |
|---|
| 23630 | #define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 23631 | #define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 23632 | //BIF_CFG_DEV0_EPF1_ADAPTER_ID |
|---|
| 23633 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 23634 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 23635 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 23636 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 23637 | //BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR |
|---|
| 23638 | #define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 23639 | #define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 23640 | //BIF_CFG_DEV0_EPF1_CAP_PTR |
|---|
| 23641 | #define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 23642 | #define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 23643 | //BIF_CFG_DEV0_EPF1_INTERRUPT_LINE |
|---|
| 23644 | #define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 23645 | #define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 23646 | //BIF_CFG_DEV0_EPF1_INTERRUPT_PIN |
|---|
| 23647 | #define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 23648 | #define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 23649 | //BIF_CFG_DEV0_EPF1_MIN_GRANT |
|---|
| 23650 | #define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 23651 | #define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 23652 | //BIF_CFG_DEV0_EPF1_MAX_LATENCY |
|---|
| 23653 | #define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 23654 | #define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 23655 | //BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST |
|---|
| 23656 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 23657 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 23658 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 23659 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 23660 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 23661 | #define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 23662 | //BIF_CFG_DEV0_EPF1_ADAPTER_ID_W |
|---|
| 23663 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 23664 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 23665 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 23666 | #define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 23667 | //BIF_CFG_DEV0_EPF1_PMI_CAP_LIST |
|---|
| 23668 | #define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 23669 | #define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 23670 | #define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 23671 | #define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 23672 | //BIF_CFG_DEV0_EPF1_PMI_CAP |
|---|
| 23673 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 23674 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 23675 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 23676 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 23677 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 23678 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 23679 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 23680 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 23681 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 23682 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 23683 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 23684 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 23685 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 23686 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 23687 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 23688 | #define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 23689 | //BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL |
|---|
| 23690 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 23691 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 23692 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 23693 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 23694 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 23695 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 23696 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 23697 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 23698 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 23699 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 23700 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 23701 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 23702 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 23703 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 23704 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 23705 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 23706 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 23707 | #define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 23708 | //BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST |
|---|
| 23709 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 23710 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 23711 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 23712 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 23713 | //BIF_CFG_DEV0_EPF1_PCIE_CAP |
|---|
| 23714 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 23715 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 23716 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 23717 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 23718 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 23719 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 23720 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 23721 | #define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 23722 | //BIF_CFG_DEV0_EPF1_DEVICE_CAP |
|---|
| 23723 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 23724 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 23725 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 23726 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 23727 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 23728 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 23729 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 23730 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 23731 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 23732 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 23733 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 23734 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 23735 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 23736 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 23737 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 23738 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 23739 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 23740 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 23741 | //BIF_CFG_DEV0_EPF1_DEVICE_CNTL |
|---|
| 23742 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 23743 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 23744 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 23745 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 23746 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 23747 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 23748 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 23749 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 23750 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 23751 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 23752 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 23753 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 23754 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 23755 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 23756 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 23757 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 23758 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 23759 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 23760 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 23761 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 23762 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 23763 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 23764 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 23765 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 23766 | //BIF_CFG_DEV0_EPF1_DEVICE_STATUS |
|---|
| 23767 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 23768 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 23769 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 23770 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 23771 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 23772 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 23773 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 23774 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 23775 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 23776 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 23777 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 23778 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 23779 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 23780 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 23781 | //BIF_CFG_DEV0_EPF1_LINK_CAP |
|---|
| 23782 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 23783 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 23784 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 23785 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 23786 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 23787 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 23788 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 23789 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 23790 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 23791 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 23792 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 23793 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 23794 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 23795 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 23796 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 23797 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 23798 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 23799 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 23800 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 23801 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 23802 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 23803 | #define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 23804 | //BIF_CFG_DEV0_EPF1_LINK_CNTL |
|---|
| 23805 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 23806 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 23807 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 23808 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 23809 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 23810 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 23811 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 23812 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 23813 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 23814 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 23815 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 23816 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 23817 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 23818 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 23819 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 23820 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 23821 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 23822 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 23823 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 23824 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 23825 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 23826 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 23827 | //BIF_CFG_DEV0_EPF1_LINK_STATUS |
|---|
| 23828 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 23829 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 23830 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 23831 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 23832 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 23833 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 23834 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 23835 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 23836 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 23837 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 23838 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 23839 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 23840 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 23841 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 23842 | //BIF_CFG_DEV0_EPF1_DEVICE_CAP2 |
|---|
| 23843 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 23844 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 23845 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 23846 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 23847 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 23848 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 23849 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 23850 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 23851 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 23852 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 23853 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 23854 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 23855 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 23856 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 23857 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 23858 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 23859 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 23860 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 23861 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 23862 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 23863 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 23864 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 23865 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 23866 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 23867 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 23868 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 23869 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 23870 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 23871 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 23872 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 23873 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 23874 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 23875 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 23876 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 23877 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 23878 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 23879 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 23880 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 23881 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 23882 | #define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 23883 | //BIF_CFG_DEV0_EPF1_DEVICE_CNTL2 |
|---|
| 23884 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 23885 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 23886 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 23887 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 23888 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 23889 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 23890 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 23891 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 23892 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 23893 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 23894 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 23895 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 23896 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 23897 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 23898 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 23899 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 23900 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 23901 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 23902 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 23903 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 23904 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 23905 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 23906 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 23907 | #define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 23908 | //BIF_CFG_DEV0_EPF1_DEVICE_STATUS2 |
|---|
| 23909 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 23910 | #define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 23911 | //BIF_CFG_DEV0_EPF1_LINK_CAP2 |
|---|
| 23912 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 23913 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 23914 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 23915 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 23916 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 23917 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 23918 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 23919 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 23920 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 23921 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 23922 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 23923 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 23924 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 23925 | #define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 23926 | //BIF_CFG_DEV0_EPF1_LINK_CNTL2 |
|---|
| 23927 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 23928 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 23929 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 23930 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 23931 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 23932 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 23933 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 23934 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 23935 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 23936 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 23937 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 23938 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 23939 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 23940 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 23941 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 23942 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 23943 | //BIF_CFG_DEV0_EPF1_LINK_STATUS2 |
|---|
| 23944 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 23945 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 23946 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 23947 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 23948 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 23949 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 23950 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 23951 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 23952 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 23953 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 23954 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 23955 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 23956 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 23957 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 23958 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 23959 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 23960 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 23961 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 23962 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 23963 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 23964 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 23965 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 23966 | //BIF_CFG_DEV0_EPF1_MSI_CAP_LIST |
|---|
| 23967 | #define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 23968 | #define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 23969 | #define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 23970 | #define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 23971 | //BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL |
|---|
| 23972 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 23973 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 23974 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 23975 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 23976 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 23977 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 23978 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 23979 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 23980 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 23981 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 23982 | //BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO |
|---|
| 23983 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 23984 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 23985 | //BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI |
|---|
| 23986 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 23987 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 23988 | //BIF_CFG_DEV0_EPF1_MSI_MSG_DATA |
|---|
| 23989 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 23990 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 23991 | //BIF_CFG_DEV0_EPF1_MSI_MASK |
|---|
| 23992 | #define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 23993 | #define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 23994 | //BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 |
|---|
| 23995 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 23996 | #define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 23997 | //BIF_CFG_DEV0_EPF1_MSI_MASK_64 |
|---|
| 23998 | #define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 23999 | #define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 24000 | //BIF_CFG_DEV0_EPF1_MSI_PENDING |
|---|
| 24001 | #define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 24002 | #define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 24003 | //BIF_CFG_DEV0_EPF1_MSI_PENDING_64 |
|---|
| 24004 | #define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 24005 | #define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 24006 | //BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST |
|---|
| 24007 | #define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24008 | #define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 24009 | #define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 24010 | #define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 24011 | //BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL |
|---|
| 24012 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 24013 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 24014 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 24015 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 24016 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 24017 | #define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 24018 | //BIF_CFG_DEV0_EPF1_MSIX_TABLE |
|---|
| 24019 | #define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 24020 | #define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 24021 | #define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 24022 | #define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 24023 | //BIF_CFG_DEV0_EPF1_MSIX_PBA |
|---|
| 24024 | #define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 24025 | #define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 24026 | #define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 24027 | #define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 24028 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 24029 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24030 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24031 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24032 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24033 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24034 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24035 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 24036 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 24037 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 24038 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 24039 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 24040 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 24041 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 24042 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 24043 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 24044 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 24045 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 24046 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 24047 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 24048 | //BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST |
|---|
| 24049 | #define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24050 | #define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24051 | #define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24052 | #define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24053 | #define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24054 | #define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24055 | //BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1 |
|---|
| 24056 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 24057 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 24058 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 24059 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 24060 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 24061 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 24062 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 24063 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 24064 | //BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2 |
|---|
| 24065 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 24066 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 24067 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 24068 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 24069 | //BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL |
|---|
| 24070 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 24071 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 24072 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 24073 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 24074 | //BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS |
|---|
| 24075 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 24076 | #define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 24077 | //BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP |
|---|
| 24078 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 24079 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 24080 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 24081 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 24082 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 24083 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 24084 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 24085 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 24086 | //BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL |
|---|
| 24087 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 24088 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 24089 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 24090 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 24091 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 24092 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 24093 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 24094 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 24095 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 24096 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 24097 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 24098 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 24099 | //BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS |
|---|
| 24100 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 24101 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 24102 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 24103 | #define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 24104 | //BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP |
|---|
| 24105 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 24106 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 24107 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 24108 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 24109 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 24110 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 24111 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 24112 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 24113 | //BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL |
|---|
| 24114 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 24115 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 24116 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 24117 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 24118 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 24119 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 24120 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 24121 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 24122 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 24123 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 24124 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 24125 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 24126 | //BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS |
|---|
| 24127 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 24128 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 24129 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 24130 | #define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 24131 | //BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 24132 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24133 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24134 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24135 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24136 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24137 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24138 | //BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 24139 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 24140 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 24141 | //BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 24142 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 24143 | #define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 24144 | //BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 24145 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24146 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24147 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24148 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24149 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24150 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24151 | //BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS |
|---|
| 24152 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 24153 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 24154 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 24155 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 24156 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 24157 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 24158 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 24159 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 24160 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 24161 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 24162 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 24163 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 24164 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 24165 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 24166 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 24167 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 24168 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 24169 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 24170 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 24171 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 24172 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 24173 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 24174 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 24175 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 24176 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 24177 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 24178 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 24179 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 24180 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 24181 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 24182 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 24183 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 24184 | //BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK |
|---|
| 24185 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 24186 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 24187 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 24188 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 24189 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 24190 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 24191 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 24192 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 24193 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 24194 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 24195 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 24196 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 24197 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 24198 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 24199 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 24200 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 24201 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 24202 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 24203 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 24204 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 24205 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 24206 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 24207 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 24208 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 24209 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 24210 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 24211 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 24212 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 24213 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 24214 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 24215 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 24216 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 24217 | //BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 24218 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 24219 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 24220 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 24221 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 24222 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 24223 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 24224 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 24225 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 24226 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 24227 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 24228 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 24229 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 24230 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 24231 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 24232 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 24233 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 24234 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 24235 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 24236 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 24237 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 24238 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 24239 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 24240 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 24241 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 24242 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 24243 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 24244 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 24245 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 24246 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 24247 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 24248 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 24249 | #define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 24250 | //BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS |
|---|
| 24251 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 24252 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 24253 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 24254 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 24255 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 24256 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 24257 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 24258 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 24259 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 24260 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 24261 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 24262 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 24263 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 24264 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 24265 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 24266 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 24267 | //BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK |
|---|
| 24268 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 24269 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 24270 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 24271 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 24272 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 24273 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 24274 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 24275 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 24276 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 24277 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 24278 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 24279 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 24280 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 24281 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 24282 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 24283 | #define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 24284 | //BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 24285 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 24286 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 24287 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 24288 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 24289 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 24290 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 24291 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 24292 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 24293 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 24294 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 24295 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 24296 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 24297 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 24298 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 24299 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 24300 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 24301 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 24302 | #define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 24303 | //BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 |
|---|
| 24304 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 24305 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 24306 | //BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 |
|---|
| 24307 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 24308 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 24309 | //BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 |
|---|
| 24310 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 24311 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 24312 | //BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 |
|---|
| 24313 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 24314 | #define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 24315 | //BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 24316 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 24317 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 24318 | //BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 24319 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 24320 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 24321 | //BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 24322 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 24323 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 24324 | //BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 24325 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 24326 | #define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 24327 | //BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST |
|---|
| 24328 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24329 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24330 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24331 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24332 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24333 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24334 | //BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP |
|---|
| 24335 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 24336 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 24337 | //BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL |
|---|
| 24338 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 24339 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 24340 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 24341 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 24342 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 24343 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 24344 | //BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP |
|---|
| 24345 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 24346 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 24347 | //BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL |
|---|
| 24348 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 24349 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 24350 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 24351 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 24352 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 24353 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 24354 | //BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP |
|---|
| 24355 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 24356 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 24357 | //BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL |
|---|
| 24358 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 24359 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 24360 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 24361 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 24362 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 24363 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 24364 | //BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP |
|---|
| 24365 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 24366 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 24367 | //BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL |
|---|
| 24368 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 24369 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 24370 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 24371 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 24372 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 24373 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 24374 | //BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP |
|---|
| 24375 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 24376 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 24377 | //BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL |
|---|
| 24378 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 24379 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 24380 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 24381 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 24382 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 24383 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 24384 | //BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP |
|---|
| 24385 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 24386 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 24387 | //BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL |
|---|
| 24388 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 24389 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 24390 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 24391 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 24392 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 24393 | #define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 24394 | //BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 24395 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24396 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24397 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24398 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24399 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24400 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24401 | //BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 24402 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 24403 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 24404 | //BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA |
|---|
| 24405 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 24406 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 24407 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 24408 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 24409 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 24410 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 24411 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 24412 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 24413 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 24414 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 24415 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 24416 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 24417 | //BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP |
|---|
| 24418 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 24419 | #define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 24420 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST |
|---|
| 24421 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24422 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24423 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24424 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24425 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24426 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24427 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP |
|---|
| 24428 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 24429 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 24430 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 24431 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 24432 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 24433 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 24434 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 24435 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 24436 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 24437 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 24438 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 24439 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 24440 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 24441 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS |
|---|
| 24442 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 24443 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 24444 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 24445 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 24446 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL |
|---|
| 24447 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 24448 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 24449 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 24450 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 24451 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 24452 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 24453 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 24454 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 24455 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 24456 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 24457 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 24458 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 24459 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 24460 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 24461 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 24462 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 24463 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 24464 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 24465 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 24466 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 24467 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 24468 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 24469 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 24470 | //BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 24471 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 24472 | #define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 24473 | //BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 24474 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24475 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24476 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24477 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24478 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24479 | #define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24480 | //BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 |
|---|
| 24481 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 24482 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
|---|
| 24483 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
|---|
| 24484 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 24485 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 24486 | #define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
|---|
| 24487 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS |
|---|
| 24488 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 24489 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
|---|
| 24490 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 24491 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
|---|
| 24492 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 24493 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24494 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24495 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24496 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24497 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24498 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24499 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24500 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24501 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24502 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24503 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL |
|---|
| 24504 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24505 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24506 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24507 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24508 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24509 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24510 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24511 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24512 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24513 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24514 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL |
|---|
| 24515 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24516 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24517 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24518 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24519 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24520 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24521 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24522 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24523 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24524 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24525 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL |
|---|
| 24526 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24527 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24528 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24529 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24530 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24531 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24532 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24533 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24534 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24535 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24536 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL |
|---|
| 24537 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24538 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24539 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24540 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24541 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24542 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24543 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24544 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24545 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24546 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24547 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 24548 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24549 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24550 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24551 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24552 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24553 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24554 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24555 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24556 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24557 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24558 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 24559 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24560 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24561 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24562 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24563 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24564 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24565 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24566 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24567 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24568 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24569 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 24570 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24571 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24572 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24573 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24574 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24575 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24576 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24577 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24578 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24579 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24580 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 24581 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24582 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24583 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24584 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24585 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24586 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24587 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24588 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24589 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24590 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24591 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 24592 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24593 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24594 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24595 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24596 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24597 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24598 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24599 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24600 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24601 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24602 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 24603 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24604 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24605 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24606 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24607 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24608 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24609 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24610 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24611 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24612 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24613 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 24614 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24615 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24616 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24617 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24618 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24619 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24620 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24621 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24622 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24623 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24624 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 24625 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24626 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24627 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24628 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24629 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24630 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24631 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24632 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24633 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24634 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24635 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 24636 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24637 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24638 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24639 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24640 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24641 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24642 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24643 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24644 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24645 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24646 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 24647 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24648 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24649 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24650 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24651 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24652 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24653 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24654 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24655 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24656 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24657 | //BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 24658 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 24659 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 24660 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 24661 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 24662 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 24663 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 24664 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 24665 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 24666 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 24667 | #define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 24668 | //BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST |
|---|
| 24669 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24670 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24671 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24672 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24673 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24674 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24675 | //BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP |
|---|
| 24676 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 24677 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 24678 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 24679 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 24680 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 24681 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 24682 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 24683 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 24684 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 24685 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 24686 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 24687 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 24688 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 24689 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 24690 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 24691 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 24692 | //BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL |
|---|
| 24693 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 24694 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 24695 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 24696 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 24697 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 24698 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 24699 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 24700 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 24701 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 24702 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 24703 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 24704 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 24705 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 24706 | #define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 24707 | //BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 24708 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24709 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24710 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24711 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24712 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24713 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24714 | //BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP |
|---|
| 24715 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 24716 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 24717 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 24718 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 24719 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 24720 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 24721 | //BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL |
|---|
| 24722 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 24723 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 24724 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 24725 | #define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 24726 | //BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST |
|---|
| 24727 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24728 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24729 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24730 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24731 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24732 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24733 | //BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL |
|---|
| 24734 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
|---|
| 24735 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
|---|
| 24736 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
|---|
| 24737 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
|---|
| 24738 | //BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS |
|---|
| 24739 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
|---|
| 24740 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
|---|
| 24741 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
|---|
| 24742 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
|---|
| 24743 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
|---|
| 24744 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
|---|
| 24745 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
|---|
| 24746 | #define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
|---|
| 24747 | //BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
|---|
| 24748 | #define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
|---|
| 24749 | #define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
|---|
| 24750 | //BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
|---|
| 24751 | #define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
|---|
| 24752 | #define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
|---|
| 24753 | //BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST |
|---|
| 24754 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24755 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24756 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24757 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24758 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24759 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24760 | //BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP |
|---|
| 24761 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 24762 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 24763 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 24764 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 24765 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 24766 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 24767 | //BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL |
|---|
| 24768 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 24769 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 24770 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 24771 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 24772 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 24773 | #define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 24774 | //BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST |
|---|
| 24775 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24776 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24777 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24778 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24779 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24780 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24781 | //BIF_CFG_DEV0_EPF1_PCIE_MC_CAP |
|---|
| 24782 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
|---|
| 24783 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
|---|
| 24784 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
|---|
| 24785 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
|---|
| 24786 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
|---|
| 24787 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
|---|
| 24788 | //BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL |
|---|
| 24789 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
|---|
| 24790 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
|---|
| 24791 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
|---|
| 24792 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
|---|
| 24793 | //BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0 |
|---|
| 24794 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
|---|
| 24795 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
|---|
| 24796 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
|---|
| 24797 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
|---|
| 24798 | //BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1 |
|---|
| 24799 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
|---|
| 24800 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
|---|
| 24801 | //BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0 |
|---|
| 24802 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
|---|
| 24803 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
|---|
| 24804 | //BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1 |
|---|
| 24805 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
|---|
| 24806 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
|---|
| 24807 | //BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0 |
|---|
| 24808 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
|---|
| 24809 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
|---|
| 24810 | //BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1 |
|---|
| 24811 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
|---|
| 24812 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
|---|
| 24813 | //BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
|---|
| 24814 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
|---|
| 24815 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
|---|
| 24816 | //BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
|---|
| 24817 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
|---|
| 24818 | #define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
|---|
| 24819 | //BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST |
|---|
| 24820 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24821 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24822 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24823 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24824 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24825 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24826 | //BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP |
|---|
| 24827 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 24828 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
|---|
| 24829 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 24830 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 24831 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 24832 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 24833 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 24834 | #define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 24835 | //BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 24836 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24837 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24838 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24839 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24840 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24841 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24842 | //BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP |
|---|
| 24843 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 24844 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 24845 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 24846 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 24847 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 24848 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 24849 | //BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL |
|---|
| 24850 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 24851 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 24852 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 24853 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 24854 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 24855 | #define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 24856 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST |
|---|
| 24857 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24858 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24859 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24860 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24861 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24862 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24863 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP |
|---|
| 24864 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
|---|
| 24865 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
|---|
| 24866 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
|---|
| 24867 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
|---|
| 24868 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
|---|
| 24869 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
|---|
| 24870 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
|---|
| 24871 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
|---|
| 24872 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL |
|---|
| 24873 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
|---|
| 24874 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
|---|
| 24875 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
|---|
| 24876 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
|---|
| 24877 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
|---|
| 24878 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
|---|
| 24879 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
|---|
| 24880 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
|---|
| 24881 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
|---|
| 24882 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
|---|
| 24883 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
|---|
| 24884 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
|---|
| 24885 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS |
|---|
| 24886 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
|---|
| 24887 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
|---|
| 24888 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS |
|---|
| 24889 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
|---|
| 24890 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
|---|
| 24891 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS |
|---|
| 24892 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
|---|
| 24893 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
|---|
| 24894 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS |
|---|
| 24895 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
|---|
| 24896 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
|---|
| 24897 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK |
|---|
| 24898 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
|---|
| 24899 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
|---|
| 24900 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET |
|---|
| 24901 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
|---|
| 24902 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
|---|
| 24903 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE |
|---|
| 24904 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
|---|
| 24905 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
|---|
| 24906 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID |
|---|
| 24907 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
|---|
| 24908 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
|---|
| 24909 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
|---|
| 24910 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
|---|
| 24911 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 24912 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
|---|
| 24913 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
|---|
| 24914 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 24915 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 |
|---|
| 24916 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 24917 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 24918 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 |
|---|
| 24919 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 24920 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 24921 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 |
|---|
| 24922 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 24923 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 24924 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 |
|---|
| 24925 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 24926 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 24927 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 |
|---|
| 24928 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 24929 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 24930 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 |
|---|
| 24931 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 24932 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 24933 | //BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
|---|
| 24934 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 |
|---|
| 24935 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
|---|
| 24936 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L |
|---|
| 24937 | #define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 24938 | //BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 24939 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24940 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24941 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24942 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24943 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24944 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24945 | //BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP |
|---|
| 24946 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 24947 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 24948 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 24949 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 24950 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 24951 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 24952 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 24953 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 24954 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 24955 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 24956 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 24957 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 24958 | //BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL |
|---|
| 24959 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 24960 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 24961 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 24962 | #define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 24963 | //BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST |
|---|
| 24964 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24965 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24966 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24967 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24968 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24969 | #define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24970 | //BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP |
|---|
| 24971 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 24972 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
|---|
| 24973 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 24974 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
|---|
| 24975 | //BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS |
|---|
| 24976 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 24977 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
|---|
| 24978 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 24979 | #define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
|---|
| 24980 | //BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST |
|---|
| 24981 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 24982 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 24983 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 24984 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 24985 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 24986 | #define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 24987 | //BIF_CFG_DEV0_EPF1_LINK_CAP_16GT |
|---|
| 24988 | #define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
|---|
| 24989 | #define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 24990 | //BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT |
|---|
| 24991 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
|---|
| 24992 | #define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 24993 | //BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT |
|---|
| 24994 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
|---|
| 24995 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
|---|
| 24996 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
|---|
| 24997 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
|---|
| 24998 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
|---|
| 24999 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
|---|
| 25000 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
|---|
| 25001 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
|---|
| 25002 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
|---|
| 25003 | #define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
|---|
| 25004 | //BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT |
|---|
| 25005 | #define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 25006 | #define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 25007 | //BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT |
|---|
| 25008 | #define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 25009 | #define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 25010 | //BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT |
|---|
| 25011 | #define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 25012 | #define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 25013 | //BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT |
|---|
| 25014 | #define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25015 | #define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25016 | #define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25017 | #define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25018 | //BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT |
|---|
| 25019 | #define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25020 | #define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25021 | #define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25022 | #define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25023 | //BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT |
|---|
| 25024 | #define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25025 | #define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25026 | #define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25027 | #define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25028 | //BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT |
|---|
| 25029 | #define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25030 | #define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25031 | #define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25032 | #define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25033 | //BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT |
|---|
| 25034 | #define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25035 | #define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25036 | #define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25037 | #define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25038 | //BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT |
|---|
| 25039 | #define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25040 | #define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25041 | #define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25042 | #define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25043 | //BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT |
|---|
| 25044 | #define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25045 | #define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25046 | #define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25047 | #define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25048 | //BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT |
|---|
| 25049 | #define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25050 | #define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25051 | #define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25052 | #define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25053 | //BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT |
|---|
| 25054 | #define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25055 | #define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25056 | #define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25057 | #define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25058 | //BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT |
|---|
| 25059 | #define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25060 | #define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25061 | #define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25062 | #define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25063 | //BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT |
|---|
| 25064 | #define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25065 | #define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25066 | #define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25067 | #define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25068 | //BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT |
|---|
| 25069 | #define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25070 | #define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25071 | #define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25072 | #define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25073 | //BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT |
|---|
| 25074 | #define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25075 | #define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25076 | #define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25077 | #define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25078 | //BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT |
|---|
| 25079 | #define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25080 | #define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25081 | #define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25082 | #define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25083 | //BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 25084 | #define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25085 | #define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25086 | #define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25087 | #define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25088 | //BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 25089 | #define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 25090 | #define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 25091 | #define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 25092 | #define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 25093 | //BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 25094 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 25095 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 25096 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 25097 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 25098 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 25099 | #define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 25100 | //BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP |
|---|
| 25101 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 25102 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 25103 | //BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS |
|---|
| 25104 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
|---|
| 25105 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
|---|
| 25106 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
|---|
| 25107 | #define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
|---|
| 25108 | //BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL |
|---|
| 25109 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25110 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25111 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25112 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25113 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25114 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25115 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 25116 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25117 | //BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS |
|---|
| 25118 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25119 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25120 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25121 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25122 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25123 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25124 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25125 | #define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25126 | //BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL |
|---|
| 25127 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25128 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25129 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25130 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25131 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25132 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25133 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 25134 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25135 | //BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS |
|---|
| 25136 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25137 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25138 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25139 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25140 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25141 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25142 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25143 | #define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25144 | //BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL |
|---|
| 25145 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25146 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25147 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25148 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25149 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25150 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25151 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 25152 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25153 | //BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS |
|---|
| 25154 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25155 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25156 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25157 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25158 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25159 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25160 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25161 | #define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25162 | //BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL |
|---|
| 25163 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25164 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25165 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25166 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25167 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25168 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25169 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 25170 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25171 | //BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS |
|---|
| 25172 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25173 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25174 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25175 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25176 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25177 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25178 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25179 | #define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25180 | //BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL |
|---|
| 25181 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25182 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25183 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25184 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25185 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25186 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25187 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 25188 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25189 | //BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS |
|---|
| 25190 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25191 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25192 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25193 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25194 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25195 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25196 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25197 | #define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25198 | //BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL |
|---|
| 25199 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25200 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25201 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25202 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25203 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25204 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25205 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 25206 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25207 | //BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS |
|---|
| 25208 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25209 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25210 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25211 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25212 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25213 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25214 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25215 | #define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25216 | //BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL |
|---|
| 25217 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25218 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25219 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25220 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25221 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25222 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25223 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 25224 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25225 | //BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS |
|---|
| 25226 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25227 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25228 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25229 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25230 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25231 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25232 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25233 | #define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25234 | //BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL |
|---|
| 25235 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25236 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25237 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25238 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25239 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25240 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25241 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 25242 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25243 | //BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS |
|---|
| 25244 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25245 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25246 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25247 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25248 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25249 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25250 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25251 | #define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25252 | //BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL |
|---|
| 25253 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25254 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25255 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25256 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25257 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25258 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25259 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 25260 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25261 | //BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS |
|---|
| 25262 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25263 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25264 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25265 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25266 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25267 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25268 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25269 | #define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25270 | //BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL |
|---|
| 25271 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25272 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25273 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25274 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25275 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25276 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25277 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 25278 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25279 | //BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS |
|---|
| 25280 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25281 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25282 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25283 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25284 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25285 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25286 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25287 | #define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25288 | //BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL |
|---|
| 25289 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25290 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25291 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25292 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25293 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25294 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25295 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 25296 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25297 | //BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS |
|---|
| 25298 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25299 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25300 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25301 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25302 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25303 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25304 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25305 | #define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25306 | //BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL |
|---|
| 25307 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25308 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25309 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25310 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25311 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25312 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25313 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 25314 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25315 | //BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS |
|---|
| 25316 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25317 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25318 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25319 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25320 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25321 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25322 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25323 | #define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25324 | //BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL |
|---|
| 25325 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25326 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25327 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25328 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25329 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25330 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25331 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 25332 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25333 | //BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS |
|---|
| 25334 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25335 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25336 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25337 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25338 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25339 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25340 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25341 | #define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25342 | //BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL |
|---|
| 25343 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25344 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25345 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25346 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25347 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25348 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25349 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 25350 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25351 | //BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS |
|---|
| 25352 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25353 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25354 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25355 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25356 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25357 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25358 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25359 | #define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25360 | //BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL |
|---|
| 25361 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25362 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25363 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25364 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25365 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25366 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25367 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 25368 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25369 | //BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS |
|---|
| 25370 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25371 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25372 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25373 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25374 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25375 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25376 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25377 | #define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25378 | //BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL |
|---|
| 25379 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 25380 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 25381 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 25382 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 25383 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 25384 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 25385 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 25386 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 25387 | //BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS |
|---|
| 25388 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 25389 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 25390 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 25391 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 25392 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 25393 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 25394 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 25395 | #define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 25396 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
|---|
| 25397 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 25398 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 25399 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 25400 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 25401 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 25402 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 25403 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP |
|---|
| 25404 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 25405 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 25406 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL |
|---|
| 25407 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 25408 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 25409 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 25410 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 25411 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 25412 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 25413 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP |
|---|
| 25414 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 25415 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 25416 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL |
|---|
| 25417 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 25418 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 25419 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 25420 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 25421 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 25422 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 25423 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP |
|---|
| 25424 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 25425 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 25426 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL |
|---|
| 25427 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 25428 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 25429 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 25430 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 25431 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 25432 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 25433 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP |
|---|
| 25434 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 25435 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 25436 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL |
|---|
| 25437 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 25438 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 25439 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 25440 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 25441 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 25442 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 25443 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP |
|---|
| 25444 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 25445 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 25446 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL |
|---|
| 25447 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 25448 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 25449 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 25450 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 25451 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 25452 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 25453 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP |
|---|
| 25454 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 25455 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 25456 | //BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL |
|---|
| 25457 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 25458 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 25459 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 25460 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 25461 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 25462 | #define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 25463 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
|---|
| 25464 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
|---|
| 25465 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
|---|
| 25466 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
|---|
| 25467 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
|---|
| 25468 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
|---|
| 25469 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 25470 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
|---|
| 25471 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
|---|
| 25472 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
|---|
| 25473 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 25474 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 25475 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
|---|
| 25476 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 25477 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
|---|
| 25478 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
|---|
| 25479 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
|---|
| 25480 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
|---|
| 25481 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
|---|
| 25482 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
|---|
| 25483 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
|---|
| 25484 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
|---|
| 25485 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
|---|
| 25486 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
|---|
| 25487 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
|---|
| 25488 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
|---|
| 25489 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
|---|
| 25490 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
|---|
| 25491 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc |
|---|
| 25492 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd |
|---|
| 25493 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe |
|---|
| 25494 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf |
|---|
| 25495 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
|---|
| 25496 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
|---|
| 25497 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
|---|
| 25498 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
|---|
| 25499 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
|---|
| 25500 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
|---|
| 25501 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
|---|
| 25502 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
|---|
| 25503 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
|---|
| 25504 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
|---|
| 25505 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
|---|
| 25506 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
|---|
| 25507 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
|---|
| 25508 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
|---|
| 25509 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L |
|---|
| 25510 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L |
|---|
| 25511 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L |
|---|
| 25512 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L |
|---|
| 25513 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
|---|
| 25514 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
|---|
| 25515 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
|---|
| 25516 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
|---|
| 25517 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
|---|
| 25518 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
|---|
| 25519 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
|---|
| 25520 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
|---|
| 25521 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
|---|
| 25522 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
|---|
| 25523 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
|---|
| 25524 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
|---|
| 25525 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
|---|
| 25526 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
|---|
| 25527 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
|---|
| 25528 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc |
|---|
| 25529 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd |
|---|
| 25530 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe |
|---|
| 25531 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf |
|---|
| 25532 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
|---|
| 25533 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
|---|
| 25534 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
|---|
| 25535 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
|---|
| 25536 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
|---|
| 25537 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
|---|
| 25538 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
|---|
| 25539 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
|---|
| 25540 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
|---|
| 25541 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
|---|
| 25542 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
|---|
| 25543 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
|---|
| 25544 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
|---|
| 25545 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
|---|
| 25546 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L |
|---|
| 25547 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L |
|---|
| 25548 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L |
|---|
| 25549 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L |
|---|
| 25550 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
|---|
| 25551 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
|---|
| 25552 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
|---|
| 25553 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
|---|
| 25554 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
|---|
| 25555 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
|---|
| 25556 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
|---|
| 25557 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
|---|
| 25558 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
|---|
| 25559 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
|---|
| 25560 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
|---|
| 25561 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 25562 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
|---|
| 25563 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 25564 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
|---|
| 25565 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
|---|
| 25566 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 25567 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 25568 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 25569 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
|---|
| 25570 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
|---|
| 25571 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
|---|
| 25572 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
|---|
| 25573 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
|---|
| 25574 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
|---|
| 25575 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
|---|
| 25576 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
|---|
| 25577 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
|---|
| 25578 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
|---|
| 25579 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
|---|
| 25580 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
|---|
| 25581 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
|---|
| 25582 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
|---|
| 25583 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
|---|
| 25584 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
|---|
| 25585 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
|---|
| 25586 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
|---|
| 25587 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
|---|
| 25588 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
|---|
| 25589 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
|---|
| 25590 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
|---|
| 25591 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
|---|
| 25592 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
|---|
| 25593 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
|---|
| 25594 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
|---|
| 25595 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
|---|
| 25596 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
|---|
| 25597 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
|---|
| 25598 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
|---|
| 25599 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
|---|
| 25600 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
|---|
| 25601 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
|---|
| 25602 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
|---|
| 25603 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
|---|
| 25604 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
|---|
| 25605 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
|---|
| 25606 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
|---|
| 25607 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
|---|
| 25608 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
|---|
| 25609 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
|---|
| 25610 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
|---|
| 25611 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
|---|
| 25612 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
|---|
| 25613 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
|---|
| 25614 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
|---|
| 25615 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
|---|
| 25616 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
|---|
| 25617 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
|---|
| 25618 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
|---|
| 25619 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
|---|
| 25620 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
|---|
| 25621 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
|---|
| 25622 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
|---|
| 25623 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
|---|
| 25624 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
|---|
| 25625 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
|---|
| 25626 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
|---|
| 25627 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
|---|
| 25628 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
|---|
| 25629 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
|---|
| 25630 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
|---|
| 25631 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
|---|
| 25632 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
|---|
| 25633 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
|---|
| 25634 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
|---|
| 25635 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
|---|
| 25636 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 |
|---|
| 25637 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 |
|---|
| 25638 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 |
|---|
| 25639 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 |
|---|
| 25640 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 |
|---|
| 25641 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 |
|---|
| 25642 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 |
|---|
| 25643 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 |
|---|
| 25644 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 |
|---|
| 25645 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 |
|---|
| 25646 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa |
|---|
| 25647 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb |
|---|
| 25648 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc |
|---|
| 25649 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd |
|---|
| 25650 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe |
|---|
| 25651 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf |
|---|
| 25652 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 |
|---|
| 25653 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 |
|---|
| 25654 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 |
|---|
| 25655 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 |
|---|
| 25656 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 |
|---|
| 25657 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 |
|---|
| 25658 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 |
|---|
| 25659 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 |
|---|
| 25660 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 |
|---|
| 25661 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 |
|---|
| 25662 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a |
|---|
| 25663 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b |
|---|
| 25664 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c |
|---|
| 25665 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d |
|---|
| 25666 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e |
|---|
| 25667 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f |
|---|
| 25668 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L |
|---|
| 25669 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L |
|---|
| 25670 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L |
|---|
| 25671 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L |
|---|
| 25672 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L |
|---|
| 25673 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L |
|---|
| 25674 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L |
|---|
| 25675 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L |
|---|
| 25676 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L |
|---|
| 25677 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L |
|---|
| 25678 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L |
|---|
| 25679 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L |
|---|
| 25680 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L |
|---|
| 25681 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L |
|---|
| 25682 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L |
|---|
| 25683 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L |
|---|
| 25684 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L |
|---|
| 25685 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L |
|---|
| 25686 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L |
|---|
| 25687 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L |
|---|
| 25688 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L |
|---|
| 25689 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L |
|---|
| 25690 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L |
|---|
| 25691 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L |
|---|
| 25692 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L |
|---|
| 25693 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L |
|---|
| 25694 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L |
|---|
| 25695 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L |
|---|
| 25696 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L |
|---|
| 25697 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L |
|---|
| 25698 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L |
|---|
| 25699 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L |
|---|
| 25700 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
|---|
| 25701 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
|---|
| 25702 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
|---|
| 25703 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
|---|
| 25704 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
|---|
| 25705 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
|---|
| 25706 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
|---|
| 25707 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
|---|
| 25708 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
|---|
| 25709 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
|---|
| 25710 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
|---|
| 25711 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
|---|
| 25712 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
|---|
| 25713 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
|---|
| 25714 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
|---|
| 25715 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
|---|
| 25716 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18 |
|---|
| 25717 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
|---|
| 25718 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
|---|
| 25719 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
|---|
| 25720 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L |
|---|
| 25721 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION |
|---|
| 25722 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 |
|---|
| 25723 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 |
|---|
| 25724 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L |
|---|
| 25725 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L |
|---|
| 25726 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE |
|---|
| 25727 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 |
|---|
| 25728 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f |
|---|
| 25729 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL |
|---|
| 25730 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L |
|---|
| 25731 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
|---|
| 25732 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
|---|
| 25733 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
|---|
| 25734 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25735 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25736 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
|---|
| 25737 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
|---|
| 25738 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
|---|
| 25739 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25740 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25741 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
|---|
| 25742 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
|---|
| 25743 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
|---|
| 25744 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25745 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25746 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
|---|
| 25747 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
|---|
| 25748 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
|---|
| 25749 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25750 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25751 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
|---|
| 25752 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
|---|
| 25753 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
|---|
| 25754 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25755 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25756 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
|---|
| 25757 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
|---|
| 25758 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
|---|
| 25759 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25760 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25761 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
|---|
| 25762 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
|---|
| 25763 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
|---|
| 25764 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25765 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25766 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
|---|
| 25767 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
|---|
| 25768 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
|---|
| 25769 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25770 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25771 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
|---|
| 25772 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
|---|
| 25773 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
|---|
| 25774 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25775 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25776 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
|---|
| 25777 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
|---|
| 25778 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
|---|
| 25779 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25780 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25781 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
|---|
| 25782 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
|---|
| 25783 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
|---|
| 25784 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25785 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25786 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
|---|
| 25787 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
|---|
| 25788 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
|---|
| 25789 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25790 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25791 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
|---|
| 25792 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
|---|
| 25793 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
|---|
| 25794 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25795 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25796 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
|---|
| 25797 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
|---|
| 25798 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
|---|
| 25799 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25800 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25801 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
|---|
| 25802 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
|---|
| 25803 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
|---|
| 25804 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25805 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25806 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
|---|
| 25807 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
|---|
| 25808 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
|---|
| 25809 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25810 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25811 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB |
|---|
| 25812 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0 |
|---|
| 25813 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10 |
|---|
| 25814 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25815 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25816 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB |
|---|
| 25817 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0 |
|---|
| 25818 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10 |
|---|
| 25819 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25820 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25821 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB |
|---|
| 25822 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0 |
|---|
| 25823 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10 |
|---|
| 25824 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25825 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25826 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB |
|---|
| 25827 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0 |
|---|
| 25828 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10 |
|---|
| 25829 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25830 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25831 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB |
|---|
| 25832 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0 |
|---|
| 25833 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10 |
|---|
| 25834 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25835 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25836 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB |
|---|
| 25837 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0 |
|---|
| 25838 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10 |
|---|
| 25839 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25840 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25841 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB |
|---|
| 25842 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0 |
|---|
| 25843 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10 |
|---|
| 25844 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25845 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25846 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB |
|---|
| 25847 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0 |
|---|
| 25848 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10 |
|---|
| 25849 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25850 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25851 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB |
|---|
| 25852 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0 |
|---|
| 25853 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10 |
|---|
| 25854 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25855 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25856 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB |
|---|
| 25857 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0 |
|---|
| 25858 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10 |
|---|
| 25859 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25860 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25861 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB |
|---|
| 25862 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0 |
|---|
| 25863 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10 |
|---|
| 25864 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25865 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25866 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB |
|---|
| 25867 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0 |
|---|
| 25868 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10 |
|---|
| 25869 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25870 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25871 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB |
|---|
| 25872 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0 |
|---|
| 25873 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10 |
|---|
| 25874 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25875 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25876 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB |
|---|
| 25877 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0 |
|---|
| 25878 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10 |
|---|
| 25879 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25880 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25881 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB |
|---|
| 25882 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0 |
|---|
| 25883 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10 |
|---|
| 25884 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 25885 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 25886 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
|---|
| 25887 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 25888 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 25889 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
|---|
| 25890 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 25891 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 25892 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
|---|
| 25893 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 25894 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 25895 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
|---|
| 25896 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 25897 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 25898 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
|---|
| 25899 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 25900 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 25901 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
|---|
| 25902 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 25903 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 25904 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
|---|
| 25905 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 25906 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 25907 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
|---|
| 25908 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 25909 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 25910 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
|---|
| 25911 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 25912 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 25913 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
|---|
| 25914 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
|---|
| 25915 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 25916 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
|---|
| 25917 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
|---|
| 25918 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 25919 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
|---|
| 25920 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
|---|
| 25921 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 25922 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
|---|
| 25923 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
|---|
| 25924 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 25925 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
|---|
| 25926 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
|---|
| 25927 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 25928 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
|---|
| 25929 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
|---|
| 25930 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 25931 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
|---|
| 25932 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
|---|
| 25933 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 25934 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
|---|
| 25935 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
|---|
| 25936 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 25937 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
|---|
| 25938 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
|---|
| 25939 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 25940 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
|---|
| 25941 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 25942 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 25943 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
|---|
| 25944 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 25945 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 25946 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
|---|
| 25947 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 25948 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 25949 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
|---|
| 25950 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 25951 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 25952 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
|---|
| 25953 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 25954 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 25955 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
|---|
| 25956 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 25957 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 25958 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
|---|
| 25959 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 25960 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 25961 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
|---|
| 25962 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 25963 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 25964 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
|---|
| 25965 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 25966 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 25967 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 |
|---|
| 25968 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0 |
|---|
| 25969 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 25970 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 |
|---|
| 25971 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0 |
|---|
| 25972 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 25973 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 |
|---|
| 25974 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0 |
|---|
| 25975 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 25976 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 |
|---|
| 25977 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0 |
|---|
| 25978 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 25979 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 |
|---|
| 25980 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0 |
|---|
| 25981 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 25982 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 |
|---|
| 25983 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0 |
|---|
| 25984 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 25985 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 |
|---|
| 25986 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0 |
|---|
| 25987 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 25988 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 |
|---|
| 25989 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0 |
|---|
| 25990 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 25991 | //BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 |
|---|
| 25992 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0 |
|---|
| 25993 | #define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 25994 | |
|---|
| 25995 | |
|---|
| 25996 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
|---|
| 25997 | //BIF_CFG_DEV0_EPF2_VENDOR_ID |
|---|
| 25998 | #define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 25999 | #define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 26000 | //BIF_CFG_DEV0_EPF2_DEVICE_ID |
|---|
| 26001 | #define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 26002 | #define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 26003 | //BIF_CFG_DEV0_EPF2_COMMAND |
|---|
| 26004 | #define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 26005 | #define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 26006 | #define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 26007 | #define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 26008 | #define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 26009 | #define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 26010 | #define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 26011 | #define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 26012 | #define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 26013 | #define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 26014 | #define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 26015 | #define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 26016 | #define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 26017 | #define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 26018 | #define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 26019 | #define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 26020 | #define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 26021 | #define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 26022 | #define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 26023 | #define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 26024 | #define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 26025 | #define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 26026 | //BIF_CFG_DEV0_EPF2_STATUS |
|---|
| 26027 | #define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 26028 | #define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 26029 | #define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 26030 | #define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 26031 | #define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 26032 | #define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 26033 | #define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 26034 | #define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 26035 | #define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 26036 | #define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 26037 | #define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 26038 | #define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 26039 | #define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 26040 | #define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 26041 | #define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 26042 | #define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 26043 | #define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 26044 | #define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 26045 | #define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 26046 | #define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 26047 | #define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 26048 | #define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 26049 | #define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 26050 | #define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 26051 | //BIF_CFG_DEV0_EPF2_REVISION_ID |
|---|
| 26052 | #define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 26053 | #define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 26054 | #define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 26055 | #define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 26056 | //BIF_CFG_DEV0_EPF2_PROG_INTERFACE |
|---|
| 26057 | #define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 26058 | #define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 26059 | //BIF_CFG_DEV0_EPF2_SUB_CLASS |
|---|
| 26060 | #define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 26061 | #define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 26062 | //BIF_CFG_DEV0_EPF2_BASE_CLASS |
|---|
| 26063 | #define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 26064 | #define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 26065 | //BIF_CFG_DEV0_EPF2_CACHE_LINE |
|---|
| 26066 | #define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 26067 | #define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 26068 | //BIF_CFG_DEV0_EPF2_LATENCY |
|---|
| 26069 | #define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 26070 | #define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 26071 | //BIF_CFG_DEV0_EPF2_HEADER |
|---|
| 26072 | #define 0x0 |
|---|
| 26073 | #define 0x7 |
|---|
| 26074 | #define 0x7FL |
|---|
| 26075 | #define 0x80L |
|---|
| 26076 | //BIF_CFG_DEV0_EPF2_BIST |
|---|
| 26077 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 26078 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 26079 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 26080 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 26081 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK 0x40L |
|---|
| 26082 | #define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK 0x80L |
|---|
| 26083 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_1 |
|---|
| 26084 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 26085 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 26086 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_2 |
|---|
| 26087 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 26088 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 26089 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_3 |
|---|
| 26090 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 26091 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 26092 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_4 |
|---|
| 26093 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 26094 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 26095 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_5 |
|---|
| 26096 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 26097 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 26098 | //BIF_CFG_DEV0_EPF2_BASE_ADDR_6 |
|---|
| 26099 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 26100 | #define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 26101 | //BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR |
|---|
| 26102 | #define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 26103 | #define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 26104 | //BIF_CFG_DEV0_EPF2_ADAPTER_ID |
|---|
| 26105 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 26106 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 26107 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 26108 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 26109 | //BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR |
|---|
| 26110 | #define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 26111 | #define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 26112 | //BIF_CFG_DEV0_EPF2_CAP_PTR |
|---|
| 26113 | #define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 26114 | #define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 26115 | //BIF_CFG_DEV0_EPF2_INTERRUPT_LINE |
|---|
| 26116 | #define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 26117 | #define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 26118 | //BIF_CFG_DEV0_EPF2_INTERRUPT_PIN |
|---|
| 26119 | #define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 26120 | #define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 26121 | //BIF_CFG_DEV0_EPF2_MIN_GRANT |
|---|
| 26122 | #define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 26123 | #define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 26124 | //BIF_CFG_DEV0_EPF2_MAX_LATENCY |
|---|
| 26125 | #define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 26126 | #define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 26127 | //BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST |
|---|
| 26128 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26129 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 26130 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 26131 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 26132 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 26133 | #define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 26134 | //BIF_CFG_DEV0_EPF2_ADAPTER_ID_W |
|---|
| 26135 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 26136 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 26137 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 26138 | #define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 26139 | //BIF_CFG_DEV0_EPF2_PMI_CAP_LIST |
|---|
| 26140 | #define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26141 | #define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 26142 | #define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 26143 | #define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 26144 | //BIF_CFG_DEV0_EPF2_PMI_CAP |
|---|
| 26145 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 26146 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 26147 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 26148 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 26149 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 26150 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 26151 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 26152 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 26153 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 26154 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 26155 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 26156 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 26157 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 26158 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 26159 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 26160 | #define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 26161 | //BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL |
|---|
| 26162 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 26163 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 26164 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 26165 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 26166 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 26167 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 26168 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 26169 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 26170 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 26171 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 26172 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 26173 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 26174 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 26175 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 26176 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 26177 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 26178 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 26179 | #define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 26180 | //BIF_CFG_DEV0_EPF2_SBRN |
|---|
| 26181 | #define BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT 0x0 |
|---|
| 26182 | #define BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK 0xFFL |
|---|
| 26183 | //BIF_CFG_DEV0_EPF2_FLADJ |
|---|
| 26184 | #define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT 0x0 |
|---|
| 26185 | #define BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT 0x6 |
|---|
| 26186 | #define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK 0x3FL |
|---|
| 26187 | #define BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK 0x40L |
|---|
| 26188 | //BIF_CFG_DEV0_EPF2_DBESL_DBESLD |
|---|
| 26189 | #define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT 0x0 |
|---|
| 26190 | #define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
|---|
| 26191 | #define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK 0x0FL |
|---|
| 26192 | #define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK 0xF0L |
|---|
| 26193 | //BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST |
|---|
| 26194 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26195 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 26196 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 26197 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 26198 | //BIF_CFG_DEV0_EPF2_PCIE_CAP |
|---|
| 26199 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 26200 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 26201 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 26202 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 26203 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 26204 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 26205 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 26206 | #define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 26207 | //BIF_CFG_DEV0_EPF2_DEVICE_CAP |
|---|
| 26208 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 26209 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 26210 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 26211 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 26212 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 26213 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 26214 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 26215 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 26216 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 26217 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 26218 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 26219 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 26220 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 26221 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 26222 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 26223 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 26224 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 26225 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 26226 | //BIF_CFG_DEV0_EPF2_DEVICE_CNTL |
|---|
| 26227 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 26228 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 26229 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 26230 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 26231 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 26232 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 26233 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 26234 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 26235 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 26236 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 26237 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 26238 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 26239 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 26240 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 26241 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 26242 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 26243 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 26244 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 26245 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 26246 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 26247 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 26248 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 26249 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 26250 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 26251 | //BIF_CFG_DEV0_EPF2_DEVICE_STATUS |
|---|
| 26252 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 26253 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 26254 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 26255 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 26256 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 26257 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 26258 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 26259 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 26260 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 26261 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 26262 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 26263 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 26264 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 26265 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 26266 | //BIF_CFG_DEV0_EPF2_LINK_CAP |
|---|
| 26267 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 26268 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 26269 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 26270 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 26271 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 26272 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 26273 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 26274 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 26275 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 26276 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 26277 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 26278 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 26279 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 26280 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 26281 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 26282 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 26283 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 26284 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 26285 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 26286 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 26287 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 26288 | #define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 26289 | //BIF_CFG_DEV0_EPF2_LINK_CNTL |
|---|
| 26290 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 26291 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 26292 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 26293 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 26294 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 26295 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 26296 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 26297 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 26298 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 26299 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 26300 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 26301 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 26302 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 26303 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 26304 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 26305 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 26306 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 26307 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 26308 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 26309 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 26310 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 26311 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 26312 | //BIF_CFG_DEV0_EPF2_LINK_STATUS |
|---|
| 26313 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 26314 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 26315 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 26316 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 26317 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 26318 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 26319 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 26320 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 26321 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 26322 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 26323 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 26324 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 26325 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 26326 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 26327 | //BIF_CFG_DEV0_EPF2_DEVICE_CAP2 |
|---|
| 26328 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 26329 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 26330 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 26331 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 26332 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 26333 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 26334 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 26335 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 26336 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 26337 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 26338 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 26339 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 26340 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 26341 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 26342 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 26343 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 26344 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 26345 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 26346 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 26347 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 26348 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 26349 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 26350 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 26351 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 26352 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 26353 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 26354 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 26355 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 26356 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 26357 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 26358 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 26359 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 26360 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 26361 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 26362 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 26363 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 26364 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 26365 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 26366 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 26367 | #define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 26368 | //BIF_CFG_DEV0_EPF2_DEVICE_CNTL2 |
|---|
| 26369 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 26370 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 26371 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 26372 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 26373 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 26374 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 26375 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 26376 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 26377 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 26378 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 26379 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 26380 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 26381 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 26382 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 26383 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 26384 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 26385 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 26386 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 26387 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 26388 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 26389 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 26390 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 26391 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 26392 | #define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 26393 | //BIF_CFG_DEV0_EPF2_DEVICE_STATUS2 |
|---|
| 26394 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 26395 | #define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 26396 | //BIF_CFG_DEV0_EPF2_LINK_CAP2 |
|---|
| 26397 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 26398 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 26399 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 26400 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 26401 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 26402 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 26403 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 26404 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 26405 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 26406 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 26407 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 26408 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 26409 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 26410 | #define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 26411 | //BIF_CFG_DEV0_EPF2_LINK_CNTL2 |
|---|
| 26412 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 26413 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 26414 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 26415 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 26416 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 26417 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 26418 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 26419 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 26420 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 26421 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 26422 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 26423 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 26424 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 26425 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 26426 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 26427 | #define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 26428 | //BIF_CFG_DEV0_EPF2_LINK_STATUS2 |
|---|
| 26429 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 26430 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 26431 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 26432 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 26433 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 26434 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 26435 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 26436 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 26437 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 26438 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 26439 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 26440 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 26441 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 26442 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 26443 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 26444 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 26445 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 26446 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 26447 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 26448 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 26449 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 26450 | #define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 26451 | //BIF_CFG_DEV0_EPF2_MSI_CAP_LIST |
|---|
| 26452 | #define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26453 | #define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 26454 | #define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 26455 | #define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 26456 | //BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL |
|---|
| 26457 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 26458 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 26459 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 26460 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 26461 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 26462 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 26463 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 26464 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 26465 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 26466 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 26467 | //BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO |
|---|
| 26468 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 26469 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 26470 | //BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI |
|---|
| 26471 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 26472 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 26473 | //BIF_CFG_DEV0_EPF2_MSI_MSG_DATA |
|---|
| 26474 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 26475 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 26476 | //BIF_CFG_DEV0_EPF2_MSI_MASK |
|---|
| 26477 | #define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 26478 | #define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 26479 | //BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 |
|---|
| 26480 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 26481 | #define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 26482 | //BIF_CFG_DEV0_EPF2_MSI_MASK_64 |
|---|
| 26483 | #define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 26484 | #define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 26485 | //BIF_CFG_DEV0_EPF2_MSI_PENDING |
|---|
| 26486 | #define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 26487 | #define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 26488 | //BIF_CFG_DEV0_EPF2_MSI_PENDING_64 |
|---|
| 26489 | #define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 26490 | #define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 26491 | //BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST |
|---|
| 26492 | #define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26493 | #define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 26494 | #define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 26495 | #define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 26496 | //BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL |
|---|
| 26497 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 26498 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 26499 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 26500 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 26501 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 26502 | #define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 26503 | //BIF_CFG_DEV0_EPF2_MSIX_TABLE |
|---|
| 26504 | #define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 26505 | #define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 26506 | #define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 26507 | #define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 26508 | //BIF_CFG_DEV0_EPF2_MSIX_PBA |
|---|
| 26509 | #define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 26510 | #define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 26511 | #define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 26512 | #define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 26513 | //BIF_CFG_DEV0_EPF2_SATA_CAP_0 |
|---|
| 26514 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
|---|
| 26515 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
|---|
| 26516 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
|---|
| 26517 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
|---|
| 26518 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
|---|
| 26519 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
|---|
| 26520 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 26521 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
|---|
| 26522 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
|---|
| 26523 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
|---|
| 26524 | //BIF_CFG_DEV0_EPF2_SATA_CAP_1 |
|---|
| 26525 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
|---|
| 26526 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
|---|
| 26527 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
|---|
| 26528 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
|---|
| 26529 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
|---|
| 26530 | #define BIF_CFG_DEV0_EPF2_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
|---|
| 26531 | //BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX |
|---|
| 26532 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
|---|
| 26533 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
|---|
| 26534 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
|---|
| 26535 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
|---|
| 26536 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
|---|
| 26537 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
|---|
| 26538 | //BIF_CFG_DEV0_EPF2_SATA_IDP_DATA |
|---|
| 26539 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
|---|
| 26540 | #define BIF_CFG_DEV0_EPF2_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
|---|
| 26541 | //BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 26542 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26543 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 26544 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 26545 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 26546 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 26547 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 26548 | //BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 26549 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 26550 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 26551 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 26552 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 26553 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 26554 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 26555 | //BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 |
|---|
| 26556 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 26557 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 26558 | //BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 |
|---|
| 26559 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 26560 | #define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 26561 | //BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 26562 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26563 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 26564 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 26565 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 26566 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 26567 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 26568 | //BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS |
|---|
| 26569 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 26570 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 26571 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 26572 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 26573 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 26574 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 26575 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 26576 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 26577 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 26578 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 26579 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 26580 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 26581 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 26582 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 26583 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 26584 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 26585 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 26586 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 26587 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 26588 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 26589 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 26590 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 26591 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 26592 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 26593 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 26594 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 26595 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 26596 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 26597 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 26598 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 26599 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 26600 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 26601 | //BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK |
|---|
| 26602 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 26603 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 26604 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 26605 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 26606 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 26607 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 26608 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 26609 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 26610 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 26611 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 26612 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 26613 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 26614 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 26615 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 26616 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 26617 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 26618 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 26619 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 26620 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 26621 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 26622 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 26623 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 26624 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 26625 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 26626 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 26627 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 26628 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 26629 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 26630 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 26631 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 26632 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 26633 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 26634 | //BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 26635 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 26636 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 26637 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 26638 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 26639 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 26640 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 26641 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 26642 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 26643 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 26644 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 26645 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 26646 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 26647 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 26648 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 26649 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 26650 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 26651 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 26652 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 26653 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 26654 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 26655 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 26656 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 26657 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 26658 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 26659 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 26660 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 26661 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 26662 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 26663 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 26664 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 26665 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 26666 | #define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 26667 | //BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS |
|---|
| 26668 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 26669 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 26670 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 26671 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 26672 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 26673 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 26674 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 26675 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 26676 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 26677 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 26678 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 26679 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 26680 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 26681 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 26682 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 26683 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 26684 | //BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK |
|---|
| 26685 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 26686 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 26687 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 26688 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 26689 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 26690 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 26691 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 26692 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 26693 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 26694 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 26695 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 26696 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 26697 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 26698 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 26699 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 26700 | #define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 26701 | //BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 26702 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 26703 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 26704 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 26705 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 26706 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 26707 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 26708 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 26709 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 26710 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 26711 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 26712 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 26713 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 26714 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 26715 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 26716 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 26717 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 26718 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 26719 | #define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 26720 | //BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 |
|---|
| 26721 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 26722 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 26723 | //BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 |
|---|
| 26724 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 26725 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 26726 | //BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 |
|---|
| 26727 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 26728 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 26729 | //BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 |
|---|
| 26730 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 26731 | #define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 26732 | //BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 |
|---|
| 26733 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 26734 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 26735 | //BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 |
|---|
| 26736 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 26737 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 26738 | //BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 |
|---|
| 26739 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 26740 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 26741 | //BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 |
|---|
| 26742 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 26743 | #define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 26744 | //BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST |
|---|
| 26745 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26746 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 26747 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 26748 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 26749 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 26750 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 26751 | //BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP |
|---|
| 26752 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 26753 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 26754 | //BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL |
|---|
| 26755 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 26756 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 26757 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 26758 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 26759 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 26760 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 26761 | //BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP |
|---|
| 26762 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 26763 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 26764 | //BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL |
|---|
| 26765 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 26766 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 26767 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 26768 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 26769 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 26770 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 26771 | //BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP |
|---|
| 26772 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 26773 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 26774 | //BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL |
|---|
| 26775 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 26776 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 26777 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 26778 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 26779 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 26780 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 26781 | //BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP |
|---|
| 26782 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 26783 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 26784 | //BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL |
|---|
| 26785 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 26786 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 26787 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 26788 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 26789 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 26790 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 26791 | //BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP |
|---|
| 26792 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 26793 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 26794 | //BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL |
|---|
| 26795 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 26796 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 26797 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 26798 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 26799 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 26800 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 26801 | //BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP |
|---|
| 26802 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 26803 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 26804 | //BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL |
|---|
| 26805 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 26806 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 26807 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 26808 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 26809 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 26810 | #define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 26811 | //BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 26812 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26813 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 26814 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 26815 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 26816 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 26817 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 26818 | //BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 26819 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 26820 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 26821 | //BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA |
|---|
| 26822 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 26823 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 26824 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 26825 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 26826 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 26827 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 26828 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 26829 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 26830 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 26831 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 26832 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 26833 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 26834 | //BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP |
|---|
| 26835 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 26836 | #define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 26837 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST |
|---|
| 26838 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26839 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 26840 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 26841 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 26842 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 26843 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 26844 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP |
|---|
| 26845 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 26846 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 26847 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 26848 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 26849 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 26850 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 26851 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 26852 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 26853 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 26854 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 26855 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 26856 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 26857 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 26858 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS |
|---|
| 26859 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 26860 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 26861 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 26862 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 26863 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL |
|---|
| 26864 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 26865 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 26866 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 26867 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 26868 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 26869 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 26870 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 26871 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 26872 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 26873 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 26874 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 26875 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 26876 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 26877 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 26878 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 26879 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 26880 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 26881 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 26882 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 26883 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 26884 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 26885 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 26886 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 26887 | //BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 26888 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 26889 | #define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 26890 | //BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST |
|---|
| 26891 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26892 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 26893 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 26894 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 26895 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 26896 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 26897 | //BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP |
|---|
| 26898 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 26899 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 26900 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 26901 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 26902 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 26903 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 26904 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 26905 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 26906 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 26907 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 26908 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 26909 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 26910 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 26911 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 26912 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 26913 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 26914 | //BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL |
|---|
| 26915 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 26916 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 26917 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 26918 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 26919 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 26920 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 26921 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 26922 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 26923 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 26924 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 26925 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 26926 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 26927 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 26928 | #define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 26929 | //BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST |
|---|
| 26930 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26931 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 26932 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 26933 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 26934 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 26935 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 26936 | //BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP |
|---|
| 26937 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 26938 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 26939 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 26940 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 26941 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 26942 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 26943 | //BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL |
|---|
| 26944 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 26945 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 26946 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 26947 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 26948 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 26949 | #define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 26950 | //BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST |
|---|
| 26951 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26952 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 26953 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 26954 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 26955 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 26956 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 26957 | //BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP |
|---|
| 26958 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 26959 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 26960 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 26961 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 26962 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 26963 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 26964 | //BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL |
|---|
| 26965 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 26966 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 26967 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 26968 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 26969 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 26970 | #define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 26971 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 26972 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 26973 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 26974 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 26975 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 26976 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 26977 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 26978 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP |
|---|
| 26979 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 26980 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 26981 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 26982 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 26983 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 26984 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 26985 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 26986 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 26987 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 26988 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 26989 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 26990 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 26991 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL |
|---|
| 26992 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 26993 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 26994 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 26995 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 26996 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0 |
|---|
| 26997 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 26998 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 26999 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27000 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27001 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1 |
|---|
| 27002 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27003 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27004 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27005 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27006 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2 |
|---|
| 27007 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27008 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27009 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27010 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27011 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3 |
|---|
| 27012 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27013 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27014 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27015 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27016 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4 |
|---|
| 27017 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27018 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27019 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27020 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27021 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5 |
|---|
| 27022 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27023 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27024 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27025 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27026 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6 |
|---|
| 27027 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27028 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27029 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27030 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27031 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7 |
|---|
| 27032 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27033 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27034 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27035 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27036 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8 |
|---|
| 27037 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27038 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27039 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27040 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27041 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9 |
|---|
| 27042 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27043 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27044 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27045 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27046 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10 |
|---|
| 27047 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27048 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27049 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27050 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27051 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11 |
|---|
| 27052 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27053 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27054 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27055 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27056 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12 |
|---|
| 27057 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27058 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27059 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27060 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27061 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13 |
|---|
| 27062 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27063 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27064 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27065 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27066 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14 |
|---|
| 27067 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27068 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27069 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27070 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27071 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15 |
|---|
| 27072 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27073 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27074 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27075 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27076 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16 |
|---|
| 27077 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27078 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27079 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27080 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27081 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17 |
|---|
| 27082 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27083 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27084 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27085 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27086 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18 |
|---|
| 27087 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27088 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27089 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27090 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27091 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19 |
|---|
| 27092 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27093 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27094 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27095 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27096 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20 |
|---|
| 27097 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27098 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27099 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27100 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27101 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21 |
|---|
| 27102 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27103 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27104 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27105 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27106 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22 |
|---|
| 27107 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27108 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27109 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27110 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27111 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23 |
|---|
| 27112 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27113 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27114 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27115 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27116 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24 |
|---|
| 27117 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27118 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27119 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27120 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27121 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25 |
|---|
| 27122 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27123 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27124 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27125 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27126 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26 |
|---|
| 27127 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27128 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27129 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27130 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27131 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27 |
|---|
| 27132 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27133 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27134 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27135 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27136 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28 |
|---|
| 27137 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27138 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27139 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27140 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27141 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29 |
|---|
| 27142 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27143 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27144 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27145 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27146 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30 |
|---|
| 27147 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27148 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27149 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27150 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27151 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31 |
|---|
| 27152 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27153 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27154 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27155 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27156 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32 |
|---|
| 27157 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27158 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27159 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27160 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27161 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33 |
|---|
| 27162 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27163 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27164 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27165 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27166 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34 |
|---|
| 27167 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27168 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27169 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27170 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27171 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35 |
|---|
| 27172 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27173 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27174 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27175 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27176 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36 |
|---|
| 27177 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27178 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27179 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27180 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27181 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37 |
|---|
| 27182 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27183 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27184 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27185 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27186 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38 |
|---|
| 27187 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27188 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27189 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27190 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27191 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39 |
|---|
| 27192 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27193 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27194 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27195 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27196 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40 |
|---|
| 27197 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27198 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27199 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27200 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27201 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41 |
|---|
| 27202 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27203 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27204 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27205 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27206 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42 |
|---|
| 27207 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27208 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27209 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27210 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27211 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43 |
|---|
| 27212 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27213 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27214 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27215 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27216 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44 |
|---|
| 27217 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27218 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27219 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27220 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27221 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45 |
|---|
| 27222 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27223 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27224 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27225 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27226 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46 |
|---|
| 27227 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27228 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27229 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27230 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27231 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47 |
|---|
| 27232 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27233 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27234 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27235 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27236 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48 |
|---|
| 27237 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27238 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27239 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27240 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27241 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49 |
|---|
| 27242 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27243 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27244 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27245 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27246 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50 |
|---|
| 27247 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27248 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27249 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27250 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27251 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51 |
|---|
| 27252 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27253 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27254 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27255 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27256 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52 |
|---|
| 27257 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27258 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27259 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27260 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27261 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53 |
|---|
| 27262 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27263 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27264 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27265 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27266 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54 |
|---|
| 27267 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27268 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27269 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27270 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27271 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55 |
|---|
| 27272 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27273 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27274 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27275 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27276 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56 |
|---|
| 27277 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27278 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27279 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27280 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27281 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57 |
|---|
| 27282 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27283 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27284 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27285 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27286 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58 |
|---|
| 27287 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27288 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27289 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27290 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27291 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59 |
|---|
| 27292 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27293 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27294 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27295 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27296 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60 |
|---|
| 27297 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27298 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27299 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27300 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27301 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61 |
|---|
| 27302 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27303 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27304 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27305 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27306 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62 |
|---|
| 27307 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27308 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27309 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27310 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27311 | //BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63 |
|---|
| 27312 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 27313 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 27314 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 27315 | #define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 27316 | |
|---|
| 27317 | |
|---|
| 27318 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
|---|
| 27319 | //BIF_CFG_DEV0_EPF3_VENDOR_ID |
|---|
| 27320 | #define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 27321 | #define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 27322 | //BIF_CFG_DEV0_EPF3_DEVICE_ID |
|---|
| 27323 | #define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 27324 | #define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 27325 | //BIF_CFG_DEV0_EPF3_COMMAND |
|---|
| 27326 | #define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 27327 | #define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 27328 | #define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 27329 | #define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 27330 | #define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 27331 | #define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 27332 | #define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 27333 | #define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 27334 | #define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 27335 | #define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 27336 | #define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 27337 | #define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 27338 | #define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 27339 | #define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 27340 | #define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 27341 | #define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 27342 | #define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 27343 | #define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 27344 | #define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 27345 | #define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 27346 | #define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 27347 | #define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 27348 | //BIF_CFG_DEV0_EPF3_STATUS |
|---|
| 27349 | #define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 27350 | #define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 27351 | #define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 27352 | #define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 27353 | #define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 27354 | #define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 27355 | #define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 27356 | #define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 27357 | #define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 27358 | #define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 27359 | #define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 27360 | #define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 27361 | #define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 27362 | #define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 27363 | #define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 27364 | #define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 27365 | #define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 27366 | #define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 27367 | #define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 27368 | #define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 27369 | #define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 27370 | #define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 27371 | #define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 27372 | #define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 27373 | //BIF_CFG_DEV0_EPF3_REVISION_ID |
|---|
| 27374 | #define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 27375 | #define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 27376 | #define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 27377 | #define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 27378 | //BIF_CFG_DEV0_EPF3_PROG_INTERFACE |
|---|
| 27379 | #define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 27380 | #define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 27381 | //BIF_CFG_DEV0_EPF3_SUB_CLASS |
|---|
| 27382 | #define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 27383 | #define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 27384 | //BIF_CFG_DEV0_EPF3_BASE_CLASS |
|---|
| 27385 | #define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 27386 | #define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 27387 | //BIF_CFG_DEV0_EPF3_CACHE_LINE |
|---|
| 27388 | #define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 27389 | #define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 27390 | //BIF_CFG_DEV0_EPF3_LATENCY |
|---|
| 27391 | #define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 27392 | #define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 27393 | //BIF_CFG_DEV0_EPF3_HEADER |
|---|
| 27394 | #define 0x0 |
|---|
| 27395 | #define 0x7 |
|---|
| 27396 | #define 0x7FL |
|---|
| 27397 | #define 0x80L |
|---|
| 27398 | //BIF_CFG_DEV0_EPF3_BIST |
|---|
| 27399 | #define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 27400 | #define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 27401 | #define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 27402 | #define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 27403 | #define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT_MASK 0x40L |
|---|
| 27404 | #define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP_MASK 0x80L |
|---|
| 27405 | //BIF_CFG_DEV0_EPF3_BASE_ADDR_1 |
|---|
| 27406 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 27407 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 27408 | //BIF_CFG_DEV0_EPF3_BASE_ADDR_2 |
|---|
| 27409 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 27410 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 27411 | //BIF_CFG_DEV0_EPF3_BASE_ADDR_3 |
|---|
| 27412 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 27413 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 27414 | //BIF_CFG_DEV0_EPF3_BASE_ADDR_4 |
|---|
| 27415 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 27416 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 27417 | //BIF_CFG_DEV0_EPF3_BASE_ADDR_5 |
|---|
| 27418 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 27419 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 27420 | //BIF_CFG_DEV0_EPF3_BASE_ADDR_6 |
|---|
| 27421 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 27422 | #define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 27423 | //BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR |
|---|
| 27424 | #define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 27425 | #define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 27426 | //BIF_CFG_DEV0_EPF3_ADAPTER_ID |
|---|
| 27427 | #define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 27428 | #define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 27429 | #define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 27430 | #define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 27431 | //BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR |
|---|
| 27432 | #define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 27433 | #define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 27434 | //BIF_CFG_DEV0_EPF3_CAP_PTR |
|---|
| 27435 | #define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 27436 | #define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 27437 | //BIF_CFG_DEV0_EPF3_INTERRUPT_LINE |
|---|
| 27438 | #define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 27439 | #define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 27440 | //BIF_CFG_DEV0_EPF3_INTERRUPT_PIN |
|---|
| 27441 | #define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 27442 | #define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 27443 | //BIF_CFG_DEV0_EPF3_MIN_GRANT |
|---|
| 27444 | #define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 27445 | #define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 27446 | //BIF_CFG_DEV0_EPF3_MAX_LATENCY |
|---|
| 27447 | #define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 27448 | #define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 27449 | //BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST |
|---|
| 27450 | #define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 27451 | #define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 27452 | #define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 27453 | #define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 27454 | #define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 27455 | #define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 27456 | //BIF_CFG_DEV0_EPF3_ADAPTER_ID_W |
|---|
| 27457 | #define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 27458 | #define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 27459 | #define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 27460 | #define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 27461 | //BIF_CFG_DEV0_EPF3_PMI_CAP_LIST |
|---|
| 27462 | #define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 27463 | #define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 27464 | #define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 27465 | #define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 27466 | //BIF_CFG_DEV0_EPF3_PMI_CAP |
|---|
| 27467 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 27468 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 27469 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 27470 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 27471 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 27472 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 27473 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 27474 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 27475 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 27476 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 27477 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 27478 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 27479 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 27480 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 27481 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 27482 | #define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 27483 | //BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL |
|---|
| 27484 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 27485 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 27486 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 27487 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 27488 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 27489 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 27490 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 27491 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 27492 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 27493 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 27494 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 27495 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 27496 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 27497 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 27498 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 27499 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 27500 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 27501 | #define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 27502 | //BIF_CFG_DEV0_EPF3_SBRN |
|---|
| 27503 | #define BIF_CFG_DEV0_EPF3_SBRN__SBRN__SHIFT 0x0 |
|---|
| 27504 | #define BIF_CFG_DEV0_EPF3_SBRN__SBRN_MASK 0xFFL |
|---|
| 27505 | //BIF_CFG_DEV0_EPF3_FLADJ |
|---|
| 27506 | #define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ__SHIFT 0x0 |
|---|
| 27507 | #define BIF_CFG_DEV0_EPF3_FLADJ__NFC__SHIFT 0x6 |
|---|
| 27508 | #define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ_MASK 0x3FL |
|---|
| 27509 | #define BIF_CFG_DEV0_EPF3_FLADJ__NFC_MASK 0x40L |
|---|
| 27510 | //BIF_CFG_DEV0_EPF3_DBESL_DBESLD |
|---|
| 27511 | #define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL__SHIFT 0x0 |
|---|
| 27512 | #define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
|---|
| 27513 | #define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL_MASK 0x0FL |
|---|
| 27514 | #define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD_MASK 0xF0L |
|---|
| 27515 | //BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST |
|---|
| 27516 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 27517 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 27518 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 27519 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 27520 | //BIF_CFG_DEV0_EPF3_PCIE_CAP |
|---|
| 27521 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 27522 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 27523 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 27524 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 27525 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 27526 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 27527 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 27528 | #define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 27529 | //BIF_CFG_DEV0_EPF3_DEVICE_CAP |
|---|
| 27530 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 27531 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 27532 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 27533 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 27534 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 27535 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 27536 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 27537 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 27538 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 27539 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 27540 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 27541 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 27542 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 27543 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 27544 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 27545 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 27546 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 27547 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 27548 | //BIF_CFG_DEV0_EPF3_DEVICE_CNTL |
|---|
| 27549 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 27550 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 27551 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 27552 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 27553 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 27554 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 27555 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 27556 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 27557 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 27558 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 27559 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 27560 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 27561 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 27562 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 27563 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 27564 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 27565 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 27566 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 27567 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 27568 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 27569 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 27570 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 27571 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 27572 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 27573 | //BIF_CFG_DEV0_EPF3_DEVICE_STATUS |
|---|
| 27574 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 27575 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 27576 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 27577 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 27578 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 27579 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 27580 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 27581 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 27582 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 27583 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 27584 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 27585 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 27586 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 27587 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 27588 | //BIF_CFG_DEV0_EPF3_LINK_CAP |
|---|
| 27589 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 27590 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 27591 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 27592 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 27593 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 27594 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 27595 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 27596 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 27597 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 27598 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 27599 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 27600 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 27601 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 27602 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 27603 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 27604 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 27605 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 27606 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 27607 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 27608 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 27609 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 27610 | #define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 27611 | //BIF_CFG_DEV0_EPF3_LINK_CNTL |
|---|
| 27612 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 27613 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 27614 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 27615 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 27616 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 27617 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 27618 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 27619 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 27620 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 27621 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 27622 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 27623 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 27624 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 27625 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 27626 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 27627 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 27628 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 27629 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 27630 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 27631 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 27632 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 27633 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 27634 | //BIF_CFG_DEV0_EPF3_LINK_STATUS |
|---|
| 27635 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 27636 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 27637 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 27638 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 27639 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 27640 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 27641 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 27642 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 27643 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 27644 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 27645 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 27646 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 27647 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 27648 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 27649 | //BIF_CFG_DEV0_EPF3_DEVICE_CAP2 |
|---|
| 27650 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 27651 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 27652 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 27653 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 27654 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 27655 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 27656 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 27657 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 27658 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 27659 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 27660 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 27661 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 27662 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 27663 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 27664 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 27665 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 27666 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 27667 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 27668 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 27669 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 27670 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 27671 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 27672 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 27673 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 27674 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 27675 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 27676 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 27677 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 27678 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 27679 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 27680 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 27681 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 27682 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 27683 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 27684 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 27685 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 27686 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 27687 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 27688 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 27689 | #define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 27690 | //BIF_CFG_DEV0_EPF3_DEVICE_CNTL2 |
|---|
| 27691 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 27692 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 27693 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 27694 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 27695 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 27696 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 27697 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 27698 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 27699 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 27700 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 27701 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 27702 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 27703 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 27704 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 27705 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 27706 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 27707 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 27708 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 27709 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 27710 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 27711 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 27712 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 27713 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 27714 | #define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 27715 | //BIF_CFG_DEV0_EPF3_DEVICE_STATUS2 |
|---|
| 27716 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 27717 | #define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 27718 | //BIF_CFG_DEV0_EPF3_LINK_CAP2 |
|---|
| 27719 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 27720 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 27721 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 27722 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 27723 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 27724 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 27725 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 27726 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 27727 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 27728 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 27729 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 27730 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 27731 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 27732 | #define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 27733 | //BIF_CFG_DEV0_EPF3_LINK_CNTL2 |
|---|
| 27734 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 27735 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 27736 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 27737 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 27738 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 27739 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 27740 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 27741 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 27742 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 27743 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 27744 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 27745 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 27746 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 27747 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 27748 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 27749 | #define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 27750 | //BIF_CFG_DEV0_EPF3_LINK_STATUS2 |
|---|
| 27751 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 27752 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 27753 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 27754 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 27755 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 27756 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 27757 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 27758 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 27759 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 27760 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 27761 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 27762 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 27763 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 27764 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 27765 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 27766 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 27767 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 27768 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 27769 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 27770 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 27771 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 27772 | #define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 27773 | //BIF_CFG_DEV0_EPF3_MSI_CAP_LIST |
|---|
| 27774 | #define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 27775 | #define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 27776 | #define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 27777 | #define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 27778 | //BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL |
|---|
| 27779 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 27780 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 27781 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 27782 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 27783 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 27784 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 27785 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 27786 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 27787 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 27788 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 27789 | //BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO |
|---|
| 27790 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 27791 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 27792 | //BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI |
|---|
| 27793 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 27794 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 27795 | //BIF_CFG_DEV0_EPF3_MSI_MSG_DATA |
|---|
| 27796 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 27797 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 27798 | //BIF_CFG_DEV0_EPF3_MSI_MASK |
|---|
| 27799 | #define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 27800 | #define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 27801 | //BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64 |
|---|
| 27802 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 27803 | #define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 27804 | //BIF_CFG_DEV0_EPF3_MSI_MASK_64 |
|---|
| 27805 | #define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 27806 | #define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 27807 | //BIF_CFG_DEV0_EPF3_MSI_PENDING |
|---|
| 27808 | #define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 27809 | #define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 27810 | //BIF_CFG_DEV0_EPF3_MSI_PENDING_64 |
|---|
| 27811 | #define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 27812 | #define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 27813 | //BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST |
|---|
| 27814 | #define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 27815 | #define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 27816 | #define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 27817 | #define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 27818 | //BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL |
|---|
| 27819 | #define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 27820 | #define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 27821 | #define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 27822 | #define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 27823 | #define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 27824 | #define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 27825 | //BIF_CFG_DEV0_EPF3_MSIX_TABLE |
|---|
| 27826 | #define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 27827 | #define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 27828 | #define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 27829 | #define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 27830 | //BIF_CFG_DEV0_EPF3_MSIX_PBA |
|---|
| 27831 | #define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 27832 | #define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 27833 | #define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 27834 | #define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 27835 | //BIF_CFG_DEV0_EPF3_SATA_CAP_0 |
|---|
| 27836 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
|---|
| 27837 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
|---|
| 27838 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
|---|
| 27839 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
|---|
| 27840 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
|---|
| 27841 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
|---|
| 27842 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 27843 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
|---|
| 27844 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
|---|
| 27845 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
|---|
| 27846 | //BIF_CFG_DEV0_EPF3_SATA_CAP_1 |
|---|
| 27847 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
|---|
| 27848 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
|---|
| 27849 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
|---|
| 27850 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
|---|
| 27851 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
|---|
| 27852 | #define BIF_CFG_DEV0_EPF3_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
|---|
| 27853 | //BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX |
|---|
| 27854 | #define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
|---|
| 27855 | #define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
|---|
| 27856 | #define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
|---|
| 27857 | #define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
|---|
| 27858 | #define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
|---|
| 27859 | #define BIF_CFG_DEV0_EPF3_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
|---|
| 27860 | //BIF_CFG_DEV0_EPF3_SATA_IDP_DATA |
|---|
| 27861 | #define BIF_CFG_DEV0_EPF3_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
|---|
| 27862 | #define BIF_CFG_DEV0_EPF3_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
|---|
| 27863 | //BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 27864 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 27865 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 27866 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 27867 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 27868 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 27869 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 27870 | //BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 27871 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 27872 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 27873 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 27874 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 27875 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 27876 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 27877 | //BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1 |
|---|
| 27878 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 27879 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 27880 | //BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2 |
|---|
| 27881 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 27882 | #define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 27883 | //BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 27884 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 27885 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 27886 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 27887 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 27888 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 27889 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 27890 | //BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS |
|---|
| 27891 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 27892 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 27893 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 27894 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 27895 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 27896 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 27897 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 27898 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 27899 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 27900 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 27901 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 27902 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 27903 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 27904 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 27905 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 27906 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 27907 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 27908 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 27909 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 27910 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 27911 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 27912 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 27913 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 27914 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 27915 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 27916 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 27917 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 27918 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 27919 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 27920 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 27921 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 27922 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 27923 | //BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK |
|---|
| 27924 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 27925 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 27926 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 27927 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 27928 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 27929 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 27930 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 27931 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 27932 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 27933 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 27934 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 27935 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 27936 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 27937 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 27938 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 27939 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 27940 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 27941 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 27942 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 27943 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 27944 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 27945 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 27946 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 27947 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 27948 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 27949 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 27950 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 27951 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 27952 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 27953 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 27954 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 27955 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 27956 | //BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 27957 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 27958 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 27959 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 27960 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 27961 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 27962 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 27963 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 27964 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 27965 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 27966 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 27967 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 27968 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 27969 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 27970 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 27971 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 27972 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 27973 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 27974 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 27975 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 27976 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 27977 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 27978 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 27979 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 27980 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 27981 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 27982 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 27983 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 27984 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 27985 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 27986 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 27987 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 27988 | #define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 27989 | //BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS |
|---|
| 27990 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 27991 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 27992 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 27993 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 27994 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 27995 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 27996 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 27997 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 27998 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 27999 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 28000 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 28001 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 28002 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 28003 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 28004 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 28005 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 28006 | //BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK |
|---|
| 28007 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 28008 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 28009 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 28010 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 28011 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 28012 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 28013 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 28014 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 28015 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 28016 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 28017 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 28018 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 28019 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 28020 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 28021 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 28022 | #define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 28023 | //BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 28024 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 28025 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 28026 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 28027 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 28028 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 28029 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 28030 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 28031 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 28032 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 28033 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 28034 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 28035 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 28036 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 28037 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 28038 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 28039 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 28040 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 28041 | #define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 28042 | //BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0 |
|---|
| 28043 | #define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 28044 | #define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 28045 | //BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1 |
|---|
| 28046 | #define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 28047 | #define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 28048 | //BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2 |
|---|
| 28049 | #define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 28050 | #define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 28051 | //BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3 |
|---|
| 28052 | #define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 28053 | #define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 28054 | //BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0 |
|---|
| 28055 | #define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 28056 | #define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 28057 | //BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1 |
|---|
| 28058 | #define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 28059 | #define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 28060 | //BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2 |
|---|
| 28061 | #define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 28062 | #define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 28063 | //BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3 |
|---|
| 28064 | #define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 28065 | #define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 28066 | //BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST |
|---|
| 28067 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 28068 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 28069 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 28070 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 28071 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 28072 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 28073 | //BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP |
|---|
| 28074 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 28075 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 28076 | //BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL |
|---|
| 28077 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 28078 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 28079 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 28080 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 28081 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 28082 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 28083 | //BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP |
|---|
| 28084 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 28085 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 28086 | //BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL |
|---|
| 28087 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 28088 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 28089 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 28090 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 28091 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 28092 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 28093 | //BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP |
|---|
| 28094 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 28095 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 28096 | //BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL |
|---|
| 28097 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 28098 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 28099 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 28100 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 28101 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 28102 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 28103 | //BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP |
|---|
| 28104 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 28105 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 28106 | //BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL |
|---|
| 28107 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 28108 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 28109 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 28110 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 28111 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 28112 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 28113 | //BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP |
|---|
| 28114 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 28115 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 28116 | //BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL |
|---|
| 28117 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 28118 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 28119 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 28120 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 28121 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 28122 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 28123 | //BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP |
|---|
| 28124 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 28125 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 28126 | //BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL |
|---|
| 28127 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 28128 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 28129 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 28130 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 28131 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 28132 | #define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 28133 | //BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 28134 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 28135 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 28136 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 28137 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 28138 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 28139 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 28140 | //BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 28141 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 28142 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 28143 | //BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA |
|---|
| 28144 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 28145 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 28146 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 28147 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 28148 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 28149 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 28150 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 28151 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 28152 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 28153 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 28154 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 28155 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 28156 | //BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP |
|---|
| 28157 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 28158 | #define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 28159 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST |
|---|
| 28160 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 28161 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 28162 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 28163 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 28164 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 28165 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 28166 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP |
|---|
| 28167 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 28168 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 28169 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 28170 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 28171 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 28172 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 28173 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 28174 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 28175 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 28176 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 28177 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 28178 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 28179 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 28180 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS |
|---|
| 28181 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 28182 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 28183 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 28184 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 28185 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL |
|---|
| 28186 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 28187 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 28188 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 28189 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 28190 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 28191 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 28192 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 28193 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 28194 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 28195 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 28196 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 28197 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 28198 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 28199 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 28200 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 28201 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 28202 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 28203 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 28204 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 28205 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 28206 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 28207 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 28208 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 28209 | //BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 28210 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 28211 | #define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 28212 | //BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST |
|---|
| 28213 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 28214 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 28215 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 28216 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 28217 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 28218 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 28219 | //BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP |
|---|
| 28220 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 28221 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 28222 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 28223 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 28224 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 28225 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 28226 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 28227 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 28228 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 28229 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 28230 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 28231 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 28232 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 28233 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 28234 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 28235 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 28236 | //BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL |
|---|
| 28237 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 28238 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 28239 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 28240 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 28241 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 28242 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 28243 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 28244 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 28245 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 28246 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 28247 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 28248 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 28249 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 28250 | #define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 28251 | //BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST |
|---|
| 28252 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 28253 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 28254 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 28255 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 28256 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 28257 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 28258 | //BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP |
|---|
| 28259 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 28260 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 28261 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 28262 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 28263 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 28264 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 28265 | //BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL |
|---|
| 28266 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 28267 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 28268 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 28269 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 28270 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 28271 | #define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 28272 | //BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST |
|---|
| 28273 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 28274 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 28275 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 28276 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 28277 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 28278 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 28279 | //BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP |
|---|
| 28280 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 28281 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 28282 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 28283 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 28284 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 28285 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 28286 | //BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL |
|---|
| 28287 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 28288 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 28289 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 28290 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 28291 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 28292 | #define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 28293 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 28294 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 28295 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 28296 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 28297 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 28298 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 28299 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 28300 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP |
|---|
| 28301 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 28302 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 28303 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 28304 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 28305 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 28306 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 28307 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 28308 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 28309 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 28310 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 28311 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 28312 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 28313 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL |
|---|
| 28314 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 28315 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 28316 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 28317 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 28318 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0 |
|---|
| 28319 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28320 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28321 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28322 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28323 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1 |
|---|
| 28324 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28325 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28326 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28327 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28328 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2 |
|---|
| 28329 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28330 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28331 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28332 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28333 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3 |
|---|
| 28334 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28335 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28336 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28337 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28338 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4 |
|---|
| 28339 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28340 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28341 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28342 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28343 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5 |
|---|
| 28344 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28345 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28346 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28347 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28348 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6 |
|---|
| 28349 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28350 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28351 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28352 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28353 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7 |
|---|
| 28354 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28355 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28356 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28357 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28358 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8 |
|---|
| 28359 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28360 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28361 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28362 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28363 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9 |
|---|
| 28364 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28365 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28366 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28367 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28368 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10 |
|---|
| 28369 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28370 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28371 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28372 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28373 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11 |
|---|
| 28374 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28375 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28376 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28377 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28378 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12 |
|---|
| 28379 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28380 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28381 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28382 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28383 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13 |
|---|
| 28384 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28385 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28386 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28387 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28388 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14 |
|---|
| 28389 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28390 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28391 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28392 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28393 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15 |
|---|
| 28394 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28395 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28396 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28397 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28398 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16 |
|---|
| 28399 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28400 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28401 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28402 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28403 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17 |
|---|
| 28404 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28405 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28406 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28407 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28408 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18 |
|---|
| 28409 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28410 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28411 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28412 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28413 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19 |
|---|
| 28414 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28415 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28416 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28417 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28418 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20 |
|---|
| 28419 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28420 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28421 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28422 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28423 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21 |
|---|
| 28424 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28425 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28426 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28427 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28428 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22 |
|---|
| 28429 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28430 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28431 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28432 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28433 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23 |
|---|
| 28434 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28435 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28436 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28437 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28438 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24 |
|---|
| 28439 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28440 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28441 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28442 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28443 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25 |
|---|
| 28444 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28445 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28446 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28447 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28448 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26 |
|---|
| 28449 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28450 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28451 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28452 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28453 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27 |
|---|
| 28454 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28455 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28456 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28457 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28458 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28 |
|---|
| 28459 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28460 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28461 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28462 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28463 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29 |
|---|
| 28464 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28465 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28466 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28467 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28468 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30 |
|---|
| 28469 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28470 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28471 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28472 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28473 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31 |
|---|
| 28474 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28475 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28476 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28477 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28478 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32 |
|---|
| 28479 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28480 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28481 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28482 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28483 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33 |
|---|
| 28484 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28485 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28486 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28487 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28488 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34 |
|---|
| 28489 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28490 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28491 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28492 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28493 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35 |
|---|
| 28494 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28495 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28496 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28497 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28498 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36 |
|---|
| 28499 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28500 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28501 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28502 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28503 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37 |
|---|
| 28504 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28505 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28506 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28507 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28508 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38 |
|---|
| 28509 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28510 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28511 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28512 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28513 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39 |
|---|
| 28514 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28515 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28516 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28517 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28518 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40 |
|---|
| 28519 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28520 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28521 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28522 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28523 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41 |
|---|
| 28524 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28525 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28526 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28527 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28528 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42 |
|---|
| 28529 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28530 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28531 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28532 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28533 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43 |
|---|
| 28534 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28535 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28536 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28537 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28538 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44 |
|---|
| 28539 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28540 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28541 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28542 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28543 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45 |
|---|
| 28544 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28545 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28546 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28547 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28548 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46 |
|---|
| 28549 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28550 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28551 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28552 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28553 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47 |
|---|
| 28554 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28555 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28556 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28557 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28558 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48 |
|---|
| 28559 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28560 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28561 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28562 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28563 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49 |
|---|
| 28564 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28565 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28566 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28567 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28568 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50 |
|---|
| 28569 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28570 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28571 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28572 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28573 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51 |
|---|
| 28574 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28575 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28576 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28577 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28578 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52 |
|---|
| 28579 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28580 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28581 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28582 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28583 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53 |
|---|
| 28584 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28585 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28586 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28587 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28588 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54 |
|---|
| 28589 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28590 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28591 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28592 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28593 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55 |
|---|
| 28594 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28595 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28596 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28597 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28598 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56 |
|---|
| 28599 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28600 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28601 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28602 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28603 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57 |
|---|
| 28604 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28605 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28606 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28607 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28608 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58 |
|---|
| 28609 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28610 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28611 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28612 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28613 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59 |
|---|
| 28614 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28615 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28616 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28617 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28618 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60 |
|---|
| 28619 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28620 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28621 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28622 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28623 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61 |
|---|
| 28624 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28625 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28626 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28627 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28628 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62 |
|---|
| 28629 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28630 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28631 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28632 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28633 | //BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63 |
|---|
| 28634 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 28635 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 28636 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 28637 | #define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 28638 | |
|---|
| 28639 | |
|---|
| 28640 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp |
|---|
| 28641 | //BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID |
|---|
| 28642 | #define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 28643 | #define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 28644 | //BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID |
|---|
| 28645 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 28646 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 28647 | //BIF_CFG_DEV0_EPF0_VF0_COMMAND |
|---|
| 28648 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 28649 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 28650 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 28651 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 28652 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 28653 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 28654 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 28655 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 28656 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 28657 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 28658 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 28659 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 28660 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 28661 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 28662 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 28663 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 28664 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 28665 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 28666 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 28667 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 28668 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 28669 | #define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 28670 | //BIF_CFG_DEV0_EPF0_VF0_STATUS |
|---|
| 28671 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 28672 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 28673 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 28674 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 28675 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 28676 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 28677 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 28678 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 28679 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 28680 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 28681 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 28682 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 28683 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 28684 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 28685 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 28686 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 28687 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 28688 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 28689 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 28690 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 28691 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 28692 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 28693 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 28694 | #define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 28695 | //BIF_CFG_DEV0_EPF0_VF0_REVISION_ID |
|---|
| 28696 | #define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 28697 | #define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 28698 | #define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 28699 | #define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 28700 | //BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE |
|---|
| 28701 | #define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 28702 | #define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 28703 | //BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS |
|---|
| 28704 | #define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 28705 | #define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 28706 | //BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS |
|---|
| 28707 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 28708 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 28709 | //BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE |
|---|
| 28710 | #define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 28711 | #define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 28712 | //BIF_CFG_DEV0_EPF0_VF0_LATENCY |
|---|
| 28713 | #define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 28714 | #define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 28715 | //BIF_CFG_DEV0_EPF0_VF0_HEADER |
|---|
| 28716 | #define 0x0 |
|---|
| 28717 | #define 0x7 |
|---|
| 28718 | #define 0x7FL |
|---|
| 28719 | #define 0x80L |
|---|
| 28720 | //BIF_CFG_DEV0_EPF0_VF0_BIST |
|---|
| 28721 | #define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 28722 | #define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 28723 | #define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 28724 | #define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 28725 | #define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 28726 | #define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 28727 | //BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 |
|---|
| 28728 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 28729 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 28730 | //BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 |
|---|
| 28731 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 28732 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 28733 | //BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 |
|---|
| 28734 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 28735 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 28736 | //BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 |
|---|
| 28737 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 28738 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 28739 | //BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 |
|---|
| 28740 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 28741 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 28742 | //BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 |
|---|
| 28743 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 28744 | #define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 28745 | //BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR |
|---|
| 28746 | #define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 28747 | #define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 28748 | //BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID |
|---|
| 28749 | #define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 28750 | #define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 28751 | #define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 28752 | #define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 28753 | //BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR |
|---|
| 28754 | #define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 28755 | #define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 28756 | //BIF_CFG_DEV0_EPF0_VF0_CAP_PTR |
|---|
| 28757 | #define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 28758 | #define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 28759 | //BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE |
|---|
| 28760 | #define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 28761 | #define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 28762 | //BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN |
|---|
| 28763 | #define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 28764 | #define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 28765 | //BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT |
|---|
| 28766 | #define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 28767 | #define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 28768 | //BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY |
|---|
| 28769 | #define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 28770 | #define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 28771 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST |
|---|
| 28772 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 28773 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 28774 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 28775 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 28776 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP |
|---|
| 28777 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 28778 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 28779 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 28780 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 28781 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 28782 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 28783 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 28784 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 28785 | //BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP |
|---|
| 28786 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 28787 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 28788 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 28789 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 28790 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 28791 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 28792 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 28793 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 28794 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 28795 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 28796 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 28797 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 28798 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 28799 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 28800 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 28801 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 28802 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 28803 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 28804 | //BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL |
|---|
| 28805 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 28806 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 28807 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 28808 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 28809 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 28810 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 28811 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 28812 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 28813 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 28814 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 28815 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 28816 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 28817 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 28818 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 28819 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 28820 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 28821 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 28822 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 28823 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 28824 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 28825 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 28826 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 28827 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 28828 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 28829 | //BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS |
|---|
| 28830 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 28831 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 28832 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 28833 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 28834 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 28835 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 28836 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 28837 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 28838 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 28839 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 28840 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 28841 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 28842 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 28843 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 28844 | //BIF_CFG_DEV0_EPF0_VF0_LINK_CAP |
|---|
| 28845 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 28846 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 28847 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 28848 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 28849 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 28850 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 28851 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 28852 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 28853 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 28854 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 28855 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 28856 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 28857 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 28858 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 28859 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 28860 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 28861 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 28862 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 28863 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 28864 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 28865 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 28866 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 28867 | //BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL |
|---|
| 28868 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 28869 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 28870 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 28871 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 28872 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 28873 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 28874 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 28875 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 28876 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 28877 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 28878 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 28879 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 28880 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 28881 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 28882 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 28883 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 28884 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 28885 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 28886 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 28887 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 28888 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 28889 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 28890 | //BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS |
|---|
| 28891 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 28892 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 28893 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 28894 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 28895 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 28896 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 28897 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 28898 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 28899 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 28900 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 28901 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 28902 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 28903 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 28904 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 28905 | //BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 |
|---|
| 28906 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 28907 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 28908 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 28909 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 28910 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 28911 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 28912 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 28913 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 28914 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 28915 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 28916 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 28917 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 28918 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 28919 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 28920 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 28921 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 28922 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 28923 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 28924 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 28925 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 28926 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 28927 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 28928 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 28929 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 28930 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 28931 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 28932 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 28933 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 28934 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 28935 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 28936 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 28937 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 28938 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 28939 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 28940 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 28941 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 28942 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 28943 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 28944 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 28945 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 28946 | //BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 |
|---|
| 28947 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 28948 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 28949 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 28950 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 28951 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 28952 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 28953 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 28954 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 28955 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 28956 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 28957 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 28958 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 28959 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 28960 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 28961 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 28962 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 28963 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 28964 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 28965 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 28966 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 28967 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 28968 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 28969 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 28970 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 28971 | //BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 |
|---|
| 28972 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 28973 | #define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 28974 | //BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 |
|---|
| 28975 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 28976 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 28977 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 28978 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 28979 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 28980 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 28981 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 28982 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 28983 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 28984 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 28985 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 28986 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 28987 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 28988 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 28989 | //BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 |
|---|
| 28990 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 28991 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 28992 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 28993 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 28994 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 28995 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 28996 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 28997 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 28998 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 28999 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 29000 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 29001 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 29002 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 29003 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 29004 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 29005 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 29006 | //BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 |
|---|
| 29007 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 29008 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 29009 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 29010 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 29011 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 29012 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 29013 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 29014 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 29015 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 29016 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 29017 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 29018 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 29019 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 29020 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 29021 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 29022 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 29023 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 29024 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 29025 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 29026 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 29027 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 29028 | #define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 29029 | //BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST |
|---|
| 29030 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29031 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 29032 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 29033 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 29034 | //BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL |
|---|
| 29035 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 29036 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 29037 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 29038 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 29039 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 29040 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 29041 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 29042 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 29043 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 29044 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 29045 | //BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO |
|---|
| 29046 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 29047 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 29048 | //BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI |
|---|
| 29049 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 29050 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 29051 | //BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA |
|---|
| 29052 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 29053 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 29054 | //BIF_CFG_DEV0_EPF0_VF0_MSI_MASK |
|---|
| 29055 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 29056 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 29057 | //BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 |
|---|
| 29058 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 29059 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 29060 | //BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 |
|---|
| 29061 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 29062 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 29063 | //BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING |
|---|
| 29064 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 29065 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 29066 | //BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 |
|---|
| 29067 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 29068 | #define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 29069 | //BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST |
|---|
| 29070 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29071 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 29072 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 29073 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 29074 | //BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL |
|---|
| 29075 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 29076 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 29077 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 29078 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 29079 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 29080 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 29081 | //BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE |
|---|
| 29082 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 29083 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 29084 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 29085 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 29086 | //BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA |
|---|
| 29087 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 29088 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 29089 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 29090 | #define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 29091 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 29092 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29093 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 29094 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 29095 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 29096 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 29097 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 29098 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 29099 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 29100 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 29101 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 29102 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 29103 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 29104 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 29105 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 29106 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 29107 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 29108 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 29109 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 29110 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 29111 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 29112 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29113 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 29114 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 29115 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 29116 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 29117 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 29118 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS |
|---|
| 29119 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 29120 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 29121 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 29122 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 29123 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 29124 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 29125 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 29126 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 29127 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 29128 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 29129 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 29130 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 29131 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 29132 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 29133 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 29134 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 29135 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 29136 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 29137 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 29138 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 29139 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 29140 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 29141 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 29142 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 29143 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 29144 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 29145 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 29146 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 29147 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 29148 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 29149 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 29150 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 29151 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK |
|---|
| 29152 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 29153 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 29154 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 29155 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 29156 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 29157 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 29158 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 29159 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 29160 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 29161 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 29162 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 29163 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 29164 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 29165 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 29166 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 29167 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 29168 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 29169 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 29170 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 29171 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 29172 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 29173 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 29174 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 29175 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 29176 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 29177 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 29178 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 29179 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 29180 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 29181 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 29182 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 29183 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 29184 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 29185 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 29186 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 29187 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 29188 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 29189 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 29190 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 29191 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 29192 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 29193 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 29194 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 29195 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 29196 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 29197 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 29198 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 29199 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 29200 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 29201 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 29202 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 29203 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 29204 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 29205 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 29206 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 29207 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 29208 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 29209 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 29210 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 29211 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 29212 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 29213 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 29214 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 29215 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 29216 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 29217 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS |
|---|
| 29218 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 29219 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 29220 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 29221 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 29222 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 29223 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 29224 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 29225 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 29226 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 29227 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 29228 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 29229 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 29230 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 29231 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 29232 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 29233 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 29234 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK |
|---|
| 29235 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 29236 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 29237 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 29238 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 29239 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 29240 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 29241 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 29242 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 29243 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 29244 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 29245 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 29246 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 29247 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 29248 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 29249 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 29250 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 29251 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 29252 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 29253 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 29254 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 29255 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 29256 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 29257 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 29258 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 29259 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 29260 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 29261 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 29262 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 29263 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 29264 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 29265 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 29266 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 29267 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 29268 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 29269 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 29270 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 |
|---|
| 29271 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 29272 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 29273 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 |
|---|
| 29274 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 29275 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 29276 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 |
|---|
| 29277 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 29278 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 29279 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 |
|---|
| 29280 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 29281 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 29282 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 29283 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 29284 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 29285 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 29286 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 29287 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 29288 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 29289 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 29290 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 29291 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 29292 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 29293 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 29294 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 29295 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29296 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 29297 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 29298 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 29299 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 29300 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 29301 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP |
|---|
| 29302 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 29303 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 29304 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 29305 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 29306 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 29307 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 29308 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL |
|---|
| 29309 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 29310 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 29311 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 29312 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 29313 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 29314 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29315 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 29316 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 29317 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 29318 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 29319 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 29320 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP |
|---|
| 29321 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 29322 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 29323 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 29324 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 29325 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 29326 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 29327 | //BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL |
|---|
| 29328 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 29329 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 29330 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 29331 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 29332 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 29333 | #define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 29334 | |
|---|
| 29335 | |
|---|
| 29336 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp |
|---|
| 29337 | //BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID |
|---|
| 29338 | #define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 29339 | #define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 29340 | //BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID |
|---|
| 29341 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 29342 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 29343 | //BIF_CFG_DEV0_EPF0_VF1_COMMAND |
|---|
| 29344 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 29345 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 29346 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 29347 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 29348 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 29349 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 29350 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 29351 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 29352 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 29353 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 29354 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 29355 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 29356 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 29357 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 29358 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 29359 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 29360 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 29361 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 29362 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 29363 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 29364 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 29365 | #define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 29366 | //BIF_CFG_DEV0_EPF0_VF1_STATUS |
|---|
| 29367 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 29368 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 29369 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 29370 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 29371 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 29372 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 29373 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 29374 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 29375 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 29376 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 29377 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 29378 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 29379 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 29380 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 29381 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 29382 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 29383 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 29384 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 29385 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 29386 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 29387 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 29388 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 29389 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 29390 | #define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 29391 | //BIF_CFG_DEV0_EPF0_VF1_REVISION_ID |
|---|
| 29392 | #define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 29393 | #define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 29394 | #define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 29395 | #define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 29396 | //BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE |
|---|
| 29397 | #define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 29398 | #define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 29399 | //BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS |
|---|
| 29400 | #define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 29401 | #define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 29402 | //BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS |
|---|
| 29403 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 29404 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 29405 | //BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE |
|---|
| 29406 | #define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 29407 | #define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 29408 | //BIF_CFG_DEV0_EPF0_VF1_LATENCY |
|---|
| 29409 | #define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 29410 | #define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 29411 | //BIF_CFG_DEV0_EPF0_VF1_HEADER |
|---|
| 29412 | #define 0x0 |
|---|
| 29413 | #define 0x7 |
|---|
| 29414 | #define 0x7FL |
|---|
| 29415 | #define 0x80L |
|---|
| 29416 | //BIF_CFG_DEV0_EPF0_VF1_BIST |
|---|
| 29417 | #define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 29418 | #define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 29419 | #define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 29420 | #define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 29421 | #define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 29422 | #define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 29423 | //BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 |
|---|
| 29424 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 29425 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 29426 | //BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 |
|---|
| 29427 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 29428 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 29429 | //BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 |
|---|
| 29430 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 29431 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 29432 | //BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 |
|---|
| 29433 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 29434 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 29435 | //BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 |
|---|
| 29436 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 29437 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 29438 | //BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 |
|---|
| 29439 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 29440 | #define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 29441 | //BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR |
|---|
| 29442 | #define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 29443 | #define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 29444 | //BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID |
|---|
| 29445 | #define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 29446 | #define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 29447 | #define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 29448 | #define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 29449 | //BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR |
|---|
| 29450 | #define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 29451 | #define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 29452 | //BIF_CFG_DEV0_EPF0_VF1_CAP_PTR |
|---|
| 29453 | #define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 29454 | #define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 29455 | //BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE |
|---|
| 29456 | #define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 29457 | #define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 29458 | //BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN |
|---|
| 29459 | #define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 29460 | #define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 29461 | //BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT |
|---|
| 29462 | #define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 29463 | #define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 29464 | //BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY |
|---|
| 29465 | #define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 29466 | #define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 29467 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST |
|---|
| 29468 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29469 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 29470 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 29471 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 29472 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP |
|---|
| 29473 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 29474 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 29475 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 29476 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 29477 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 29478 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 29479 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 29480 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 29481 | //BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP |
|---|
| 29482 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 29483 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 29484 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 29485 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 29486 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 29487 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 29488 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 29489 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 29490 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 29491 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 29492 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 29493 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 29494 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 29495 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 29496 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 29497 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 29498 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 29499 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 29500 | //BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL |
|---|
| 29501 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 29502 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 29503 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 29504 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 29505 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 29506 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 29507 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 29508 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 29509 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 29510 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 29511 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 29512 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 29513 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 29514 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 29515 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 29516 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 29517 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 29518 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 29519 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 29520 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 29521 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 29522 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 29523 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 29524 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 29525 | //BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS |
|---|
| 29526 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 29527 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 29528 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 29529 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 29530 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 29531 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 29532 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 29533 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 29534 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 29535 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 29536 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 29537 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 29538 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 29539 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 29540 | //BIF_CFG_DEV0_EPF0_VF1_LINK_CAP |
|---|
| 29541 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 29542 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 29543 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 29544 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 29545 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 29546 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 29547 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 29548 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 29549 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 29550 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 29551 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 29552 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 29553 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 29554 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 29555 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 29556 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 29557 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 29558 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 29559 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 29560 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 29561 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 29562 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 29563 | //BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL |
|---|
| 29564 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 29565 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 29566 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 29567 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 29568 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 29569 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 29570 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 29571 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 29572 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 29573 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 29574 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 29575 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 29576 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 29577 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 29578 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 29579 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 29580 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 29581 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 29582 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 29583 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 29584 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 29585 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 29586 | //BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS |
|---|
| 29587 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 29588 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 29589 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 29590 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 29591 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 29592 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 29593 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 29594 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 29595 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 29596 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 29597 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 29598 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 29599 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 29600 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 29601 | //BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 |
|---|
| 29602 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 29603 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 29604 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 29605 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 29606 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 29607 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 29608 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 29609 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 29610 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 29611 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 29612 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 29613 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 29614 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 29615 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 29616 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 29617 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 29618 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 29619 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 29620 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 29621 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 29622 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 29623 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 29624 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 29625 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 29626 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 29627 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 29628 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 29629 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 29630 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 29631 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 29632 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 29633 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 29634 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 29635 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 29636 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 29637 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 29638 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 29639 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 29640 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 29641 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 29642 | //BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 |
|---|
| 29643 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 29644 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 29645 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 29646 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 29647 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 29648 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 29649 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 29650 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 29651 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 29652 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 29653 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 29654 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 29655 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 29656 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 29657 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 29658 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 29659 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 29660 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 29661 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 29662 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 29663 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 29664 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 29665 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 29666 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 29667 | //BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 |
|---|
| 29668 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 29669 | #define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 29670 | //BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 |
|---|
| 29671 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 29672 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 29673 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 29674 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 29675 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 29676 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 29677 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 29678 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 29679 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 29680 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 29681 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 29682 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 29683 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 29684 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 29685 | //BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 |
|---|
| 29686 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 29687 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 29688 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 29689 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 29690 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 29691 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 29692 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 29693 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 29694 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 29695 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 29696 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 29697 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 29698 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 29699 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 29700 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 29701 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 29702 | //BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 |
|---|
| 29703 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 29704 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 29705 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 29706 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 29707 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 29708 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 29709 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 29710 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 29711 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 29712 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 29713 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 29714 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 29715 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 29716 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 29717 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 29718 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 29719 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 29720 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 29721 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 29722 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 29723 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 29724 | #define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 29725 | //BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST |
|---|
| 29726 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29727 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 29728 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 29729 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 29730 | //BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL |
|---|
| 29731 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 29732 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 29733 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 29734 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 29735 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 29736 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 29737 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 29738 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 29739 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 29740 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 29741 | //BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO |
|---|
| 29742 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 29743 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 29744 | //BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI |
|---|
| 29745 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 29746 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 29747 | //BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA |
|---|
| 29748 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 29749 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 29750 | //BIF_CFG_DEV0_EPF0_VF1_MSI_MASK |
|---|
| 29751 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 29752 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 29753 | //BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 |
|---|
| 29754 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 29755 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 29756 | //BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 |
|---|
| 29757 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 29758 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 29759 | //BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING |
|---|
| 29760 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 29761 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 29762 | //BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 |
|---|
| 29763 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 29764 | #define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 29765 | //BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST |
|---|
| 29766 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29767 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 29768 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 29769 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 29770 | //BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL |
|---|
| 29771 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 29772 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 29773 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 29774 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 29775 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 29776 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 29777 | //BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE |
|---|
| 29778 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 29779 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 29780 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 29781 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 29782 | //BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA |
|---|
| 29783 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 29784 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 29785 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 29786 | #define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 29787 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 29788 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29789 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 29790 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 29791 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 29792 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 29793 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 29794 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 29795 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 29796 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 29797 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 29798 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 29799 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 29800 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 29801 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 29802 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 29803 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 29804 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 29805 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 29806 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 29807 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 29808 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29809 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 29810 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 29811 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 29812 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 29813 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 29814 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS |
|---|
| 29815 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 29816 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 29817 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 29818 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 29819 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 29820 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 29821 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 29822 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 29823 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 29824 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 29825 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 29826 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 29827 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 29828 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 29829 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 29830 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 29831 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 29832 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 29833 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 29834 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 29835 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 29836 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 29837 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 29838 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 29839 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 29840 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 29841 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 29842 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 29843 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 29844 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 29845 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 29846 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 29847 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK |
|---|
| 29848 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 29849 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 29850 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 29851 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 29852 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 29853 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 29854 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 29855 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 29856 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 29857 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 29858 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 29859 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 29860 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 29861 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 29862 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 29863 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 29864 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 29865 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 29866 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 29867 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 29868 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 29869 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 29870 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 29871 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 29872 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 29873 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 29874 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 29875 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 29876 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 29877 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 29878 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 29879 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 29880 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 29881 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 29882 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 29883 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 29884 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 29885 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 29886 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 29887 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 29888 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 29889 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 29890 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 29891 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 29892 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 29893 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 29894 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 29895 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 29896 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 29897 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 29898 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 29899 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 29900 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 29901 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 29902 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 29903 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 29904 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 29905 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 29906 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 29907 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 29908 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 29909 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 29910 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 29911 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 29912 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 29913 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS |
|---|
| 29914 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 29915 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 29916 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 29917 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 29918 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 29919 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 29920 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 29921 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 29922 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 29923 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 29924 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 29925 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 29926 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 29927 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 29928 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 29929 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 29930 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK |
|---|
| 29931 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 29932 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 29933 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 29934 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 29935 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 29936 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 29937 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 29938 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 29939 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 29940 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 29941 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 29942 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 29943 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 29944 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 29945 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 29946 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 29947 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 29948 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 29949 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 29950 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 29951 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 29952 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 29953 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 29954 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 29955 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 29956 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 29957 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 29958 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 29959 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 29960 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 29961 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 29962 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 29963 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 29964 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 29965 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 29966 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 |
|---|
| 29967 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 29968 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 29969 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 |
|---|
| 29970 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 29971 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 29972 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 |
|---|
| 29973 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 29974 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 29975 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 |
|---|
| 29976 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 29977 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 29978 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 29979 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 29980 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 29981 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 29982 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 29983 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 29984 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 29985 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 29986 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 29987 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 29988 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 29989 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 29990 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 29991 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 29992 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 29993 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 29994 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 29995 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 29996 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 29997 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP |
|---|
| 29998 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 29999 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 30000 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 30001 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 30002 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 30003 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 30004 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL |
|---|
| 30005 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 30006 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 30007 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 30008 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 30009 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 30010 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 30011 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 30012 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 30013 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 30014 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 30015 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 30016 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP |
|---|
| 30017 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 30018 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 30019 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 30020 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 30021 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 30022 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 30023 | //BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL |
|---|
| 30024 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 30025 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 30026 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 30027 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 30028 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 30029 | #define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 30030 | |
|---|
| 30031 | |
|---|
| 30032 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp |
|---|
| 30033 | //BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID |
|---|
| 30034 | #define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 30035 | #define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 30036 | //BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID |
|---|
| 30037 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 30038 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 30039 | //BIF_CFG_DEV0_EPF0_VF2_COMMAND |
|---|
| 30040 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 30041 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 30042 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 30043 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 30044 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 30045 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 30046 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 30047 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 30048 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 30049 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 30050 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 30051 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 30052 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 30053 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 30054 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 30055 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 30056 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 30057 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 30058 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 30059 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 30060 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 30061 | #define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 30062 | //BIF_CFG_DEV0_EPF0_VF2_STATUS |
|---|
| 30063 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 30064 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 30065 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 30066 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 30067 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 30068 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 30069 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 30070 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 30071 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 30072 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 30073 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 30074 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 30075 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 30076 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 30077 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 30078 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 30079 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 30080 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 30081 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 30082 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 30083 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 30084 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 30085 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 30086 | #define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 30087 | //BIF_CFG_DEV0_EPF0_VF2_REVISION_ID |
|---|
| 30088 | #define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 30089 | #define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 30090 | #define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 30091 | #define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 30092 | //BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE |
|---|
| 30093 | #define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 30094 | #define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 30095 | //BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS |
|---|
| 30096 | #define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 30097 | #define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 30098 | //BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS |
|---|
| 30099 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 30100 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 30101 | //BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE |
|---|
| 30102 | #define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 30103 | #define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 30104 | //BIF_CFG_DEV0_EPF0_VF2_LATENCY |
|---|
| 30105 | #define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 30106 | #define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 30107 | //BIF_CFG_DEV0_EPF0_VF2_HEADER |
|---|
| 30108 | #define 0x0 |
|---|
| 30109 | #define 0x7 |
|---|
| 30110 | #define 0x7FL |
|---|
| 30111 | #define 0x80L |
|---|
| 30112 | //BIF_CFG_DEV0_EPF0_VF2_BIST |
|---|
| 30113 | #define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 30114 | #define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 30115 | #define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 30116 | #define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 30117 | #define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK 0x40L |
|---|
| 30118 | #define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK 0x80L |
|---|
| 30119 | //BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 |
|---|
| 30120 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 30121 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30122 | //BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 |
|---|
| 30123 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 30124 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30125 | //BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 |
|---|
| 30126 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 30127 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30128 | //BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 |
|---|
| 30129 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 30130 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30131 | //BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 |
|---|
| 30132 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 30133 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30134 | //BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 |
|---|
| 30135 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 30136 | #define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30137 | //BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR |
|---|
| 30138 | #define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 30139 | #define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 30140 | //BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID |
|---|
| 30141 | #define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 30142 | #define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 30143 | #define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 30144 | #define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 30145 | //BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR |
|---|
| 30146 | #define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 30147 | #define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30148 | //BIF_CFG_DEV0_EPF0_VF2_CAP_PTR |
|---|
| 30149 | #define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 30150 | #define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 30151 | //BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE |
|---|
| 30152 | #define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 30153 | #define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 30154 | //BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN |
|---|
| 30155 | #define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 30156 | #define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 30157 | //BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT |
|---|
| 30158 | #define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 30159 | #define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 30160 | //BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY |
|---|
| 30161 | #define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 30162 | #define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 30163 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST |
|---|
| 30164 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 30165 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 30166 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 30167 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 30168 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP |
|---|
| 30169 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 30170 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 30171 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 30172 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 30173 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 30174 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 30175 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 30176 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 30177 | //BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP |
|---|
| 30178 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 30179 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 30180 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 30181 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 30182 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 30183 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 30184 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 30185 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 30186 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 30187 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 30188 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 30189 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 30190 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 30191 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 30192 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 30193 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 30194 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 30195 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 30196 | //BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL |
|---|
| 30197 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
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| 30198 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
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| 30199 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
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| 30200 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
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| 30201 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 30202 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 30203 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
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| 30204 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
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| 30205 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
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| 30206 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 30207 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 30208 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
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| 30209 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
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| 30210 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
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| 30211 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
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| 30212 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
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| 30213 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
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| 30214 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
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| 30215 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
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| 30216 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
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| 30217 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
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| 30218 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
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| 30219 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
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| 30220 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
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| 30221 | //BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS |
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| 30222 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
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| 30223 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
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| 30224 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
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| 30225 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 30226 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 30227 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 30228 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
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| 30229 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
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| 30230 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 30231 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
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| 30232 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
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| 30233 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
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| 30234 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
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| 30235 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
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| 30236 | //BIF_CFG_DEV0_EPF0_VF2_LINK_CAP |
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| 30237 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
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| 30238 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 30239 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 30240 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
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| 30241 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 30242 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
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| 30243 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
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| 30244 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 30245 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
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| 30246 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 30247 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 30248 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
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| 30249 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
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| 30250 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
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| 30251 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 30252 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
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| 30253 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
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| 30254 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
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| 30255 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
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| 30256 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
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| 30257 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
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| 30258 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
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| 30259 | //BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL |
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| 30260 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
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| 30261 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
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| 30262 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
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| 30263 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
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| 30264 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
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| 30265 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
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| 30266 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
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| 30267 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
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| 30268 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
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| 30269 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
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| 30270 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
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| 30271 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
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| 30272 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
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| 30273 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK 0x0010L |
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| 30274 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
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| 30275 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
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| 30276 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
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| 30277 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
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| 30278 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
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| 30279 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
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| 30280 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
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| 30281 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
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| 30282 | //BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS |
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| 30283 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
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| 30284 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
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| 30285 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
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| 30286 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
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| 30287 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
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| 30288 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
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| 30289 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
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| 30290 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
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| 30291 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
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| 30292 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
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| 30293 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
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| 30294 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
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| 30295 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
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| 30296 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
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| 30297 | //BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 |
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| 30298 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
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| 30299 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
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| 30300 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
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| 30301 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
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| 30302 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
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| 30303 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
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| 30304 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
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| 30305 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
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| 30306 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
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| 30307 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
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| 30308 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
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| 30309 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
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| 30310 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
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| 30311 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
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| 30312 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
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| 30313 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
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| 30314 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
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| 30315 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
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| 30316 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
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| 30317 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
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| 30318 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
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| 30319 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
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| 30320 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
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| 30321 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
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| 30322 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
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| 30323 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
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| 30324 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
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| 30325 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
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| 30326 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
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| 30327 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
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| 30328 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
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| 30329 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
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| 30330 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
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| 30331 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
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| 30332 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
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| 30333 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
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| 30334 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
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| 30335 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
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| 30336 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
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| 30337 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
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| 30338 | //BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 |
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| 30339 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
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| 30340 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
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| 30341 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
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| 30342 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
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| 30343 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
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| 30344 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
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| 30345 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
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| 30346 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
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| 30347 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
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| 30348 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
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| 30349 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
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| 30350 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
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| 30351 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
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| 30352 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
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| 30353 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
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| 30354 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
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| 30355 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
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| 30356 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
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| 30357 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
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| 30358 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
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| 30359 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 30360 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
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| 30361 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
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| 30362 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
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| 30363 | //BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 |
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| 30364 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
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| 30365 | #define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
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| 30366 | //BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 |
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| 30367 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
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| 30368 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
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| 30369 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
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| 30370 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
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| 30371 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
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| 30372 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
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| 30373 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 30374 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 30375 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 30376 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 30377 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 30378 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 30379 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 30380 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 30381 | //BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 |
|---|
| 30382 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 30383 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 30384 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 30385 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 30386 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 30387 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 30388 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 30389 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 30390 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 30391 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 30392 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 30393 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 30394 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 30395 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 30396 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 30397 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 30398 | //BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 |
|---|
| 30399 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 30400 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 30401 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 30402 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 30403 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 30404 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 30405 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 30406 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 30407 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 30408 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 30409 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 30410 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 30411 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 30412 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 30413 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 30414 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 30415 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 30416 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 30417 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 30418 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 30419 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 30420 | #define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 30421 | //BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST |
|---|
| 30422 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 30423 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 30424 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 30425 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 30426 | //BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL |
|---|
| 30427 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 30428 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 30429 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 30430 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 30431 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 30432 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 30433 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 30434 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 30435 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 30436 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 30437 | //BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO |
|---|
| 30438 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 30439 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 30440 | //BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI |
|---|
| 30441 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 30442 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 30443 | //BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA |
|---|
| 30444 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 30445 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 30446 | //BIF_CFG_DEV0_EPF0_VF2_MSI_MASK |
|---|
| 30447 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 30448 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 30449 | //BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 |
|---|
| 30450 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 30451 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 30452 | //BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 |
|---|
| 30453 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 30454 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 30455 | //BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING |
|---|
| 30456 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 30457 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 30458 | //BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 |
|---|
| 30459 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 30460 | #define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 30461 | //BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST |
|---|
| 30462 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 30463 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 30464 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 30465 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 30466 | //BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL |
|---|
| 30467 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 30468 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 30469 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 30470 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 30471 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 30472 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 30473 | //BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE |
|---|
| 30474 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 30475 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 30476 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 30477 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 30478 | //BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA |
|---|
| 30479 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 30480 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 30481 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 30482 | #define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 30483 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 30484 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 30485 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 30486 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 30487 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 30488 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 30489 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 30490 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 30491 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 30492 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 30493 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 30494 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 30495 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 30496 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 30497 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 |
|---|
| 30498 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 30499 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 30500 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 |
|---|
| 30501 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 30502 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 30503 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 30504 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 30505 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 30506 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 30507 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 30508 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 30509 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 30510 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS |
|---|
| 30511 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 30512 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 30513 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 30514 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 30515 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 30516 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 30517 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 30518 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 30519 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 30520 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 30521 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 30522 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 30523 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 30524 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 30525 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 30526 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 30527 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 30528 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 30529 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 30530 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 30531 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 30532 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 30533 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 30534 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 30535 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 30536 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 30537 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 30538 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 30539 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 30540 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 30541 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 30542 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 30543 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK |
|---|
| 30544 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 30545 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 30546 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 30547 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 30548 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 30549 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 30550 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 30551 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 30552 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 30553 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 30554 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 30555 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 30556 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 30557 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 30558 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 30559 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 30560 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 30561 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 30562 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 30563 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 30564 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 30565 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 30566 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 30567 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 30568 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 30569 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 30570 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 30571 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 30572 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 30573 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 30574 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 30575 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 30576 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 30577 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 30578 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 30579 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 30580 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 30581 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 30582 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 30583 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 30584 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 30585 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 30586 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 30587 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 30588 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 30589 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 30590 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 30591 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 30592 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 30593 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 30594 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 30595 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 30596 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 30597 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 30598 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 30599 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 30600 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 30601 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 30602 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 30603 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 30604 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 30605 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 30606 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 30607 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 30608 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 30609 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS |
|---|
| 30610 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 30611 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 30612 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 30613 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 30614 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 30615 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 30616 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 30617 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 30618 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 30619 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 30620 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 30621 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 30622 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 30623 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 30624 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 30625 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 30626 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK |
|---|
| 30627 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 30628 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 30629 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 30630 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 30631 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 30632 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 30633 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 30634 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 30635 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 30636 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 30637 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 30638 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 30639 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 30640 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 30641 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 30642 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 30643 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 30644 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 30645 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 30646 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 30647 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 30648 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 30649 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 30650 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 30651 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 30652 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 30653 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 30654 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 30655 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 30656 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 30657 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 30658 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 30659 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 30660 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 30661 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 30662 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 |
|---|
| 30663 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 30664 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 30665 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 |
|---|
| 30666 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 30667 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 30668 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 |
|---|
| 30669 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 30670 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 30671 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 |
|---|
| 30672 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 30673 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 30674 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 |
|---|
| 30675 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 30676 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 30677 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 |
|---|
| 30678 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 30679 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 30680 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 |
|---|
| 30681 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 30682 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 30683 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 |
|---|
| 30684 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 30685 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 30686 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST |
|---|
| 30687 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 30688 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 30689 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 30690 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 30691 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 30692 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 30693 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP |
|---|
| 30694 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 30695 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 30696 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 30697 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 30698 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 30699 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 30700 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL |
|---|
| 30701 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 30702 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 30703 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 30704 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 30705 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST |
|---|
| 30706 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 30707 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 30708 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 30709 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 30710 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 30711 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 30712 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP |
|---|
| 30713 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 30714 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 30715 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 30716 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 30717 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 30718 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 30719 | //BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL |
|---|
| 30720 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 30721 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 30722 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 30723 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 30724 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 30725 | #define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 30726 | |
|---|
| 30727 | |
|---|
| 30728 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp |
|---|
| 30729 | //BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID |
|---|
| 30730 | #define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 30731 | #define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 30732 | //BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID |
|---|
| 30733 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 30734 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 30735 | //BIF_CFG_DEV0_EPF0_VF3_COMMAND |
|---|
| 30736 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 30737 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 30738 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 30739 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 30740 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 30741 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 30742 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 30743 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 30744 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 30745 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 30746 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 30747 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 30748 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 30749 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 30750 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 30751 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 30752 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 30753 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 30754 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 30755 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 30756 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 30757 | #define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 30758 | //BIF_CFG_DEV0_EPF0_VF3_STATUS |
|---|
| 30759 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 30760 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 30761 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 30762 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 30763 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 30764 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 30765 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 30766 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 30767 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 30768 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 30769 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 30770 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 30771 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 30772 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 30773 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 30774 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 30775 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 30776 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 30777 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 30778 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 30779 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 30780 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 30781 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 30782 | #define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 30783 | //BIF_CFG_DEV0_EPF0_VF3_REVISION_ID |
|---|
| 30784 | #define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 30785 | #define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 30786 | #define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 30787 | #define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 30788 | //BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE |
|---|
| 30789 | #define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 30790 | #define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 30791 | //BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS |
|---|
| 30792 | #define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 30793 | #define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 30794 | //BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS |
|---|
| 30795 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 30796 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 30797 | //BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE |
|---|
| 30798 | #define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 30799 | #define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 30800 | //BIF_CFG_DEV0_EPF0_VF3_LATENCY |
|---|
| 30801 | #define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 30802 | #define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 30803 | //BIF_CFG_DEV0_EPF0_VF3_HEADER |
|---|
| 30804 | #define 0x0 |
|---|
| 30805 | #define 0x7 |
|---|
| 30806 | #define 0x7FL |
|---|
| 30807 | #define 0x80L |
|---|
| 30808 | //BIF_CFG_DEV0_EPF0_VF3_BIST |
|---|
| 30809 | #define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 30810 | #define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 30811 | #define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 30812 | #define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 30813 | #define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK 0x40L |
|---|
| 30814 | #define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK 0x80L |
|---|
| 30815 | //BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 |
|---|
| 30816 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 30817 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30818 | //BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 |
|---|
| 30819 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 30820 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30821 | //BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 |
|---|
| 30822 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 30823 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30824 | //BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 |
|---|
| 30825 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 30826 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30827 | //BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 |
|---|
| 30828 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 30829 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30830 | //BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 |
|---|
| 30831 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 30832 | #define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30833 | //BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR |
|---|
| 30834 | #define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 30835 | #define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 30836 | //BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID |
|---|
| 30837 | #define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 30838 | #define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 30839 | #define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 30840 | #define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 30841 | //BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR |
|---|
| 30842 | #define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 30843 | #define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 30844 | //BIF_CFG_DEV0_EPF0_VF3_CAP_PTR |
|---|
| 30845 | #define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 30846 | #define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 30847 | //BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE |
|---|
| 30848 | #define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 30849 | #define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 30850 | //BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN |
|---|
| 30851 | #define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 30852 | #define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 30853 | //BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT |
|---|
| 30854 | #define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 30855 | #define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 30856 | //BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY |
|---|
| 30857 | #define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 30858 | #define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 30859 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST |
|---|
| 30860 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 30861 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 30862 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 30863 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 30864 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP |
|---|
| 30865 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 30866 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 30867 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 30868 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 30869 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 30870 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 30871 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 30872 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 30873 | //BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP |
|---|
| 30874 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 30875 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 30876 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 30877 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 30878 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 30879 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 30880 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 30881 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 30882 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 30883 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 30884 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 30885 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 30886 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 30887 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 30888 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 30889 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 30890 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 30891 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 30892 | //BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL |
|---|
| 30893 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 30894 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 30895 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 30896 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 30897 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 30898 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 30899 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 30900 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 30901 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 30902 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 30903 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 30904 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 30905 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 30906 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 30907 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 30908 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 30909 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 30910 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 30911 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 30912 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 30913 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 30914 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 30915 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 30916 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 30917 | //BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS |
|---|
| 30918 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 30919 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 30920 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 30921 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 30922 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 30923 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 30924 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 30925 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 30926 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 30927 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 30928 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 30929 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 30930 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 30931 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 30932 | //BIF_CFG_DEV0_EPF0_VF3_LINK_CAP |
|---|
| 30933 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 30934 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 30935 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 30936 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 30937 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 30938 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 30939 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 30940 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 30941 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 30942 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 30943 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 30944 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 30945 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 30946 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 30947 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 30948 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 30949 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 30950 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 30951 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 30952 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 30953 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 30954 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 30955 | //BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL |
|---|
| 30956 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 30957 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 30958 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 30959 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 30960 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 30961 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 30962 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 30963 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 30964 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 30965 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 30966 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 30967 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 30968 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 30969 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 30970 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 30971 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 30972 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 30973 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 30974 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 30975 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 30976 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 30977 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 30978 | //BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS |
|---|
| 30979 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 30980 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 30981 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 30982 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 30983 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 30984 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 30985 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 30986 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 30987 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 30988 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 30989 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 30990 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 30991 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 30992 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 30993 | //BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 |
|---|
| 30994 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 30995 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 30996 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 30997 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 30998 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 30999 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 31000 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 31001 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 31002 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 31003 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 31004 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 31005 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 31006 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 31007 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 31008 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 31009 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 31010 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 31011 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 31012 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 31013 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 31014 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 31015 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 31016 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 31017 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 31018 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 31019 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 31020 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 31021 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 31022 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 31023 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 31024 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 31025 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 31026 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 31027 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 31028 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 31029 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 31030 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 31031 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 31032 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 31033 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 31034 | //BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 |
|---|
| 31035 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 31036 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 31037 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 31038 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 31039 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 31040 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 31041 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 31042 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 31043 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 31044 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 31045 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 31046 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 31047 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 31048 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 31049 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 31050 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 31051 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 31052 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 31053 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 31054 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 31055 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 31056 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 31057 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 31058 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 31059 | //BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 |
|---|
| 31060 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 31061 | #define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 31062 | //BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 |
|---|
| 31063 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 31064 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 31065 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 31066 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 31067 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 31068 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 31069 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 31070 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 31071 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 31072 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 31073 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 31074 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 31075 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 31076 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 31077 | //BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 |
|---|
| 31078 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 31079 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 31080 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 31081 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 31082 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 31083 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 31084 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 31085 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 31086 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 31087 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 31088 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 31089 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 31090 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 31091 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 31092 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 31093 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 31094 | //BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 |
|---|
| 31095 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 31096 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 31097 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 31098 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 31099 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 31100 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 31101 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 31102 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 31103 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 31104 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 31105 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 31106 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 31107 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 31108 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 31109 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 31110 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 31111 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 31112 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 31113 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 31114 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 31115 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 31116 | #define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 31117 | //BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST |
|---|
| 31118 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31119 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 31120 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 31121 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 31122 | //BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL |
|---|
| 31123 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 31124 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 31125 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 31126 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 31127 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 31128 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 31129 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 31130 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 31131 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 31132 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 31133 | //BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO |
|---|
| 31134 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 31135 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 31136 | //BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI |
|---|
| 31137 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 31138 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 31139 | //BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA |
|---|
| 31140 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 31141 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 31142 | //BIF_CFG_DEV0_EPF0_VF3_MSI_MASK |
|---|
| 31143 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 31144 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 31145 | //BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 |
|---|
| 31146 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 31147 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 31148 | //BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 |
|---|
| 31149 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 31150 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 31151 | //BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING |
|---|
| 31152 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 31153 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 31154 | //BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 |
|---|
| 31155 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 31156 | #define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 31157 | //BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST |
|---|
| 31158 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31159 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 31160 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 31161 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 31162 | //BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL |
|---|
| 31163 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 31164 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 31165 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 31166 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 31167 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 31168 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 31169 | //BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE |
|---|
| 31170 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 31171 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 31172 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 31173 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 31174 | //BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA |
|---|
| 31175 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 31176 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 31177 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 31178 | #define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 31179 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 31180 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31181 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 31182 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 31183 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 31184 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 31185 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 31186 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 31187 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 31188 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 31189 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 31190 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 31191 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 31192 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 31193 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 |
|---|
| 31194 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 31195 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 31196 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 |
|---|
| 31197 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 31198 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 31199 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 31200 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31201 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 31202 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 31203 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 31204 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 31205 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 31206 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS |
|---|
| 31207 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 31208 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 31209 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 31210 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 31211 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 31212 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 31213 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 31214 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 31215 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 31216 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 31217 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 31218 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 31219 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 31220 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 31221 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 31222 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 31223 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 31224 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 31225 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 31226 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 31227 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 31228 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 31229 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 31230 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 31231 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 31232 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 31233 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 31234 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 31235 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 31236 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 31237 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 31238 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 31239 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK |
|---|
| 31240 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 31241 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 31242 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 31243 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 31244 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 31245 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 31246 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 31247 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 31248 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 31249 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 31250 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 31251 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 31252 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 31253 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 31254 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 31255 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 31256 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 31257 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 31258 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 31259 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 31260 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 31261 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 31262 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 31263 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 31264 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 31265 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 31266 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 31267 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 31268 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 31269 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 31270 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 31271 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 31272 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 31273 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 31274 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 31275 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 31276 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 31277 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 31278 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 31279 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 31280 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 31281 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 31282 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 31283 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 31284 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 31285 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 31286 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 31287 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 31288 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 31289 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 31290 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 31291 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 31292 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 31293 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 31294 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 31295 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 31296 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 31297 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 31298 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 31299 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 31300 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 31301 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 31302 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 31303 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 31304 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 31305 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS |
|---|
| 31306 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 31307 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 31308 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 31309 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 31310 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 31311 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 31312 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 31313 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 31314 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 31315 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 31316 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 31317 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 31318 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 31319 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 31320 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 31321 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 31322 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK |
|---|
| 31323 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 31324 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 31325 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 31326 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 31327 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 31328 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 31329 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 31330 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 31331 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 31332 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 31333 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 31334 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 31335 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 31336 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 31337 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 31338 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 31339 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 31340 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 31341 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 31342 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 31343 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 31344 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 31345 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 31346 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 31347 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 31348 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 31349 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 31350 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 31351 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 31352 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 31353 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 31354 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 31355 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 31356 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 31357 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 31358 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 |
|---|
| 31359 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 31360 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 31361 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 |
|---|
| 31362 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 31363 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 31364 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 |
|---|
| 31365 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 31366 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 31367 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 |
|---|
| 31368 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 31369 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 31370 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 |
|---|
| 31371 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 31372 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 31373 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 |
|---|
| 31374 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 31375 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 31376 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 |
|---|
| 31377 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 31378 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 31379 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 |
|---|
| 31380 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 31381 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 31382 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST |
|---|
| 31383 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31384 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 31385 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 31386 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 31387 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 31388 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 31389 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP |
|---|
| 31390 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 31391 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 31392 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 31393 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 31394 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 31395 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 31396 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL |
|---|
| 31397 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 31398 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 31399 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 31400 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 31401 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST |
|---|
| 31402 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31403 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 31404 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 31405 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 31406 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 31407 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 31408 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP |
|---|
| 31409 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 31410 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 31411 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 31412 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 31413 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 31414 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 31415 | //BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL |
|---|
| 31416 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 31417 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 31418 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 31419 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 31420 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 31421 | #define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 31422 | |
|---|
| 31423 | |
|---|
| 31424 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp |
|---|
| 31425 | //BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID |
|---|
| 31426 | #define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 31427 | #define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 31428 | //BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID |
|---|
| 31429 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 31430 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 31431 | //BIF_CFG_DEV0_EPF0_VF4_COMMAND |
|---|
| 31432 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 31433 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 31434 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 31435 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 31436 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 31437 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 31438 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 31439 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 31440 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 31441 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 31442 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 31443 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 31444 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 31445 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 31446 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 31447 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 31448 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 31449 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 31450 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 31451 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 31452 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 31453 | #define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 31454 | //BIF_CFG_DEV0_EPF0_VF4_STATUS |
|---|
| 31455 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 31456 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 31457 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 31458 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 31459 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 31460 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 31461 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 31462 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 31463 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 31464 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 31465 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 31466 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 31467 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 31468 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 31469 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 31470 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 31471 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 31472 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 31473 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 31474 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 31475 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 31476 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 31477 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 31478 | #define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 31479 | //BIF_CFG_DEV0_EPF0_VF4_REVISION_ID |
|---|
| 31480 | #define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 31481 | #define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 31482 | #define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 31483 | #define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 31484 | //BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE |
|---|
| 31485 | #define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 31486 | #define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 31487 | //BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS |
|---|
| 31488 | #define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 31489 | #define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 31490 | //BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS |
|---|
| 31491 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 31492 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 31493 | //BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE |
|---|
| 31494 | #define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 31495 | #define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 31496 | //BIF_CFG_DEV0_EPF0_VF4_LATENCY |
|---|
| 31497 | #define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 31498 | #define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 31499 | //BIF_CFG_DEV0_EPF0_VF4_HEADER |
|---|
| 31500 | #define 0x0 |
|---|
| 31501 | #define 0x7 |
|---|
| 31502 | #define 0x7FL |
|---|
| 31503 | #define 0x80L |
|---|
| 31504 | //BIF_CFG_DEV0_EPF0_VF4_BIST |
|---|
| 31505 | #define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 31506 | #define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 31507 | #define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 31508 | #define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 31509 | #define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK 0x40L |
|---|
| 31510 | #define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK 0x80L |
|---|
| 31511 | //BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 |
|---|
| 31512 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 31513 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 31514 | //BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 |
|---|
| 31515 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 31516 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 31517 | //BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 |
|---|
| 31518 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 31519 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 31520 | //BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 |
|---|
| 31521 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 31522 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 31523 | //BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 |
|---|
| 31524 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 31525 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 31526 | //BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 |
|---|
| 31527 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 31528 | #define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 31529 | //BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR |
|---|
| 31530 | #define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 31531 | #define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 31532 | //BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID |
|---|
| 31533 | #define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 31534 | #define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 31535 | #define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 31536 | #define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 31537 | //BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR |
|---|
| 31538 | #define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 31539 | #define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 31540 | //BIF_CFG_DEV0_EPF0_VF4_CAP_PTR |
|---|
| 31541 | #define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 31542 | #define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 31543 | //BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE |
|---|
| 31544 | #define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 31545 | #define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 31546 | //BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN |
|---|
| 31547 | #define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 31548 | #define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 31549 | //BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT |
|---|
| 31550 | #define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 31551 | #define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 31552 | //BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY |
|---|
| 31553 | #define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 31554 | #define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 31555 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST |
|---|
| 31556 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31557 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 31558 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 31559 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 31560 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP |
|---|
| 31561 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 31562 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 31563 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 31564 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 31565 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 31566 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 31567 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 31568 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 31569 | //BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP |
|---|
| 31570 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 31571 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 31572 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 31573 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 31574 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 31575 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 31576 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 31577 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 31578 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 31579 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 31580 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 31581 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 31582 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 31583 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 31584 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 31585 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 31586 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 31587 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 31588 | //BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL |
|---|
| 31589 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 31590 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 31591 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 31592 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 31593 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 31594 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 31595 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 31596 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 31597 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 31598 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 31599 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 31600 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 31601 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 31602 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 31603 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 31604 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 31605 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 31606 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 31607 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 31608 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 31609 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 31610 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 31611 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 31612 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 31613 | //BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS |
|---|
| 31614 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 31615 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 31616 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 31617 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 31618 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 31619 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 31620 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 31621 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 31622 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 31623 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 31624 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 31625 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 31626 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 31627 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 31628 | //BIF_CFG_DEV0_EPF0_VF4_LINK_CAP |
|---|
| 31629 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 31630 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 31631 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 31632 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 31633 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 31634 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 31635 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 31636 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 31637 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 31638 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 31639 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 31640 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 31641 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 31642 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 31643 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 31644 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 31645 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 31646 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 31647 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 31648 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 31649 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 31650 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 31651 | //BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL |
|---|
| 31652 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 31653 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 31654 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 31655 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 31656 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 31657 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 31658 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 31659 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 31660 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 31661 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 31662 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 31663 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 31664 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 31665 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 31666 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 31667 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 31668 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 31669 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 31670 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 31671 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 31672 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 31673 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 31674 | //BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS |
|---|
| 31675 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 31676 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 31677 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 31678 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 31679 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 31680 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 31681 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 31682 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 31683 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 31684 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 31685 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 31686 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 31687 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 31688 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 31689 | //BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 |
|---|
| 31690 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 31691 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 31692 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 31693 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 31694 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 31695 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 31696 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 31697 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 31698 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 31699 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 31700 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 31701 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 31702 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 31703 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 31704 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 31705 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 31706 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 31707 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 31708 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 31709 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 31710 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 31711 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 31712 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 31713 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 31714 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 31715 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 31716 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 31717 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 31718 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 31719 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 31720 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 31721 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 31722 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 31723 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 31724 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 31725 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 31726 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 31727 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 31728 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 31729 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 31730 | //BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 |
|---|
| 31731 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 31732 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 31733 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 31734 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 31735 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 31736 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 31737 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 31738 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 31739 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 31740 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 31741 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 31742 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 31743 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 31744 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 31745 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 31746 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 31747 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 31748 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 31749 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 31750 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 31751 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 31752 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 31753 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 31754 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 31755 | //BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 |
|---|
| 31756 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 31757 | #define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 31758 | //BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 |
|---|
| 31759 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 31760 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 31761 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 31762 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 31763 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 31764 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 31765 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 31766 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 31767 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 31768 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 31769 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 31770 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 31771 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 31772 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 31773 | //BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 |
|---|
| 31774 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 31775 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 31776 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 31777 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 31778 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 31779 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 31780 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 31781 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 31782 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 31783 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 31784 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 31785 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 31786 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 31787 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 31788 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 31789 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 31790 | //BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 |
|---|
| 31791 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 31792 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 31793 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 31794 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 31795 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 31796 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 31797 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 31798 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 31799 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 31800 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 31801 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 31802 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 31803 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 31804 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 31805 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 31806 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 31807 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 31808 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 31809 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 31810 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 31811 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 31812 | #define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 31813 | //BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST |
|---|
| 31814 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31815 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 31816 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 31817 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 31818 | //BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL |
|---|
| 31819 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 31820 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 31821 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 31822 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 31823 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 31824 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 31825 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 31826 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 31827 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 31828 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 31829 | //BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO |
|---|
| 31830 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 31831 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 31832 | //BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI |
|---|
| 31833 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 31834 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 31835 | //BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA |
|---|
| 31836 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 31837 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 31838 | //BIF_CFG_DEV0_EPF0_VF4_MSI_MASK |
|---|
| 31839 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 31840 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 31841 | //BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 |
|---|
| 31842 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 31843 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 31844 | //BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 |
|---|
| 31845 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 31846 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 31847 | //BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING |
|---|
| 31848 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 31849 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 31850 | //BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 |
|---|
| 31851 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 31852 | #define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 31853 | //BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST |
|---|
| 31854 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31855 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 31856 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 31857 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 31858 | //BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL |
|---|
| 31859 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 31860 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 31861 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 31862 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 31863 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 31864 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 31865 | //BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE |
|---|
| 31866 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 31867 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 31868 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 31869 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 31870 | //BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA |
|---|
| 31871 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 31872 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 31873 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 31874 | #define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 31875 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 31876 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31877 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 31878 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 31879 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 31880 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 31881 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 31882 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 31883 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 31884 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 31885 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 31886 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 31887 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 31888 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 31889 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 |
|---|
| 31890 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 31891 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 31892 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 |
|---|
| 31893 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 31894 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 31895 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 31896 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 31897 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 31898 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 31899 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 31900 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 31901 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 31902 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS |
|---|
| 31903 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 31904 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 31905 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 31906 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 31907 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 31908 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 31909 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 31910 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 31911 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 31912 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 31913 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 31914 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 31915 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 31916 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 31917 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 31918 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 31919 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 31920 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 31921 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 31922 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 31923 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 31924 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 31925 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 31926 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 31927 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 31928 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 31929 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 31930 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 31931 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 31932 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 31933 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 31934 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 31935 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK |
|---|
| 31936 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 31937 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 31938 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 31939 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 31940 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 31941 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 31942 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 31943 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 31944 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 31945 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 31946 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 31947 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 31948 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 31949 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 31950 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 31951 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 31952 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 31953 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 31954 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 31955 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 31956 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 31957 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 31958 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 31959 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 31960 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 31961 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 31962 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 31963 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 31964 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 31965 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 31966 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 31967 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 31968 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 31969 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 31970 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 31971 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 31972 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 31973 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 31974 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 31975 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 31976 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 31977 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 31978 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 31979 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 31980 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 31981 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 31982 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 31983 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 31984 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 31985 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 31986 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 31987 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 31988 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 31989 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 31990 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 31991 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 31992 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 31993 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 31994 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 31995 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 31996 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 31997 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 31998 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 31999 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 32000 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 32001 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS |
|---|
| 32002 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 32003 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 32004 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 32005 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 32006 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 32007 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 32008 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 32009 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 32010 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 32011 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 32012 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 32013 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 32014 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 32015 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 32016 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 32017 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 32018 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK |
|---|
| 32019 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 32020 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 32021 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 32022 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 32023 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 32024 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 32025 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 32026 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 32027 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 32028 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 32029 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 32030 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 32031 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 32032 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 32033 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 32034 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 32035 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 32036 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 32037 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 32038 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 32039 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 32040 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 32041 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 32042 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 32043 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 32044 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 32045 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 32046 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 32047 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 32048 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 32049 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 32050 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 32051 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 32052 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 32053 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 32054 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 |
|---|
| 32055 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 32056 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 32057 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 |
|---|
| 32058 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 32059 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 32060 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 |
|---|
| 32061 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 32062 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 32063 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 |
|---|
| 32064 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 32065 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 32066 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 |
|---|
| 32067 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 32068 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 32069 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 |
|---|
| 32070 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 32071 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 32072 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 |
|---|
| 32073 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 32074 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 32075 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 |
|---|
| 32076 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 32077 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 32078 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST |
|---|
| 32079 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 32080 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 32081 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 32082 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 32083 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 32084 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 32085 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP |
|---|
| 32086 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 32087 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 32088 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 32089 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 32090 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 32091 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 32092 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL |
|---|
| 32093 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 32094 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 32095 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 32096 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 32097 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST |
|---|
| 32098 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 32099 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 32100 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 32101 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 32102 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 32103 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 32104 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP |
|---|
| 32105 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 32106 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 32107 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 32108 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 32109 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 32110 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 32111 | //BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL |
|---|
| 32112 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 32113 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 32114 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 32115 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 32116 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 32117 | #define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 32118 | |
|---|
| 32119 | |
|---|
| 32120 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp |
|---|
| 32121 | //BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID |
|---|
| 32122 | #define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 32123 | #define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 32124 | //BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID |
|---|
| 32125 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 32126 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 32127 | //BIF_CFG_DEV0_EPF0_VF5_COMMAND |
|---|
| 32128 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 32129 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 32130 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 32131 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 32132 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 32133 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 32134 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 32135 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 32136 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 32137 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 32138 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 32139 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 32140 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 32141 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 32142 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 32143 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 32144 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 32145 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 32146 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 32147 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 32148 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 32149 | #define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 32150 | //BIF_CFG_DEV0_EPF0_VF5_STATUS |
|---|
| 32151 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 32152 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 32153 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 32154 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 32155 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 32156 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 32157 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 32158 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 32159 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 32160 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 32161 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 32162 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 32163 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 32164 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 32165 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 32166 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 32167 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 32168 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 32169 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 32170 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 32171 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 32172 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 32173 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 32174 | #define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 32175 | //BIF_CFG_DEV0_EPF0_VF5_REVISION_ID |
|---|
| 32176 | #define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 32177 | #define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 32178 | #define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 32179 | #define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 32180 | //BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE |
|---|
| 32181 | #define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 32182 | #define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 32183 | //BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS |
|---|
| 32184 | #define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 32185 | #define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 32186 | //BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS |
|---|
| 32187 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 32188 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 32189 | //BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE |
|---|
| 32190 | #define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 32191 | #define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 32192 | //BIF_CFG_DEV0_EPF0_VF5_LATENCY |
|---|
| 32193 | #define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 32194 | #define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 32195 | //BIF_CFG_DEV0_EPF0_VF5_HEADER |
|---|
| 32196 | #define 0x0 |
|---|
| 32197 | #define 0x7 |
|---|
| 32198 | #define 0x7FL |
|---|
| 32199 | #define 0x80L |
|---|
| 32200 | //BIF_CFG_DEV0_EPF0_VF5_BIST |
|---|
| 32201 | #define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 32202 | #define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 32203 | #define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 32204 | #define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 32205 | #define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK 0x40L |
|---|
| 32206 | #define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK 0x80L |
|---|
| 32207 | //BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 |
|---|
| 32208 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 32209 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32210 | //BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 |
|---|
| 32211 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 32212 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32213 | //BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 |
|---|
| 32214 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 32215 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32216 | //BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 |
|---|
| 32217 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 32218 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32219 | //BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 |
|---|
| 32220 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 32221 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32222 | //BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 |
|---|
| 32223 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 32224 | #define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32225 | //BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR |
|---|
| 32226 | #define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 32227 | #define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 32228 | //BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID |
|---|
| 32229 | #define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 32230 | #define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 32231 | #define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 32232 | #define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 32233 | //BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR |
|---|
| 32234 | #define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 32235 | #define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32236 | //BIF_CFG_DEV0_EPF0_VF5_CAP_PTR |
|---|
| 32237 | #define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 32238 | #define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 32239 | //BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE |
|---|
| 32240 | #define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 32241 | #define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 32242 | //BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN |
|---|
| 32243 | #define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 32244 | #define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 32245 | //BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT |
|---|
| 32246 | #define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 32247 | #define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 32248 | //BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY |
|---|
| 32249 | #define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 32250 | #define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 32251 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST |
|---|
| 32252 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 32253 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 32254 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 32255 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 32256 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP |
|---|
| 32257 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 32258 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 32259 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 32260 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 32261 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 32262 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 32263 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 32264 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 32265 | //BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP |
|---|
| 32266 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 32267 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 32268 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 32269 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 32270 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 32271 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 32272 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 32273 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 32274 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 32275 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 32276 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 32277 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 32278 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 32279 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 32280 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 32281 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 32282 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 32283 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 32284 | //BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL |
|---|
| 32285 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 32286 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 32287 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 32288 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 32289 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 32290 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 32291 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 32292 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 32293 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 32294 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 32295 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 32296 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 32297 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 32298 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 32299 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 32300 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 32301 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 32302 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 32303 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 32304 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 32305 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 32306 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 32307 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 32308 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 32309 | //BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS |
|---|
| 32310 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 32311 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 32312 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 32313 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 32314 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 32315 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 32316 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 32317 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 32318 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 32319 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 32320 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 32321 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 32322 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 32323 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 32324 | //BIF_CFG_DEV0_EPF0_VF5_LINK_CAP |
|---|
| 32325 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 32326 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 32327 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 32328 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 32329 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 32330 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 32331 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 32332 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 32333 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 32334 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 32335 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 32336 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 32337 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 32338 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 32339 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 32340 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 32341 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 32342 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 32343 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 32344 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 32345 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 32346 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 32347 | //BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL |
|---|
| 32348 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 32349 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 32350 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 32351 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 32352 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 32353 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 32354 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 32355 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 32356 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 32357 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 32358 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 32359 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 32360 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 32361 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 32362 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 32363 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 32364 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 32365 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 32366 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 32367 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 32368 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 32369 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 32370 | //BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS |
|---|
| 32371 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 32372 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 32373 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 32374 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 32375 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 32376 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 32377 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 32378 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 32379 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 32380 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 32381 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 32382 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 32383 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 32384 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 32385 | //BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 |
|---|
| 32386 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 32387 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 32388 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 32389 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 32390 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 32391 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 32392 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 32393 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 32394 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 32395 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 32396 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 32397 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 32398 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 32399 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 32400 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 32401 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 32402 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 32403 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 32404 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 32405 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 32406 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 32407 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 32408 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 32409 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 32410 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 32411 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 32412 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 32413 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 32414 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 32415 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 32416 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 32417 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 32418 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 32419 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 32420 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 32421 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 32422 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 32423 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 32424 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 32425 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 32426 | //BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 |
|---|
| 32427 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 32428 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 32429 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 32430 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 32431 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 32432 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 32433 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 32434 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 32435 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 32436 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 32437 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 32438 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 32439 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 32440 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 32441 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 32442 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 32443 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 32444 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 32445 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 32446 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 32447 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 32448 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 32449 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 32450 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 32451 | //BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 |
|---|
| 32452 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 32453 | #define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 32454 | //BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 |
|---|
| 32455 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 32456 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 32457 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 32458 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 32459 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 32460 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 32461 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 32462 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 32463 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 32464 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 32465 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 32466 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 32467 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 32468 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 32469 | //BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 |
|---|
| 32470 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 32471 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 32472 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 32473 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 32474 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 32475 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 32476 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 32477 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 32478 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 32479 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 32480 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 32481 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 32482 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 32483 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 32484 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 32485 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 32486 | //BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 |
|---|
| 32487 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 32488 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 32489 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 32490 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 32491 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 32492 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 32493 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 32494 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 32495 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 32496 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 32497 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 32498 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 32499 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 32500 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 32501 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 32502 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 32503 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 32504 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 32505 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 32506 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 32507 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 32508 | #define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 32509 | //BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST |
|---|
| 32510 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 32511 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 32512 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 32513 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 32514 | //BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL |
|---|
| 32515 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 32516 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 32517 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 32518 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 32519 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 32520 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 32521 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 32522 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 32523 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 32524 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 32525 | //BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO |
|---|
| 32526 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 32527 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 32528 | //BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI |
|---|
| 32529 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 32530 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 32531 | //BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA |
|---|
| 32532 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 32533 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 32534 | //BIF_CFG_DEV0_EPF0_VF5_MSI_MASK |
|---|
| 32535 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 32536 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 32537 | //BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 |
|---|
| 32538 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 32539 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 32540 | //BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 |
|---|
| 32541 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 32542 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 32543 | //BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING |
|---|
| 32544 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 32545 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 32546 | //BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 |
|---|
| 32547 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 32548 | #define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 32549 | //BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST |
|---|
| 32550 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 32551 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 32552 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 32553 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 32554 | //BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL |
|---|
| 32555 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 32556 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 32557 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 32558 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 32559 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 32560 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 32561 | //BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE |
|---|
| 32562 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 32563 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 32564 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 32565 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 32566 | //BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA |
|---|
| 32567 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 32568 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 32569 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 32570 | #define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 32571 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 32572 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 32573 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 32574 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 32575 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 32576 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 32577 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 32578 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 32579 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 32580 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 32581 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 32582 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 32583 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 32584 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 32585 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 |
|---|
| 32586 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 32587 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 32588 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 |
|---|
| 32589 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 32590 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 32591 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 32592 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 32593 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 32594 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 32595 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 32596 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 32597 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 32598 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS |
|---|
| 32599 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 32600 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 32601 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 32602 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 32603 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 32604 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 32605 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 32606 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 32607 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 32608 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 32609 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 32610 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 32611 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 32612 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 32613 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 32614 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 32615 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 32616 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 32617 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 32618 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 32619 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 32620 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 32621 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 32622 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 32623 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 32624 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 32625 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 32626 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 32627 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 32628 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 32629 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 32630 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 32631 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK |
|---|
| 32632 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 32633 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 32634 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 32635 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 32636 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 32637 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 32638 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 32639 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 32640 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 32641 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 32642 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 32643 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 32644 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 32645 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 32646 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 32647 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 32648 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 32649 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 32650 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 32651 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 32652 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 32653 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 32654 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 32655 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 32656 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 32657 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 32658 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 32659 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 32660 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 32661 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 32662 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 32663 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 32664 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 32665 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 32666 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 32667 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 32668 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 32669 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 32670 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 32671 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 32672 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 32673 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 32674 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 32675 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 32676 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 32677 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 32678 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 32679 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 32680 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 32681 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 32682 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 32683 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 32684 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 32685 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 32686 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 32687 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 32688 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 32689 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 32690 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 32691 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 32692 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 32693 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 32694 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 32695 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 32696 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 32697 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS |
|---|
| 32698 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 32699 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 32700 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 32701 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 32702 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 32703 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 32704 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 32705 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 32706 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 32707 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 32708 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 32709 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 32710 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 32711 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 32712 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 32713 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 32714 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK |
|---|
| 32715 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 32716 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 32717 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 32718 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 32719 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 32720 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 32721 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 32722 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 32723 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 32724 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 32725 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 32726 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 32727 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 32728 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 32729 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 32730 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 32731 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 32732 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 32733 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 32734 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 32735 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 32736 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 32737 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 32738 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 32739 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 32740 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 32741 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 32742 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 32743 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 32744 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 32745 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 32746 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 32747 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 32748 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 32749 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 32750 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 |
|---|
| 32751 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 32752 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 32753 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 |
|---|
| 32754 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 32755 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 32756 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 |
|---|
| 32757 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 32758 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 32759 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 |
|---|
| 32760 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 32761 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 32762 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 |
|---|
| 32763 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 32764 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 32765 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 |
|---|
| 32766 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 32767 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 32768 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 |
|---|
| 32769 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 32770 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 32771 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 |
|---|
| 32772 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 32773 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 32774 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST |
|---|
| 32775 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 32776 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 32777 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 32778 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 32779 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 32780 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 32781 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP |
|---|
| 32782 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 32783 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 32784 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 32785 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 32786 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 32787 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 32788 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL |
|---|
| 32789 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 32790 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 32791 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 32792 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 32793 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST |
|---|
| 32794 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 32795 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 32796 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 32797 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 32798 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 32799 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 32800 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP |
|---|
| 32801 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 32802 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 32803 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 32804 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 32805 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 32806 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 32807 | //BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL |
|---|
| 32808 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 32809 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 32810 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 32811 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 32812 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 32813 | #define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 32814 | |
|---|
| 32815 | |
|---|
| 32816 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp |
|---|
| 32817 | //BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID |
|---|
| 32818 | #define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 32819 | #define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 32820 | //BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID |
|---|
| 32821 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 32822 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 32823 | //BIF_CFG_DEV0_EPF0_VF6_COMMAND |
|---|
| 32824 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 32825 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 32826 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 32827 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 32828 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 32829 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 32830 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 32831 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 32832 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 32833 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 32834 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 32835 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 32836 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 32837 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 32838 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 32839 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 32840 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 32841 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 32842 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 32843 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 32844 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 32845 | #define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 32846 | //BIF_CFG_DEV0_EPF0_VF6_STATUS |
|---|
| 32847 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 32848 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 32849 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 32850 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 32851 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 32852 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 32853 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 32854 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 32855 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 32856 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 32857 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 32858 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 32859 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 32860 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 32861 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 32862 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 32863 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 32864 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 32865 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 32866 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 32867 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 32868 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 32869 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 32870 | #define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 32871 | //BIF_CFG_DEV0_EPF0_VF6_REVISION_ID |
|---|
| 32872 | #define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 32873 | #define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 32874 | #define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 32875 | #define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 32876 | //BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE |
|---|
| 32877 | #define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 32878 | #define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 32879 | //BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS |
|---|
| 32880 | #define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 32881 | #define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 32882 | //BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS |
|---|
| 32883 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 32884 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 32885 | //BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE |
|---|
| 32886 | #define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 32887 | #define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 32888 | //BIF_CFG_DEV0_EPF0_VF6_LATENCY |
|---|
| 32889 | #define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 32890 | #define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 32891 | //BIF_CFG_DEV0_EPF0_VF6_HEADER |
|---|
| 32892 | #define 0x0 |
|---|
| 32893 | #define 0x7 |
|---|
| 32894 | #define 0x7FL |
|---|
| 32895 | #define 0x80L |
|---|
| 32896 | //BIF_CFG_DEV0_EPF0_VF6_BIST |
|---|
| 32897 | #define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 32898 | #define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 32899 | #define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 32900 | #define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 32901 | #define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK 0x40L |
|---|
| 32902 | #define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK 0x80L |
|---|
| 32903 | //BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 |
|---|
| 32904 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 32905 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32906 | //BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 |
|---|
| 32907 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 32908 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32909 | //BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 |
|---|
| 32910 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 32911 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32912 | //BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 |
|---|
| 32913 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 32914 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32915 | //BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 |
|---|
| 32916 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 32917 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32918 | //BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 |
|---|
| 32919 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 32920 | #define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32921 | //BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR |
|---|
| 32922 | #define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 32923 | #define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 32924 | //BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID |
|---|
| 32925 | #define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 32926 | #define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 32927 | #define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 32928 | #define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 32929 | //BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR |
|---|
| 32930 | #define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 32931 | #define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 32932 | //BIF_CFG_DEV0_EPF0_VF6_CAP_PTR |
|---|
| 32933 | #define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 32934 | #define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 32935 | //BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE |
|---|
| 32936 | #define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 32937 | #define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 32938 | //BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN |
|---|
| 32939 | #define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 32940 | #define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 32941 | //BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT |
|---|
| 32942 | #define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 32943 | #define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 32944 | //BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY |
|---|
| 32945 | #define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 32946 | #define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 32947 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST |
|---|
| 32948 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 32949 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 32950 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 32951 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 32952 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP |
|---|
| 32953 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 32954 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 32955 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 32956 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 32957 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 32958 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 32959 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 32960 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 32961 | //BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP |
|---|
| 32962 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 32963 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 32964 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 32965 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 32966 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 32967 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 32968 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 32969 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 32970 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 32971 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 32972 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 32973 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 32974 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 32975 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 32976 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 32977 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 32978 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 32979 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 32980 | //BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL |
|---|
| 32981 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 32982 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 32983 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 32984 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 32985 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 32986 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 32987 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 32988 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 32989 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 32990 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 32991 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 32992 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 32993 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 32994 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 32995 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 32996 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 32997 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 32998 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 32999 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 33000 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 33001 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 33002 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 33003 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 33004 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 33005 | //BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS |
|---|
| 33006 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
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| 33007 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
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| 33008 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
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| 33009 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 33010 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 33011 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 33012 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
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| 33013 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 33014 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 33015 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 33016 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
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| 33017 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
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| 33018 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 33019 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
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| 33020 | //BIF_CFG_DEV0_EPF0_VF6_LINK_CAP |
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| 33021 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 33022 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 33023 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 33024 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
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| 33025 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 33026 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
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| 33027 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
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| 33028 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 33029 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 33030 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 33031 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 33032 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
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| 33033 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 33034 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
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| 33035 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 33036 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 33037 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 33038 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 33039 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
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| 33040 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 33041 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 33042 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 33043 | //BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL |
|---|
| 33044 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 33045 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 33046 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 33047 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 33048 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 33049 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 33050 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 33051 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 33052 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 33053 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 33054 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 33055 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 33056 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 33057 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 33058 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
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| 33059 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 33060 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 33061 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
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| 33062 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
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| 33063 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 33064 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 33065 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
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| 33066 | //BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS |
|---|
| 33067 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
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| 33068 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
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| 33069 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
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| 33070 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
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| 33071 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
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| 33072 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
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| 33073 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 33074 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
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| 33075 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
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| 33076 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
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| 33077 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 33078 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 33079 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 33080 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 33081 | //BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 |
|---|
| 33082 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 33083 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
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| 33084 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
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| 33085 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
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| 33086 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 33087 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 33088 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
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| 33089 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 33090 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
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| 33091 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 33092 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
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| 33093 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 33094 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 33095 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 33096 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 33097 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
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| 33098 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
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| 33099 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 33100 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
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| 33101 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
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| 33102 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 33103 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 33104 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 33105 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 33106 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 33107 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 33108 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 33109 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 33110 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 33111 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 33112 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 33113 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 33114 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 33115 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
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| 33116 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 33117 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 33118 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 33119 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 33120 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 33121 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
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| 33122 | //BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 |
|---|
| 33123 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 33124 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 33125 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 33126 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 33127 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 33128 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 33129 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 33130 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 33131 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 33132 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 33133 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 33134 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 33135 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 33136 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 33137 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 33138 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 33139 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 33140 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 33141 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 33142 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 33143 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 33144 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 33145 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 33146 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 33147 | //BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 |
|---|
| 33148 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 33149 | #define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 33150 | //BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 |
|---|
| 33151 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 33152 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 33153 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 33154 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 33155 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 33156 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
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| 33157 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 33158 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
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| 33159 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 33160 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 33161 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 33162 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 33163 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 33164 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
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| 33165 | //BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 |
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| 33166 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 33167 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
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| 33168 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
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| 33169 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
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| 33170 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
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| 33171 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 33172 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
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| 33173 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
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| 33174 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 33175 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
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| 33176 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 33177 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 33178 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 33179 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 33180 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 33181 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 33182 | //BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 |
|---|
| 33183 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 33184 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 33185 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 33186 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 33187 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 33188 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 33189 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 33190 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 33191 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 33192 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 33193 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 33194 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 33195 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 33196 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 33197 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 33198 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 33199 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 33200 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 33201 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 33202 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 33203 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 33204 | #define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 33205 | //BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST |
|---|
| 33206 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33207 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 33208 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 33209 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 33210 | //BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL |
|---|
| 33211 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 33212 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 33213 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 33214 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 33215 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 33216 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 33217 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 33218 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 33219 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 33220 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 33221 | //BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO |
|---|
| 33222 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 33223 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 33224 | //BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI |
|---|
| 33225 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 33226 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 33227 | //BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA |
|---|
| 33228 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 33229 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 33230 | //BIF_CFG_DEV0_EPF0_VF6_MSI_MASK |
|---|
| 33231 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 33232 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 33233 | //BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 |
|---|
| 33234 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 33235 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 33236 | //BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 |
|---|
| 33237 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 33238 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 33239 | //BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING |
|---|
| 33240 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 33241 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 33242 | //BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 |
|---|
| 33243 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 33244 | #define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 33245 | //BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST |
|---|
| 33246 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33247 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 33248 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 33249 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 33250 | //BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL |
|---|
| 33251 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 33252 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 33253 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 33254 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 33255 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 33256 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 33257 | //BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE |
|---|
| 33258 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 33259 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 33260 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 33261 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 33262 | //BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA |
|---|
| 33263 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 33264 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 33265 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 33266 | #define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 33267 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 33268 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33269 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 33270 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 33271 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 33272 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 33273 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 33274 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 33275 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 33276 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 33277 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 33278 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 33279 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 33280 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 33281 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 |
|---|
| 33282 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 33283 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 33284 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 |
|---|
| 33285 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 33286 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 33287 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 33288 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33289 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 33290 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 33291 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 33292 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 33293 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 33294 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS |
|---|
| 33295 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 33296 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 33297 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 33298 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 33299 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 33300 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 33301 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 33302 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 33303 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 33304 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 33305 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 33306 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 33307 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 33308 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 33309 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 33310 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 33311 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 33312 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 33313 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 33314 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 33315 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 33316 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 33317 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 33318 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 33319 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 33320 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 33321 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 33322 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 33323 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 33324 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 33325 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 33326 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 33327 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK |
|---|
| 33328 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 33329 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 33330 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 33331 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 33332 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 33333 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 33334 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 33335 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 33336 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 33337 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 33338 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 33339 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 33340 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 33341 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 33342 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 33343 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 33344 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 33345 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 33346 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 33347 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 33348 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 33349 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 33350 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 33351 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 33352 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 33353 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 33354 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 33355 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 33356 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 33357 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 33358 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 33359 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 33360 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 33361 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 33362 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 33363 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 33364 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 33365 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 33366 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 33367 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 33368 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 33369 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 33370 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 33371 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 33372 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 33373 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 33374 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 33375 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 33376 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 33377 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 33378 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 33379 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 33380 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 33381 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 33382 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 33383 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 33384 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 33385 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 33386 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 33387 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 33388 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 33389 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 33390 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 33391 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 33392 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 33393 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS |
|---|
| 33394 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 33395 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 33396 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 33397 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 33398 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 33399 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 33400 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 33401 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 33402 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 33403 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 33404 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 33405 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 33406 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 33407 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 33408 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 33409 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 33410 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK |
|---|
| 33411 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 33412 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 33413 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 33414 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 33415 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 33416 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 33417 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 33418 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 33419 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 33420 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 33421 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 33422 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 33423 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 33424 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 33425 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 33426 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 33427 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 33428 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 33429 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 33430 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 33431 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 33432 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 33433 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 33434 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 33435 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 33436 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 33437 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 33438 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 33439 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 33440 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 33441 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 33442 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 33443 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 33444 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 33445 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 33446 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 |
|---|
| 33447 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 33448 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 33449 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 |
|---|
| 33450 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 33451 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 33452 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 |
|---|
| 33453 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 33454 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 33455 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 |
|---|
| 33456 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 33457 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 33458 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 |
|---|
| 33459 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 33460 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 33461 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 |
|---|
| 33462 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 33463 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 33464 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 |
|---|
| 33465 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 33466 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 33467 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 |
|---|
| 33468 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 33469 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 33470 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST |
|---|
| 33471 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33472 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 33473 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 33474 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 33475 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 33476 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 33477 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP |
|---|
| 33478 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 33479 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 33480 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 33481 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 33482 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 33483 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 33484 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL |
|---|
| 33485 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 33486 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 33487 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 33488 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 33489 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST |
|---|
| 33490 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33491 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 33492 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 33493 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 33494 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 33495 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 33496 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP |
|---|
| 33497 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 33498 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 33499 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 33500 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 33501 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 33502 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 33503 | //BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL |
|---|
| 33504 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 33505 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 33506 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 33507 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 33508 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 33509 | #define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 33510 | |
|---|
| 33511 | |
|---|
| 33512 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp |
|---|
| 33513 | //BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID |
|---|
| 33514 | #define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 33515 | #define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 33516 | //BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID |
|---|
| 33517 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 33518 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 33519 | //BIF_CFG_DEV0_EPF0_VF7_COMMAND |
|---|
| 33520 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 33521 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 33522 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 33523 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 33524 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 33525 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 33526 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 33527 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 33528 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 33529 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 33530 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 33531 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 33532 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 33533 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 33534 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 33535 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 33536 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 33537 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 33538 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 33539 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 33540 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 33541 | #define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 33542 | //BIF_CFG_DEV0_EPF0_VF7_STATUS |
|---|
| 33543 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 33544 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 33545 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 33546 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 33547 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 33548 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 33549 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 33550 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 33551 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 33552 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 33553 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 33554 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 33555 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 33556 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 33557 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 33558 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 33559 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 33560 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 33561 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 33562 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 33563 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 33564 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 33565 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 33566 | #define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 33567 | //BIF_CFG_DEV0_EPF0_VF7_REVISION_ID |
|---|
| 33568 | #define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 33569 | #define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 33570 | #define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 33571 | #define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 33572 | //BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE |
|---|
| 33573 | #define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 33574 | #define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 33575 | //BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS |
|---|
| 33576 | #define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 33577 | #define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 33578 | //BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS |
|---|
| 33579 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 33580 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 33581 | //BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE |
|---|
| 33582 | #define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 33583 | #define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 33584 | //BIF_CFG_DEV0_EPF0_VF7_LATENCY |
|---|
| 33585 | #define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 33586 | #define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 33587 | //BIF_CFG_DEV0_EPF0_VF7_HEADER |
|---|
| 33588 | #define 0x0 |
|---|
| 33589 | #define 0x7 |
|---|
| 33590 | #define 0x7FL |
|---|
| 33591 | #define 0x80L |
|---|
| 33592 | //BIF_CFG_DEV0_EPF0_VF7_BIST |
|---|
| 33593 | #define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 33594 | #define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 33595 | #define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 33596 | #define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 33597 | #define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK 0x40L |
|---|
| 33598 | #define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK 0x80L |
|---|
| 33599 | //BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 |
|---|
| 33600 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 33601 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 33602 | //BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 |
|---|
| 33603 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 33604 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 33605 | //BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 |
|---|
| 33606 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 33607 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 33608 | //BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 |
|---|
| 33609 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 33610 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 33611 | //BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 |
|---|
| 33612 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 33613 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 33614 | //BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 |
|---|
| 33615 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 33616 | #define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 33617 | //BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR |
|---|
| 33618 | #define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 33619 | #define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 33620 | //BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID |
|---|
| 33621 | #define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 33622 | #define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 33623 | #define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 33624 | #define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 33625 | //BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR |
|---|
| 33626 | #define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 33627 | #define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 33628 | //BIF_CFG_DEV0_EPF0_VF7_CAP_PTR |
|---|
| 33629 | #define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 33630 | #define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 33631 | //BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE |
|---|
| 33632 | #define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 33633 | #define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 33634 | //BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN |
|---|
| 33635 | #define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 33636 | #define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 33637 | //BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT |
|---|
| 33638 | #define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 33639 | #define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 33640 | //BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY |
|---|
| 33641 | #define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 33642 | #define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 33643 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST |
|---|
| 33644 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33645 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 33646 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 33647 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 33648 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP |
|---|
| 33649 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 33650 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 33651 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 33652 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 33653 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 33654 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 33655 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 33656 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 33657 | //BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP |
|---|
| 33658 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 33659 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 33660 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 33661 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 33662 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 33663 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 33664 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 33665 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 33666 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 33667 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 33668 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 33669 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 33670 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 33671 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 33672 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 33673 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 33674 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 33675 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 33676 | //BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL |
|---|
| 33677 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 33678 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 33679 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 33680 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 33681 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 33682 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 33683 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 33684 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 33685 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 33686 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 33687 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 33688 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 33689 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 33690 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 33691 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 33692 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 33693 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 33694 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 33695 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 33696 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 33697 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 33698 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 33699 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 33700 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 33701 | //BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS |
|---|
| 33702 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 33703 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 33704 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 33705 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 33706 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 33707 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 33708 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 33709 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 33710 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 33711 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 33712 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 33713 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 33714 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 33715 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 33716 | //BIF_CFG_DEV0_EPF0_VF7_LINK_CAP |
|---|
| 33717 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 33718 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 33719 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 33720 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 33721 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 33722 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 33723 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 33724 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 33725 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 33726 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 33727 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 33728 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 33729 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 33730 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 33731 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 33732 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 33733 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 33734 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 33735 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 33736 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 33737 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 33738 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 33739 | //BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL |
|---|
| 33740 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 33741 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 33742 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 33743 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 33744 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 33745 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 33746 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 33747 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 33748 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 33749 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 33750 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 33751 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 33752 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 33753 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 33754 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 33755 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 33756 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 33757 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 33758 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 33759 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 33760 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 33761 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 33762 | //BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS |
|---|
| 33763 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 33764 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 33765 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 33766 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 33767 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 33768 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 33769 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 33770 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 33771 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 33772 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 33773 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 33774 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 33775 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 33776 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 33777 | //BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 |
|---|
| 33778 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 33779 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 33780 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 33781 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 33782 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 33783 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 33784 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 33785 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 33786 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 33787 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 33788 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 33789 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 33790 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 33791 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 33792 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 33793 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 33794 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 33795 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 33796 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 33797 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 33798 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 33799 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 33800 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 33801 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 33802 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 33803 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 33804 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 33805 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 33806 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 33807 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 33808 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 33809 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 33810 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 33811 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 33812 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 33813 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 33814 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 33815 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 33816 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 33817 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 33818 | //BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 |
|---|
| 33819 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 33820 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 33821 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 33822 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 33823 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 33824 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 33825 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 33826 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 33827 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 33828 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 33829 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 33830 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 33831 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 33832 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 33833 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 33834 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 33835 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 33836 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 33837 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 33838 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 33839 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 33840 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 33841 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 33842 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 33843 | //BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 |
|---|
| 33844 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 33845 | #define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 33846 | //BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 |
|---|
| 33847 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 33848 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 33849 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 33850 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 33851 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 33852 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 33853 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 33854 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 33855 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 33856 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 33857 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 33858 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 33859 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 33860 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 33861 | //BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 |
|---|
| 33862 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 33863 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 33864 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 33865 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 33866 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 33867 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 33868 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 33869 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 33870 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 33871 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 33872 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 33873 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 33874 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 33875 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 33876 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 33877 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 33878 | //BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 |
|---|
| 33879 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 33880 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 33881 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 33882 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 33883 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 33884 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 33885 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 33886 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 33887 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 33888 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 33889 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 33890 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 33891 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 33892 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 33893 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 33894 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 33895 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 33896 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 33897 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 33898 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 33899 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 33900 | #define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 33901 | //BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST |
|---|
| 33902 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33903 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 33904 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 33905 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 33906 | //BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL |
|---|
| 33907 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 33908 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 33909 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 33910 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 33911 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 33912 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 33913 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 33914 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 33915 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 33916 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 33917 | //BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO |
|---|
| 33918 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 33919 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 33920 | //BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI |
|---|
| 33921 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 33922 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 33923 | //BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA |
|---|
| 33924 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 33925 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 33926 | //BIF_CFG_DEV0_EPF0_VF7_MSI_MASK |
|---|
| 33927 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 33928 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 33929 | //BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 |
|---|
| 33930 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 33931 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 33932 | //BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 |
|---|
| 33933 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 33934 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 33935 | //BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING |
|---|
| 33936 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 33937 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 33938 | //BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 |
|---|
| 33939 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 33940 | #define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 33941 | //BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST |
|---|
| 33942 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33943 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 33944 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 33945 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 33946 | //BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL |
|---|
| 33947 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 33948 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 33949 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 33950 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 33951 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 33952 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 33953 | //BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE |
|---|
| 33954 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 33955 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 33956 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 33957 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 33958 | //BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA |
|---|
| 33959 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 33960 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 33961 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 33962 | #define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 33963 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 33964 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33965 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 33966 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 33967 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 33968 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 33969 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 33970 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 33971 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 33972 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 33973 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 33974 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 33975 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 33976 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 33977 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 |
|---|
| 33978 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 33979 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 33980 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 |
|---|
| 33981 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 33982 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 33983 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 33984 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 33985 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 33986 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 33987 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 33988 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 33989 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 33990 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS |
|---|
| 33991 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 33992 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 33993 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 33994 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 33995 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 33996 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 33997 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 33998 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 33999 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 34000 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 34001 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 34002 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 34003 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 34004 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 34005 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 34006 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 34007 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 34008 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 34009 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 34010 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 34011 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 34012 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 34013 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 34014 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 34015 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 34016 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 34017 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 34018 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 34019 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 34020 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 34021 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 34022 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 34023 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK |
|---|
| 34024 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 34025 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 34026 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 34027 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 34028 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 34029 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 34030 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 34031 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 34032 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 34033 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 34034 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 34035 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 34036 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 34037 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 34038 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 34039 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 34040 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 34041 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 34042 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 34043 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 34044 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 34045 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 34046 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 34047 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 34048 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 34049 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 34050 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 34051 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 34052 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 34053 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 34054 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 34055 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 34056 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 34057 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 34058 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 34059 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 34060 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 34061 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 34062 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 34063 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 34064 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 34065 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 34066 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 34067 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 34068 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 34069 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 34070 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 34071 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 34072 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 34073 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 34074 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 34075 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 34076 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 34077 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 34078 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 34079 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 34080 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 34081 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 34082 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 34083 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 34084 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 34085 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 34086 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 34087 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 34088 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 34089 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS |
|---|
| 34090 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 34091 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 34092 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 34093 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 34094 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 34095 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 34096 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 34097 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 34098 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 34099 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 34100 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 34101 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 34102 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 34103 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 34104 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 34105 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 34106 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK |
|---|
| 34107 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 34108 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 34109 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 34110 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 34111 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 34112 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 34113 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 34114 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 34115 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 34116 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 34117 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 34118 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 34119 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 34120 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 34121 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 34122 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 34123 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 34124 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 34125 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 34126 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 34127 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 34128 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 34129 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 34130 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 34131 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 34132 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 34133 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 34134 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 34135 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 34136 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 34137 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 34138 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 34139 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 34140 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 34141 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 34142 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 |
|---|
| 34143 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 34144 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 34145 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 |
|---|
| 34146 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 34147 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 34148 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 |
|---|
| 34149 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 34150 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 34151 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 |
|---|
| 34152 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 34153 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 34154 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 |
|---|
| 34155 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 34156 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 34157 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 |
|---|
| 34158 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 34159 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 34160 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 |
|---|
| 34161 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 34162 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 34163 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 |
|---|
| 34164 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 34165 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 34166 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST |
|---|
| 34167 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 34168 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 34169 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 34170 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 34171 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 34172 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 34173 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP |
|---|
| 34174 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 34175 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 34176 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 34177 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 34178 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 34179 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 34180 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL |
|---|
| 34181 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 34182 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 34183 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 34184 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 34185 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST |
|---|
| 34186 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 34187 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 34188 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 34189 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 34190 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 34191 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 34192 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP |
|---|
| 34193 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 34194 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 34195 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 34196 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 34197 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 34198 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 34199 | //BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL |
|---|
| 34200 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 34201 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 34202 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 34203 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 34204 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 34205 | #define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 34206 | |
|---|
| 34207 | |
|---|
| 34208 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp |
|---|
| 34209 | //BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID |
|---|
| 34210 | #define BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 34211 | #define BIF_CFG_DEV0_EPF0_VF8_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 34212 | //BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID |
|---|
| 34213 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 34214 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 34215 | //BIF_CFG_DEV0_EPF0_VF8_COMMAND |
|---|
| 34216 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 34217 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 34218 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 34219 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 34220 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 34221 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 34222 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 34223 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 34224 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 34225 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 34226 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 34227 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 34228 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 34229 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 34230 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 34231 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 34232 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 34233 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 34234 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 34235 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 34236 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 34237 | #define BIF_CFG_DEV0_EPF0_VF8_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 34238 | //BIF_CFG_DEV0_EPF0_VF8_STATUS |
|---|
| 34239 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 34240 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 34241 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 34242 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 34243 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 34244 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 34245 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 34246 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 34247 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 34248 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 34249 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 34250 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 34251 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 34252 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 34253 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 34254 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 34255 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 34256 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 34257 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 34258 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 34259 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 34260 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 34261 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 34262 | #define BIF_CFG_DEV0_EPF0_VF8_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 34263 | //BIF_CFG_DEV0_EPF0_VF8_REVISION_ID |
|---|
| 34264 | #define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 34265 | #define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 34266 | #define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 34267 | #define BIF_CFG_DEV0_EPF0_VF8_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 34268 | //BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE |
|---|
| 34269 | #define BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 34270 | #define BIF_CFG_DEV0_EPF0_VF8_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 34271 | //BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS |
|---|
| 34272 | #define BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 34273 | #define BIF_CFG_DEV0_EPF0_VF8_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 34274 | //BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS |
|---|
| 34275 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 34276 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 34277 | //BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE |
|---|
| 34278 | #define BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 34279 | #define BIF_CFG_DEV0_EPF0_VF8_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 34280 | //BIF_CFG_DEV0_EPF0_VF8_LATENCY |
|---|
| 34281 | #define BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 34282 | #define BIF_CFG_DEV0_EPF0_VF8_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 34283 | //BIF_CFG_DEV0_EPF0_VF8_HEADER |
|---|
| 34284 | #define 0x0 |
|---|
| 34285 | #define 0x7 |
|---|
| 34286 | #define 0x7FL |
|---|
| 34287 | #define 0x80L |
|---|
| 34288 | //BIF_CFG_DEV0_EPF0_VF8_BIST |
|---|
| 34289 | #define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 34290 | #define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 34291 | #define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 34292 | #define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 34293 | #define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_STRT_MASK 0x40L |
|---|
| 34294 | #define BIF_CFG_DEV0_EPF0_VF8_BIST__BIST_CAP_MASK 0x80L |
|---|
| 34295 | //BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1 |
|---|
| 34296 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 34297 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 34298 | //BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2 |
|---|
| 34299 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 34300 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 34301 | //BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3 |
|---|
| 34302 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 34303 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 34304 | //BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4 |
|---|
| 34305 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 34306 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 34307 | //BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5 |
|---|
| 34308 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 34309 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 34310 | //BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6 |
|---|
| 34311 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 34312 | #define BIF_CFG_DEV0_EPF0_VF8_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 34313 | //BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR |
|---|
| 34314 | #define BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 34315 | #define BIF_CFG_DEV0_EPF0_VF8_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 34316 | //BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID |
|---|
| 34317 | #define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 34318 | #define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 34319 | #define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 34320 | #define BIF_CFG_DEV0_EPF0_VF8_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 34321 | //BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR |
|---|
| 34322 | #define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 34323 | #define BIF_CFG_DEV0_EPF0_VF8_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 34324 | //BIF_CFG_DEV0_EPF0_VF8_CAP_PTR |
|---|
| 34325 | #define BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 34326 | #define BIF_CFG_DEV0_EPF0_VF8_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 34327 | //BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE |
|---|
| 34328 | #define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 34329 | #define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 34330 | //BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN |
|---|
| 34331 | #define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 34332 | #define BIF_CFG_DEV0_EPF0_VF8_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 34333 | //BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT |
|---|
| 34334 | #define BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 34335 | #define BIF_CFG_DEV0_EPF0_VF8_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 34336 | //BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY |
|---|
| 34337 | #define BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 34338 | #define BIF_CFG_DEV0_EPF0_VF8_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 34339 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST |
|---|
| 34340 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 34341 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 34342 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 34343 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 34344 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP |
|---|
| 34345 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 34346 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 34347 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 34348 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 34349 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 34350 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 34351 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 34352 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 34353 | //BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP |
|---|
| 34354 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 34355 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 34356 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 34357 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 34358 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 34359 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 34360 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 34361 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 34362 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 34363 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 34364 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 34365 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 34366 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 34367 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 34368 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 34369 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 34370 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 34371 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 34372 | //BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL |
|---|
| 34373 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 34374 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 34375 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 34376 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 34377 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 34378 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 34379 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 34380 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 34381 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 34382 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 34383 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 34384 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 34385 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 34386 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 34387 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 34388 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 34389 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 34390 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 34391 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 34392 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 34393 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 34394 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 34395 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 34396 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 34397 | //BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS |
|---|
| 34398 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 34399 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 34400 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 34401 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 34402 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 34403 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 34404 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 34405 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 34406 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 34407 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 34408 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 34409 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 34410 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 34411 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 34412 | //BIF_CFG_DEV0_EPF0_VF8_LINK_CAP |
|---|
| 34413 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 34414 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 34415 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 34416 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 34417 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 34418 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 34419 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 34420 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 34421 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 34422 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 34423 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 34424 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 34425 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 34426 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 34427 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 34428 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 34429 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 34430 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 34431 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 34432 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 34433 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 34434 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 34435 | //BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL |
|---|
| 34436 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 34437 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 34438 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 34439 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 34440 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 34441 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 34442 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 34443 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 34444 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 34445 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 34446 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 34447 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 34448 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 34449 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 34450 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 34451 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 34452 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 34453 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 34454 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 34455 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 34456 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 34457 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 34458 | //BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS |
|---|
| 34459 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 34460 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 34461 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 34462 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 34463 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 34464 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 34465 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 34466 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 34467 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 34468 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 34469 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 34470 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 34471 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 34472 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 34473 | //BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2 |
|---|
| 34474 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 34475 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 34476 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 34477 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 34478 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 34479 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 34480 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 34481 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 34482 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 34483 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 34484 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 34485 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 34486 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 34487 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 34488 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 34489 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 34490 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 34491 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 34492 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 34493 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 34494 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 34495 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 34496 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 34497 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 34498 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 34499 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 34500 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 34501 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 34502 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 34503 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 34504 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 34505 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 34506 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 34507 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 34508 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 34509 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 34510 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 34511 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 34512 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 34513 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 34514 | //BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2 |
|---|
| 34515 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 34516 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 34517 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 34518 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 34519 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 34520 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 34521 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 34522 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 34523 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 34524 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 34525 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 34526 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 34527 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 34528 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 34529 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 34530 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 34531 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 34532 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 34533 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 34534 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 34535 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 34536 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 34537 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 34538 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 34539 | //BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2 |
|---|
| 34540 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 34541 | #define BIF_CFG_DEV0_EPF0_VF8_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 34542 | //BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2 |
|---|
| 34543 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 34544 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 34545 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 34546 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 34547 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 34548 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 34549 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 34550 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 34551 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 34552 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 34553 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 34554 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 34555 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 34556 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 34557 | //BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2 |
|---|
| 34558 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 34559 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 34560 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 34561 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 34562 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 34563 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 34564 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 34565 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 34566 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 34567 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 34568 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 34569 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 34570 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 34571 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 34572 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 34573 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 34574 | //BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2 |
|---|
| 34575 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 34576 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 34577 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 34578 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 34579 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 34580 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 34581 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 34582 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 34583 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 34584 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 34585 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 34586 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 34587 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 34588 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 34589 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 34590 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 34591 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 34592 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 34593 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 34594 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 34595 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 34596 | #define BIF_CFG_DEV0_EPF0_VF8_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 34597 | //BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST |
|---|
| 34598 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 34599 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 34600 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 34601 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 34602 | //BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL |
|---|
| 34603 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 34604 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 34605 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 34606 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 34607 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 34608 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 34609 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 34610 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 34611 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 34612 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 34613 | //BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO |
|---|
| 34614 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 34615 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 34616 | //BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI |
|---|
| 34617 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 34618 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 34619 | //BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA |
|---|
| 34620 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 34621 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 34622 | //BIF_CFG_DEV0_EPF0_VF8_MSI_MASK |
|---|
| 34623 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 34624 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 34625 | //BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64 |
|---|
| 34626 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 34627 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 34628 | //BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64 |
|---|
| 34629 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 34630 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 34631 | //BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING |
|---|
| 34632 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 34633 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 34634 | //BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64 |
|---|
| 34635 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 34636 | #define BIF_CFG_DEV0_EPF0_VF8_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 34637 | //BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST |
|---|
| 34638 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 34639 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 34640 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 34641 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 34642 | //BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL |
|---|
| 34643 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 34644 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 34645 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 34646 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 34647 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 34648 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 34649 | //BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE |
|---|
| 34650 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 34651 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 34652 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 34653 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 34654 | //BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA |
|---|
| 34655 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 34656 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 34657 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 34658 | #define BIF_CFG_DEV0_EPF0_VF8_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 34659 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 34660 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 34661 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 34662 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 34663 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 34664 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 34665 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 34666 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 34667 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 34668 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 34669 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 34670 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 34671 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 34672 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 34673 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1 |
|---|
| 34674 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 34675 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 34676 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2 |
|---|
| 34677 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 34678 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 34679 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 34680 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 34681 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 34682 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 34683 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 34684 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 34685 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 34686 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS |
|---|
| 34687 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 34688 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 34689 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 34690 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 34691 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 34692 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 34693 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 34694 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 34695 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 34696 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 34697 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 34698 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 34699 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 34700 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 34701 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 34702 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 34703 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 34704 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 34705 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 34706 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 34707 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 34708 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 34709 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 34710 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 34711 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 34712 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 34713 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 34714 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 34715 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 34716 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 34717 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 34718 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 34719 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK |
|---|
| 34720 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 34721 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 34722 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 34723 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 34724 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 34725 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 34726 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 34727 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 34728 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 34729 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 34730 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 34731 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 34732 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 34733 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 34734 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 34735 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 34736 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 34737 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 34738 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 34739 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 34740 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 34741 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 34742 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 34743 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 34744 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 34745 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 34746 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 34747 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 34748 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 34749 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 34750 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 34751 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 34752 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 34753 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 34754 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 34755 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 34756 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 34757 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 34758 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 34759 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 34760 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 34761 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 34762 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 34763 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 34764 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 34765 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 34766 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 34767 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 34768 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 34769 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 34770 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 34771 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 34772 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 34773 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 34774 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 34775 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 34776 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 34777 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 34778 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 34779 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 34780 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 34781 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 34782 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 34783 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 34784 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 34785 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS |
|---|
| 34786 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 34787 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 34788 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 34789 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 34790 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 34791 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 34792 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 34793 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 34794 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 34795 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 34796 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 34797 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 34798 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 34799 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 34800 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 34801 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 34802 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK |
|---|
| 34803 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 34804 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 34805 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 34806 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 34807 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 34808 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 34809 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 34810 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 34811 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 34812 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 34813 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 34814 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 34815 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 34816 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 34817 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 34818 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 34819 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 34820 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 34821 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 34822 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 34823 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 34824 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 34825 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 34826 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 34827 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 34828 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 34829 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 34830 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 34831 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 34832 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 34833 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 34834 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 34835 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 34836 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 34837 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 34838 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0 |
|---|
| 34839 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 34840 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 34841 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1 |
|---|
| 34842 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 34843 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 34844 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2 |
|---|
| 34845 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 34846 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 34847 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3 |
|---|
| 34848 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 34849 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 34850 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0 |
|---|
| 34851 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 34852 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 34853 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1 |
|---|
| 34854 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 34855 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 34856 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2 |
|---|
| 34857 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 34858 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 34859 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3 |
|---|
| 34860 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 34861 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 34862 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST |
|---|
| 34863 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 34864 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 34865 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 34866 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 34867 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 34868 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 34869 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP |
|---|
| 34870 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 34871 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 34872 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 34873 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 34874 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 34875 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 34876 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL |
|---|
| 34877 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 34878 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 34879 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 34880 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 34881 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST |
|---|
| 34882 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 34883 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 34884 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 34885 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 34886 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 34887 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 34888 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP |
|---|
| 34889 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 34890 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 34891 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 34892 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 34893 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 34894 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 34895 | //BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL |
|---|
| 34896 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 34897 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 34898 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 34899 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 34900 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 34901 | #define BIF_CFG_DEV0_EPF0_VF8_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 34902 | |
|---|
| 34903 | |
|---|
| 34904 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp |
|---|
| 34905 | //BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID |
|---|
| 34906 | #define BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 34907 | #define BIF_CFG_DEV0_EPF0_VF9_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 34908 | //BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID |
|---|
| 34909 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 34910 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 34911 | //BIF_CFG_DEV0_EPF0_VF9_COMMAND |
|---|
| 34912 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 34913 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 34914 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 34915 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 34916 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 34917 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 34918 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 34919 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 34920 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 34921 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 34922 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 34923 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 34924 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 34925 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 34926 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 34927 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 34928 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 34929 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 34930 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 34931 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 34932 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 34933 | #define BIF_CFG_DEV0_EPF0_VF9_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 34934 | //BIF_CFG_DEV0_EPF0_VF9_STATUS |
|---|
| 34935 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 34936 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 34937 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 34938 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 34939 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 34940 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 34941 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 34942 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 34943 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 34944 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 34945 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 34946 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 34947 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 34948 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 34949 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 34950 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 34951 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 34952 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 34953 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 34954 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 34955 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 34956 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 34957 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 34958 | #define BIF_CFG_DEV0_EPF0_VF9_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 34959 | //BIF_CFG_DEV0_EPF0_VF9_REVISION_ID |
|---|
| 34960 | #define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 34961 | #define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 34962 | #define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 34963 | #define BIF_CFG_DEV0_EPF0_VF9_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 34964 | //BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE |
|---|
| 34965 | #define BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 34966 | #define BIF_CFG_DEV0_EPF0_VF9_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 34967 | //BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS |
|---|
| 34968 | #define BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 34969 | #define BIF_CFG_DEV0_EPF0_VF9_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 34970 | //BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS |
|---|
| 34971 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 34972 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 34973 | //BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE |
|---|
| 34974 | #define BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 34975 | #define BIF_CFG_DEV0_EPF0_VF9_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 34976 | //BIF_CFG_DEV0_EPF0_VF9_LATENCY |
|---|
| 34977 | #define BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 34978 | #define BIF_CFG_DEV0_EPF0_VF9_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 34979 | //BIF_CFG_DEV0_EPF0_VF9_HEADER |
|---|
| 34980 | #define 0x0 |
|---|
| 34981 | #define 0x7 |
|---|
| 34982 | #define 0x7FL |
|---|
| 34983 | #define 0x80L |
|---|
| 34984 | //BIF_CFG_DEV0_EPF0_VF9_BIST |
|---|
| 34985 | #define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 34986 | #define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 34987 | #define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 34988 | #define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 34989 | #define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_STRT_MASK 0x40L |
|---|
| 34990 | #define BIF_CFG_DEV0_EPF0_VF9_BIST__BIST_CAP_MASK 0x80L |
|---|
| 34991 | //BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1 |
|---|
| 34992 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 34993 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 34994 | //BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2 |
|---|
| 34995 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 34996 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 34997 | //BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3 |
|---|
| 34998 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 34999 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35000 | //BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4 |
|---|
| 35001 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 35002 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35003 | //BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5 |
|---|
| 35004 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 35005 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35006 | //BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6 |
|---|
| 35007 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 35008 | #define BIF_CFG_DEV0_EPF0_VF9_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35009 | //BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR |
|---|
| 35010 | #define BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 35011 | #define BIF_CFG_DEV0_EPF0_VF9_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 35012 | //BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID |
|---|
| 35013 | #define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 35014 | #define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 35015 | #define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 35016 | #define BIF_CFG_DEV0_EPF0_VF9_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 35017 | //BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR |
|---|
| 35018 | #define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 35019 | #define BIF_CFG_DEV0_EPF0_VF9_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35020 | //BIF_CFG_DEV0_EPF0_VF9_CAP_PTR |
|---|
| 35021 | #define BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 35022 | #define BIF_CFG_DEV0_EPF0_VF9_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 35023 | //BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE |
|---|
| 35024 | #define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 35025 | #define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 35026 | //BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN |
|---|
| 35027 | #define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 35028 | #define BIF_CFG_DEV0_EPF0_VF9_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 35029 | //BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT |
|---|
| 35030 | #define BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 35031 | #define BIF_CFG_DEV0_EPF0_VF9_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 35032 | //BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY |
|---|
| 35033 | #define BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 35034 | #define BIF_CFG_DEV0_EPF0_VF9_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 35035 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST |
|---|
| 35036 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 35037 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 35038 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 35039 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 35040 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP |
|---|
| 35041 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 35042 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 35043 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 35044 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 35045 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 35046 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 35047 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 35048 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 35049 | //BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP |
|---|
| 35050 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 35051 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 35052 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 35053 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 35054 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 35055 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 35056 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 35057 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 35058 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 35059 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 35060 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 35061 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 35062 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 35063 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 35064 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 35065 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 35066 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 35067 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 35068 | //BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL |
|---|
| 35069 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 35070 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 35071 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 35072 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 35073 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 35074 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 35075 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 35076 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 35077 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 35078 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 35079 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 35080 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 35081 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 35082 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 35083 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 35084 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 35085 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 35086 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 35087 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 35088 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 35089 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 35090 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 35091 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 35092 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 35093 | //BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS |
|---|
| 35094 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 35095 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 35096 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 35097 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 35098 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 35099 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 35100 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 35101 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 35102 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 35103 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 35104 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 35105 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 35106 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 35107 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 35108 | //BIF_CFG_DEV0_EPF0_VF9_LINK_CAP |
|---|
| 35109 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 35110 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 35111 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 35112 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 35113 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 35114 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 35115 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 35116 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 35117 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 35118 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 35119 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 35120 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 35121 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 35122 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 35123 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 35124 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 35125 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 35126 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 35127 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 35128 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 35129 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 35130 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 35131 | //BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL |
|---|
| 35132 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 35133 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 35134 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 35135 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 35136 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 35137 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 35138 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 35139 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 35140 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 35141 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 35142 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 35143 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 35144 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 35145 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 35146 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 35147 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 35148 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 35149 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 35150 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 35151 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 35152 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 35153 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 35154 | //BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS |
|---|
| 35155 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 35156 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 35157 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 35158 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 35159 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 35160 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 35161 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 35162 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 35163 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 35164 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 35165 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 35166 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 35167 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 35168 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 35169 | //BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2 |
|---|
| 35170 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 35171 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 35172 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 35173 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 35174 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 35175 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 35176 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 35177 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 35178 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 35179 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 35180 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 35181 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 35182 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 35183 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 35184 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 35185 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 35186 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 35187 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 35188 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 35189 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 35190 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 35191 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 35192 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 35193 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 35194 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 35195 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 35196 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 35197 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 35198 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 35199 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 35200 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 35201 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 35202 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 35203 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 35204 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 35205 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 35206 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 35207 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 35208 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 35209 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 35210 | //BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2 |
|---|
| 35211 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 35212 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 35213 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 35214 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 35215 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 35216 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 35217 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 35218 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 35219 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 35220 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 35221 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 35222 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 35223 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 35224 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 35225 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 35226 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 35227 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 35228 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 35229 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 35230 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 35231 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 35232 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 35233 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 35234 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 35235 | //BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2 |
|---|
| 35236 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 35237 | #define BIF_CFG_DEV0_EPF0_VF9_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 35238 | //BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2 |
|---|
| 35239 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 35240 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 35241 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 35242 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 35243 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 35244 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 35245 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 35246 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 35247 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 35248 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 35249 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 35250 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 35251 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 35252 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 35253 | //BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2 |
|---|
| 35254 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 35255 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 35256 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 35257 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 35258 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 35259 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 35260 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 35261 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 35262 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 35263 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 35264 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 35265 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 35266 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 35267 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 35268 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 35269 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 35270 | //BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2 |
|---|
| 35271 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 35272 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 35273 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 35274 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 35275 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 35276 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 35277 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 35278 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 35279 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 35280 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 35281 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 35282 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 35283 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 35284 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 35285 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 35286 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 35287 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 35288 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 35289 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 35290 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 35291 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 35292 | #define BIF_CFG_DEV0_EPF0_VF9_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 35293 | //BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST |
|---|
| 35294 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 35295 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 35296 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 35297 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 35298 | //BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL |
|---|
| 35299 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 35300 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 35301 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 35302 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 35303 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 35304 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 35305 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 35306 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 35307 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 35308 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 35309 | //BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO |
|---|
| 35310 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 35311 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 35312 | //BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI |
|---|
| 35313 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 35314 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 35315 | //BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA |
|---|
| 35316 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 35317 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 35318 | //BIF_CFG_DEV0_EPF0_VF9_MSI_MASK |
|---|
| 35319 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 35320 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 35321 | //BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64 |
|---|
| 35322 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 35323 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 35324 | //BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64 |
|---|
| 35325 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 35326 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 35327 | //BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING |
|---|
| 35328 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 35329 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 35330 | //BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64 |
|---|
| 35331 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 35332 | #define BIF_CFG_DEV0_EPF0_VF9_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 35333 | //BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST |
|---|
| 35334 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 35335 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 35336 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 35337 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 35338 | //BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL |
|---|
| 35339 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 35340 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 35341 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 35342 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 35343 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 35344 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 35345 | //BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE |
|---|
| 35346 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 35347 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 35348 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 35349 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 35350 | //BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA |
|---|
| 35351 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 35352 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 35353 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 35354 | #define BIF_CFG_DEV0_EPF0_VF9_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 35355 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 35356 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 35357 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 35358 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 35359 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 35360 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 35361 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 35362 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 35363 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 35364 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 35365 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 35366 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 35367 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 35368 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 35369 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1 |
|---|
| 35370 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 35371 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 35372 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2 |
|---|
| 35373 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 35374 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 35375 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 35376 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 35377 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 35378 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 35379 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 35380 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 35381 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 35382 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS |
|---|
| 35383 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 35384 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 35385 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 35386 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 35387 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 35388 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 35389 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 35390 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 35391 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 35392 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 35393 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 35394 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 35395 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 35396 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 35397 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 35398 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 35399 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 35400 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 35401 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 35402 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 35403 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 35404 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 35405 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 35406 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 35407 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 35408 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 35409 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 35410 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 35411 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 35412 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 35413 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 35414 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 35415 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK |
|---|
| 35416 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 35417 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 35418 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 35419 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 35420 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 35421 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 35422 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 35423 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 35424 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 35425 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 35426 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 35427 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 35428 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 35429 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 35430 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 35431 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 35432 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 35433 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 35434 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 35435 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 35436 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 35437 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 35438 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 35439 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 35440 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 35441 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 35442 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 35443 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 35444 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 35445 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 35446 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 35447 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 35448 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 35449 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 35450 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 35451 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 35452 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 35453 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 35454 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 35455 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 35456 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 35457 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 35458 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 35459 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 35460 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 35461 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 35462 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 35463 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 35464 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 35465 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 35466 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 35467 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 35468 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 35469 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 35470 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 35471 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 35472 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 35473 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 35474 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 35475 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 35476 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 35477 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 35478 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 35479 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 35480 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 35481 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS |
|---|
| 35482 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 35483 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 35484 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 35485 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 35486 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 35487 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 35488 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 35489 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 35490 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 35491 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 35492 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 35493 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 35494 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 35495 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 35496 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 35497 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 35498 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK |
|---|
| 35499 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 35500 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 35501 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 35502 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 35503 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 35504 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 35505 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 35506 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 35507 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 35508 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 35509 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 35510 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 35511 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 35512 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 35513 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 35514 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 35515 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 35516 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 35517 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 35518 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 35519 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 35520 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 35521 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 35522 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 35523 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 35524 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 35525 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 35526 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 35527 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 35528 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 35529 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 35530 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 35531 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 35532 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 35533 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 35534 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0 |
|---|
| 35535 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 35536 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 35537 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1 |
|---|
| 35538 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 35539 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 35540 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2 |
|---|
| 35541 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 35542 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 35543 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3 |
|---|
| 35544 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 35545 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 35546 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0 |
|---|
| 35547 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 35548 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 35549 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1 |
|---|
| 35550 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 35551 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 35552 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2 |
|---|
| 35553 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 35554 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 35555 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3 |
|---|
| 35556 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 35557 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 35558 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST |
|---|
| 35559 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 35560 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 35561 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 35562 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 35563 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 35564 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 35565 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP |
|---|
| 35566 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 35567 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 35568 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 35569 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 35570 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 35571 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 35572 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL |
|---|
| 35573 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 35574 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 35575 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 35576 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 35577 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST |
|---|
| 35578 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 35579 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 35580 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 35581 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 35582 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 35583 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 35584 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP |
|---|
| 35585 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 35586 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 35587 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 35588 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 35589 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 35590 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 35591 | //BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL |
|---|
| 35592 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 35593 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 35594 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 35595 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 35596 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 35597 | #define BIF_CFG_DEV0_EPF0_VF9_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 35598 | |
|---|
| 35599 | |
|---|
| 35600 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp |
|---|
| 35601 | //BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID |
|---|
| 35602 | #define BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 35603 | #define BIF_CFG_DEV0_EPF0_VF10_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 35604 | //BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID |
|---|
| 35605 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 35606 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 35607 | //BIF_CFG_DEV0_EPF0_VF10_COMMAND |
|---|
| 35608 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 35609 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 35610 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 35611 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 35612 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 35613 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 35614 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 35615 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 35616 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 35617 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 35618 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 35619 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 35620 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 35621 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 35622 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 35623 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 35624 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 35625 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 35626 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 35627 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 35628 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 35629 | #define BIF_CFG_DEV0_EPF0_VF10_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 35630 | //BIF_CFG_DEV0_EPF0_VF10_STATUS |
|---|
| 35631 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 35632 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 35633 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 35634 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 35635 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 35636 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 35637 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 35638 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 35639 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 35640 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 35641 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 35642 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 35643 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 35644 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 35645 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 35646 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 35647 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 35648 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 35649 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 35650 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 35651 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 35652 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 35653 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 35654 | #define BIF_CFG_DEV0_EPF0_VF10_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 35655 | //BIF_CFG_DEV0_EPF0_VF10_REVISION_ID |
|---|
| 35656 | #define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 35657 | #define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 35658 | #define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 35659 | #define BIF_CFG_DEV0_EPF0_VF10_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 35660 | //BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE |
|---|
| 35661 | #define BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 35662 | #define BIF_CFG_DEV0_EPF0_VF10_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 35663 | //BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS |
|---|
| 35664 | #define BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 35665 | #define BIF_CFG_DEV0_EPF0_VF10_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 35666 | //BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS |
|---|
| 35667 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 35668 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 35669 | //BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE |
|---|
| 35670 | #define BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 35671 | #define BIF_CFG_DEV0_EPF0_VF10_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 35672 | //BIF_CFG_DEV0_EPF0_VF10_LATENCY |
|---|
| 35673 | #define BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 35674 | #define BIF_CFG_DEV0_EPF0_VF10_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 35675 | //BIF_CFG_DEV0_EPF0_VF10_HEADER |
|---|
| 35676 | #define 0x0 |
|---|
| 35677 | #define 0x7 |
|---|
| 35678 | #define 0x7FL |
|---|
| 35679 | #define 0x80L |
|---|
| 35680 | //BIF_CFG_DEV0_EPF0_VF10_BIST |
|---|
| 35681 | #define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 35682 | #define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 35683 | #define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 35684 | #define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 35685 | #define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_STRT_MASK 0x40L |
|---|
| 35686 | #define BIF_CFG_DEV0_EPF0_VF10_BIST__BIST_CAP_MASK 0x80L |
|---|
| 35687 | //BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1 |
|---|
| 35688 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 35689 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35690 | //BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2 |
|---|
| 35691 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 35692 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35693 | //BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3 |
|---|
| 35694 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 35695 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35696 | //BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4 |
|---|
| 35697 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 35698 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35699 | //BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5 |
|---|
| 35700 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 35701 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35702 | //BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6 |
|---|
| 35703 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 35704 | #define BIF_CFG_DEV0_EPF0_VF10_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35705 | //BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR |
|---|
| 35706 | #define BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 35707 | #define BIF_CFG_DEV0_EPF0_VF10_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 35708 | //BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID |
|---|
| 35709 | #define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 35710 | #define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 35711 | #define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 35712 | #define BIF_CFG_DEV0_EPF0_VF10_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 35713 | //BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR |
|---|
| 35714 | #define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 35715 | #define BIF_CFG_DEV0_EPF0_VF10_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 35716 | //BIF_CFG_DEV0_EPF0_VF10_CAP_PTR |
|---|
| 35717 | #define BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 35718 | #define BIF_CFG_DEV0_EPF0_VF10_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 35719 | //BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE |
|---|
| 35720 | #define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 35721 | #define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 35722 | //BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN |
|---|
| 35723 | #define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 35724 | #define BIF_CFG_DEV0_EPF0_VF10_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 35725 | //BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT |
|---|
| 35726 | #define BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 35727 | #define BIF_CFG_DEV0_EPF0_VF10_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 35728 | //BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY |
|---|
| 35729 | #define BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 35730 | #define BIF_CFG_DEV0_EPF0_VF10_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 35731 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST |
|---|
| 35732 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 35733 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 35734 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 35735 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 35736 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP |
|---|
| 35737 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 35738 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 35739 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 35740 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 35741 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 35742 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 35743 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 35744 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 35745 | //BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP |
|---|
| 35746 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 35747 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 35748 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 35749 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 35750 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 35751 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 35752 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 35753 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 35754 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 35755 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 35756 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 35757 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 35758 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 35759 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 35760 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 35761 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 35762 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 35763 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 35764 | //BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL |
|---|
| 35765 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 35766 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 35767 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 35768 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 35769 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 35770 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 35771 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 35772 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 35773 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 35774 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 35775 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 35776 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 35777 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 35778 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 35779 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 35780 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 35781 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 35782 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 35783 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 35784 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 35785 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 35786 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 35787 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 35788 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 35789 | //BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS |
|---|
| 35790 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 35791 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 35792 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 35793 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 35794 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 35795 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 35796 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 35797 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 35798 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 35799 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 35800 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 35801 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 35802 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 35803 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 35804 | //BIF_CFG_DEV0_EPF0_VF10_LINK_CAP |
|---|
| 35805 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 35806 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 35807 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 35808 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 35809 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 35810 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 35811 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 35812 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 35813 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 35814 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 35815 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 35816 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 35817 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 35818 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 35819 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 35820 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 35821 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 35822 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 35823 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 35824 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 35825 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 35826 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 35827 | //BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL |
|---|
| 35828 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 35829 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 35830 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 35831 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 35832 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 35833 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 35834 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 35835 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 35836 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 35837 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 35838 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 35839 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 35840 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 35841 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 35842 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 35843 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 35844 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 35845 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 35846 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 35847 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 35848 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 35849 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 35850 | //BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS |
|---|
| 35851 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 35852 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 35853 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 35854 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 35855 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 35856 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 35857 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 35858 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 35859 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 35860 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 35861 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 35862 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 35863 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 35864 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 35865 | //BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2 |
|---|
| 35866 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 35867 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 35868 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 35869 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 35870 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 35871 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 35872 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 35873 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 35874 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 35875 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 35876 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 35877 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 35878 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 35879 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 35880 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 35881 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 35882 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 35883 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 35884 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 35885 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 35886 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 35887 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 35888 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 35889 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 35890 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 35891 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 35892 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 35893 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 35894 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 35895 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 35896 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 35897 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 35898 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 35899 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 35900 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 35901 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 35902 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 35903 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 35904 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 35905 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 35906 | //BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2 |
|---|
| 35907 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 35908 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 35909 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 35910 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 35911 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 35912 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 35913 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 35914 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 35915 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 35916 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 35917 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 35918 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 35919 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 35920 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 35921 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 35922 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 35923 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 35924 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 35925 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 35926 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 35927 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 35928 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 35929 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 35930 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 35931 | //BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2 |
|---|
| 35932 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 35933 | #define BIF_CFG_DEV0_EPF0_VF10_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 35934 | //BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2 |
|---|
| 35935 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 35936 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 35937 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 35938 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 35939 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 35940 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 35941 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 35942 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 35943 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 35944 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 35945 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 35946 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 35947 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 35948 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 35949 | //BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2 |
|---|
| 35950 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 35951 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 35952 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 35953 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 35954 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 35955 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 35956 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 35957 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 35958 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 35959 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 35960 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 35961 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 35962 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 35963 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 35964 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 35965 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 35966 | //BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2 |
|---|
| 35967 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 35968 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 35969 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 35970 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 35971 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 35972 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 35973 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 35974 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 35975 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 35976 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 35977 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 35978 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 35979 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 35980 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 35981 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 35982 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 35983 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 35984 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 35985 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 35986 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 35987 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 35988 | #define BIF_CFG_DEV0_EPF0_VF10_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 35989 | //BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST |
|---|
| 35990 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 35991 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 35992 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 35993 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 35994 | //BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL |
|---|
| 35995 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 35996 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 35997 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 35998 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 35999 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 36000 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 36001 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 36002 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 36003 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 36004 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 36005 | //BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO |
|---|
| 36006 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 36007 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 36008 | //BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI |
|---|
| 36009 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 36010 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 36011 | //BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA |
|---|
| 36012 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 36013 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 36014 | //BIF_CFG_DEV0_EPF0_VF10_MSI_MASK |
|---|
| 36015 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 36016 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 36017 | //BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64 |
|---|
| 36018 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 36019 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 36020 | //BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64 |
|---|
| 36021 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 36022 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 36023 | //BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING |
|---|
| 36024 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 36025 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 36026 | //BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64 |
|---|
| 36027 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 36028 | #define BIF_CFG_DEV0_EPF0_VF10_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 36029 | //BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST |
|---|
| 36030 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36031 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 36032 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 36033 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 36034 | //BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL |
|---|
| 36035 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 36036 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 36037 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 36038 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 36039 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 36040 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 36041 | //BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE |
|---|
| 36042 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 36043 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 36044 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 36045 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 36046 | //BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA |
|---|
| 36047 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 36048 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 36049 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 36050 | #define BIF_CFG_DEV0_EPF0_VF10_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 36051 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 36052 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36053 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 36054 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 36055 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 36056 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 36057 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 36058 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 36059 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 36060 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 36061 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 36062 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 36063 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 36064 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 36065 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1 |
|---|
| 36066 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 36067 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 36068 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2 |
|---|
| 36069 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 36070 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 36071 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 36072 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36073 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 36074 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 36075 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 36076 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 36077 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 36078 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS |
|---|
| 36079 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 36080 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 36081 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 36082 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 36083 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 36084 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 36085 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 36086 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 36087 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 36088 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 36089 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 36090 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 36091 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 36092 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 36093 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 36094 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 36095 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 36096 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 36097 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 36098 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 36099 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 36100 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 36101 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 36102 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 36103 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 36104 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 36105 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 36106 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 36107 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 36108 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 36109 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 36110 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 36111 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK |
|---|
| 36112 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 36113 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 36114 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 36115 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 36116 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 36117 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 36118 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 36119 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 36120 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 36121 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 36122 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 36123 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 36124 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 36125 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 36126 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 36127 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 36128 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 36129 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 36130 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 36131 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 36132 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 36133 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 36134 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 36135 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 36136 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 36137 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 36138 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 36139 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 36140 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 36141 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 36142 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 36143 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 36144 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 36145 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 36146 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 36147 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 36148 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 36149 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 36150 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 36151 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 36152 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 36153 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 36154 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 36155 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 36156 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 36157 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 36158 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 36159 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 36160 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 36161 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 36162 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 36163 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 36164 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 36165 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 36166 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 36167 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 36168 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 36169 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 36170 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 36171 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 36172 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 36173 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 36174 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 36175 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 36176 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 36177 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS |
|---|
| 36178 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 36179 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 36180 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 36181 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 36182 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 36183 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 36184 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 36185 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 36186 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 36187 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 36188 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 36189 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 36190 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 36191 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 36192 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 36193 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 36194 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK |
|---|
| 36195 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 36196 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 36197 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 36198 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 36199 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 36200 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 36201 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 36202 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 36203 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 36204 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 36205 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 36206 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 36207 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 36208 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 36209 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 36210 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 36211 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 36212 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 36213 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 36214 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 36215 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 36216 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 36217 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 36218 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 36219 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 36220 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 36221 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 36222 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 36223 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 36224 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 36225 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 36226 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 36227 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 36228 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 36229 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 36230 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0 |
|---|
| 36231 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 36232 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 36233 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1 |
|---|
| 36234 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 36235 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 36236 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2 |
|---|
| 36237 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 36238 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 36239 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3 |
|---|
| 36240 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 36241 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 36242 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0 |
|---|
| 36243 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 36244 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 36245 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1 |
|---|
| 36246 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 36247 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 36248 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2 |
|---|
| 36249 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 36250 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 36251 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3 |
|---|
| 36252 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 36253 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 36254 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST |
|---|
| 36255 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36256 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 36257 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 36258 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 36259 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 36260 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 36261 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP |
|---|
| 36262 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 36263 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 36264 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 36265 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 36266 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 36267 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 36268 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL |
|---|
| 36269 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 36270 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 36271 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 36272 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 36273 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST |
|---|
| 36274 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36275 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 36276 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 36277 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 36278 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 36279 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 36280 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP |
|---|
| 36281 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 36282 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 36283 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 36284 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 36285 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 36286 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 36287 | //BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL |
|---|
| 36288 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 36289 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 36290 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 36291 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 36292 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 36293 | #define BIF_CFG_DEV0_EPF0_VF10_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 36294 | |
|---|
| 36295 | |
|---|
| 36296 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp |
|---|
| 36297 | //BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID |
|---|
| 36298 | #define BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 36299 | #define BIF_CFG_DEV0_EPF0_VF11_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 36300 | //BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID |
|---|
| 36301 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 36302 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 36303 | //BIF_CFG_DEV0_EPF0_VF11_COMMAND |
|---|
| 36304 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 36305 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 36306 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 36307 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 36308 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 36309 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 36310 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 36311 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 36312 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 36313 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 36314 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 36315 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 36316 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 36317 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 36318 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 36319 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 36320 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 36321 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 36322 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 36323 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 36324 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 36325 | #define BIF_CFG_DEV0_EPF0_VF11_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 36326 | //BIF_CFG_DEV0_EPF0_VF11_STATUS |
|---|
| 36327 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 36328 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 36329 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 36330 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 36331 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 36332 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 36333 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 36334 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 36335 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 36336 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 36337 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 36338 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 36339 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 36340 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 36341 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 36342 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 36343 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 36344 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 36345 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 36346 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 36347 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 36348 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 36349 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 36350 | #define BIF_CFG_DEV0_EPF0_VF11_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 36351 | //BIF_CFG_DEV0_EPF0_VF11_REVISION_ID |
|---|
| 36352 | #define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 36353 | #define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 36354 | #define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 36355 | #define BIF_CFG_DEV0_EPF0_VF11_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 36356 | //BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE |
|---|
| 36357 | #define BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 36358 | #define BIF_CFG_DEV0_EPF0_VF11_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 36359 | //BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS |
|---|
| 36360 | #define BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 36361 | #define BIF_CFG_DEV0_EPF0_VF11_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 36362 | //BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS |
|---|
| 36363 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 36364 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 36365 | //BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE |
|---|
| 36366 | #define BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 36367 | #define BIF_CFG_DEV0_EPF0_VF11_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 36368 | //BIF_CFG_DEV0_EPF0_VF11_LATENCY |
|---|
| 36369 | #define BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 36370 | #define BIF_CFG_DEV0_EPF0_VF11_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 36371 | //BIF_CFG_DEV0_EPF0_VF11_HEADER |
|---|
| 36372 | #define 0x0 |
|---|
| 36373 | #define 0x7 |
|---|
| 36374 | #define 0x7FL |
|---|
| 36375 | #define 0x80L |
|---|
| 36376 | //BIF_CFG_DEV0_EPF0_VF11_BIST |
|---|
| 36377 | #define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 36378 | #define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 36379 | #define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 36380 | #define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 36381 | #define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_STRT_MASK 0x40L |
|---|
| 36382 | #define BIF_CFG_DEV0_EPF0_VF11_BIST__BIST_CAP_MASK 0x80L |
|---|
| 36383 | //BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1 |
|---|
| 36384 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 36385 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 36386 | //BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2 |
|---|
| 36387 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 36388 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 36389 | //BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3 |
|---|
| 36390 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 36391 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 36392 | //BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4 |
|---|
| 36393 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 36394 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 36395 | //BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5 |
|---|
| 36396 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 36397 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 36398 | //BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6 |
|---|
| 36399 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 36400 | #define BIF_CFG_DEV0_EPF0_VF11_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 36401 | //BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR |
|---|
| 36402 | #define BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 36403 | #define BIF_CFG_DEV0_EPF0_VF11_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 36404 | //BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID |
|---|
| 36405 | #define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 36406 | #define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 36407 | #define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 36408 | #define BIF_CFG_DEV0_EPF0_VF11_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 36409 | //BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR |
|---|
| 36410 | #define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 36411 | #define BIF_CFG_DEV0_EPF0_VF11_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 36412 | //BIF_CFG_DEV0_EPF0_VF11_CAP_PTR |
|---|
| 36413 | #define BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 36414 | #define BIF_CFG_DEV0_EPF0_VF11_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 36415 | //BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE |
|---|
| 36416 | #define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 36417 | #define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 36418 | //BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN |
|---|
| 36419 | #define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 36420 | #define BIF_CFG_DEV0_EPF0_VF11_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 36421 | //BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT |
|---|
| 36422 | #define BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 36423 | #define BIF_CFG_DEV0_EPF0_VF11_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 36424 | //BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY |
|---|
| 36425 | #define BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 36426 | #define BIF_CFG_DEV0_EPF0_VF11_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 36427 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST |
|---|
| 36428 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36429 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 36430 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 36431 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 36432 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP |
|---|
| 36433 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 36434 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 36435 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 36436 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 36437 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 36438 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 36439 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 36440 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 36441 | //BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP |
|---|
| 36442 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 36443 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 36444 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 36445 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 36446 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 36447 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 36448 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 36449 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 36450 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 36451 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 36452 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 36453 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 36454 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 36455 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 36456 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 36457 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 36458 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 36459 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 36460 | //BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL |
|---|
| 36461 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 36462 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 36463 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 36464 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 36465 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 36466 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 36467 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 36468 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 36469 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 36470 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 36471 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 36472 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 36473 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 36474 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 36475 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 36476 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 36477 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 36478 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 36479 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 36480 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 36481 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 36482 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 36483 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 36484 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 36485 | //BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS |
|---|
| 36486 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 36487 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 36488 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 36489 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 36490 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 36491 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 36492 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 36493 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 36494 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 36495 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 36496 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 36497 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 36498 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 36499 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 36500 | //BIF_CFG_DEV0_EPF0_VF11_LINK_CAP |
|---|
| 36501 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 36502 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 36503 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 36504 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 36505 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 36506 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 36507 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 36508 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 36509 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 36510 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 36511 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 36512 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 36513 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 36514 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 36515 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 36516 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 36517 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 36518 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 36519 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 36520 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 36521 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 36522 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 36523 | //BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL |
|---|
| 36524 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 36525 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 36526 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 36527 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 36528 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 36529 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 36530 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 36531 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 36532 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 36533 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 36534 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 36535 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 36536 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 36537 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 36538 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 36539 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 36540 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 36541 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 36542 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 36543 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 36544 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 36545 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 36546 | //BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS |
|---|
| 36547 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 36548 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 36549 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 36550 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 36551 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 36552 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 36553 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 36554 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 36555 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 36556 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 36557 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 36558 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 36559 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 36560 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 36561 | //BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2 |
|---|
| 36562 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 36563 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 36564 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 36565 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 36566 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 36567 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 36568 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 36569 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 36570 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 36571 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 36572 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 36573 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 36574 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 36575 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 36576 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 36577 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 36578 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 36579 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 36580 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 36581 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 36582 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 36583 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 36584 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 36585 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 36586 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 36587 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 36588 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 36589 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 36590 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 36591 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 36592 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 36593 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 36594 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 36595 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 36596 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 36597 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 36598 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 36599 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 36600 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 36601 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 36602 | //BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2 |
|---|
| 36603 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 36604 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 36605 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 36606 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 36607 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 36608 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 36609 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 36610 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 36611 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 36612 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 36613 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 36614 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 36615 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 36616 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 36617 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 36618 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 36619 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 36620 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 36621 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 36622 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 36623 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 36624 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 36625 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 36626 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 36627 | //BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2 |
|---|
| 36628 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 36629 | #define BIF_CFG_DEV0_EPF0_VF11_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 36630 | //BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2 |
|---|
| 36631 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 36632 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 36633 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 36634 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 36635 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 36636 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 36637 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 36638 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 36639 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 36640 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 36641 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 36642 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 36643 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 36644 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 36645 | //BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2 |
|---|
| 36646 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 36647 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 36648 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 36649 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 36650 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 36651 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 36652 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 36653 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 36654 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 36655 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 36656 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 36657 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 36658 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 36659 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 36660 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 36661 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 36662 | //BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2 |
|---|
| 36663 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 36664 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 36665 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 36666 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 36667 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 36668 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 36669 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 36670 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 36671 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 36672 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 36673 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 36674 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 36675 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 36676 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 36677 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 36678 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 36679 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 36680 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 36681 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 36682 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 36683 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 36684 | #define BIF_CFG_DEV0_EPF0_VF11_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 36685 | //BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST |
|---|
| 36686 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36687 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 36688 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 36689 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 36690 | //BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL |
|---|
| 36691 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 36692 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 36693 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 36694 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 36695 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 36696 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 36697 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 36698 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 36699 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 36700 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 36701 | //BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO |
|---|
| 36702 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 36703 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 36704 | //BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI |
|---|
| 36705 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 36706 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 36707 | //BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA |
|---|
| 36708 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 36709 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 36710 | //BIF_CFG_DEV0_EPF0_VF11_MSI_MASK |
|---|
| 36711 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 36712 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 36713 | //BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64 |
|---|
| 36714 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 36715 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 36716 | //BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64 |
|---|
| 36717 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 36718 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 36719 | //BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING |
|---|
| 36720 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 36721 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 36722 | //BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64 |
|---|
| 36723 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 36724 | #define BIF_CFG_DEV0_EPF0_VF11_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 36725 | //BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST |
|---|
| 36726 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36727 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 36728 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 36729 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 36730 | //BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL |
|---|
| 36731 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 36732 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 36733 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 36734 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 36735 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 36736 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 36737 | //BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE |
|---|
| 36738 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 36739 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 36740 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 36741 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 36742 | //BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA |
|---|
| 36743 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 36744 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 36745 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 36746 | #define BIF_CFG_DEV0_EPF0_VF11_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 36747 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 36748 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36749 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 36750 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 36751 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 36752 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 36753 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 36754 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 36755 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 36756 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 36757 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 36758 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 36759 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 36760 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 36761 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1 |
|---|
| 36762 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 36763 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 36764 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2 |
|---|
| 36765 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 36766 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 36767 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 36768 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36769 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 36770 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 36771 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 36772 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 36773 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 36774 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS |
|---|
| 36775 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 36776 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 36777 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 36778 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 36779 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 36780 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 36781 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 36782 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 36783 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 36784 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 36785 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 36786 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 36787 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 36788 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 36789 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 36790 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 36791 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 36792 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 36793 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 36794 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 36795 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 36796 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 36797 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 36798 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 36799 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 36800 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 36801 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 36802 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 36803 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 36804 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 36805 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 36806 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 36807 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK |
|---|
| 36808 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 36809 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 36810 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 36811 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 36812 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 36813 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 36814 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 36815 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 36816 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 36817 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 36818 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 36819 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 36820 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 36821 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 36822 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 36823 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 36824 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 36825 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 36826 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 36827 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 36828 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 36829 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 36830 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 36831 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 36832 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 36833 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 36834 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 36835 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 36836 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 36837 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 36838 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 36839 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 36840 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 36841 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 36842 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 36843 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 36844 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 36845 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 36846 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 36847 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 36848 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 36849 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 36850 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 36851 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 36852 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 36853 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 36854 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 36855 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 36856 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 36857 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 36858 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 36859 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 36860 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 36861 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 36862 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 36863 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 36864 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 36865 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 36866 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 36867 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 36868 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 36869 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 36870 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 36871 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 36872 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 36873 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS |
|---|
| 36874 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 36875 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 36876 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 36877 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 36878 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 36879 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 36880 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 36881 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 36882 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 36883 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 36884 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 36885 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 36886 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 36887 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 36888 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 36889 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 36890 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK |
|---|
| 36891 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 36892 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 36893 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 36894 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 36895 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 36896 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 36897 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 36898 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 36899 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 36900 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 36901 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 36902 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 36903 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 36904 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 36905 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 36906 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 36907 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 36908 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 36909 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 36910 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 36911 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 36912 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 36913 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 36914 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 36915 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 36916 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 36917 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 36918 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 36919 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 36920 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 36921 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 36922 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 36923 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 36924 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 36925 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 36926 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0 |
|---|
| 36927 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 36928 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 36929 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1 |
|---|
| 36930 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 36931 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 36932 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2 |
|---|
| 36933 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 36934 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 36935 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3 |
|---|
| 36936 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 36937 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 36938 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0 |
|---|
| 36939 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 36940 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 36941 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1 |
|---|
| 36942 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 36943 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 36944 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2 |
|---|
| 36945 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 36946 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 36947 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3 |
|---|
| 36948 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 36949 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 36950 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST |
|---|
| 36951 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36952 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 36953 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 36954 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 36955 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 36956 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 36957 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP |
|---|
| 36958 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 36959 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 36960 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 36961 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 36962 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 36963 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 36964 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL |
|---|
| 36965 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 36966 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 36967 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 36968 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 36969 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST |
|---|
| 36970 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 36971 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 36972 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 36973 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 36974 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 36975 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 36976 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP |
|---|
| 36977 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 36978 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 36979 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 36980 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 36981 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 36982 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 36983 | //BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL |
|---|
| 36984 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 36985 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 36986 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 36987 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 36988 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 36989 | #define BIF_CFG_DEV0_EPF0_VF11_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 36990 | |
|---|
| 36991 | |
|---|
| 36992 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp |
|---|
| 36993 | //BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID |
|---|
| 36994 | #define BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 36995 | #define BIF_CFG_DEV0_EPF0_VF12_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 36996 | //BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID |
|---|
| 36997 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 36998 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 36999 | //BIF_CFG_DEV0_EPF0_VF12_COMMAND |
|---|
| 37000 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 37001 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 37002 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 37003 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 37004 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 37005 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 37006 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 37007 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 37008 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 37009 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 37010 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 37011 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 37012 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 37013 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 37014 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 37015 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 37016 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 37017 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 37018 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 37019 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 37020 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 37021 | #define BIF_CFG_DEV0_EPF0_VF12_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 37022 | //BIF_CFG_DEV0_EPF0_VF12_STATUS |
|---|
| 37023 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 37024 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 37025 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 37026 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 37027 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 37028 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 37029 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 37030 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 37031 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 37032 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 37033 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 37034 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 37035 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 37036 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 37037 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 37038 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 37039 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 37040 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 37041 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 37042 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 37043 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 37044 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 37045 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 37046 | #define BIF_CFG_DEV0_EPF0_VF12_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 37047 | //BIF_CFG_DEV0_EPF0_VF12_REVISION_ID |
|---|
| 37048 | #define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 37049 | #define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 37050 | #define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 37051 | #define BIF_CFG_DEV0_EPF0_VF12_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 37052 | //BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE |
|---|
| 37053 | #define BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 37054 | #define BIF_CFG_DEV0_EPF0_VF12_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 37055 | //BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS |
|---|
| 37056 | #define BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 37057 | #define BIF_CFG_DEV0_EPF0_VF12_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 37058 | //BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS |
|---|
| 37059 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 37060 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 37061 | //BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE |
|---|
| 37062 | #define BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 37063 | #define BIF_CFG_DEV0_EPF0_VF12_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 37064 | //BIF_CFG_DEV0_EPF0_VF12_LATENCY |
|---|
| 37065 | #define BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 37066 | #define BIF_CFG_DEV0_EPF0_VF12_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 37067 | //BIF_CFG_DEV0_EPF0_VF12_HEADER |
|---|
| 37068 | #define 0x0 |
|---|
| 37069 | #define 0x7 |
|---|
| 37070 | #define 0x7FL |
|---|
| 37071 | #define 0x80L |
|---|
| 37072 | //BIF_CFG_DEV0_EPF0_VF12_BIST |
|---|
| 37073 | #define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 37074 | #define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 37075 | #define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 37076 | #define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 37077 | #define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_STRT_MASK 0x40L |
|---|
| 37078 | #define BIF_CFG_DEV0_EPF0_VF12_BIST__BIST_CAP_MASK 0x80L |
|---|
| 37079 | //BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1 |
|---|
| 37080 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 37081 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37082 | //BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2 |
|---|
| 37083 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 37084 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37085 | //BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3 |
|---|
| 37086 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 37087 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37088 | //BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4 |
|---|
| 37089 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 37090 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37091 | //BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5 |
|---|
| 37092 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 37093 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37094 | //BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6 |
|---|
| 37095 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 37096 | #define BIF_CFG_DEV0_EPF0_VF12_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37097 | //BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR |
|---|
| 37098 | #define BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 37099 | #define BIF_CFG_DEV0_EPF0_VF12_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 37100 | //BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID |
|---|
| 37101 | #define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 37102 | #define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 37103 | #define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 37104 | #define BIF_CFG_DEV0_EPF0_VF12_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 37105 | //BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR |
|---|
| 37106 | #define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 37107 | #define BIF_CFG_DEV0_EPF0_VF12_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37108 | //BIF_CFG_DEV0_EPF0_VF12_CAP_PTR |
|---|
| 37109 | #define BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 37110 | #define BIF_CFG_DEV0_EPF0_VF12_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 37111 | //BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE |
|---|
| 37112 | #define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 37113 | #define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 37114 | //BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN |
|---|
| 37115 | #define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 37116 | #define BIF_CFG_DEV0_EPF0_VF12_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 37117 | //BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT |
|---|
| 37118 | #define BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 37119 | #define BIF_CFG_DEV0_EPF0_VF12_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 37120 | //BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY |
|---|
| 37121 | #define BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 37122 | #define BIF_CFG_DEV0_EPF0_VF12_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 37123 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST |
|---|
| 37124 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 37125 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 37126 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 37127 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 37128 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP |
|---|
| 37129 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 37130 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 37131 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 37132 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 37133 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 37134 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 37135 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 37136 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 37137 | //BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP |
|---|
| 37138 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 37139 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 37140 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 37141 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 37142 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 37143 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 37144 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 37145 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 37146 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 37147 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 37148 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 37149 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 37150 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 37151 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 37152 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 37153 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 37154 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 37155 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 37156 | //BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL |
|---|
| 37157 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 37158 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 37159 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 37160 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 37161 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 37162 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 37163 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 37164 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 37165 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 37166 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 37167 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 37168 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 37169 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 37170 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 37171 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 37172 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 37173 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 37174 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 37175 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 37176 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 37177 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 37178 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 37179 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 37180 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 37181 | //BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS |
|---|
| 37182 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 37183 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 37184 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 37185 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 37186 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 37187 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 37188 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 37189 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 37190 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 37191 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 37192 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 37193 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 37194 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 37195 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 37196 | //BIF_CFG_DEV0_EPF0_VF12_LINK_CAP |
|---|
| 37197 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 37198 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 37199 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 37200 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 37201 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 37202 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 37203 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 37204 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 37205 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 37206 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 37207 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 37208 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 37209 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 37210 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 37211 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 37212 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 37213 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 37214 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 37215 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 37216 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 37217 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 37218 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 37219 | //BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL |
|---|
| 37220 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 37221 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 37222 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 37223 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 37224 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 37225 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 37226 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 37227 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 37228 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 37229 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 37230 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 37231 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 37232 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 37233 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 37234 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 37235 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 37236 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 37237 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 37238 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 37239 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 37240 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 37241 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 37242 | //BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS |
|---|
| 37243 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 37244 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 37245 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 37246 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 37247 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 37248 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 37249 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 37250 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 37251 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 37252 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 37253 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 37254 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 37255 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 37256 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 37257 | //BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2 |
|---|
| 37258 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 37259 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 37260 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 37261 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 37262 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 37263 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 37264 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 37265 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 37266 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 37267 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 37268 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 37269 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 37270 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 37271 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 37272 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 37273 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 37274 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 37275 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 37276 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 37277 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 37278 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 37279 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 37280 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 37281 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 37282 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 37283 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 37284 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 37285 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 37286 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 37287 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 37288 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 37289 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 37290 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 37291 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 37292 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 37293 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 37294 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 37295 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 37296 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 37297 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 37298 | //BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2 |
|---|
| 37299 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 37300 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 37301 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 37302 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 37303 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 37304 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 37305 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 37306 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 37307 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 37308 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 37309 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 37310 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 37311 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 37312 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 37313 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 37314 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 37315 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 37316 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 37317 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 37318 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 37319 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 37320 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 37321 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 37322 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 37323 | //BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2 |
|---|
| 37324 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 37325 | #define BIF_CFG_DEV0_EPF0_VF12_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 37326 | //BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2 |
|---|
| 37327 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 37328 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 37329 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 37330 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 37331 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 37332 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 37333 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 37334 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 37335 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 37336 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 37337 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 37338 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 37339 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 37340 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 37341 | //BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2 |
|---|
| 37342 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 37343 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 37344 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 37345 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 37346 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 37347 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 37348 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 37349 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 37350 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 37351 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 37352 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 37353 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 37354 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 37355 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 37356 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 37357 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 37358 | //BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2 |
|---|
| 37359 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 37360 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 37361 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 37362 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 37363 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 37364 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 37365 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 37366 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 37367 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 37368 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 37369 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 37370 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 37371 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 37372 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 37373 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 37374 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 37375 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 37376 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 37377 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 37378 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 37379 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 37380 | #define BIF_CFG_DEV0_EPF0_VF12_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 37381 | //BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST |
|---|
| 37382 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 37383 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 37384 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 37385 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 37386 | //BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL |
|---|
| 37387 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 37388 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 37389 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 37390 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 37391 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 37392 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 37393 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 37394 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 37395 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 37396 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 37397 | //BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO |
|---|
| 37398 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 37399 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 37400 | //BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI |
|---|
| 37401 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 37402 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 37403 | //BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA |
|---|
| 37404 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 37405 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 37406 | //BIF_CFG_DEV0_EPF0_VF12_MSI_MASK |
|---|
| 37407 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 37408 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 37409 | //BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64 |
|---|
| 37410 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 37411 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 37412 | //BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64 |
|---|
| 37413 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 37414 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 37415 | //BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING |
|---|
| 37416 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 37417 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 37418 | //BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64 |
|---|
| 37419 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 37420 | #define BIF_CFG_DEV0_EPF0_VF12_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 37421 | //BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST |
|---|
| 37422 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 37423 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 37424 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 37425 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 37426 | //BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL |
|---|
| 37427 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 37428 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 37429 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 37430 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 37431 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 37432 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 37433 | //BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE |
|---|
| 37434 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 37435 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 37436 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 37437 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 37438 | //BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA |
|---|
| 37439 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 37440 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 37441 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 37442 | #define BIF_CFG_DEV0_EPF0_VF12_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 37443 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 37444 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 37445 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 37446 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 37447 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 37448 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 37449 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 37450 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 37451 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 37452 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 37453 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 37454 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 37455 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 37456 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 37457 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1 |
|---|
| 37458 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 37459 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 37460 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2 |
|---|
| 37461 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 37462 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 37463 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 37464 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 37465 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 37466 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 37467 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 37468 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 37469 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 37470 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS |
|---|
| 37471 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 37472 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 37473 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 37474 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 37475 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 37476 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 37477 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 37478 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 37479 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 37480 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 37481 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 37482 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 37483 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 37484 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 37485 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 37486 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 37487 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 37488 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 37489 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 37490 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 37491 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 37492 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 37493 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 37494 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 37495 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 37496 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 37497 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 37498 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 37499 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 37500 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 37501 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 37502 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 37503 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK |
|---|
| 37504 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 37505 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 37506 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 37507 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 37508 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 37509 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 37510 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 37511 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 37512 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 37513 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 37514 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 37515 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 37516 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 37517 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 37518 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 37519 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 37520 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 37521 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 37522 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 37523 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 37524 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 37525 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 37526 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 37527 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 37528 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 37529 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 37530 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 37531 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 37532 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 37533 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 37534 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 37535 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 37536 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 37537 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 37538 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 37539 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 37540 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 37541 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 37542 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 37543 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 37544 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 37545 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 37546 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 37547 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 37548 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 37549 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 37550 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 37551 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 37552 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 37553 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 37554 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 37555 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 37556 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 37557 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 37558 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 37559 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 37560 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 37561 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 37562 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 37563 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 37564 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 37565 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 37566 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 37567 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 37568 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 37569 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS |
|---|
| 37570 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 37571 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 37572 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 37573 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 37574 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 37575 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 37576 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 37577 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 37578 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 37579 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 37580 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 37581 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 37582 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 37583 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 37584 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 37585 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 37586 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK |
|---|
| 37587 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 37588 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 37589 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 37590 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 37591 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 37592 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 37593 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 37594 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 37595 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 37596 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 37597 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 37598 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 37599 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 37600 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 37601 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 37602 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 37603 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 37604 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 37605 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 37606 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 37607 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 37608 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 37609 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 37610 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 37611 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 37612 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 37613 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 37614 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 37615 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 37616 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 37617 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 37618 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 37619 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 37620 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 37621 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 37622 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0 |
|---|
| 37623 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 37624 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 37625 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1 |
|---|
| 37626 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 37627 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 37628 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2 |
|---|
| 37629 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 37630 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 37631 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3 |
|---|
| 37632 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 37633 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 37634 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0 |
|---|
| 37635 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 37636 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 37637 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1 |
|---|
| 37638 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 37639 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 37640 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2 |
|---|
| 37641 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 37642 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 37643 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3 |
|---|
| 37644 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 37645 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 37646 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST |
|---|
| 37647 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 37648 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 37649 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 37650 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 37651 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 37652 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 37653 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP |
|---|
| 37654 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 37655 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 37656 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 37657 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 37658 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 37659 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 37660 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL |
|---|
| 37661 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 37662 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 37663 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 37664 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 37665 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST |
|---|
| 37666 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 37667 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 37668 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 37669 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 37670 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 37671 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 37672 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP |
|---|
| 37673 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 37674 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 37675 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 37676 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 37677 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 37678 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 37679 | //BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL |
|---|
| 37680 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 37681 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 37682 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 37683 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 37684 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 37685 | #define BIF_CFG_DEV0_EPF0_VF12_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 37686 | |
|---|
| 37687 | |
|---|
| 37688 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp |
|---|
| 37689 | //BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID |
|---|
| 37690 | #define BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 37691 | #define BIF_CFG_DEV0_EPF0_VF13_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 37692 | //BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID |
|---|
| 37693 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 37694 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 37695 | //BIF_CFG_DEV0_EPF0_VF13_COMMAND |
|---|
| 37696 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 37697 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 37698 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 37699 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 37700 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 37701 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 37702 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 37703 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 37704 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 37705 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 37706 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 37707 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 37708 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 37709 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 37710 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 37711 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 37712 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 37713 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 37714 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 37715 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 37716 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 37717 | #define BIF_CFG_DEV0_EPF0_VF13_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 37718 | //BIF_CFG_DEV0_EPF0_VF13_STATUS |
|---|
| 37719 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 37720 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 37721 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 37722 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 37723 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 37724 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 37725 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 37726 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 37727 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 37728 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 37729 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 37730 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 37731 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 37732 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 37733 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 37734 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 37735 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 37736 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 37737 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 37738 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 37739 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 37740 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 37741 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 37742 | #define BIF_CFG_DEV0_EPF0_VF13_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 37743 | //BIF_CFG_DEV0_EPF0_VF13_REVISION_ID |
|---|
| 37744 | #define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 37745 | #define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 37746 | #define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 37747 | #define BIF_CFG_DEV0_EPF0_VF13_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 37748 | //BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE |
|---|
| 37749 | #define BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 37750 | #define BIF_CFG_DEV0_EPF0_VF13_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 37751 | //BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS |
|---|
| 37752 | #define BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 37753 | #define BIF_CFG_DEV0_EPF0_VF13_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 37754 | //BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS |
|---|
| 37755 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 37756 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 37757 | //BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE |
|---|
| 37758 | #define BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 37759 | #define BIF_CFG_DEV0_EPF0_VF13_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 37760 | //BIF_CFG_DEV0_EPF0_VF13_LATENCY |
|---|
| 37761 | #define BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 37762 | #define BIF_CFG_DEV0_EPF0_VF13_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 37763 | //BIF_CFG_DEV0_EPF0_VF13_HEADER |
|---|
| 37764 | #define 0x0 |
|---|
| 37765 | #define 0x7 |
|---|
| 37766 | #define 0x7FL |
|---|
| 37767 | #define 0x80L |
|---|
| 37768 | //BIF_CFG_DEV0_EPF0_VF13_BIST |
|---|
| 37769 | #define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 37770 | #define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 37771 | #define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 37772 | #define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 37773 | #define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_STRT_MASK 0x40L |
|---|
| 37774 | #define BIF_CFG_DEV0_EPF0_VF13_BIST__BIST_CAP_MASK 0x80L |
|---|
| 37775 | //BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1 |
|---|
| 37776 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 37777 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37778 | //BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2 |
|---|
| 37779 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 37780 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37781 | //BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3 |
|---|
| 37782 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 37783 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37784 | //BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4 |
|---|
| 37785 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 37786 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37787 | //BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5 |
|---|
| 37788 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 37789 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37790 | //BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6 |
|---|
| 37791 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 37792 | #define BIF_CFG_DEV0_EPF0_VF13_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37793 | //BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR |
|---|
| 37794 | #define BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 37795 | #define BIF_CFG_DEV0_EPF0_VF13_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 37796 | //BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID |
|---|
| 37797 | #define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 37798 | #define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 37799 | #define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 37800 | #define BIF_CFG_DEV0_EPF0_VF13_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 37801 | //BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR |
|---|
| 37802 | #define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 37803 | #define BIF_CFG_DEV0_EPF0_VF13_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 37804 | //BIF_CFG_DEV0_EPF0_VF13_CAP_PTR |
|---|
| 37805 | #define BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 37806 | #define BIF_CFG_DEV0_EPF0_VF13_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 37807 | //BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE |
|---|
| 37808 | #define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 37809 | #define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 37810 | //BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN |
|---|
| 37811 | #define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 37812 | #define BIF_CFG_DEV0_EPF0_VF13_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 37813 | //BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT |
|---|
| 37814 | #define BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 37815 | #define BIF_CFG_DEV0_EPF0_VF13_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 37816 | //BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY |
|---|
| 37817 | #define BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 37818 | #define BIF_CFG_DEV0_EPF0_VF13_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 37819 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST |
|---|
| 37820 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 37821 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 37822 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 37823 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 37824 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP |
|---|
| 37825 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 37826 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 37827 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 37828 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 37829 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 37830 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 37831 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 37832 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 37833 | //BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP |
|---|
| 37834 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 37835 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 37836 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 37837 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 37838 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 37839 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 37840 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 37841 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 37842 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 37843 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 37844 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 37845 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 37846 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 37847 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 37848 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 37849 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 37850 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 37851 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 37852 | //BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL |
|---|
| 37853 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 37854 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 37855 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 37856 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 37857 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 37858 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 37859 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 37860 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 37861 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 37862 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 37863 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 37864 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 37865 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 37866 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 37867 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 37868 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 37869 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 37870 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 37871 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 37872 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 37873 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 37874 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 37875 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 37876 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 37877 | //BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS |
|---|
| 37878 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 37879 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 37880 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 37881 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 37882 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 37883 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 37884 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 37885 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 37886 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 37887 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 37888 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 37889 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 37890 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 37891 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 37892 | //BIF_CFG_DEV0_EPF0_VF13_LINK_CAP |
|---|
| 37893 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 37894 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 37895 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 37896 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 37897 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 37898 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 37899 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 37900 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 37901 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 37902 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 37903 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 37904 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 37905 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 37906 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 37907 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 37908 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 37909 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 37910 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 37911 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 37912 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 37913 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 37914 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 37915 | //BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL |
|---|
| 37916 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 37917 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 37918 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 37919 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 37920 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 37921 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 37922 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 37923 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 37924 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 37925 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 37926 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 37927 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 37928 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 37929 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 37930 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 37931 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 37932 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 37933 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 37934 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 37935 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 37936 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 37937 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 37938 | //BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS |
|---|
| 37939 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 37940 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 37941 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 37942 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 37943 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 37944 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 37945 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 37946 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 37947 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 37948 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 37949 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 37950 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 37951 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 37952 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 37953 | //BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2 |
|---|
| 37954 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 37955 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 37956 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 37957 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 37958 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 37959 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 37960 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 37961 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 37962 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 37963 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 37964 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 37965 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 37966 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 37967 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 37968 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 37969 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 37970 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 37971 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 37972 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 37973 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 37974 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 37975 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 37976 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 37977 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 37978 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 37979 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 37980 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 37981 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 37982 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 37983 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 37984 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 37985 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 37986 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 37987 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 37988 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 37989 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 37990 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 37991 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 37992 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 37993 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 37994 | //BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2 |
|---|
| 37995 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 37996 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 37997 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 37998 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 37999 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 38000 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 38001 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 38002 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 38003 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 38004 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 38005 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 38006 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 38007 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 38008 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 38009 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 38010 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 38011 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 38012 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 38013 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 38014 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 38015 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 38016 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 38017 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 38018 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 38019 | //BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2 |
|---|
| 38020 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 38021 | #define BIF_CFG_DEV0_EPF0_VF13_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 38022 | //BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2 |
|---|
| 38023 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 38024 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 38025 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 38026 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 38027 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 38028 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 38029 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 38030 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 38031 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 38032 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 38033 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 38034 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 38035 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 38036 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 38037 | //BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2 |
|---|
| 38038 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 38039 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 38040 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 38041 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 38042 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 38043 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 38044 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 38045 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 38046 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 38047 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 38048 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 38049 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 38050 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 38051 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 38052 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 38053 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 38054 | //BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2 |
|---|
| 38055 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 38056 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 38057 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 38058 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 38059 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 38060 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 38061 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 38062 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 38063 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 38064 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 38065 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 38066 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 38067 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 38068 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 38069 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 38070 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 38071 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 38072 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 38073 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 38074 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 38075 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 38076 | #define BIF_CFG_DEV0_EPF0_VF13_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 38077 | //BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST |
|---|
| 38078 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38079 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 38080 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 38081 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 38082 | //BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL |
|---|
| 38083 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 38084 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 38085 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 38086 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 38087 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 38088 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 38089 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 38090 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 38091 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 38092 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 38093 | //BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO |
|---|
| 38094 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 38095 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 38096 | //BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI |
|---|
| 38097 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 38098 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 38099 | //BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA |
|---|
| 38100 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 38101 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 38102 | //BIF_CFG_DEV0_EPF0_VF13_MSI_MASK |
|---|
| 38103 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 38104 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 38105 | //BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64 |
|---|
| 38106 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 38107 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 38108 | //BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64 |
|---|
| 38109 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 38110 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 38111 | //BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING |
|---|
| 38112 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 38113 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 38114 | //BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64 |
|---|
| 38115 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 38116 | #define BIF_CFG_DEV0_EPF0_VF13_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 38117 | //BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST |
|---|
| 38118 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38119 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 38120 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 38121 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 38122 | //BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL |
|---|
| 38123 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 38124 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 38125 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 38126 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 38127 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 38128 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 38129 | //BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE |
|---|
| 38130 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 38131 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 38132 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 38133 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 38134 | //BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA |
|---|
| 38135 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 38136 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 38137 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 38138 | #define BIF_CFG_DEV0_EPF0_VF13_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 38139 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 38140 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38141 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 38142 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 38143 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 38144 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 38145 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 38146 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 38147 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 38148 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 38149 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 38150 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 38151 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 38152 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 38153 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1 |
|---|
| 38154 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 38155 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 38156 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2 |
|---|
| 38157 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 38158 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 38159 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 38160 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38161 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 38162 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 38163 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 38164 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 38165 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 38166 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS |
|---|
| 38167 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 38168 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 38169 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 38170 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 38171 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 38172 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 38173 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 38174 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 38175 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 38176 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 38177 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 38178 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 38179 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 38180 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 38181 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 38182 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 38183 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 38184 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 38185 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 38186 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 38187 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 38188 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 38189 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 38190 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 38191 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 38192 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 38193 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 38194 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 38195 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 38196 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 38197 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 38198 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 38199 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK |
|---|
| 38200 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 38201 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 38202 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 38203 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 38204 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 38205 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 38206 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 38207 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 38208 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 38209 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 38210 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 38211 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 38212 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 38213 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 38214 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 38215 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 38216 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 38217 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 38218 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 38219 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 38220 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 38221 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 38222 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 38223 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 38224 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 38225 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 38226 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 38227 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 38228 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 38229 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 38230 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 38231 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 38232 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 38233 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 38234 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 38235 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 38236 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 38237 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 38238 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 38239 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 38240 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 38241 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 38242 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 38243 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 38244 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 38245 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 38246 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 38247 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 38248 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 38249 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 38250 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 38251 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 38252 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 38253 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 38254 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 38255 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 38256 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 38257 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 38258 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 38259 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 38260 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 38261 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 38262 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 38263 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 38264 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 38265 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS |
|---|
| 38266 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 38267 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 38268 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 38269 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 38270 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 38271 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 38272 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 38273 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 38274 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 38275 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 38276 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 38277 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 38278 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 38279 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 38280 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 38281 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 38282 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK |
|---|
| 38283 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 38284 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 38285 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 38286 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 38287 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 38288 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 38289 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 38290 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 38291 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 38292 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 38293 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 38294 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 38295 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 38296 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 38297 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 38298 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 38299 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 38300 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 38301 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 38302 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 38303 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 38304 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 38305 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 38306 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 38307 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 38308 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 38309 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 38310 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 38311 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 38312 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 38313 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 38314 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 38315 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 38316 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 38317 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 38318 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0 |
|---|
| 38319 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 38320 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 38321 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1 |
|---|
| 38322 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 38323 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 38324 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2 |
|---|
| 38325 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 38326 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 38327 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3 |
|---|
| 38328 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 38329 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 38330 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0 |
|---|
| 38331 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 38332 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 38333 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1 |
|---|
| 38334 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 38335 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 38336 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2 |
|---|
| 38337 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 38338 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 38339 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3 |
|---|
| 38340 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 38341 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 38342 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST |
|---|
| 38343 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38344 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 38345 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 38346 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 38347 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 38348 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 38349 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP |
|---|
| 38350 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 38351 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 38352 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 38353 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 38354 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 38355 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 38356 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL |
|---|
| 38357 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 38358 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 38359 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 38360 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 38361 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST |
|---|
| 38362 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38363 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 38364 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 38365 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 38366 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 38367 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 38368 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP |
|---|
| 38369 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 38370 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 38371 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 38372 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 38373 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 38374 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 38375 | //BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL |
|---|
| 38376 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 38377 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 38378 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 38379 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 38380 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 38381 | #define BIF_CFG_DEV0_EPF0_VF13_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 38382 | |
|---|
| 38383 | |
|---|
| 38384 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp |
|---|
| 38385 | //BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID |
|---|
| 38386 | #define BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 38387 | #define BIF_CFG_DEV0_EPF0_VF14_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 38388 | //BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID |
|---|
| 38389 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 38390 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 38391 | //BIF_CFG_DEV0_EPF0_VF14_COMMAND |
|---|
| 38392 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 38393 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 38394 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 38395 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 38396 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 38397 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 38398 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 38399 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 38400 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 38401 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 38402 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 38403 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 38404 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 38405 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 38406 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 38407 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 38408 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 38409 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 38410 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 38411 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 38412 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 38413 | #define BIF_CFG_DEV0_EPF0_VF14_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 38414 | //BIF_CFG_DEV0_EPF0_VF14_STATUS |
|---|
| 38415 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 38416 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 38417 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 38418 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 38419 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 38420 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 38421 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 38422 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 38423 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 38424 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 38425 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 38426 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 38427 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 38428 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 38429 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 38430 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 38431 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 38432 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 38433 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 38434 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 38435 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 38436 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 38437 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 38438 | #define BIF_CFG_DEV0_EPF0_VF14_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 38439 | //BIF_CFG_DEV0_EPF0_VF14_REVISION_ID |
|---|
| 38440 | #define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 38441 | #define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 38442 | #define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 38443 | #define BIF_CFG_DEV0_EPF0_VF14_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 38444 | //BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE |
|---|
| 38445 | #define BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 38446 | #define BIF_CFG_DEV0_EPF0_VF14_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 38447 | //BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS |
|---|
| 38448 | #define BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 38449 | #define BIF_CFG_DEV0_EPF0_VF14_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 38450 | //BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS |
|---|
| 38451 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 38452 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 38453 | //BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE |
|---|
| 38454 | #define BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 38455 | #define BIF_CFG_DEV0_EPF0_VF14_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 38456 | //BIF_CFG_DEV0_EPF0_VF14_LATENCY |
|---|
| 38457 | #define BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 38458 | #define BIF_CFG_DEV0_EPF0_VF14_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 38459 | //BIF_CFG_DEV0_EPF0_VF14_HEADER |
|---|
| 38460 | #define 0x0 |
|---|
| 38461 | #define 0x7 |
|---|
| 38462 | #define 0x7FL |
|---|
| 38463 | #define 0x80L |
|---|
| 38464 | //BIF_CFG_DEV0_EPF0_VF14_BIST |
|---|
| 38465 | #define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 38466 | #define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 38467 | #define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 38468 | #define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 38469 | #define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_STRT_MASK 0x40L |
|---|
| 38470 | #define BIF_CFG_DEV0_EPF0_VF14_BIST__BIST_CAP_MASK 0x80L |
|---|
| 38471 | //BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1 |
|---|
| 38472 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 38473 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 38474 | //BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2 |
|---|
| 38475 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 38476 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 38477 | //BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3 |
|---|
| 38478 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 38479 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 38480 | //BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4 |
|---|
| 38481 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 38482 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 38483 | //BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5 |
|---|
| 38484 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 38485 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 38486 | //BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6 |
|---|
| 38487 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 38488 | #define BIF_CFG_DEV0_EPF0_VF14_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 38489 | //BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR |
|---|
| 38490 | #define BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 38491 | #define BIF_CFG_DEV0_EPF0_VF14_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 38492 | //BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID |
|---|
| 38493 | #define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 38494 | #define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 38495 | #define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 38496 | #define BIF_CFG_DEV0_EPF0_VF14_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 38497 | //BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR |
|---|
| 38498 | #define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 38499 | #define BIF_CFG_DEV0_EPF0_VF14_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 38500 | //BIF_CFG_DEV0_EPF0_VF14_CAP_PTR |
|---|
| 38501 | #define BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 38502 | #define BIF_CFG_DEV0_EPF0_VF14_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 38503 | //BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE |
|---|
| 38504 | #define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 38505 | #define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 38506 | //BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN |
|---|
| 38507 | #define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 38508 | #define BIF_CFG_DEV0_EPF0_VF14_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 38509 | //BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT |
|---|
| 38510 | #define BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 38511 | #define BIF_CFG_DEV0_EPF0_VF14_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 38512 | //BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY |
|---|
| 38513 | #define BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 38514 | #define BIF_CFG_DEV0_EPF0_VF14_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 38515 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST |
|---|
| 38516 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38517 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 38518 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 38519 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 38520 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP |
|---|
| 38521 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 38522 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 38523 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 38524 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 38525 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 38526 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 38527 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 38528 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 38529 | //BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP |
|---|
| 38530 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 38531 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 38532 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 38533 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 38534 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 38535 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 38536 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 38537 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 38538 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 38539 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 38540 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 38541 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 38542 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 38543 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 38544 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 38545 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 38546 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 38547 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 38548 | //BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL |
|---|
| 38549 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 38550 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 38551 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 38552 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 38553 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 38554 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 38555 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 38556 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 38557 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 38558 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 38559 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 38560 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 38561 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 38562 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 38563 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 38564 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 38565 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 38566 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 38567 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 38568 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 38569 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 38570 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 38571 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 38572 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 38573 | //BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS |
|---|
| 38574 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 38575 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 38576 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 38577 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 38578 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 38579 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 38580 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 38581 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 38582 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 38583 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 38584 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 38585 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 38586 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 38587 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 38588 | //BIF_CFG_DEV0_EPF0_VF14_LINK_CAP |
|---|
| 38589 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 38590 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 38591 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 38592 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 38593 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 38594 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 38595 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 38596 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 38597 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 38598 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 38599 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 38600 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 38601 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 38602 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 38603 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 38604 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 38605 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 38606 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 38607 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 38608 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 38609 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 38610 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 38611 | //BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL |
|---|
| 38612 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 38613 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 38614 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 38615 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 38616 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 38617 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 38618 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 38619 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 38620 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 38621 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 38622 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 38623 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 38624 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 38625 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 38626 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 38627 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 38628 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 38629 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 38630 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 38631 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 38632 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 38633 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 38634 | //BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS |
|---|
| 38635 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 38636 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 38637 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 38638 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 38639 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 38640 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 38641 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 38642 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 38643 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 38644 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 38645 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 38646 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 38647 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 38648 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 38649 | //BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2 |
|---|
| 38650 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 38651 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 38652 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 38653 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 38654 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 38655 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 38656 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 38657 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 38658 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 38659 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 38660 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 38661 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 38662 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 38663 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 38664 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 38665 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 38666 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 38667 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 38668 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 38669 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 38670 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 38671 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 38672 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 38673 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 38674 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 38675 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 38676 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 38677 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 38678 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 38679 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 38680 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 38681 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 38682 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 38683 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 38684 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 38685 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 38686 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 38687 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 38688 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 38689 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 38690 | //BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2 |
|---|
| 38691 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 38692 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 38693 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 38694 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 38695 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 38696 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 38697 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 38698 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 38699 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 38700 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 38701 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 38702 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 38703 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 38704 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 38705 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 38706 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 38707 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 38708 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 38709 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 38710 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 38711 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 38712 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 38713 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 38714 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 38715 | //BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2 |
|---|
| 38716 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 38717 | #define BIF_CFG_DEV0_EPF0_VF14_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 38718 | //BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2 |
|---|
| 38719 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 38720 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 38721 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 38722 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 38723 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 38724 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 38725 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 38726 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 38727 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 38728 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 38729 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 38730 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 38731 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 38732 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 38733 | //BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2 |
|---|
| 38734 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 38735 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 38736 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 38737 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 38738 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 38739 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 38740 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 38741 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 38742 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 38743 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 38744 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 38745 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 38746 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 38747 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 38748 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 38749 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 38750 | //BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2 |
|---|
| 38751 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 38752 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 38753 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 38754 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 38755 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 38756 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 38757 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 38758 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 38759 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 38760 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 38761 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 38762 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 38763 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 38764 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 38765 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 38766 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 38767 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 38768 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 38769 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 38770 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 38771 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 38772 | #define BIF_CFG_DEV0_EPF0_VF14_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 38773 | //BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST |
|---|
| 38774 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38775 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 38776 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 38777 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 38778 | //BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL |
|---|
| 38779 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 38780 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 38781 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 38782 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 38783 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 38784 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 38785 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 38786 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 38787 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 38788 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 38789 | //BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO |
|---|
| 38790 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 38791 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 38792 | //BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI |
|---|
| 38793 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 38794 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 38795 | //BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA |
|---|
| 38796 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 38797 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 38798 | //BIF_CFG_DEV0_EPF0_VF14_MSI_MASK |
|---|
| 38799 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 38800 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 38801 | //BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64 |
|---|
| 38802 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 38803 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 38804 | //BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64 |
|---|
| 38805 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 38806 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 38807 | //BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING |
|---|
| 38808 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 38809 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 38810 | //BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64 |
|---|
| 38811 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 38812 | #define BIF_CFG_DEV0_EPF0_VF14_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 38813 | //BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST |
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| 38814 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38815 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 38816 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 38817 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 38818 | //BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL |
|---|
| 38819 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 38820 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 38821 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 38822 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 38823 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 38824 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 38825 | //BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE |
|---|
| 38826 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 38827 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 38828 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
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| 38829 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
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| 38830 | //BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA |
|---|
| 38831 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 38832 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
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| 38833 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
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| 38834 | #define BIF_CFG_DEV0_EPF0_VF14_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 38835 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 38836 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38837 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 38838 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 38839 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 38840 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 38841 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 38842 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 38843 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 38844 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 38845 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 38846 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 38847 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 38848 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 38849 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1 |
|---|
| 38850 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 38851 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 38852 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2 |
|---|
| 38853 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 38854 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 38855 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 38856 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 38857 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 38858 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 38859 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 38860 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 38861 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 38862 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS |
|---|
| 38863 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 38864 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 38865 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 38866 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 38867 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 38868 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 38869 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 38870 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 38871 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 38872 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 38873 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 38874 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 38875 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 38876 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 38877 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 38878 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 38879 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 38880 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 38881 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 38882 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 38883 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 38884 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 38885 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 38886 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 38887 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 38888 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 38889 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 38890 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 38891 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 38892 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 38893 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 38894 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 38895 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK |
|---|
| 38896 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 38897 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 38898 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 38899 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 38900 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 38901 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 38902 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 38903 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 38904 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 38905 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 38906 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 38907 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 38908 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 38909 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 38910 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 38911 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 38912 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 38913 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 38914 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 38915 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 38916 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 38917 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 38918 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 38919 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 38920 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 38921 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 38922 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 38923 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 38924 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 38925 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 38926 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 38927 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 38928 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 38929 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 38930 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 38931 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 38932 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 38933 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 38934 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 38935 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 38936 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 38937 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 38938 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 38939 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 38940 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 38941 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 38942 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 38943 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 38944 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 38945 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 38946 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 38947 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 38948 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 38949 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 38950 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 38951 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 38952 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 38953 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 38954 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 38955 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 38956 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 38957 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 38958 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 38959 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 38960 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 38961 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS |
|---|
| 38962 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 38963 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 38964 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 38965 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 38966 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 38967 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 38968 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 38969 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 38970 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 38971 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 38972 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 38973 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 38974 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 38975 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 38976 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 38977 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 38978 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK |
|---|
| 38979 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 38980 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 38981 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 38982 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 38983 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 38984 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 38985 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 38986 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 38987 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 38988 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 38989 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 38990 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 38991 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 38992 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 38993 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 38994 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 38995 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 38996 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 38997 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 38998 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 38999 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 39000 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 39001 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 39002 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 39003 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 39004 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 39005 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 39006 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 39007 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 39008 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 39009 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 39010 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 39011 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 39012 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 39013 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 39014 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0 |
|---|
| 39015 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 39016 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 39017 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1 |
|---|
| 39018 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 39019 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 39020 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2 |
|---|
| 39021 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 39022 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 39023 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3 |
|---|
| 39024 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 39025 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 39026 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0 |
|---|
| 39027 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 39028 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 39029 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1 |
|---|
| 39030 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 39031 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 39032 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2 |
|---|
| 39033 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 39034 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 39035 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3 |
|---|
| 39036 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 39037 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 39038 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST |
|---|
| 39039 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 39040 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 39041 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 39042 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 39043 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 39044 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 39045 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP |
|---|
| 39046 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 39047 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 39048 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 39049 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 39050 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 39051 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 39052 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL |
|---|
| 39053 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 39054 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 39055 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 39056 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 39057 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST |
|---|
| 39058 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 39059 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 39060 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 39061 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 39062 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 39063 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 39064 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP |
|---|
| 39065 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 39066 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 39067 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 39068 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 39069 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 39070 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 39071 | //BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL |
|---|
| 39072 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 39073 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 39074 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 39075 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 39076 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 39077 | #define BIF_CFG_DEV0_EPF0_VF14_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 39078 | |
|---|
| 39079 | |
|---|
| 39080 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp |
|---|
| 39081 | //BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID |
|---|
| 39082 | #define BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 39083 | #define BIF_CFG_DEV0_EPF0_VF15_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 39084 | //BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID |
|---|
| 39085 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 39086 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 39087 | //BIF_CFG_DEV0_EPF0_VF15_COMMAND |
|---|
| 39088 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 39089 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 39090 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 39091 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 39092 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 39093 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 39094 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 39095 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 39096 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 39097 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 39098 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 39099 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 39100 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 39101 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 39102 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 39103 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 39104 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 39105 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 39106 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 39107 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 39108 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 39109 | #define BIF_CFG_DEV0_EPF0_VF15_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 39110 | //BIF_CFG_DEV0_EPF0_VF15_STATUS |
|---|
| 39111 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 39112 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 39113 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 39114 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 39115 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 39116 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 39117 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 39118 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 39119 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 39120 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 39121 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 39122 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 39123 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 39124 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 39125 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 39126 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 39127 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 39128 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 39129 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 39130 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 39131 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 39132 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 39133 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 39134 | #define BIF_CFG_DEV0_EPF0_VF15_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 39135 | //BIF_CFG_DEV0_EPF0_VF15_REVISION_ID |
|---|
| 39136 | #define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 39137 | #define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 39138 | #define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 39139 | #define BIF_CFG_DEV0_EPF0_VF15_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 39140 | //BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE |
|---|
| 39141 | #define BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 39142 | #define BIF_CFG_DEV0_EPF0_VF15_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 39143 | //BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS |
|---|
| 39144 | #define BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 39145 | #define BIF_CFG_DEV0_EPF0_VF15_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 39146 | //BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS |
|---|
| 39147 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 39148 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 39149 | //BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE |
|---|
| 39150 | #define BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 39151 | #define BIF_CFG_DEV0_EPF0_VF15_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 39152 | //BIF_CFG_DEV0_EPF0_VF15_LATENCY |
|---|
| 39153 | #define BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 39154 | #define BIF_CFG_DEV0_EPF0_VF15_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 39155 | //BIF_CFG_DEV0_EPF0_VF15_HEADER |
|---|
| 39156 | #define 0x0 |
|---|
| 39157 | #define 0x7 |
|---|
| 39158 | #define 0x7FL |
|---|
| 39159 | #define 0x80L |
|---|
| 39160 | //BIF_CFG_DEV0_EPF0_VF15_BIST |
|---|
| 39161 | #define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 39162 | #define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 39163 | #define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 39164 | #define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 39165 | #define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_STRT_MASK 0x40L |
|---|
| 39166 | #define BIF_CFG_DEV0_EPF0_VF15_BIST__BIST_CAP_MASK 0x80L |
|---|
| 39167 | //BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1 |
|---|
| 39168 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 39169 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39170 | //BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2 |
|---|
| 39171 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 39172 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39173 | //BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3 |
|---|
| 39174 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 39175 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39176 | //BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4 |
|---|
| 39177 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 39178 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39179 | //BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5 |
|---|
| 39180 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 39181 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39182 | //BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6 |
|---|
| 39183 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 39184 | #define BIF_CFG_DEV0_EPF0_VF15_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39185 | //BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR |
|---|
| 39186 | #define BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 39187 | #define BIF_CFG_DEV0_EPF0_VF15_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 39188 | //BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID |
|---|
| 39189 | #define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 39190 | #define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 39191 | #define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 39192 | #define BIF_CFG_DEV0_EPF0_VF15_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 39193 | //BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR |
|---|
| 39194 | #define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 39195 | #define BIF_CFG_DEV0_EPF0_VF15_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39196 | //BIF_CFG_DEV0_EPF0_VF15_CAP_PTR |
|---|
| 39197 | #define BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 39198 | #define BIF_CFG_DEV0_EPF0_VF15_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 39199 | //BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE |
|---|
| 39200 | #define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 39201 | #define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 39202 | //BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN |
|---|
| 39203 | #define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 39204 | #define BIF_CFG_DEV0_EPF0_VF15_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 39205 | //BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT |
|---|
| 39206 | #define BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 39207 | #define BIF_CFG_DEV0_EPF0_VF15_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 39208 | //BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY |
|---|
| 39209 | #define BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 39210 | #define BIF_CFG_DEV0_EPF0_VF15_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 39211 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST |
|---|
| 39212 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 39213 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 39214 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 39215 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 39216 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP |
|---|
| 39217 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 39218 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 39219 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 39220 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 39221 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 39222 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 39223 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 39224 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 39225 | //BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP |
|---|
| 39226 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 39227 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 39228 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 39229 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 39230 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 39231 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 39232 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 39233 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 39234 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 39235 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 39236 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 39237 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 39238 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 39239 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 39240 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 39241 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 39242 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 39243 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 39244 | //BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL |
|---|
| 39245 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 39246 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 39247 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 39248 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 39249 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 39250 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 39251 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 39252 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 39253 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 39254 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 39255 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 39256 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 39257 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 39258 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 39259 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 39260 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 39261 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 39262 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 39263 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 39264 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 39265 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 39266 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 39267 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 39268 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 39269 | //BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS |
|---|
| 39270 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 39271 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 39272 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 39273 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 39274 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 39275 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 39276 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 39277 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 39278 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 39279 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 39280 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 39281 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 39282 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 39283 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 39284 | //BIF_CFG_DEV0_EPF0_VF15_LINK_CAP |
|---|
| 39285 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 39286 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 39287 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 39288 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 39289 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 39290 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 39291 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 39292 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 39293 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 39294 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 39295 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 39296 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 39297 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 39298 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 39299 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 39300 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 39301 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 39302 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 39303 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 39304 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 39305 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 39306 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 39307 | //BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL |
|---|
| 39308 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 39309 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 39310 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 39311 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 39312 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 39313 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 39314 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 39315 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 39316 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 39317 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 39318 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 39319 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 39320 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 39321 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 39322 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 39323 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 39324 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 39325 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 39326 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 39327 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 39328 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 39329 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 39330 | //BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS |
|---|
| 39331 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 39332 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 39333 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 39334 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 39335 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 39336 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 39337 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 39338 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 39339 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 39340 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 39341 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 39342 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 39343 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 39344 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 39345 | //BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2 |
|---|
| 39346 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 39347 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 39348 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 39349 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 39350 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 39351 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 39352 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 39353 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 39354 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 39355 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 39356 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 39357 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 39358 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 39359 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 39360 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 39361 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 39362 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 39363 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 39364 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 39365 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 39366 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 39367 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 39368 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 39369 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 39370 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 39371 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 39372 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 39373 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 39374 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 39375 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 39376 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 39377 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 39378 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 39379 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 39380 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 39381 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 39382 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 39383 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 39384 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 39385 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 39386 | //BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2 |
|---|
| 39387 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 39388 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 39389 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 39390 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 39391 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 39392 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 39393 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 39394 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 39395 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 39396 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 39397 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 39398 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 39399 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 39400 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 39401 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 39402 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 39403 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 39404 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 39405 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 39406 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 39407 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 39408 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 39409 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 39410 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 39411 | //BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2 |
|---|
| 39412 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 39413 | #define BIF_CFG_DEV0_EPF0_VF15_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 39414 | //BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2 |
|---|
| 39415 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 39416 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 39417 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 39418 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 39419 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 39420 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 39421 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 39422 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 39423 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 39424 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 39425 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 39426 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 39427 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 39428 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 39429 | //BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2 |
|---|
| 39430 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 39431 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 39432 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 39433 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 39434 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 39435 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 39436 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 39437 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 39438 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 39439 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 39440 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 39441 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 39442 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 39443 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 39444 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 39445 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 39446 | //BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2 |
|---|
| 39447 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 39448 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 39449 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 39450 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 39451 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 39452 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 39453 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 39454 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 39455 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 39456 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 39457 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 39458 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 39459 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 39460 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 39461 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 39462 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 39463 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 39464 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 39465 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 39466 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 39467 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 39468 | #define BIF_CFG_DEV0_EPF0_VF15_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 39469 | //BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST |
|---|
| 39470 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 39471 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 39472 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 39473 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 39474 | //BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL |
|---|
| 39475 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 39476 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 39477 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 39478 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 39479 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 39480 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 39481 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 39482 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 39483 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 39484 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 39485 | //BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO |
|---|
| 39486 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 39487 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 39488 | //BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI |
|---|
| 39489 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 39490 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 39491 | //BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA |
|---|
| 39492 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 39493 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 39494 | //BIF_CFG_DEV0_EPF0_VF15_MSI_MASK |
|---|
| 39495 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 39496 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 39497 | //BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64 |
|---|
| 39498 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 39499 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 39500 | //BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64 |
|---|
| 39501 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 39502 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 39503 | //BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING |
|---|
| 39504 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 39505 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 39506 | //BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64 |
|---|
| 39507 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 39508 | #define BIF_CFG_DEV0_EPF0_VF15_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 39509 | //BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST |
|---|
| 39510 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 39511 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 39512 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 39513 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 39514 | //BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL |
|---|
| 39515 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 39516 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 39517 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 39518 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 39519 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 39520 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 39521 | //BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE |
|---|
| 39522 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 39523 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 39524 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 39525 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 39526 | //BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA |
|---|
| 39527 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 39528 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 39529 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 39530 | #define BIF_CFG_DEV0_EPF0_VF15_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 39531 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 39532 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 39533 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 39534 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 39535 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 39536 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 39537 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 39538 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 39539 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 39540 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 39541 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 39542 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 39543 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 39544 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 39545 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1 |
|---|
| 39546 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 39547 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 39548 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2 |
|---|
| 39549 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 39550 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 39551 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 39552 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 39553 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 39554 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 39555 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 39556 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 39557 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 39558 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS |
|---|
| 39559 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 39560 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 39561 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 39562 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 39563 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 39564 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 39565 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 39566 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 39567 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 39568 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 39569 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 39570 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 39571 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 39572 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 39573 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 39574 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 39575 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 39576 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 39577 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 39578 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 39579 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 39580 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 39581 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 39582 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 39583 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 39584 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 39585 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 39586 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 39587 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 39588 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 39589 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 39590 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 39591 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK |
|---|
| 39592 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 39593 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 39594 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 39595 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 39596 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 39597 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 39598 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 39599 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 39600 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 39601 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 39602 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 39603 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 39604 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 39605 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 39606 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 39607 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 39608 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 39609 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 39610 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 39611 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 39612 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 39613 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 39614 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 39615 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 39616 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 39617 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 39618 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 39619 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 39620 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 39621 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 39622 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 39623 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 39624 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 39625 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 39626 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 39627 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 39628 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 39629 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 39630 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 39631 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 39632 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 39633 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 39634 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 39635 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 39636 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 39637 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 39638 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 39639 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 39640 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 39641 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 39642 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 39643 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 39644 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 39645 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 39646 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 39647 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 39648 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 39649 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 39650 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 39651 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 39652 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 39653 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 39654 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 39655 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 39656 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 39657 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS |
|---|
| 39658 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 39659 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 39660 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 39661 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 39662 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 39663 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 39664 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 39665 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 39666 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 39667 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 39668 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 39669 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 39670 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 39671 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 39672 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 39673 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 39674 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK |
|---|
| 39675 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 39676 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 39677 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 39678 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 39679 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 39680 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 39681 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 39682 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 39683 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 39684 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 39685 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 39686 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 39687 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 39688 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 39689 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 39690 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 39691 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 39692 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 39693 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 39694 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 39695 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 39696 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 39697 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 39698 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 39699 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 39700 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 39701 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 39702 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 39703 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 39704 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 39705 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 39706 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 39707 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 39708 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 39709 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 39710 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0 |
|---|
| 39711 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 39712 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 39713 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1 |
|---|
| 39714 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 39715 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 39716 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2 |
|---|
| 39717 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 39718 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 39719 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3 |
|---|
| 39720 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 39721 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 39722 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0 |
|---|
| 39723 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 39724 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 39725 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1 |
|---|
| 39726 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 39727 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 39728 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2 |
|---|
| 39729 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 39730 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 39731 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3 |
|---|
| 39732 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 39733 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 39734 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST |
|---|
| 39735 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 39736 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 39737 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 39738 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 39739 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 39740 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 39741 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP |
|---|
| 39742 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 39743 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 39744 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 39745 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 39746 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 39747 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 39748 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL |
|---|
| 39749 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 39750 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 39751 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 39752 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 39753 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST |
|---|
| 39754 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 39755 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 39756 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 39757 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 39758 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 39759 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 39760 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP |
|---|
| 39761 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 39762 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 39763 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 39764 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 39765 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 39766 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 39767 | //BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL |
|---|
| 39768 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 39769 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 39770 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 39771 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 39772 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 39773 | #define BIF_CFG_DEV0_EPF0_VF15_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 39774 | |
|---|
| 39775 | |
|---|
| 39776 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp |
|---|
| 39777 | //BIF_CFG_DEV0_EPF0_VF16_VENDOR_ID |
|---|
| 39778 | #define BIF_CFG_DEV0_EPF0_VF16_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 39779 | #define BIF_CFG_DEV0_EPF0_VF16_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 39780 | //BIF_CFG_DEV0_EPF0_VF16_DEVICE_ID |
|---|
| 39781 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 39782 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 39783 | //BIF_CFG_DEV0_EPF0_VF16_COMMAND |
|---|
| 39784 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 39785 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 39786 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 39787 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 39788 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 39789 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 39790 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 39791 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 39792 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 39793 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 39794 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 39795 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 39796 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 39797 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 39798 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 39799 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 39800 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 39801 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 39802 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 39803 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 39804 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 39805 | #define BIF_CFG_DEV0_EPF0_VF16_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 39806 | //BIF_CFG_DEV0_EPF0_VF16_STATUS |
|---|
| 39807 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 39808 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 39809 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 39810 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 39811 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 39812 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 39813 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 39814 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 39815 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 39816 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 39817 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 39818 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 39819 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 39820 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 39821 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 39822 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 39823 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 39824 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 39825 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 39826 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 39827 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 39828 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 39829 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 39830 | #define BIF_CFG_DEV0_EPF0_VF16_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 39831 | //BIF_CFG_DEV0_EPF0_VF16_REVISION_ID |
|---|
| 39832 | #define BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 39833 | #define BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 39834 | #define BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 39835 | #define BIF_CFG_DEV0_EPF0_VF16_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 39836 | //BIF_CFG_DEV0_EPF0_VF16_PROG_INTERFACE |
|---|
| 39837 | #define BIF_CFG_DEV0_EPF0_VF16_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 39838 | #define BIF_CFG_DEV0_EPF0_VF16_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 39839 | //BIF_CFG_DEV0_EPF0_VF16_SUB_CLASS |
|---|
| 39840 | #define BIF_CFG_DEV0_EPF0_VF16_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 39841 | #define BIF_CFG_DEV0_EPF0_VF16_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 39842 | //BIF_CFG_DEV0_EPF0_VF16_BASE_CLASS |
|---|
| 39843 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 39844 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 39845 | //BIF_CFG_DEV0_EPF0_VF16_CACHE_LINE |
|---|
| 39846 | #define BIF_CFG_DEV0_EPF0_VF16_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 39847 | #define BIF_CFG_DEV0_EPF0_VF16_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 39848 | //BIF_CFG_DEV0_EPF0_VF16_LATENCY |
|---|
| 39849 | #define BIF_CFG_DEV0_EPF0_VF16_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 39850 | #define BIF_CFG_DEV0_EPF0_VF16_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 39851 | //BIF_CFG_DEV0_EPF0_VF16_HEADER |
|---|
| 39852 | #define 0x0 |
|---|
| 39853 | #define 0x7 |
|---|
| 39854 | #define 0x7FL |
|---|
| 39855 | #define 0x80L |
|---|
| 39856 | //BIF_CFG_DEV0_EPF0_VF16_BIST |
|---|
| 39857 | #define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 39858 | #define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 39859 | #define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 39860 | #define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 39861 | #define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_STRT_MASK 0x40L |
|---|
| 39862 | #define BIF_CFG_DEV0_EPF0_VF16_BIST__BIST_CAP_MASK 0x80L |
|---|
| 39863 | //BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_1 |
|---|
| 39864 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 39865 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39866 | //BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_2 |
|---|
| 39867 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 39868 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39869 | //BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_3 |
|---|
| 39870 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 39871 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39872 | //BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_4 |
|---|
| 39873 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 39874 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39875 | //BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_5 |
|---|
| 39876 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 39877 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39878 | //BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_6 |
|---|
| 39879 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 39880 | #define BIF_CFG_DEV0_EPF0_VF16_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39881 | //BIF_CFG_DEV0_EPF0_VF16_CARDBUS_CIS_PTR |
|---|
| 39882 | #define BIF_CFG_DEV0_EPF0_VF16_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 39883 | #define BIF_CFG_DEV0_EPF0_VF16_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 39884 | //BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID |
|---|
| 39885 | #define BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 39886 | #define BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 39887 | #define BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 39888 | #define BIF_CFG_DEV0_EPF0_VF16_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 39889 | //BIF_CFG_DEV0_EPF0_VF16_ROM_BASE_ADDR |
|---|
| 39890 | #define BIF_CFG_DEV0_EPF0_VF16_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 39891 | #define BIF_CFG_DEV0_EPF0_VF16_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 39892 | //BIF_CFG_DEV0_EPF0_VF16_CAP_PTR |
|---|
| 39893 | #define BIF_CFG_DEV0_EPF0_VF16_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 39894 | #define BIF_CFG_DEV0_EPF0_VF16_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 39895 | //BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_LINE |
|---|
| 39896 | #define BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 39897 | #define BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 39898 | //BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_PIN |
|---|
| 39899 | #define BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 39900 | #define BIF_CFG_DEV0_EPF0_VF16_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 39901 | //BIF_CFG_DEV0_EPF0_VF16_MIN_GRANT |
|---|
| 39902 | #define BIF_CFG_DEV0_EPF0_VF16_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 39903 | #define BIF_CFG_DEV0_EPF0_VF16_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 39904 | //BIF_CFG_DEV0_EPF0_VF16_MAX_LATENCY |
|---|
| 39905 | #define BIF_CFG_DEV0_EPF0_VF16_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 39906 | #define BIF_CFG_DEV0_EPF0_VF16_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 39907 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST |
|---|
| 39908 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 39909 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 39910 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 39911 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 39912 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP |
|---|
| 39913 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 39914 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 39915 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 39916 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 39917 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 39918 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 39919 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 39920 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 39921 | //BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP |
|---|
| 39922 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 39923 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 39924 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 39925 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 39926 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 39927 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 39928 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 39929 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 39930 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 39931 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 39932 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 39933 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 39934 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 39935 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 39936 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 39937 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 39938 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 39939 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 39940 | //BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL |
|---|
| 39941 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 39942 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 39943 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 39944 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 39945 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 39946 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 39947 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 39948 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 39949 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 39950 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 39951 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 39952 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 39953 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 39954 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 39955 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 39956 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 39957 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 39958 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 39959 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 39960 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 39961 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 39962 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 39963 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 39964 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 39965 | //BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS |
|---|
| 39966 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 39967 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 39968 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 39969 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 39970 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 39971 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 39972 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 39973 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 39974 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 39975 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 39976 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 39977 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 39978 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 39979 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 39980 | //BIF_CFG_DEV0_EPF0_VF16_LINK_CAP |
|---|
| 39981 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 39982 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 39983 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 39984 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 39985 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 39986 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 39987 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 39988 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 39989 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 39990 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 39991 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 39992 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 39993 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 39994 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 39995 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 39996 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 39997 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 39998 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 39999 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 40000 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 40001 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 40002 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 40003 | //BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL |
|---|
| 40004 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 40005 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 40006 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 40007 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 40008 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 40009 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 40010 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 40011 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 40012 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 40013 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 40014 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 40015 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 40016 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 40017 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 40018 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 40019 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 40020 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 40021 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 40022 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 40023 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 40024 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 40025 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 40026 | //BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS |
|---|
| 40027 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 40028 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 40029 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 40030 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 40031 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 40032 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 40033 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 40034 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 40035 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 40036 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 40037 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 40038 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 40039 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 40040 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 40041 | //BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2 |
|---|
| 40042 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 40043 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 40044 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 40045 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 40046 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 40047 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 40048 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 40049 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 40050 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 40051 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 40052 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 40053 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 40054 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 40055 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 40056 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 40057 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 40058 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 40059 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 40060 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 40061 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 40062 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 40063 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 40064 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 40065 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 40066 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 40067 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 40068 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 40069 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 40070 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 40071 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 40072 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 40073 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 40074 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 40075 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 40076 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 40077 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 40078 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 40079 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 40080 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 40081 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 40082 | //BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2 |
|---|
| 40083 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 40084 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 40085 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 40086 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 40087 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 40088 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 40089 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 40090 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 40091 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 40092 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 40093 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 40094 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 40095 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 40096 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 40097 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 40098 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 40099 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 40100 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 40101 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 40102 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 40103 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 40104 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 40105 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 40106 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 40107 | //BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS2 |
|---|
| 40108 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 40109 | #define BIF_CFG_DEV0_EPF0_VF16_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 40110 | //BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2 |
|---|
| 40111 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 40112 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 40113 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 40114 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 40115 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 40116 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 40117 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 40118 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 40119 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 40120 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 40121 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 40122 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 40123 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 40124 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 40125 | //BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2 |
|---|
| 40126 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 40127 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 40128 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 40129 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 40130 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 40131 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 40132 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 40133 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 40134 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 40135 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 40136 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 40137 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 40138 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 40139 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 40140 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 40141 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 40142 | //BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2 |
|---|
| 40143 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 40144 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 40145 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 40146 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 40147 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 40148 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 40149 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 40150 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 40151 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 40152 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 40153 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 40154 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 40155 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 40156 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 40157 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 40158 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 40159 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 40160 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 40161 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 40162 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 40163 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 40164 | #define BIF_CFG_DEV0_EPF0_VF16_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 40165 | //BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST |
|---|
| 40166 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40167 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 40168 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 40169 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 40170 | //BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL |
|---|
| 40171 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 40172 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 40173 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 40174 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 40175 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 40176 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 40177 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 40178 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 40179 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 40180 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 40181 | //BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_LO |
|---|
| 40182 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 40183 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 40184 | //BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_HI |
|---|
| 40185 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 40186 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 40187 | //BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA |
|---|
| 40188 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 40189 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 40190 | //BIF_CFG_DEV0_EPF0_VF16_MSI_MASK |
|---|
| 40191 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 40192 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 40193 | //BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_64 |
|---|
| 40194 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 40195 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 40196 | //BIF_CFG_DEV0_EPF0_VF16_MSI_MASK_64 |
|---|
| 40197 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 40198 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 40199 | //BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING |
|---|
| 40200 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 40201 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 40202 | //BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_64 |
|---|
| 40203 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 40204 | #define BIF_CFG_DEV0_EPF0_VF16_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 40205 | //BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST |
|---|
| 40206 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40207 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 40208 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 40209 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 40210 | //BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL |
|---|
| 40211 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 40212 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 40213 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 40214 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 40215 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 40216 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 40217 | //BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE |
|---|
| 40218 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 40219 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 40220 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 40221 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 40222 | //BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA |
|---|
| 40223 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 40224 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 40225 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 40226 | #define BIF_CFG_DEV0_EPF0_VF16_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 40227 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 40228 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40229 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 40230 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 40231 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 40232 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 40233 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 40234 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 40235 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 40236 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 40237 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 40238 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 40239 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 40240 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 40241 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC1 |
|---|
| 40242 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 40243 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 40244 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC2 |
|---|
| 40245 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 40246 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 40247 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 40248 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40249 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 40250 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 40251 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 40252 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 40253 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 40254 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS |
|---|
| 40255 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 40256 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 40257 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 40258 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 40259 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 40260 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 40261 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 40262 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 40263 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 40264 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 40265 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 40266 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 40267 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 40268 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 40269 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 40270 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 40271 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 40272 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 40273 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 40274 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 40275 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 40276 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 40277 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 40278 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 40279 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 40280 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 40281 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 40282 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 40283 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 40284 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 40285 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 40286 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 40287 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK |
|---|
| 40288 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 40289 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 40290 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 40291 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 40292 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 40293 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 40294 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 40295 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 40296 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 40297 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 40298 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 40299 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 40300 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 40301 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 40302 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 40303 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 40304 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 40305 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 40306 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 40307 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 40308 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 40309 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 40310 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 40311 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 40312 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 40313 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 40314 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 40315 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 40316 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 40317 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 40318 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 40319 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 40320 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 40321 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 40322 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 40323 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 40324 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 40325 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 40326 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 40327 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 40328 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 40329 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 40330 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 40331 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 40332 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 40333 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 40334 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 40335 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 40336 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 40337 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 40338 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 40339 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 40340 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 40341 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 40342 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 40343 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 40344 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 40345 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 40346 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 40347 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 40348 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 40349 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 40350 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 40351 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 40352 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 40353 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS |
|---|
| 40354 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 40355 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 40356 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 40357 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 40358 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 40359 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 40360 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 40361 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 40362 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 40363 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 40364 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 40365 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 40366 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 40367 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 40368 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 40369 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 40370 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK |
|---|
| 40371 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 40372 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 40373 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 40374 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 40375 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 40376 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 40377 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 40378 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 40379 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 40380 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 40381 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 40382 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 40383 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 40384 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 40385 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 40386 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 40387 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 40388 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 40389 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 40390 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 40391 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 40392 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 40393 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 40394 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
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| 40395 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 40396 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 40397 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 40398 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 40399 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 40400 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 40401 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 40402 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 40403 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 40404 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 40405 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 40406 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG0 |
|---|
| 40407 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 40408 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 40409 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG1 |
|---|
| 40410 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 40411 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 40412 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG2 |
|---|
| 40413 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 40414 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 40415 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG3 |
|---|
| 40416 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 40417 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 40418 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG0 |
|---|
| 40419 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 40420 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 40421 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG1 |
|---|
| 40422 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 40423 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 40424 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG2 |
|---|
| 40425 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 40426 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 40427 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG3 |
|---|
| 40428 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 40429 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 40430 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST |
|---|
| 40431 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40432 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 40433 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 40434 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 40435 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 40436 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 40437 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP |
|---|
| 40438 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 40439 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 40440 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 40441 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 40442 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 40443 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 40444 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL |
|---|
| 40445 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 40446 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 40447 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 40448 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 40449 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST |
|---|
| 40450 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40451 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 40452 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 40453 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 40454 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 40455 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 40456 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP |
|---|
| 40457 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 40458 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 40459 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 40460 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 40461 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 40462 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 40463 | //BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL |
|---|
| 40464 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 40465 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 40466 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 40467 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 40468 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 40469 | #define BIF_CFG_DEV0_EPF0_VF16_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 40470 | |
|---|
| 40471 | |
|---|
| 40472 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp |
|---|
| 40473 | //BIF_CFG_DEV0_EPF0_VF17_VENDOR_ID |
|---|
| 40474 | #define BIF_CFG_DEV0_EPF0_VF17_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 40475 | #define BIF_CFG_DEV0_EPF0_VF17_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 40476 | //BIF_CFG_DEV0_EPF0_VF17_DEVICE_ID |
|---|
| 40477 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 40478 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 40479 | //BIF_CFG_DEV0_EPF0_VF17_COMMAND |
|---|
| 40480 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 40481 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 40482 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 40483 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 40484 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 40485 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 40486 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 40487 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 40488 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 40489 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 40490 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 40491 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 40492 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 40493 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 40494 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 40495 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 40496 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 40497 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 40498 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 40499 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 40500 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 40501 | #define BIF_CFG_DEV0_EPF0_VF17_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 40502 | //BIF_CFG_DEV0_EPF0_VF17_STATUS |
|---|
| 40503 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 40504 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 40505 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 40506 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 40507 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 40508 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 40509 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 40510 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 40511 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 40512 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 40513 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 40514 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 40515 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 40516 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 40517 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 40518 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 40519 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 40520 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 40521 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 40522 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 40523 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 40524 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 40525 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 40526 | #define BIF_CFG_DEV0_EPF0_VF17_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 40527 | //BIF_CFG_DEV0_EPF0_VF17_REVISION_ID |
|---|
| 40528 | #define BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 40529 | #define BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 40530 | #define BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 40531 | #define BIF_CFG_DEV0_EPF0_VF17_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 40532 | //BIF_CFG_DEV0_EPF0_VF17_PROG_INTERFACE |
|---|
| 40533 | #define BIF_CFG_DEV0_EPF0_VF17_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 40534 | #define BIF_CFG_DEV0_EPF0_VF17_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 40535 | //BIF_CFG_DEV0_EPF0_VF17_SUB_CLASS |
|---|
| 40536 | #define BIF_CFG_DEV0_EPF0_VF17_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 40537 | #define BIF_CFG_DEV0_EPF0_VF17_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 40538 | //BIF_CFG_DEV0_EPF0_VF17_BASE_CLASS |
|---|
| 40539 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 40540 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 40541 | //BIF_CFG_DEV0_EPF0_VF17_CACHE_LINE |
|---|
| 40542 | #define BIF_CFG_DEV0_EPF0_VF17_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 40543 | #define BIF_CFG_DEV0_EPF0_VF17_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 40544 | //BIF_CFG_DEV0_EPF0_VF17_LATENCY |
|---|
| 40545 | #define BIF_CFG_DEV0_EPF0_VF17_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 40546 | #define BIF_CFG_DEV0_EPF0_VF17_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 40547 | //BIF_CFG_DEV0_EPF0_VF17_HEADER |
|---|
| 40548 | #define 0x0 |
|---|
| 40549 | #define 0x7 |
|---|
| 40550 | #define 0x7FL |
|---|
| 40551 | #define 0x80L |
|---|
| 40552 | //BIF_CFG_DEV0_EPF0_VF17_BIST |
|---|
| 40553 | #define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 40554 | #define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 40555 | #define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 40556 | #define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 40557 | #define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_STRT_MASK 0x40L |
|---|
| 40558 | #define BIF_CFG_DEV0_EPF0_VF17_BIST__BIST_CAP_MASK 0x80L |
|---|
| 40559 | //BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_1 |
|---|
| 40560 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 40561 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 40562 | //BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_2 |
|---|
| 40563 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 40564 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 40565 | //BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_3 |
|---|
| 40566 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 40567 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 40568 | //BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_4 |
|---|
| 40569 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 40570 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 40571 | //BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_5 |
|---|
| 40572 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 40573 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 40574 | //BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_6 |
|---|
| 40575 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 40576 | #define BIF_CFG_DEV0_EPF0_VF17_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 40577 | //BIF_CFG_DEV0_EPF0_VF17_CARDBUS_CIS_PTR |
|---|
| 40578 | #define BIF_CFG_DEV0_EPF0_VF17_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 40579 | #define BIF_CFG_DEV0_EPF0_VF17_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 40580 | //BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID |
|---|
| 40581 | #define BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 40582 | #define BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 40583 | #define BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 40584 | #define BIF_CFG_DEV0_EPF0_VF17_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 40585 | //BIF_CFG_DEV0_EPF0_VF17_ROM_BASE_ADDR |
|---|
| 40586 | #define BIF_CFG_DEV0_EPF0_VF17_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 40587 | #define BIF_CFG_DEV0_EPF0_VF17_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 40588 | //BIF_CFG_DEV0_EPF0_VF17_CAP_PTR |
|---|
| 40589 | #define BIF_CFG_DEV0_EPF0_VF17_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 40590 | #define BIF_CFG_DEV0_EPF0_VF17_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 40591 | //BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_LINE |
|---|
| 40592 | #define BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 40593 | #define BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 40594 | //BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_PIN |
|---|
| 40595 | #define BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 40596 | #define BIF_CFG_DEV0_EPF0_VF17_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 40597 | //BIF_CFG_DEV0_EPF0_VF17_MIN_GRANT |
|---|
| 40598 | #define BIF_CFG_DEV0_EPF0_VF17_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 40599 | #define BIF_CFG_DEV0_EPF0_VF17_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 40600 | //BIF_CFG_DEV0_EPF0_VF17_MAX_LATENCY |
|---|
| 40601 | #define BIF_CFG_DEV0_EPF0_VF17_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 40602 | #define BIF_CFG_DEV0_EPF0_VF17_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 40603 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST |
|---|
| 40604 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40605 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 40606 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 40607 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 40608 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP |
|---|
| 40609 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 40610 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 40611 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 40612 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 40613 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 40614 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 40615 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 40616 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 40617 | //BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP |
|---|
| 40618 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 40619 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 40620 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 40621 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 40622 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 40623 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 40624 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 40625 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 40626 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 40627 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 40628 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 40629 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 40630 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 40631 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 40632 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 40633 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 40634 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 40635 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 40636 | //BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL |
|---|
| 40637 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 40638 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 40639 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 40640 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 40641 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 40642 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 40643 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 40644 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 40645 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 40646 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 40647 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 40648 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 40649 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 40650 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 40651 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 40652 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 40653 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 40654 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 40655 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 40656 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 40657 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 40658 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 40659 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 40660 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 40661 | //BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS |
|---|
| 40662 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 40663 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 40664 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 40665 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 40666 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 40667 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 40668 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 40669 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 40670 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 40671 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 40672 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 40673 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 40674 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 40675 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 40676 | //BIF_CFG_DEV0_EPF0_VF17_LINK_CAP |
|---|
| 40677 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 40678 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 40679 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 40680 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 40681 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 40682 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 40683 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 40684 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 40685 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 40686 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 40687 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 40688 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 40689 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 40690 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 40691 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 40692 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 40693 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 40694 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 40695 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 40696 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 40697 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 40698 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 40699 | //BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL |
|---|
| 40700 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 40701 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 40702 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 40703 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 40704 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 40705 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 40706 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 40707 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 40708 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 40709 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 40710 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 40711 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 40712 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 40713 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 40714 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 40715 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 40716 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 40717 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 40718 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 40719 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 40720 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 40721 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 40722 | //BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS |
|---|
| 40723 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 40724 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 40725 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 40726 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 40727 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 40728 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 40729 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 40730 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 40731 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 40732 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 40733 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 40734 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 40735 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 40736 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 40737 | //BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2 |
|---|
| 40738 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 40739 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 40740 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 40741 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 40742 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 40743 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 40744 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 40745 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 40746 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 40747 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 40748 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 40749 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 40750 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 40751 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 40752 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 40753 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 40754 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 40755 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 40756 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 40757 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 40758 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 40759 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 40760 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 40761 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 40762 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 40763 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 40764 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 40765 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 40766 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 40767 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 40768 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 40769 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 40770 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 40771 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 40772 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 40773 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 40774 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 40775 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 40776 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 40777 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 40778 | //BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2 |
|---|
| 40779 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 40780 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 40781 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 40782 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 40783 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 40784 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 40785 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 40786 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 40787 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 40788 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 40789 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 40790 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 40791 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 40792 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 40793 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 40794 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 40795 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 40796 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 40797 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 40798 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 40799 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 40800 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 40801 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 40802 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 40803 | //BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS2 |
|---|
| 40804 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 40805 | #define BIF_CFG_DEV0_EPF0_VF17_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 40806 | //BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2 |
|---|
| 40807 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 40808 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 40809 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 40810 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 40811 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 40812 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 40813 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 40814 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 40815 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 40816 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 40817 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 40818 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 40819 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 40820 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 40821 | //BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2 |
|---|
| 40822 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 40823 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 40824 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 40825 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 40826 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 40827 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 40828 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 40829 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 40830 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 40831 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 40832 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 40833 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 40834 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 40835 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 40836 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 40837 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 40838 | //BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2 |
|---|
| 40839 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 40840 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 40841 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 40842 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 40843 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 40844 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 40845 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 40846 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 40847 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 40848 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 40849 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 40850 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 40851 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 40852 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 40853 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 40854 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 40855 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 40856 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 40857 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 40858 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 40859 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 40860 | #define BIF_CFG_DEV0_EPF0_VF17_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 40861 | //BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST |
|---|
| 40862 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40863 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 40864 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 40865 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 40866 | //BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL |
|---|
| 40867 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 40868 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 40869 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 40870 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 40871 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 40872 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 40873 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 40874 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 40875 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 40876 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 40877 | //BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_LO |
|---|
| 40878 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 40879 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 40880 | //BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_HI |
|---|
| 40881 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 40882 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 40883 | //BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA |
|---|
| 40884 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 40885 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 40886 | //BIF_CFG_DEV0_EPF0_VF17_MSI_MASK |
|---|
| 40887 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 40888 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 40889 | //BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_64 |
|---|
| 40890 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 40891 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 40892 | //BIF_CFG_DEV0_EPF0_VF17_MSI_MASK_64 |
|---|
| 40893 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 40894 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 40895 | //BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING |
|---|
| 40896 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 40897 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 40898 | //BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_64 |
|---|
| 40899 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 40900 | #define BIF_CFG_DEV0_EPF0_VF17_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 40901 | //BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST |
|---|
| 40902 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40903 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 40904 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 40905 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 40906 | //BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL |
|---|
| 40907 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 40908 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 40909 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 40910 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 40911 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 40912 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 40913 | //BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE |
|---|
| 40914 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 40915 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 40916 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 40917 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 40918 | //BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA |
|---|
| 40919 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 40920 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 40921 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 40922 | #define BIF_CFG_DEV0_EPF0_VF17_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 40923 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 40924 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40925 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 40926 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 40927 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 40928 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 40929 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 40930 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 40931 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 40932 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 40933 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 40934 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 40935 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 40936 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 40937 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC1 |
|---|
| 40938 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 40939 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 40940 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC2 |
|---|
| 40941 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 40942 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 40943 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 40944 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 40945 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 40946 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 40947 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 40948 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 40949 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 40950 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS |
|---|
| 40951 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 40952 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 40953 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 40954 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 40955 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 40956 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 40957 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 40958 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 40959 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 40960 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 40961 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 40962 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 40963 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 40964 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 40965 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 40966 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 40967 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 40968 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 40969 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 40970 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 40971 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 40972 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 40973 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 40974 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 40975 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 40976 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 40977 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 40978 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 40979 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 40980 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 40981 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 40982 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 40983 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK |
|---|
| 40984 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 40985 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 40986 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 40987 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 40988 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 40989 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 40990 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 40991 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 40992 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 40993 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 40994 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 40995 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 40996 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 40997 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 40998 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 40999 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 41000 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 41001 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 41002 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 41003 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 41004 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 41005 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 41006 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 41007 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 41008 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 41009 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 41010 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 41011 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 41012 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 41013 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 41014 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 41015 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 41016 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 41017 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 41018 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 41019 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 41020 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 41021 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 41022 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 41023 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 41024 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 41025 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 41026 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 41027 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 41028 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 41029 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 41030 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 41031 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 41032 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 41033 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 41034 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 41035 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 41036 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 41037 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 41038 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 41039 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 41040 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 41041 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 41042 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 41043 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 41044 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 41045 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 41046 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 41047 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 41048 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 41049 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS |
|---|
| 41050 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 41051 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 41052 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 41053 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 41054 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 41055 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 41056 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 41057 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 41058 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 41059 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 41060 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 41061 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 41062 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 41063 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 41064 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 41065 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 41066 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK |
|---|
| 41067 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 41068 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 41069 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 41070 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 41071 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 41072 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 41073 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 41074 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 41075 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 41076 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 41077 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 41078 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 41079 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 41080 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 41081 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 41082 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 41083 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 41084 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 41085 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 41086 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 41087 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 41088 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 41089 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 41090 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 41091 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 41092 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 41093 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 41094 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 41095 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 41096 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 41097 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 41098 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 41099 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 41100 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 41101 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 41102 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG0 |
|---|
| 41103 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 41104 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 41105 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG1 |
|---|
| 41106 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 41107 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 41108 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG2 |
|---|
| 41109 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 41110 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 41111 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG3 |
|---|
| 41112 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 41113 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 41114 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG0 |
|---|
| 41115 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 41116 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 41117 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG1 |
|---|
| 41118 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 41119 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 41120 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG2 |
|---|
| 41121 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 41122 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 41123 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG3 |
|---|
| 41124 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 41125 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 41126 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST |
|---|
| 41127 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 41128 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 41129 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 41130 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 41131 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 41132 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 41133 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP |
|---|
| 41134 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 41135 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 41136 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 41137 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 41138 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 41139 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 41140 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL |
|---|
| 41141 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 41142 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 41143 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 41144 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 41145 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST |
|---|
| 41146 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 41147 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 41148 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 41149 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 41150 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 41151 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 41152 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP |
|---|
| 41153 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 41154 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 41155 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 41156 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 41157 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 41158 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 41159 | //BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL |
|---|
| 41160 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 41161 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 41162 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 41163 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 41164 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 41165 | #define BIF_CFG_DEV0_EPF0_VF17_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 41166 | |
|---|
| 41167 | |
|---|
| 41168 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp |
|---|
| 41169 | //BIF_CFG_DEV0_EPF0_VF18_VENDOR_ID |
|---|
| 41170 | #define BIF_CFG_DEV0_EPF0_VF18_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 41171 | #define BIF_CFG_DEV0_EPF0_VF18_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 41172 | //BIF_CFG_DEV0_EPF0_VF18_DEVICE_ID |
|---|
| 41173 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 41174 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 41175 | //BIF_CFG_DEV0_EPF0_VF18_COMMAND |
|---|
| 41176 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 41177 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 41178 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 41179 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 41180 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 41181 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 41182 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 41183 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 41184 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 41185 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 41186 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 41187 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 41188 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 41189 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 41190 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 41191 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 41192 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 41193 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 41194 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 41195 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 41196 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 41197 | #define BIF_CFG_DEV0_EPF0_VF18_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 41198 | //BIF_CFG_DEV0_EPF0_VF18_STATUS |
|---|
| 41199 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 41200 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 41201 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 41202 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 41203 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 41204 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 41205 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 41206 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 41207 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 41208 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 41209 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 41210 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 41211 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 41212 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 41213 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 41214 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 41215 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 41216 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 41217 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 41218 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 41219 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 41220 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 41221 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 41222 | #define BIF_CFG_DEV0_EPF0_VF18_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 41223 | //BIF_CFG_DEV0_EPF0_VF18_REVISION_ID |
|---|
| 41224 | #define BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 41225 | #define BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 41226 | #define BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 41227 | #define BIF_CFG_DEV0_EPF0_VF18_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 41228 | //BIF_CFG_DEV0_EPF0_VF18_PROG_INTERFACE |
|---|
| 41229 | #define BIF_CFG_DEV0_EPF0_VF18_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 41230 | #define BIF_CFG_DEV0_EPF0_VF18_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 41231 | //BIF_CFG_DEV0_EPF0_VF18_SUB_CLASS |
|---|
| 41232 | #define BIF_CFG_DEV0_EPF0_VF18_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 41233 | #define BIF_CFG_DEV0_EPF0_VF18_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 41234 | //BIF_CFG_DEV0_EPF0_VF18_BASE_CLASS |
|---|
| 41235 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 41236 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 41237 | //BIF_CFG_DEV0_EPF0_VF18_CACHE_LINE |
|---|
| 41238 | #define BIF_CFG_DEV0_EPF0_VF18_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 41239 | #define BIF_CFG_DEV0_EPF0_VF18_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 41240 | //BIF_CFG_DEV0_EPF0_VF18_LATENCY |
|---|
| 41241 | #define BIF_CFG_DEV0_EPF0_VF18_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 41242 | #define BIF_CFG_DEV0_EPF0_VF18_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 41243 | //BIF_CFG_DEV0_EPF0_VF18_HEADER |
|---|
| 41244 | #define 0x0 |
|---|
| 41245 | #define 0x7 |
|---|
| 41246 | #define 0x7FL |
|---|
| 41247 | #define 0x80L |
|---|
| 41248 | //BIF_CFG_DEV0_EPF0_VF18_BIST |
|---|
| 41249 | #define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 41250 | #define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 41251 | #define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 41252 | #define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 41253 | #define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_STRT_MASK 0x40L |
|---|
| 41254 | #define BIF_CFG_DEV0_EPF0_VF18_BIST__BIST_CAP_MASK 0x80L |
|---|
| 41255 | //BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_1 |
|---|
| 41256 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 41257 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41258 | //BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_2 |
|---|
| 41259 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 41260 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41261 | //BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_3 |
|---|
| 41262 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 41263 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41264 | //BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_4 |
|---|
| 41265 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 41266 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41267 | //BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_5 |
|---|
| 41268 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 41269 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41270 | //BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_6 |
|---|
| 41271 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 41272 | #define BIF_CFG_DEV0_EPF0_VF18_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41273 | //BIF_CFG_DEV0_EPF0_VF18_CARDBUS_CIS_PTR |
|---|
| 41274 | #define BIF_CFG_DEV0_EPF0_VF18_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 41275 | #define BIF_CFG_DEV0_EPF0_VF18_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 41276 | //BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID |
|---|
| 41277 | #define BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 41278 | #define BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 41279 | #define BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 41280 | #define BIF_CFG_DEV0_EPF0_VF18_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 41281 | //BIF_CFG_DEV0_EPF0_VF18_ROM_BASE_ADDR |
|---|
| 41282 | #define BIF_CFG_DEV0_EPF0_VF18_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 41283 | #define BIF_CFG_DEV0_EPF0_VF18_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41284 | //BIF_CFG_DEV0_EPF0_VF18_CAP_PTR |
|---|
| 41285 | #define BIF_CFG_DEV0_EPF0_VF18_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 41286 | #define BIF_CFG_DEV0_EPF0_VF18_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 41287 | //BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_LINE |
|---|
| 41288 | #define BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 41289 | #define BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 41290 | //BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_PIN |
|---|
| 41291 | #define BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 41292 | #define BIF_CFG_DEV0_EPF0_VF18_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 41293 | //BIF_CFG_DEV0_EPF0_VF18_MIN_GRANT |
|---|
| 41294 | #define BIF_CFG_DEV0_EPF0_VF18_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 41295 | #define BIF_CFG_DEV0_EPF0_VF18_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 41296 | //BIF_CFG_DEV0_EPF0_VF18_MAX_LATENCY |
|---|
| 41297 | #define BIF_CFG_DEV0_EPF0_VF18_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 41298 | #define BIF_CFG_DEV0_EPF0_VF18_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 41299 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST |
|---|
| 41300 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 41301 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 41302 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 41303 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 41304 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP |
|---|
| 41305 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 41306 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 41307 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 41308 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 41309 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 41310 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 41311 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 41312 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 41313 | //BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP |
|---|
| 41314 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 41315 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 41316 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 41317 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 41318 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 41319 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 41320 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 41321 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 41322 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 41323 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 41324 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 41325 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 41326 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 41327 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 41328 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 41329 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 41330 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 41331 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 41332 | //BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL |
|---|
| 41333 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 41334 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 41335 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 41336 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 41337 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 41338 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 41339 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 41340 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 41341 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 41342 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 41343 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 41344 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 41345 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 41346 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 41347 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 41348 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 41349 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 41350 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 41351 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 41352 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 41353 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 41354 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 41355 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 41356 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 41357 | //BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS |
|---|
| 41358 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 41359 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 41360 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 41361 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 41362 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 41363 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 41364 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 41365 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 41366 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 41367 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 41368 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 41369 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 41370 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 41371 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 41372 | //BIF_CFG_DEV0_EPF0_VF18_LINK_CAP |
|---|
| 41373 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 41374 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 41375 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 41376 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 41377 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 41378 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 41379 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 41380 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 41381 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 41382 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 41383 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 41384 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 41385 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 41386 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 41387 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 41388 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 41389 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 41390 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 41391 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 41392 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 41393 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 41394 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 41395 | //BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL |
|---|
| 41396 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 41397 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 41398 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 41399 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 41400 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 41401 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 41402 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 41403 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 41404 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 41405 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 41406 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 41407 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 41408 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 41409 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 41410 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 41411 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 41412 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 41413 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 41414 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 41415 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 41416 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 41417 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 41418 | //BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS |
|---|
| 41419 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 41420 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 41421 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 41422 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 41423 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 41424 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 41425 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 41426 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 41427 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 41428 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 41429 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 41430 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 41431 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 41432 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 41433 | //BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2 |
|---|
| 41434 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 41435 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 41436 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 41437 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 41438 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 41439 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 41440 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 41441 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 41442 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 41443 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 41444 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 41445 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 41446 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 41447 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 41448 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 41449 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 41450 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 41451 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 41452 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 41453 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 41454 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 41455 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 41456 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 41457 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 41458 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 41459 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 41460 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 41461 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 41462 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 41463 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 41464 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 41465 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 41466 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 41467 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 41468 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 41469 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 41470 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 41471 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 41472 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 41473 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 41474 | //BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2 |
|---|
| 41475 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 41476 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 41477 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 41478 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 41479 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 41480 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 41481 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 41482 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 41483 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 41484 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 41485 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 41486 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 41487 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 41488 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 41489 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 41490 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 41491 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 41492 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 41493 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 41494 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 41495 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 41496 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 41497 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 41498 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 41499 | //BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS2 |
|---|
| 41500 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 41501 | #define BIF_CFG_DEV0_EPF0_VF18_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 41502 | //BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2 |
|---|
| 41503 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 41504 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 41505 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 41506 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 41507 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 41508 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 41509 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 41510 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 41511 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 41512 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 41513 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 41514 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 41515 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 41516 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 41517 | //BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2 |
|---|
| 41518 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 41519 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 41520 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 41521 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 41522 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 41523 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 41524 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 41525 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 41526 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 41527 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 41528 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 41529 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 41530 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 41531 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 41532 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 41533 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 41534 | //BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2 |
|---|
| 41535 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 41536 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 41537 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 41538 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 41539 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 41540 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 41541 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 41542 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 41543 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 41544 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 41545 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 41546 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 41547 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 41548 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 41549 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 41550 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 41551 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 41552 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 41553 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 41554 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 41555 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 41556 | #define BIF_CFG_DEV0_EPF0_VF18_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 41557 | //BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST |
|---|
| 41558 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 41559 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 41560 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 41561 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 41562 | //BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL |
|---|
| 41563 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 41564 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 41565 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 41566 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 41567 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 41568 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 41569 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 41570 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 41571 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 41572 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 41573 | //BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_LO |
|---|
| 41574 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 41575 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 41576 | //BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_HI |
|---|
| 41577 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 41578 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 41579 | //BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA |
|---|
| 41580 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 41581 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 41582 | //BIF_CFG_DEV0_EPF0_VF18_MSI_MASK |
|---|
| 41583 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 41584 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 41585 | //BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_64 |
|---|
| 41586 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 41587 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 41588 | //BIF_CFG_DEV0_EPF0_VF18_MSI_MASK_64 |
|---|
| 41589 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 41590 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 41591 | //BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING |
|---|
| 41592 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 41593 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 41594 | //BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_64 |
|---|
| 41595 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 41596 | #define BIF_CFG_DEV0_EPF0_VF18_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 41597 | //BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST |
|---|
| 41598 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 41599 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 41600 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 41601 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 41602 | //BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL |
|---|
| 41603 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 41604 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 41605 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 41606 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 41607 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 41608 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 41609 | //BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE |
|---|
| 41610 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 41611 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 41612 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 41613 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 41614 | //BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA |
|---|
| 41615 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 41616 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 41617 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 41618 | #define BIF_CFG_DEV0_EPF0_VF18_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 41619 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 41620 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 41621 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 41622 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 41623 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 41624 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 41625 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 41626 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 41627 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 41628 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 41629 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 41630 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 41631 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 41632 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 41633 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC1 |
|---|
| 41634 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 41635 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 41636 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC2 |
|---|
| 41637 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 41638 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 41639 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 41640 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 41641 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 41642 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 41643 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 41644 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 41645 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 41646 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS |
|---|
| 41647 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 41648 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 41649 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 41650 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 41651 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 41652 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 41653 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 41654 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 41655 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 41656 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 41657 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 41658 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 41659 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 41660 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 41661 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 41662 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 41663 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 41664 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 41665 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 41666 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 41667 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 41668 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 41669 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 41670 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 41671 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 41672 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 41673 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 41674 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 41675 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 41676 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 41677 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 41678 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 41679 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK |
|---|
| 41680 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 41681 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 41682 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 41683 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 41684 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 41685 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 41686 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 41687 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 41688 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 41689 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 41690 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 41691 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 41692 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 41693 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 41694 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 41695 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 41696 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 41697 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 41698 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 41699 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 41700 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 41701 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 41702 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 41703 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 41704 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 41705 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 41706 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 41707 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 41708 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 41709 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 41710 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 41711 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 41712 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 41713 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 41714 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 41715 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 41716 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 41717 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 41718 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 41719 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 41720 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 41721 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 41722 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 41723 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 41724 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 41725 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 41726 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 41727 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 41728 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 41729 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 41730 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 41731 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 41732 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 41733 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 41734 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 41735 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 41736 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 41737 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 41738 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 41739 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 41740 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 41741 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 41742 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 41743 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 41744 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 41745 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS |
|---|
| 41746 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 41747 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 41748 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 41749 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 41750 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 41751 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 41752 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 41753 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 41754 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 41755 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 41756 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 41757 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 41758 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 41759 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 41760 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 41761 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 41762 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK |
|---|
| 41763 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 41764 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 41765 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 41766 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 41767 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 41768 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 41769 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 41770 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 41771 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 41772 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 41773 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 41774 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 41775 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 41776 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 41777 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 41778 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 41779 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 41780 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 41781 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 41782 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 41783 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 41784 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 41785 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 41786 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 41787 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 41788 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 41789 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 41790 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 41791 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 41792 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 41793 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 41794 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 41795 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 41796 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 41797 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 41798 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG0 |
|---|
| 41799 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 41800 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 41801 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG1 |
|---|
| 41802 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 41803 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 41804 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG2 |
|---|
| 41805 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 41806 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 41807 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG3 |
|---|
| 41808 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 41809 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 41810 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG0 |
|---|
| 41811 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 41812 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 41813 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG1 |
|---|
| 41814 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 41815 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 41816 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG2 |
|---|
| 41817 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 41818 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 41819 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG3 |
|---|
| 41820 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 41821 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 41822 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST |
|---|
| 41823 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 41824 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 41825 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 41826 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 41827 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 41828 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 41829 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP |
|---|
| 41830 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 41831 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 41832 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 41833 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 41834 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 41835 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 41836 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL |
|---|
| 41837 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 41838 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 41839 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 41840 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 41841 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST |
|---|
| 41842 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 41843 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 41844 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 41845 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 41846 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 41847 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 41848 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP |
|---|
| 41849 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 41850 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 41851 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 41852 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 41853 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 41854 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 41855 | //BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL |
|---|
| 41856 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 41857 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 41858 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 41859 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 41860 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 41861 | #define BIF_CFG_DEV0_EPF0_VF18_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 41862 | |
|---|
| 41863 | |
|---|
| 41864 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp |
|---|
| 41865 | //BIF_CFG_DEV0_EPF0_VF19_VENDOR_ID |
|---|
| 41866 | #define BIF_CFG_DEV0_EPF0_VF19_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 41867 | #define BIF_CFG_DEV0_EPF0_VF19_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 41868 | //BIF_CFG_DEV0_EPF0_VF19_DEVICE_ID |
|---|
| 41869 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 41870 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 41871 | //BIF_CFG_DEV0_EPF0_VF19_COMMAND |
|---|
| 41872 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 41873 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 41874 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 41875 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 41876 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 41877 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 41878 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 41879 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 41880 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 41881 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 41882 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 41883 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 41884 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 41885 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 41886 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 41887 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 41888 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 41889 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 41890 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 41891 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 41892 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 41893 | #define BIF_CFG_DEV0_EPF0_VF19_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 41894 | //BIF_CFG_DEV0_EPF0_VF19_STATUS |
|---|
| 41895 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 41896 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 41897 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 41898 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 41899 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 41900 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 41901 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 41902 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 41903 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 41904 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 41905 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 41906 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 41907 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 41908 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 41909 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 41910 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 41911 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 41912 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 41913 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 41914 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 41915 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 41916 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 41917 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 41918 | #define BIF_CFG_DEV0_EPF0_VF19_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 41919 | //BIF_CFG_DEV0_EPF0_VF19_REVISION_ID |
|---|
| 41920 | #define BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 41921 | #define BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 41922 | #define BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 41923 | #define BIF_CFG_DEV0_EPF0_VF19_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 41924 | //BIF_CFG_DEV0_EPF0_VF19_PROG_INTERFACE |
|---|
| 41925 | #define BIF_CFG_DEV0_EPF0_VF19_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 41926 | #define BIF_CFG_DEV0_EPF0_VF19_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 41927 | //BIF_CFG_DEV0_EPF0_VF19_SUB_CLASS |
|---|
| 41928 | #define BIF_CFG_DEV0_EPF0_VF19_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 41929 | #define BIF_CFG_DEV0_EPF0_VF19_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 41930 | //BIF_CFG_DEV0_EPF0_VF19_BASE_CLASS |
|---|
| 41931 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 41932 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 41933 | //BIF_CFG_DEV0_EPF0_VF19_CACHE_LINE |
|---|
| 41934 | #define BIF_CFG_DEV0_EPF0_VF19_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 41935 | #define BIF_CFG_DEV0_EPF0_VF19_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 41936 | //BIF_CFG_DEV0_EPF0_VF19_LATENCY |
|---|
| 41937 | #define BIF_CFG_DEV0_EPF0_VF19_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 41938 | #define BIF_CFG_DEV0_EPF0_VF19_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 41939 | //BIF_CFG_DEV0_EPF0_VF19_HEADER |
|---|
| 41940 | #define 0x0 |
|---|
| 41941 | #define 0x7 |
|---|
| 41942 | #define 0x7FL |
|---|
| 41943 | #define 0x80L |
|---|
| 41944 | //BIF_CFG_DEV0_EPF0_VF19_BIST |
|---|
| 41945 | #define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 41946 | #define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 41947 | #define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 41948 | #define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 41949 | #define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_STRT_MASK 0x40L |
|---|
| 41950 | #define BIF_CFG_DEV0_EPF0_VF19_BIST__BIST_CAP_MASK 0x80L |
|---|
| 41951 | //BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_1 |
|---|
| 41952 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 41953 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41954 | //BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_2 |
|---|
| 41955 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 41956 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41957 | //BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_3 |
|---|
| 41958 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 41959 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41960 | //BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_4 |
|---|
| 41961 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 41962 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41963 | //BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_5 |
|---|
| 41964 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 41965 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41966 | //BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_6 |
|---|
| 41967 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 41968 | #define BIF_CFG_DEV0_EPF0_VF19_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41969 | //BIF_CFG_DEV0_EPF0_VF19_CARDBUS_CIS_PTR |
|---|
| 41970 | #define BIF_CFG_DEV0_EPF0_VF19_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 41971 | #define BIF_CFG_DEV0_EPF0_VF19_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 41972 | //BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID |
|---|
| 41973 | #define BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 41974 | #define BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 41975 | #define BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 41976 | #define BIF_CFG_DEV0_EPF0_VF19_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 41977 | //BIF_CFG_DEV0_EPF0_VF19_ROM_BASE_ADDR |
|---|
| 41978 | #define BIF_CFG_DEV0_EPF0_VF19_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 41979 | #define BIF_CFG_DEV0_EPF0_VF19_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 41980 | //BIF_CFG_DEV0_EPF0_VF19_CAP_PTR |
|---|
| 41981 | #define BIF_CFG_DEV0_EPF0_VF19_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 41982 | #define BIF_CFG_DEV0_EPF0_VF19_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 41983 | //BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_LINE |
|---|
| 41984 | #define BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 41985 | #define BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 41986 | //BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_PIN |
|---|
| 41987 | #define BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 41988 | #define BIF_CFG_DEV0_EPF0_VF19_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 41989 | //BIF_CFG_DEV0_EPF0_VF19_MIN_GRANT |
|---|
| 41990 | #define BIF_CFG_DEV0_EPF0_VF19_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 41991 | #define BIF_CFG_DEV0_EPF0_VF19_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 41992 | //BIF_CFG_DEV0_EPF0_VF19_MAX_LATENCY |
|---|
| 41993 | #define BIF_CFG_DEV0_EPF0_VF19_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 41994 | #define BIF_CFG_DEV0_EPF0_VF19_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 41995 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST |
|---|
| 41996 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 41997 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 41998 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 41999 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 42000 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP |
|---|
| 42001 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 42002 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 42003 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 42004 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 42005 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 42006 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 42007 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 42008 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 42009 | //BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP |
|---|
| 42010 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 42011 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 42012 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 42013 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 42014 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 42015 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 42016 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 42017 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 42018 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 42019 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 42020 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 42021 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 42022 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 42023 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 42024 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 42025 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 42026 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 42027 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 42028 | //BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL |
|---|
| 42029 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 42030 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 42031 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 42032 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 42033 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 42034 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 42035 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 42036 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 42037 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 42038 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 42039 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 42040 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 42041 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 42042 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 42043 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 42044 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 42045 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 42046 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 42047 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 42048 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 42049 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 42050 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 42051 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 42052 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 42053 | //BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS |
|---|
| 42054 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 42055 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 42056 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 42057 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 42058 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 42059 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 42060 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 42061 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 42062 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 42063 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 42064 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 42065 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 42066 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 42067 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 42068 | //BIF_CFG_DEV0_EPF0_VF19_LINK_CAP |
|---|
| 42069 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 42070 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 42071 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 42072 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 42073 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 42074 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 42075 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 42076 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 42077 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 42078 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 42079 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 42080 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 42081 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 42082 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 42083 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 42084 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 42085 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 42086 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 42087 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 42088 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 42089 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 42090 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 42091 | //BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL |
|---|
| 42092 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 42093 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 42094 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 42095 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 42096 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 42097 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 42098 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 42099 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 42100 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 42101 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 42102 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 42103 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 42104 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 42105 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 42106 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 42107 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 42108 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 42109 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 42110 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 42111 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 42112 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 42113 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 42114 | //BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS |
|---|
| 42115 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 42116 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 42117 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 42118 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 42119 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 42120 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 42121 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 42122 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 42123 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 42124 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 42125 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 42126 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 42127 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 42128 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 42129 | //BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2 |
|---|
| 42130 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 42131 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 42132 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 42133 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 42134 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 42135 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 42136 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 42137 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 42138 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 42139 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 42140 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 42141 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 42142 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 42143 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 42144 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 42145 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 42146 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 42147 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 42148 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 42149 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 42150 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 42151 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 42152 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 42153 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 42154 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 42155 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 42156 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 42157 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 42158 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 42159 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 42160 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 42161 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 42162 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 42163 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 42164 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 42165 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 42166 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 42167 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 42168 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 42169 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 42170 | //BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2 |
|---|
| 42171 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 42172 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 42173 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 42174 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 42175 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 42176 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 42177 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 42178 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 42179 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 42180 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 42181 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 42182 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 42183 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 42184 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 42185 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 42186 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 42187 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 42188 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 42189 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 42190 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 42191 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 42192 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 42193 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 42194 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 42195 | //BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS2 |
|---|
| 42196 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 42197 | #define BIF_CFG_DEV0_EPF0_VF19_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 42198 | //BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2 |
|---|
| 42199 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 42200 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 42201 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 42202 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 42203 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 42204 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 42205 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 42206 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 42207 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 42208 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 42209 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 42210 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 42211 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 42212 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 42213 | //BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2 |
|---|
| 42214 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 42215 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 42216 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 42217 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 42218 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 42219 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 42220 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 42221 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 42222 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 42223 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 42224 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 42225 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 42226 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 42227 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 42228 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 42229 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 42230 | //BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2 |
|---|
| 42231 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 42232 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 42233 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 42234 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 42235 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 42236 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 42237 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 42238 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 42239 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 42240 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 42241 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 42242 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 42243 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 42244 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 42245 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 42246 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 42247 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 42248 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 42249 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 42250 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 42251 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 42252 | #define BIF_CFG_DEV0_EPF0_VF19_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 42253 | //BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST |
|---|
| 42254 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 42255 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 42256 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 42257 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 42258 | //BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL |
|---|
| 42259 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 42260 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 42261 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 42262 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 42263 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 42264 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 42265 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 42266 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 42267 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 42268 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 42269 | //BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_LO |
|---|
| 42270 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 42271 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 42272 | //BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_HI |
|---|
| 42273 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 42274 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 42275 | //BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA |
|---|
| 42276 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 42277 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 42278 | //BIF_CFG_DEV0_EPF0_VF19_MSI_MASK |
|---|
| 42279 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 42280 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 42281 | //BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_64 |
|---|
| 42282 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 42283 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 42284 | //BIF_CFG_DEV0_EPF0_VF19_MSI_MASK_64 |
|---|
| 42285 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 42286 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 42287 | //BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING |
|---|
| 42288 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 42289 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 42290 | //BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_64 |
|---|
| 42291 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 42292 | #define BIF_CFG_DEV0_EPF0_VF19_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 42293 | //BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST |
|---|
| 42294 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 42295 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 42296 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 42297 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 42298 | //BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL |
|---|
| 42299 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 42300 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 42301 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 42302 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 42303 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 42304 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 42305 | //BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE |
|---|
| 42306 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 42307 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 42308 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 42309 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 42310 | //BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA |
|---|
| 42311 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 42312 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 42313 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 42314 | #define BIF_CFG_DEV0_EPF0_VF19_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 42315 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 42316 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 42317 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 42318 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 42319 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 42320 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 42321 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 42322 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 42323 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
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| 42324 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
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| 42325 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
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| 42326 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
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| 42327 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
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| 42328 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
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| 42329 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC1 |
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| 42330 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 42331 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 42332 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC2 |
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| 42333 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 42334 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
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| 42335 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 42336 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 42337 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 42338 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 42339 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 42340 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 42341 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 42342 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS |
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| 42343 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 42344 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 42345 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 42346 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 42347 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 42348 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 42349 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 42350 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 42351 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 42352 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 42353 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 42354 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 42355 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 42356 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 42357 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 42358 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 42359 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 42360 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 42361 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 42362 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 42363 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 42364 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 42365 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 42366 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 42367 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 42368 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 42369 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 42370 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 42371 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 42372 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 42373 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 42374 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 42375 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK |
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| 42376 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 42377 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 42378 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 42379 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 42380 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 42381 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 42382 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 42383 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 42384 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 42385 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 42386 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 42387 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 42388 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 42389 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 42390 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 42391 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 42392 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 42393 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 42394 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 42395 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 42396 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 42397 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 42398 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 42399 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 42400 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 42401 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 42402 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 42403 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 42404 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 42405 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 42406 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 42407 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 42408 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY |
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| 42409 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 42410 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 42411 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 42412 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 42413 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 42414 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 42415 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 42416 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 42417 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 42418 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 42419 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 42420 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 42421 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 42422 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 42423 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 42424 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 42425 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 42426 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 42427 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 42428 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 42429 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 42430 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 42431 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 42432 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 42433 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 42434 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 42435 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 42436 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 42437 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 42438 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 42439 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 42440 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 42441 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS |
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| 42442 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 42443 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 42444 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 42445 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 42446 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 42447 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 42448 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 42449 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 42450 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 42451 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 42452 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 42453 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 42454 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 42455 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 42456 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 42457 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 42458 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK |
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| 42459 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 42460 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 42461 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 42462 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 42463 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 42464 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 42465 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 42466 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 42467 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 42468 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 42469 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 42470 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 42471 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 42472 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 42473 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 42474 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 42475 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 42476 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 42477 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 42478 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 42479 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 42480 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 42481 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 42482 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 42483 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 42484 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 42485 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 42486 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 42487 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 42488 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 42489 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 42490 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 42491 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 42492 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 42493 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 42494 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG0 |
|---|
| 42495 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 42496 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 42497 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG1 |
|---|
| 42498 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 42499 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 42500 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG2 |
|---|
| 42501 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 42502 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 42503 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG3 |
|---|
| 42504 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 42505 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 42506 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG0 |
|---|
| 42507 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 42508 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 42509 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG1 |
|---|
| 42510 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 42511 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 42512 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG2 |
|---|
| 42513 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 42514 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 42515 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG3 |
|---|
| 42516 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 42517 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 42518 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST |
|---|
| 42519 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 42520 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 42521 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 42522 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 42523 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 42524 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 42525 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP |
|---|
| 42526 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 42527 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 42528 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 42529 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 42530 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 42531 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 42532 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL |
|---|
| 42533 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 42534 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 42535 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 42536 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 42537 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST |
|---|
| 42538 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 42539 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 42540 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 42541 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 42542 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 42543 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 42544 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP |
|---|
| 42545 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 42546 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 42547 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 42548 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 42549 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 42550 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 42551 | //BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL |
|---|
| 42552 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 42553 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 42554 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 42555 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 42556 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 42557 | #define BIF_CFG_DEV0_EPF0_VF19_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 42558 | |
|---|
| 42559 | |
|---|
| 42560 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp |
|---|
| 42561 | //BIF_CFG_DEV0_EPF0_VF20_VENDOR_ID |
|---|
| 42562 | #define BIF_CFG_DEV0_EPF0_VF20_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 42563 | #define BIF_CFG_DEV0_EPF0_VF20_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 42564 | //BIF_CFG_DEV0_EPF0_VF20_DEVICE_ID |
|---|
| 42565 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 42566 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 42567 | //BIF_CFG_DEV0_EPF0_VF20_COMMAND |
|---|
| 42568 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 42569 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 42570 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 42571 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 42572 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 42573 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 42574 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 42575 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 42576 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 42577 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 42578 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 42579 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 42580 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 42581 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 42582 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 42583 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 42584 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 42585 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 42586 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 42587 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 42588 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 42589 | #define BIF_CFG_DEV0_EPF0_VF20_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 42590 | //BIF_CFG_DEV0_EPF0_VF20_STATUS |
|---|
| 42591 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 42592 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 42593 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 42594 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 42595 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 42596 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 42597 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 42598 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 42599 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 42600 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 42601 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 42602 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 42603 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 42604 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 42605 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 42606 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 42607 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 42608 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 42609 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 42610 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 42611 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 42612 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 42613 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 42614 | #define BIF_CFG_DEV0_EPF0_VF20_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 42615 | //BIF_CFG_DEV0_EPF0_VF20_REVISION_ID |
|---|
| 42616 | #define BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 42617 | #define BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 42618 | #define BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 42619 | #define BIF_CFG_DEV0_EPF0_VF20_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 42620 | //BIF_CFG_DEV0_EPF0_VF20_PROG_INTERFACE |
|---|
| 42621 | #define BIF_CFG_DEV0_EPF0_VF20_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 42622 | #define BIF_CFG_DEV0_EPF0_VF20_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 42623 | //BIF_CFG_DEV0_EPF0_VF20_SUB_CLASS |
|---|
| 42624 | #define BIF_CFG_DEV0_EPF0_VF20_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 42625 | #define BIF_CFG_DEV0_EPF0_VF20_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 42626 | //BIF_CFG_DEV0_EPF0_VF20_BASE_CLASS |
|---|
| 42627 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 42628 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 42629 | //BIF_CFG_DEV0_EPF0_VF20_CACHE_LINE |
|---|
| 42630 | #define BIF_CFG_DEV0_EPF0_VF20_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 42631 | #define BIF_CFG_DEV0_EPF0_VF20_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 42632 | //BIF_CFG_DEV0_EPF0_VF20_LATENCY |
|---|
| 42633 | #define BIF_CFG_DEV0_EPF0_VF20_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 42634 | #define BIF_CFG_DEV0_EPF0_VF20_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 42635 | //BIF_CFG_DEV0_EPF0_VF20_HEADER |
|---|
| 42636 | #define 0x0 |
|---|
| 42637 | #define 0x7 |
|---|
| 42638 | #define 0x7FL |
|---|
| 42639 | #define 0x80L |
|---|
| 42640 | //BIF_CFG_DEV0_EPF0_VF20_BIST |
|---|
| 42641 | #define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 42642 | #define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 42643 | #define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 42644 | #define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 42645 | #define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_STRT_MASK 0x40L |
|---|
| 42646 | #define BIF_CFG_DEV0_EPF0_VF20_BIST__BIST_CAP_MASK 0x80L |
|---|
| 42647 | //BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_1 |
|---|
| 42648 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 42649 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 42650 | //BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_2 |
|---|
| 42651 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 42652 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 42653 | //BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_3 |
|---|
| 42654 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 42655 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 42656 | //BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_4 |
|---|
| 42657 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 42658 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 42659 | //BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_5 |
|---|
| 42660 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 42661 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 42662 | //BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_6 |
|---|
| 42663 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 42664 | #define BIF_CFG_DEV0_EPF0_VF20_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 42665 | //BIF_CFG_DEV0_EPF0_VF20_CARDBUS_CIS_PTR |
|---|
| 42666 | #define BIF_CFG_DEV0_EPF0_VF20_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 42667 | #define BIF_CFG_DEV0_EPF0_VF20_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 42668 | //BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID |
|---|
| 42669 | #define BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 42670 | #define BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 42671 | #define BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 42672 | #define BIF_CFG_DEV0_EPF0_VF20_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 42673 | //BIF_CFG_DEV0_EPF0_VF20_ROM_BASE_ADDR |
|---|
| 42674 | #define BIF_CFG_DEV0_EPF0_VF20_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 42675 | #define BIF_CFG_DEV0_EPF0_VF20_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 42676 | //BIF_CFG_DEV0_EPF0_VF20_CAP_PTR |
|---|
| 42677 | #define BIF_CFG_DEV0_EPF0_VF20_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 42678 | #define BIF_CFG_DEV0_EPF0_VF20_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 42679 | //BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_LINE |
|---|
| 42680 | #define BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 42681 | #define BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 42682 | //BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_PIN |
|---|
| 42683 | #define BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 42684 | #define BIF_CFG_DEV0_EPF0_VF20_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 42685 | //BIF_CFG_DEV0_EPF0_VF20_MIN_GRANT |
|---|
| 42686 | #define BIF_CFG_DEV0_EPF0_VF20_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 42687 | #define BIF_CFG_DEV0_EPF0_VF20_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 42688 | //BIF_CFG_DEV0_EPF0_VF20_MAX_LATENCY |
|---|
| 42689 | #define BIF_CFG_DEV0_EPF0_VF20_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 42690 | #define BIF_CFG_DEV0_EPF0_VF20_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 42691 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST |
|---|
| 42692 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 42693 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 42694 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 42695 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 42696 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP |
|---|
| 42697 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 42698 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 42699 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 42700 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 42701 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 42702 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 42703 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 42704 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 42705 | //BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP |
|---|
| 42706 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 42707 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 42708 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 42709 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 42710 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 42711 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 42712 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 42713 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 42714 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 42715 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 42716 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 42717 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 42718 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 42719 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 42720 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 42721 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 42722 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 42723 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 42724 | //BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL |
|---|
| 42725 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 42726 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 42727 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 42728 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 42729 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 42730 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 42731 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 42732 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 42733 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 42734 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 42735 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 42736 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 42737 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 42738 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 42739 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 42740 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 42741 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 42742 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 42743 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 42744 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 42745 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 42746 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 42747 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 42748 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 42749 | //BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS |
|---|
| 42750 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 42751 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 42752 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 42753 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 42754 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 42755 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 42756 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 42757 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 42758 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 42759 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 42760 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 42761 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 42762 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 42763 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 42764 | //BIF_CFG_DEV0_EPF0_VF20_LINK_CAP |
|---|
| 42765 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 42766 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 42767 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 42768 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 42769 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 42770 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 42771 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 42772 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 42773 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 42774 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 42775 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 42776 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 42777 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 42778 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 42779 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 42780 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 42781 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 42782 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 42783 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 42784 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 42785 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 42786 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 42787 | //BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL |
|---|
| 42788 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 42789 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 42790 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 42791 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 42792 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 42793 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 42794 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 42795 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 42796 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 42797 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 42798 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 42799 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 42800 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 42801 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 42802 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 42803 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 42804 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 42805 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 42806 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 42807 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 42808 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 42809 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 42810 | //BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS |
|---|
| 42811 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 42812 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 42813 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 42814 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 42815 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 42816 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 42817 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 42818 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 42819 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 42820 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 42821 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 42822 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 42823 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 42824 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 42825 | //BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2 |
|---|
| 42826 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 42827 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 42828 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 42829 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 42830 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 42831 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 42832 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 42833 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 42834 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 42835 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 42836 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 42837 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 42838 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 42839 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 42840 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 42841 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 42842 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 42843 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 42844 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 42845 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 42846 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 42847 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 42848 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 42849 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 42850 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 42851 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 42852 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 42853 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 42854 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 42855 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 42856 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 42857 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 42858 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 42859 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 42860 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 42861 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 42862 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 42863 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 42864 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 42865 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 42866 | //BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2 |
|---|
| 42867 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 42868 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 42869 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 42870 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 42871 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 42872 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 42873 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 42874 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 42875 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 42876 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 42877 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 42878 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 42879 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 42880 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 42881 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 42882 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 42883 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 42884 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 42885 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 42886 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 42887 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 42888 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 42889 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 42890 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 42891 | //BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS2 |
|---|
| 42892 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 42893 | #define BIF_CFG_DEV0_EPF0_VF20_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 42894 | //BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2 |
|---|
| 42895 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 42896 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 42897 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 42898 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 42899 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 42900 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 42901 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 42902 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 42903 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 42904 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 42905 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 42906 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 42907 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 42908 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 42909 | //BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2 |
|---|
| 42910 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 42911 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 42912 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 42913 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 42914 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 42915 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 42916 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 42917 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 42918 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 42919 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 42920 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 42921 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 42922 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 42923 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 42924 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 42925 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 42926 | //BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2 |
|---|
| 42927 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 42928 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 42929 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 42930 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 42931 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 42932 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 42933 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 42934 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 42935 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 42936 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 42937 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 42938 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 42939 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 42940 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 42941 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 42942 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 42943 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 42944 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 42945 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 42946 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 42947 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 42948 | #define BIF_CFG_DEV0_EPF0_VF20_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 42949 | //BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST |
|---|
| 42950 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 42951 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 42952 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 42953 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 42954 | //BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL |
|---|
| 42955 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 42956 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 42957 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 42958 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 42959 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 42960 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 42961 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 42962 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 42963 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 42964 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 42965 | //BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_LO |
|---|
| 42966 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 42967 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 42968 | //BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_HI |
|---|
| 42969 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 42970 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 42971 | //BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA |
|---|
| 42972 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 42973 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 42974 | //BIF_CFG_DEV0_EPF0_VF20_MSI_MASK |
|---|
| 42975 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 42976 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 42977 | //BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_64 |
|---|
| 42978 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 42979 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 42980 | //BIF_CFG_DEV0_EPF0_VF20_MSI_MASK_64 |
|---|
| 42981 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 42982 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 42983 | //BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING |
|---|
| 42984 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 42985 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 42986 | //BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_64 |
|---|
| 42987 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 42988 | #define BIF_CFG_DEV0_EPF0_VF20_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 42989 | //BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST |
|---|
| 42990 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 42991 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 42992 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 42993 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 42994 | //BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL |
|---|
| 42995 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 42996 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 42997 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 42998 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 42999 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 43000 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 43001 | //BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE |
|---|
| 43002 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 43003 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 43004 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 43005 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 43006 | //BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA |
|---|
| 43007 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 43008 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 43009 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 43010 | #define BIF_CFG_DEV0_EPF0_VF20_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 43011 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 43012 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 43013 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 43014 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 43015 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 43016 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 43017 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 43018 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 43019 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 43020 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 43021 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 43022 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 43023 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 43024 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 43025 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC1 |
|---|
| 43026 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 43027 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 43028 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC2 |
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| 43029 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 43030 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
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| 43031 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 43032 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 43033 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 43034 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 43035 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 43036 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 43037 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 43038 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS |
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| 43039 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 43040 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 43041 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 43042 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 43043 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 43044 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 43045 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 43046 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 43047 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 43048 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 43049 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 43050 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 43051 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 43052 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 43053 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 43054 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 43055 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 43056 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 43057 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 43058 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 43059 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 43060 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 43061 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 43062 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 43063 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 43064 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 43065 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 43066 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 43067 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 43068 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 43069 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 43070 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 43071 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK |
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| 43072 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 43073 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 43074 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 43075 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 43076 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 43077 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 43078 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 43079 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 43080 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 43081 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 43082 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 43083 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 43084 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 43085 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 43086 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 43087 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 43088 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 43089 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 43090 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 43091 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 43092 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 43093 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 43094 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 43095 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 43096 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 43097 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 43098 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 43099 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 43100 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 43101 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 43102 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 43103 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 43104 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY |
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| 43105 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 43106 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 43107 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 43108 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 43109 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 43110 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 43111 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 43112 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 43113 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 43114 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 43115 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 43116 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 43117 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 43118 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 43119 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 43120 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 43121 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 43122 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 43123 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 43124 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 43125 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 43126 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 43127 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 43128 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 43129 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 43130 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 43131 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 43132 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 43133 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 43134 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 43135 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 43136 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 43137 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS |
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| 43138 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 43139 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 43140 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 43141 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 43142 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 43143 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 43144 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 43145 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 43146 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 43147 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 43148 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 43149 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 43150 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 43151 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 43152 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 43153 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 43154 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK |
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| 43155 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 43156 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 43157 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 43158 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 43159 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 43160 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 43161 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 43162 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 43163 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 43164 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 43165 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 43166 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
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| 43167 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
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| 43168 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
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| 43169 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
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| 43170 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 43171 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL |
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| 43172 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 43173 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 43174 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 43175 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
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| 43176 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
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| 43177 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
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| 43178 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
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| 43179 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 43180 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 43181 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 43182 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 43183 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 43184 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 43185 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 43186 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 43187 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 43188 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 43189 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 43190 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG0 |
|---|
| 43191 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 43192 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 43193 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG1 |
|---|
| 43194 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 43195 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 43196 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG2 |
|---|
| 43197 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 43198 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 43199 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG3 |
|---|
| 43200 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 43201 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 43202 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG0 |
|---|
| 43203 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 43204 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 43205 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG1 |
|---|
| 43206 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 43207 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 43208 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG2 |
|---|
| 43209 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 43210 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 43211 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG3 |
|---|
| 43212 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 43213 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 43214 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST |
|---|
| 43215 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 43216 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 43217 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 43218 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 43219 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 43220 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 43221 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP |
|---|
| 43222 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 43223 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 43224 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 43225 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 43226 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 43227 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 43228 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL |
|---|
| 43229 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 43230 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 43231 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 43232 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 43233 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST |
|---|
| 43234 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 43235 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 43236 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 43237 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 43238 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 43239 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 43240 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP |
|---|
| 43241 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 43242 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 43243 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 43244 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 43245 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 43246 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 43247 | //BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL |
|---|
| 43248 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 43249 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 43250 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 43251 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 43252 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 43253 | #define BIF_CFG_DEV0_EPF0_VF20_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 43254 | |
|---|
| 43255 | |
|---|
| 43256 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp |
|---|
| 43257 | //BIF_CFG_DEV0_EPF0_VF21_VENDOR_ID |
|---|
| 43258 | #define BIF_CFG_DEV0_EPF0_VF21_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 43259 | #define BIF_CFG_DEV0_EPF0_VF21_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 43260 | //BIF_CFG_DEV0_EPF0_VF21_DEVICE_ID |
|---|
| 43261 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 43262 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 43263 | //BIF_CFG_DEV0_EPF0_VF21_COMMAND |
|---|
| 43264 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 43265 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 43266 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 43267 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 43268 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 43269 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 43270 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 43271 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 43272 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 43273 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 43274 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 43275 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 43276 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 43277 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 43278 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 43279 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 43280 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 43281 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 43282 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 43283 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 43284 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 43285 | #define BIF_CFG_DEV0_EPF0_VF21_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 43286 | //BIF_CFG_DEV0_EPF0_VF21_STATUS |
|---|
| 43287 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 43288 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 43289 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 43290 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 43291 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 43292 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 43293 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 43294 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 43295 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 43296 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 43297 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 43298 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 43299 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 43300 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 43301 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 43302 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 43303 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 43304 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 43305 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 43306 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 43307 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 43308 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 43309 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 43310 | #define BIF_CFG_DEV0_EPF0_VF21_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 43311 | //BIF_CFG_DEV0_EPF0_VF21_REVISION_ID |
|---|
| 43312 | #define BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 43313 | #define BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 43314 | #define BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 43315 | #define BIF_CFG_DEV0_EPF0_VF21_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 43316 | //BIF_CFG_DEV0_EPF0_VF21_PROG_INTERFACE |
|---|
| 43317 | #define BIF_CFG_DEV0_EPF0_VF21_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 43318 | #define BIF_CFG_DEV0_EPF0_VF21_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 43319 | //BIF_CFG_DEV0_EPF0_VF21_SUB_CLASS |
|---|
| 43320 | #define BIF_CFG_DEV0_EPF0_VF21_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 43321 | #define BIF_CFG_DEV0_EPF0_VF21_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 43322 | //BIF_CFG_DEV0_EPF0_VF21_BASE_CLASS |
|---|
| 43323 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 43324 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 43325 | //BIF_CFG_DEV0_EPF0_VF21_CACHE_LINE |
|---|
| 43326 | #define BIF_CFG_DEV0_EPF0_VF21_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 43327 | #define BIF_CFG_DEV0_EPF0_VF21_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 43328 | //BIF_CFG_DEV0_EPF0_VF21_LATENCY |
|---|
| 43329 | #define BIF_CFG_DEV0_EPF0_VF21_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 43330 | #define BIF_CFG_DEV0_EPF0_VF21_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 43331 | //BIF_CFG_DEV0_EPF0_VF21_HEADER |
|---|
| 43332 | #define 0x0 |
|---|
| 43333 | #define 0x7 |
|---|
| 43334 | #define 0x7FL |
|---|
| 43335 | #define 0x80L |
|---|
| 43336 | //BIF_CFG_DEV0_EPF0_VF21_BIST |
|---|
| 43337 | #define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 43338 | #define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 43339 | #define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 43340 | #define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 43341 | #define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_STRT_MASK 0x40L |
|---|
| 43342 | #define BIF_CFG_DEV0_EPF0_VF21_BIST__BIST_CAP_MASK 0x80L |
|---|
| 43343 | //BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_1 |
|---|
| 43344 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 43345 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 43346 | //BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_2 |
|---|
| 43347 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 43348 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 43349 | //BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_3 |
|---|
| 43350 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 43351 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 43352 | //BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_4 |
|---|
| 43353 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 43354 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 43355 | //BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_5 |
|---|
| 43356 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 43357 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 43358 | //BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_6 |
|---|
| 43359 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 43360 | #define BIF_CFG_DEV0_EPF0_VF21_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 43361 | //BIF_CFG_DEV0_EPF0_VF21_CARDBUS_CIS_PTR |
|---|
| 43362 | #define BIF_CFG_DEV0_EPF0_VF21_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 43363 | #define BIF_CFG_DEV0_EPF0_VF21_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 43364 | //BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID |
|---|
| 43365 | #define BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 43366 | #define BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 43367 | #define BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 43368 | #define BIF_CFG_DEV0_EPF0_VF21_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 43369 | //BIF_CFG_DEV0_EPF0_VF21_ROM_BASE_ADDR |
|---|
| 43370 | #define BIF_CFG_DEV0_EPF0_VF21_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 43371 | #define BIF_CFG_DEV0_EPF0_VF21_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 43372 | //BIF_CFG_DEV0_EPF0_VF21_CAP_PTR |
|---|
| 43373 | #define BIF_CFG_DEV0_EPF0_VF21_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 43374 | #define BIF_CFG_DEV0_EPF0_VF21_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 43375 | //BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_LINE |
|---|
| 43376 | #define BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 43377 | #define BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 43378 | //BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_PIN |
|---|
| 43379 | #define BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 43380 | #define BIF_CFG_DEV0_EPF0_VF21_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 43381 | //BIF_CFG_DEV0_EPF0_VF21_MIN_GRANT |
|---|
| 43382 | #define BIF_CFG_DEV0_EPF0_VF21_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 43383 | #define BIF_CFG_DEV0_EPF0_VF21_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 43384 | //BIF_CFG_DEV0_EPF0_VF21_MAX_LATENCY |
|---|
| 43385 | #define BIF_CFG_DEV0_EPF0_VF21_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 43386 | #define BIF_CFG_DEV0_EPF0_VF21_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 43387 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST |
|---|
| 43388 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 43389 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 43390 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 43391 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 43392 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP |
|---|
| 43393 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 43394 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 43395 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 43396 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 43397 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 43398 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 43399 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 43400 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 43401 | //BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP |
|---|
| 43402 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 43403 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 43404 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 43405 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 43406 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 43407 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 43408 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 43409 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 43410 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 43411 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 43412 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 43413 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 43414 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 43415 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 43416 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 43417 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 43418 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 43419 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 43420 | //BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL |
|---|
| 43421 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 43422 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 43423 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 43424 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 43425 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 43426 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 43427 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 43428 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 43429 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 43430 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 43431 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 43432 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 43433 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 43434 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 43435 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 43436 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 43437 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 43438 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 43439 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 43440 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 43441 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 43442 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 43443 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 43444 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 43445 | //BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS |
|---|
| 43446 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 43447 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 43448 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 43449 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 43450 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 43451 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 43452 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 43453 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 43454 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 43455 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 43456 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 43457 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 43458 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 43459 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 43460 | //BIF_CFG_DEV0_EPF0_VF21_LINK_CAP |
|---|
| 43461 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 43462 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 43463 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 43464 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 43465 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 43466 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 43467 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 43468 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 43469 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 43470 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 43471 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 43472 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 43473 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 43474 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 43475 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 43476 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 43477 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 43478 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 43479 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 43480 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 43481 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 43482 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 43483 | //BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL |
|---|
| 43484 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 43485 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 43486 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 43487 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 43488 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 43489 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 43490 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 43491 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 43492 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 43493 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 43494 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 43495 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 43496 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 43497 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 43498 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 43499 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 43500 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 43501 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 43502 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 43503 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 43504 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 43505 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 43506 | //BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS |
|---|
| 43507 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 43508 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 43509 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 43510 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 43511 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 43512 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 43513 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 43514 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 43515 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 43516 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 43517 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 43518 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 43519 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 43520 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 43521 | //BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2 |
|---|
| 43522 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 43523 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 43524 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 43525 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 43526 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 43527 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 43528 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 43529 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 43530 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 43531 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 43532 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 43533 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 43534 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 43535 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 43536 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 43537 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 43538 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 43539 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 43540 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 43541 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 43542 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 43543 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 43544 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 43545 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 43546 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 43547 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 43548 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 43549 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 43550 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 43551 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 43552 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 43553 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 43554 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 43555 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 43556 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 43557 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 43558 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 43559 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 43560 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 43561 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 43562 | //BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2 |
|---|
| 43563 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 43564 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 43565 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 43566 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 43567 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 43568 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 43569 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 43570 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 43571 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 43572 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 43573 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 43574 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 43575 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 43576 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 43577 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 43578 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 43579 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 43580 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 43581 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 43582 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 43583 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 43584 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 43585 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 43586 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 43587 | //BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS2 |
|---|
| 43588 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 43589 | #define BIF_CFG_DEV0_EPF0_VF21_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 43590 | //BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2 |
|---|
| 43591 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 43592 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 43593 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 43594 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 43595 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 43596 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 43597 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 43598 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 43599 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 43600 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 43601 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 43602 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 43603 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 43604 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 43605 | //BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2 |
|---|
| 43606 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 43607 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 43608 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 43609 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 43610 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 43611 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 43612 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 43613 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 43614 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 43615 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 43616 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 43617 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 43618 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 43619 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 43620 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 43621 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 43622 | //BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2 |
|---|
| 43623 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 43624 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 43625 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 43626 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 43627 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 43628 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 43629 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 43630 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 43631 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 43632 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 43633 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 43634 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 43635 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 43636 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 43637 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 43638 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 43639 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 43640 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 43641 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 43642 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 43643 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 43644 | #define BIF_CFG_DEV0_EPF0_VF21_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 43645 | //BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST |
|---|
| 43646 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 43647 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 43648 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 43649 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 43650 | //BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL |
|---|
| 43651 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 43652 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 43653 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 43654 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 43655 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 43656 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 43657 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 43658 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 43659 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 43660 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 43661 | //BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_LO |
|---|
| 43662 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 43663 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 43664 | //BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_HI |
|---|
| 43665 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 43666 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 43667 | //BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA |
|---|
| 43668 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 43669 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 43670 | //BIF_CFG_DEV0_EPF0_VF21_MSI_MASK |
|---|
| 43671 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 43672 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 43673 | //BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_64 |
|---|
| 43674 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 43675 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 43676 | //BIF_CFG_DEV0_EPF0_VF21_MSI_MASK_64 |
|---|
| 43677 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 43678 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 43679 | //BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING |
|---|
| 43680 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 43681 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 43682 | //BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_64 |
|---|
| 43683 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 43684 | #define BIF_CFG_DEV0_EPF0_VF21_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 43685 | //BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST |
|---|
| 43686 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 43687 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 43688 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 43689 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 43690 | //BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL |
|---|
| 43691 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 43692 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 43693 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 43694 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 43695 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 43696 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 43697 | //BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE |
|---|
| 43698 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 43699 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 43700 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 43701 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 43702 | //BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA |
|---|
| 43703 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 43704 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 43705 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 43706 | #define BIF_CFG_DEV0_EPF0_VF21_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 43707 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 43708 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 43709 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 43710 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 43711 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 43712 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 43713 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 43714 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 43715 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 43716 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 43717 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 43718 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 43719 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 43720 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 43721 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC1 |
|---|
| 43722 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 43723 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 43724 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC2 |
|---|
| 43725 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 43726 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 43727 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 43728 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 43729 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 43730 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 43731 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 43732 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 43733 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 43734 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS |
|---|
| 43735 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 43736 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 43737 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 43738 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 43739 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 43740 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 43741 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 43742 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 43743 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 43744 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 43745 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 43746 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 43747 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 43748 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 43749 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 43750 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 43751 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 43752 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 43753 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 43754 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 43755 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 43756 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 43757 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 43758 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 43759 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 43760 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 43761 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 43762 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 43763 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 43764 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 43765 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 43766 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 43767 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK |
|---|
| 43768 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 43769 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 43770 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 43771 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 43772 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 43773 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 43774 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 43775 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 43776 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 43777 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 43778 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 43779 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 43780 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 43781 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 43782 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 43783 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 43784 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 43785 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 43786 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 43787 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 43788 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 43789 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 43790 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 43791 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 43792 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 43793 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 43794 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 43795 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 43796 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 43797 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 43798 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 43799 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 43800 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 43801 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 43802 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 43803 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 43804 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 43805 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 43806 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 43807 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 43808 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 43809 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 43810 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 43811 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 43812 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 43813 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 43814 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 43815 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 43816 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 43817 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 43818 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 43819 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 43820 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 43821 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 43822 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 43823 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 43824 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 43825 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 43826 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 43827 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 43828 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 43829 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 43830 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 43831 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 43832 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 43833 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS |
|---|
| 43834 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 43835 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 43836 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 43837 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 43838 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 43839 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 43840 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 43841 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 43842 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 43843 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 43844 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 43845 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 43846 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 43847 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 43848 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 43849 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 43850 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK |
|---|
| 43851 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 43852 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 43853 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 43854 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 43855 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 43856 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 43857 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 43858 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 43859 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 43860 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 43861 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 43862 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 43863 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 43864 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 43865 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 43866 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 43867 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 43868 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 43869 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 43870 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 43871 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 43872 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 43873 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 43874 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 43875 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 43876 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 43877 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 43878 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 43879 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 43880 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 43881 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 43882 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 43883 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 43884 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 43885 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 43886 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG0 |
|---|
| 43887 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 43888 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 43889 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG1 |
|---|
| 43890 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 43891 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 43892 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG2 |
|---|
| 43893 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 43894 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 43895 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG3 |
|---|
| 43896 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 43897 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 43898 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG0 |
|---|
| 43899 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 43900 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 43901 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG1 |
|---|
| 43902 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 43903 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 43904 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG2 |
|---|
| 43905 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 43906 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 43907 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG3 |
|---|
| 43908 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 43909 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 43910 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST |
|---|
| 43911 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 43912 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 43913 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 43914 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 43915 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 43916 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 43917 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP |
|---|
| 43918 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 43919 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 43920 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 43921 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 43922 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 43923 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 43924 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL |
|---|
| 43925 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 43926 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 43927 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 43928 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 43929 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST |
|---|
| 43930 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 43931 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 43932 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 43933 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 43934 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 43935 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 43936 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP |
|---|
| 43937 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 43938 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 43939 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 43940 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 43941 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 43942 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 43943 | //BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL |
|---|
| 43944 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 43945 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 43946 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 43947 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 43948 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 43949 | #define BIF_CFG_DEV0_EPF0_VF21_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 43950 | |
|---|
| 43951 | |
|---|
| 43952 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp |
|---|
| 43953 | //BIF_CFG_DEV0_EPF0_VF22_VENDOR_ID |
|---|
| 43954 | #define BIF_CFG_DEV0_EPF0_VF22_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 43955 | #define BIF_CFG_DEV0_EPF0_VF22_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 43956 | //BIF_CFG_DEV0_EPF0_VF22_DEVICE_ID |
|---|
| 43957 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 43958 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 43959 | //BIF_CFG_DEV0_EPF0_VF22_COMMAND |
|---|
| 43960 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 43961 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 43962 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 43963 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 43964 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 43965 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 43966 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 43967 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 43968 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 43969 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 43970 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 43971 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 43972 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 43973 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 43974 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 43975 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 43976 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 43977 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 43978 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 43979 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 43980 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 43981 | #define BIF_CFG_DEV0_EPF0_VF22_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 43982 | //BIF_CFG_DEV0_EPF0_VF22_STATUS |
|---|
| 43983 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 43984 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 43985 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 43986 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 43987 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 43988 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 43989 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 43990 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 43991 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 43992 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 43993 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 43994 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 43995 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 43996 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 43997 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 43998 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 43999 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 44000 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 44001 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 44002 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 44003 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 44004 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 44005 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 44006 | #define BIF_CFG_DEV0_EPF0_VF22_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 44007 | //BIF_CFG_DEV0_EPF0_VF22_REVISION_ID |
|---|
| 44008 | #define BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 44009 | #define BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 44010 | #define BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 44011 | #define BIF_CFG_DEV0_EPF0_VF22_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 44012 | //BIF_CFG_DEV0_EPF0_VF22_PROG_INTERFACE |
|---|
| 44013 | #define BIF_CFG_DEV0_EPF0_VF22_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 44014 | #define BIF_CFG_DEV0_EPF0_VF22_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 44015 | //BIF_CFG_DEV0_EPF0_VF22_SUB_CLASS |
|---|
| 44016 | #define BIF_CFG_DEV0_EPF0_VF22_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 44017 | #define BIF_CFG_DEV0_EPF0_VF22_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 44018 | //BIF_CFG_DEV0_EPF0_VF22_BASE_CLASS |
|---|
| 44019 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 44020 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 44021 | //BIF_CFG_DEV0_EPF0_VF22_CACHE_LINE |
|---|
| 44022 | #define BIF_CFG_DEV0_EPF0_VF22_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 44023 | #define BIF_CFG_DEV0_EPF0_VF22_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 44024 | //BIF_CFG_DEV0_EPF0_VF22_LATENCY |
|---|
| 44025 | #define BIF_CFG_DEV0_EPF0_VF22_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 44026 | #define BIF_CFG_DEV0_EPF0_VF22_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 44027 | //BIF_CFG_DEV0_EPF0_VF22_HEADER |
|---|
| 44028 | #define 0x0 |
|---|
| 44029 | #define 0x7 |
|---|
| 44030 | #define 0x7FL |
|---|
| 44031 | #define 0x80L |
|---|
| 44032 | //BIF_CFG_DEV0_EPF0_VF22_BIST |
|---|
| 44033 | #define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 44034 | #define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 44035 | #define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 44036 | #define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 44037 | #define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_STRT_MASK 0x40L |
|---|
| 44038 | #define BIF_CFG_DEV0_EPF0_VF22_BIST__BIST_CAP_MASK 0x80L |
|---|
| 44039 | //BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_1 |
|---|
| 44040 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 44041 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44042 | //BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_2 |
|---|
| 44043 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 44044 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44045 | //BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_3 |
|---|
| 44046 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 44047 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44048 | //BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_4 |
|---|
| 44049 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 44050 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44051 | //BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_5 |
|---|
| 44052 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 44053 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44054 | //BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_6 |
|---|
| 44055 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 44056 | #define BIF_CFG_DEV0_EPF0_VF22_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44057 | //BIF_CFG_DEV0_EPF0_VF22_CARDBUS_CIS_PTR |
|---|
| 44058 | #define BIF_CFG_DEV0_EPF0_VF22_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 44059 | #define BIF_CFG_DEV0_EPF0_VF22_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 44060 | //BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID |
|---|
| 44061 | #define BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 44062 | #define BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 44063 | #define BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 44064 | #define BIF_CFG_DEV0_EPF0_VF22_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 44065 | //BIF_CFG_DEV0_EPF0_VF22_ROM_BASE_ADDR |
|---|
| 44066 | #define BIF_CFG_DEV0_EPF0_VF22_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 44067 | #define BIF_CFG_DEV0_EPF0_VF22_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44068 | //BIF_CFG_DEV0_EPF0_VF22_CAP_PTR |
|---|
| 44069 | #define BIF_CFG_DEV0_EPF0_VF22_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 44070 | #define BIF_CFG_DEV0_EPF0_VF22_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 44071 | //BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_LINE |
|---|
| 44072 | #define BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 44073 | #define BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 44074 | //BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_PIN |
|---|
| 44075 | #define BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 44076 | #define BIF_CFG_DEV0_EPF0_VF22_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 44077 | //BIF_CFG_DEV0_EPF0_VF22_MIN_GRANT |
|---|
| 44078 | #define BIF_CFG_DEV0_EPF0_VF22_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 44079 | #define BIF_CFG_DEV0_EPF0_VF22_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 44080 | //BIF_CFG_DEV0_EPF0_VF22_MAX_LATENCY |
|---|
| 44081 | #define BIF_CFG_DEV0_EPF0_VF22_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 44082 | #define BIF_CFG_DEV0_EPF0_VF22_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 44083 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST |
|---|
| 44084 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 44085 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 44086 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 44087 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 44088 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP |
|---|
| 44089 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 44090 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 44091 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 44092 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 44093 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 44094 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 44095 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 44096 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 44097 | //BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP |
|---|
| 44098 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 44099 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 44100 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 44101 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 44102 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 44103 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 44104 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 44105 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 44106 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 44107 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 44108 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 44109 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 44110 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 44111 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 44112 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 44113 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 44114 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 44115 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 44116 | //BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL |
|---|
| 44117 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 44118 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 44119 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 44120 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 44121 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 44122 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 44123 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 44124 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 44125 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 44126 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 44127 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 44128 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 44129 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 44130 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 44131 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 44132 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 44133 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 44134 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 44135 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 44136 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 44137 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 44138 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 44139 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 44140 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 44141 | //BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS |
|---|
| 44142 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 44143 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 44144 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 44145 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 44146 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 44147 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 44148 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 44149 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 44150 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 44151 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 44152 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 44153 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 44154 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 44155 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 44156 | //BIF_CFG_DEV0_EPF0_VF22_LINK_CAP |
|---|
| 44157 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 44158 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 44159 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 44160 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 44161 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 44162 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 44163 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 44164 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 44165 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 44166 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 44167 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 44168 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 44169 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 44170 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 44171 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 44172 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 44173 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 44174 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 44175 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 44176 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 44177 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 44178 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 44179 | //BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL |
|---|
| 44180 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 44181 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 44182 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 44183 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 44184 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 44185 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 44186 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 44187 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 44188 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 44189 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 44190 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 44191 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 44192 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 44193 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 44194 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 44195 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 44196 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 44197 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 44198 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 44199 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 44200 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 44201 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 44202 | //BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS |
|---|
| 44203 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 44204 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 44205 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 44206 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 44207 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 44208 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 44209 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 44210 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 44211 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 44212 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 44213 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 44214 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 44215 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 44216 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 44217 | //BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2 |
|---|
| 44218 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 44219 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 44220 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 44221 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 44222 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 44223 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 44224 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 44225 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 44226 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 44227 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 44228 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 44229 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 44230 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 44231 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 44232 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 44233 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 44234 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 44235 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 44236 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 44237 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 44238 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 44239 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 44240 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 44241 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 44242 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 44243 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 44244 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 44245 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 44246 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 44247 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 44248 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 44249 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 44250 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 44251 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 44252 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 44253 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 44254 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 44255 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 44256 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 44257 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 44258 | //BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2 |
|---|
| 44259 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 44260 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 44261 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 44262 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 44263 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 44264 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 44265 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 44266 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 44267 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 44268 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 44269 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 44270 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 44271 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 44272 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 44273 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 44274 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 44275 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 44276 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 44277 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 44278 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 44279 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 44280 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 44281 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 44282 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 44283 | //BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS2 |
|---|
| 44284 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 44285 | #define BIF_CFG_DEV0_EPF0_VF22_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 44286 | //BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2 |
|---|
| 44287 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 44288 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 44289 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 44290 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 44291 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 44292 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 44293 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 44294 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 44295 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 44296 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 44297 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 44298 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 44299 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 44300 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 44301 | //BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2 |
|---|
| 44302 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 44303 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 44304 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 44305 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 44306 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 44307 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 44308 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 44309 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 44310 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 44311 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 44312 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 44313 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 44314 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 44315 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 44316 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 44317 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 44318 | //BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2 |
|---|
| 44319 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 44320 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 44321 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 44322 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 44323 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 44324 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 44325 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 44326 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 44327 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 44328 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 44329 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 44330 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 44331 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 44332 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 44333 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 44334 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 44335 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 44336 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 44337 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 44338 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 44339 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 44340 | #define BIF_CFG_DEV0_EPF0_VF22_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 44341 | //BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST |
|---|
| 44342 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 44343 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 44344 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 44345 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 44346 | //BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL |
|---|
| 44347 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 44348 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 44349 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 44350 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 44351 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 44352 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 44353 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 44354 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 44355 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 44356 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 44357 | //BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_LO |
|---|
| 44358 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 44359 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 44360 | //BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_HI |
|---|
| 44361 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 44362 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 44363 | //BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA |
|---|
| 44364 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 44365 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 44366 | //BIF_CFG_DEV0_EPF0_VF22_MSI_MASK |
|---|
| 44367 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 44368 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 44369 | //BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_64 |
|---|
| 44370 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 44371 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 44372 | //BIF_CFG_DEV0_EPF0_VF22_MSI_MASK_64 |
|---|
| 44373 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 44374 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 44375 | //BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING |
|---|
| 44376 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 44377 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 44378 | //BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_64 |
|---|
| 44379 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 44380 | #define BIF_CFG_DEV0_EPF0_VF22_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 44381 | //BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST |
|---|
| 44382 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 44383 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 44384 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 44385 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 44386 | //BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL |
|---|
| 44387 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 44388 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 44389 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 44390 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 44391 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 44392 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 44393 | //BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE |
|---|
| 44394 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 44395 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 44396 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 44397 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 44398 | //BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA |
|---|
| 44399 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 44400 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 44401 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 44402 | #define BIF_CFG_DEV0_EPF0_VF22_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 44403 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 44404 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 44405 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 44406 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 44407 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 44408 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 44409 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 44410 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 44411 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 44412 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 44413 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 44414 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 44415 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 44416 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 44417 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC1 |
|---|
| 44418 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 44419 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 44420 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC2 |
|---|
| 44421 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 44422 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 44423 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 44424 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 44425 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 44426 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 44427 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 44428 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 44429 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 44430 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS |
|---|
| 44431 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 44432 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 44433 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 44434 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 44435 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 44436 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 44437 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 44438 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 44439 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 44440 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 44441 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 44442 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 44443 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 44444 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 44445 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 44446 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 44447 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 44448 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 44449 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 44450 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 44451 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 44452 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 44453 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 44454 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 44455 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 44456 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 44457 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 44458 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 44459 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 44460 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 44461 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 44462 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 44463 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK |
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| 44464 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 44465 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 44466 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 44467 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 44468 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 44469 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 44470 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 44471 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 44472 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 44473 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 44474 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 44475 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 44476 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 44477 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 44478 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 44479 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 44480 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 44481 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 44482 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 44483 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 44484 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 44485 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 44486 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 44487 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 44488 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 44489 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 44490 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 44491 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 44492 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 44493 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 44494 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 44495 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 44496 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY |
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| 44497 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 44498 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 44499 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 44500 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 44501 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 44502 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 44503 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 44504 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 44505 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 44506 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 44507 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 44508 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 44509 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 44510 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 44511 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 44512 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 44513 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 44514 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 44515 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 44516 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 44517 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 44518 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 44519 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 44520 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 44521 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 44522 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 44523 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 44524 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 44525 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 44526 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 44527 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 44528 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 44529 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS |
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| 44530 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 44531 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 44532 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 44533 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 44534 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 44535 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 44536 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 44537 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 44538 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 44539 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 44540 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 44541 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 44542 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 44543 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 44544 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 44545 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 44546 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK |
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| 44547 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 44548 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 44549 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 44550 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 44551 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 44552 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 44553 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 44554 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 44555 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 44556 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 44557 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 44558 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
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| 44559 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
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| 44560 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
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| 44561 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
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| 44562 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 44563 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL |
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| 44564 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 44565 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 44566 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 44567 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
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| 44568 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 44569 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
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| 44570 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
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| 44571 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
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| 44572 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
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| 44573 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
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| 44574 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
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| 44575 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
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| 44576 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
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| 44577 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
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| 44578 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
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| 44579 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
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| 44580 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
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| 44581 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
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| 44582 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG0 |
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| 44583 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 44584 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 44585 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG1 |
|---|
| 44586 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 44587 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 44588 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG2 |
|---|
| 44589 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 44590 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 44591 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG3 |
|---|
| 44592 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 44593 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 44594 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG0 |
|---|
| 44595 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 44596 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 44597 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG1 |
|---|
| 44598 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 44599 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 44600 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG2 |
|---|
| 44601 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 44602 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 44603 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG3 |
|---|
| 44604 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 44605 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 44606 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST |
|---|
| 44607 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 44608 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 44609 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 44610 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 44611 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 44612 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 44613 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP |
|---|
| 44614 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 44615 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 44616 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 44617 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 44618 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 44619 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 44620 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL |
|---|
| 44621 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 44622 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 44623 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 44624 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 44625 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST |
|---|
| 44626 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 44627 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 44628 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 44629 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 44630 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 44631 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 44632 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP |
|---|
| 44633 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 44634 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 44635 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 44636 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 44637 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 44638 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 44639 | //BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL |
|---|
| 44640 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 44641 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 44642 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 44643 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 44644 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 44645 | #define BIF_CFG_DEV0_EPF0_VF22_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 44646 | |
|---|
| 44647 | |
|---|
| 44648 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp |
|---|
| 44649 | //BIF_CFG_DEV0_EPF0_VF23_VENDOR_ID |
|---|
| 44650 | #define BIF_CFG_DEV0_EPF0_VF23_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 44651 | #define BIF_CFG_DEV0_EPF0_VF23_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 44652 | //BIF_CFG_DEV0_EPF0_VF23_DEVICE_ID |
|---|
| 44653 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 44654 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 44655 | //BIF_CFG_DEV0_EPF0_VF23_COMMAND |
|---|
| 44656 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 44657 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 44658 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 44659 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 44660 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 44661 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 44662 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 44663 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 44664 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 44665 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 44666 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 44667 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 44668 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 44669 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 44670 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 44671 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 44672 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 44673 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 44674 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 44675 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 44676 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 44677 | #define BIF_CFG_DEV0_EPF0_VF23_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 44678 | //BIF_CFG_DEV0_EPF0_VF23_STATUS |
|---|
| 44679 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 44680 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 44681 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 44682 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 44683 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 44684 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 44685 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 44686 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 44687 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 44688 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 44689 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 44690 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 44691 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 44692 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 44693 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 44694 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 44695 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 44696 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 44697 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 44698 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 44699 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 44700 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 44701 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 44702 | #define BIF_CFG_DEV0_EPF0_VF23_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 44703 | //BIF_CFG_DEV0_EPF0_VF23_REVISION_ID |
|---|
| 44704 | #define BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 44705 | #define BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 44706 | #define BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 44707 | #define BIF_CFG_DEV0_EPF0_VF23_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 44708 | //BIF_CFG_DEV0_EPF0_VF23_PROG_INTERFACE |
|---|
| 44709 | #define BIF_CFG_DEV0_EPF0_VF23_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 44710 | #define BIF_CFG_DEV0_EPF0_VF23_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 44711 | //BIF_CFG_DEV0_EPF0_VF23_SUB_CLASS |
|---|
| 44712 | #define BIF_CFG_DEV0_EPF0_VF23_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 44713 | #define BIF_CFG_DEV0_EPF0_VF23_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 44714 | //BIF_CFG_DEV0_EPF0_VF23_BASE_CLASS |
|---|
| 44715 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 44716 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 44717 | //BIF_CFG_DEV0_EPF0_VF23_CACHE_LINE |
|---|
| 44718 | #define BIF_CFG_DEV0_EPF0_VF23_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 44719 | #define BIF_CFG_DEV0_EPF0_VF23_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 44720 | //BIF_CFG_DEV0_EPF0_VF23_LATENCY |
|---|
| 44721 | #define BIF_CFG_DEV0_EPF0_VF23_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 44722 | #define BIF_CFG_DEV0_EPF0_VF23_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 44723 | //BIF_CFG_DEV0_EPF0_VF23_HEADER |
|---|
| 44724 | #define 0x0 |
|---|
| 44725 | #define 0x7 |
|---|
| 44726 | #define 0x7FL |
|---|
| 44727 | #define 0x80L |
|---|
| 44728 | //BIF_CFG_DEV0_EPF0_VF23_BIST |
|---|
| 44729 | #define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 44730 | #define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 44731 | #define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 44732 | #define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 44733 | #define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_STRT_MASK 0x40L |
|---|
| 44734 | #define BIF_CFG_DEV0_EPF0_VF23_BIST__BIST_CAP_MASK 0x80L |
|---|
| 44735 | //BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_1 |
|---|
| 44736 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 44737 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44738 | //BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_2 |
|---|
| 44739 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 44740 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44741 | //BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_3 |
|---|
| 44742 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 44743 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44744 | //BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_4 |
|---|
| 44745 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 44746 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44747 | //BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_5 |
|---|
| 44748 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 44749 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44750 | //BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_6 |
|---|
| 44751 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 44752 | #define BIF_CFG_DEV0_EPF0_VF23_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44753 | //BIF_CFG_DEV0_EPF0_VF23_CARDBUS_CIS_PTR |
|---|
| 44754 | #define BIF_CFG_DEV0_EPF0_VF23_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 44755 | #define BIF_CFG_DEV0_EPF0_VF23_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 44756 | //BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID |
|---|
| 44757 | #define BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 44758 | #define BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 44759 | #define BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 44760 | #define BIF_CFG_DEV0_EPF0_VF23_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 44761 | //BIF_CFG_DEV0_EPF0_VF23_ROM_BASE_ADDR |
|---|
| 44762 | #define BIF_CFG_DEV0_EPF0_VF23_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 44763 | #define BIF_CFG_DEV0_EPF0_VF23_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 44764 | //BIF_CFG_DEV0_EPF0_VF23_CAP_PTR |
|---|
| 44765 | #define BIF_CFG_DEV0_EPF0_VF23_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 44766 | #define BIF_CFG_DEV0_EPF0_VF23_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 44767 | //BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_LINE |
|---|
| 44768 | #define BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 44769 | #define BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 44770 | //BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_PIN |
|---|
| 44771 | #define BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 44772 | #define BIF_CFG_DEV0_EPF0_VF23_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 44773 | //BIF_CFG_DEV0_EPF0_VF23_MIN_GRANT |
|---|
| 44774 | #define BIF_CFG_DEV0_EPF0_VF23_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 44775 | #define BIF_CFG_DEV0_EPF0_VF23_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 44776 | //BIF_CFG_DEV0_EPF0_VF23_MAX_LATENCY |
|---|
| 44777 | #define BIF_CFG_DEV0_EPF0_VF23_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 44778 | #define BIF_CFG_DEV0_EPF0_VF23_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 44779 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST |
|---|
| 44780 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 44781 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 44782 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 44783 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 44784 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP |
|---|
| 44785 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 44786 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 44787 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 44788 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 44789 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 44790 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 44791 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 44792 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 44793 | //BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP |
|---|
| 44794 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 44795 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 44796 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 44797 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 44798 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 44799 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 44800 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 44801 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 44802 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 44803 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 44804 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 44805 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 44806 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 44807 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 44808 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 44809 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 44810 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 44811 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 44812 | //BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL |
|---|
| 44813 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 44814 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 44815 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 44816 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 44817 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 44818 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 44819 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 44820 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 44821 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 44822 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 44823 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 44824 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 44825 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 44826 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 44827 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 44828 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 44829 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 44830 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 44831 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 44832 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 44833 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 44834 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 44835 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 44836 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 44837 | //BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS |
|---|
| 44838 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 44839 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 44840 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 44841 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 44842 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 44843 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 44844 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 44845 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 44846 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 44847 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 44848 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 44849 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 44850 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 44851 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 44852 | //BIF_CFG_DEV0_EPF0_VF23_LINK_CAP |
|---|
| 44853 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 44854 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 44855 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 44856 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 44857 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 44858 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 44859 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 44860 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 44861 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 44862 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 44863 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 44864 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 44865 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 44866 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 44867 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 44868 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 44869 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 44870 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 44871 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 44872 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 44873 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 44874 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 44875 | //BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL |
|---|
| 44876 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 44877 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 44878 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 44879 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 44880 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 44881 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 44882 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 44883 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 44884 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 44885 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 44886 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 44887 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 44888 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 44889 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 44890 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 44891 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 44892 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 44893 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 44894 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 44895 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 44896 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 44897 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 44898 | //BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS |
|---|
| 44899 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 44900 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 44901 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 44902 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 44903 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 44904 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 44905 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 44906 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 44907 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 44908 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 44909 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 44910 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 44911 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 44912 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 44913 | //BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2 |
|---|
| 44914 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 44915 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 44916 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 44917 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 44918 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 44919 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 44920 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 44921 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 44922 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 44923 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 44924 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 44925 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 44926 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 44927 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 44928 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 44929 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 44930 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 44931 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 44932 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 44933 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 44934 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 44935 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 44936 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 44937 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 44938 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 44939 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 44940 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 44941 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 44942 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 44943 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 44944 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 44945 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 44946 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 44947 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 44948 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 44949 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 44950 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 44951 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 44952 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 44953 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 44954 | //BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2 |
|---|
| 44955 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 44956 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 44957 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 44958 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 44959 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 44960 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 44961 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 44962 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 44963 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 44964 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 44965 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 44966 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 44967 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 44968 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 44969 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 44970 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 44971 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 44972 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 44973 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 44974 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 44975 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 44976 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 44977 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 44978 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 44979 | //BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS2 |
|---|
| 44980 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 44981 | #define BIF_CFG_DEV0_EPF0_VF23_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 44982 | //BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2 |
|---|
| 44983 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 44984 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 44985 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 44986 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 44987 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 44988 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 44989 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 44990 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 44991 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 44992 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 44993 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 44994 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 44995 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 44996 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 44997 | //BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2 |
|---|
| 44998 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 44999 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 45000 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 45001 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 45002 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 45003 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 45004 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 45005 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 45006 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 45007 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 45008 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 45009 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 45010 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 45011 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 45012 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 45013 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 45014 | //BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2 |
|---|
| 45015 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 45016 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 45017 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 45018 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 45019 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 45020 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 45021 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 45022 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 45023 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 45024 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 45025 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 45026 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 45027 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 45028 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 45029 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 45030 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 45031 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 45032 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 45033 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 45034 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 45035 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 45036 | #define BIF_CFG_DEV0_EPF0_VF23_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 45037 | //BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST |
|---|
| 45038 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45039 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 45040 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 45041 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 45042 | //BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL |
|---|
| 45043 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 45044 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 45045 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 45046 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 45047 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 45048 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 45049 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 45050 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 45051 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 45052 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 45053 | //BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_LO |
|---|
| 45054 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 45055 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 45056 | //BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_HI |
|---|
| 45057 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 45058 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 45059 | //BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA |
|---|
| 45060 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 45061 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 45062 | //BIF_CFG_DEV0_EPF0_VF23_MSI_MASK |
|---|
| 45063 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 45064 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 45065 | //BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_64 |
|---|
| 45066 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 45067 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 45068 | //BIF_CFG_DEV0_EPF0_VF23_MSI_MASK_64 |
|---|
| 45069 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 45070 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 45071 | //BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING |
|---|
| 45072 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 45073 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 45074 | //BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_64 |
|---|
| 45075 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 45076 | #define BIF_CFG_DEV0_EPF0_VF23_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 45077 | //BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST |
|---|
| 45078 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45079 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 45080 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 45081 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 45082 | //BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL |
|---|
| 45083 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 45084 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 45085 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 45086 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 45087 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 45088 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 45089 | //BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE |
|---|
| 45090 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 45091 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 45092 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 45093 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 45094 | //BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA |
|---|
| 45095 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 45096 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 45097 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 45098 | #define BIF_CFG_DEV0_EPF0_VF23_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 45099 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 45100 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45101 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 45102 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 45103 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 45104 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 45105 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 45106 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 45107 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 45108 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 45109 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 45110 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 45111 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 45112 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 45113 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC1 |
|---|
| 45114 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 45115 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 45116 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC2 |
|---|
| 45117 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 45118 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 45119 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 45120 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45121 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 45122 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 45123 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 45124 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 45125 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 45126 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS |
|---|
| 45127 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 45128 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 45129 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 45130 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 45131 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 45132 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 45133 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 45134 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 45135 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 45136 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 45137 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 45138 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 45139 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 45140 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 45141 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 45142 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 45143 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 45144 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 45145 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 45146 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 45147 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 45148 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 45149 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 45150 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 45151 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 45152 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 45153 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 45154 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 45155 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 45156 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 45157 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 45158 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 45159 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK |
|---|
| 45160 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 45161 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 45162 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 45163 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 45164 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 45165 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 45166 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 45167 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 45168 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 45169 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 45170 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 45171 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 45172 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 45173 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 45174 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 45175 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 45176 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 45177 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 45178 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 45179 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 45180 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 45181 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 45182 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 45183 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 45184 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 45185 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 45186 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 45187 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 45188 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 45189 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 45190 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 45191 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 45192 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 45193 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 45194 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 45195 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 45196 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 45197 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 45198 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 45199 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 45200 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 45201 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 45202 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 45203 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 45204 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 45205 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 45206 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 45207 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 45208 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 45209 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 45210 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 45211 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 45212 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 45213 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 45214 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 45215 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 45216 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 45217 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 45218 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 45219 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 45220 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 45221 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 45222 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 45223 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 45224 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 45225 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS |
|---|
| 45226 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 45227 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 45228 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 45229 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 45230 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 45231 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 45232 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 45233 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 45234 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 45235 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 45236 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 45237 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 45238 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 45239 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 45240 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 45241 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 45242 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK |
|---|
| 45243 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 45244 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 45245 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 45246 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 45247 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 45248 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 45249 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 45250 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 45251 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 45252 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 45253 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 45254 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 45255 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 45256 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 45257 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 45258 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 45259 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 45260 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 45261 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 45262 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 45263 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 45264 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 45265 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 45266 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 45267 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 45268 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 45269 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 45270 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 45271 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 45272 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 45273 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 45274 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 45275 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 45276 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 45277 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 45278 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG0 |
|---|
| 45279 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 45280 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 45281 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG1 |
|---|
| 45282 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 45283 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 45284 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG2 |
|---|
| 45285 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 45286 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 45287 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG3 |
|---|
| 45288 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 45289 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 45290 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG0 |
|---|
| 45291 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 45292 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 45293 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG1 |
|---|
| 45294 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 45295 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 45296 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG2 |
|---|
| 45297 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 45298 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 45299 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG3 |
|---|
| 45300 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 45301 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 45302 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST |
|---|
| 45303 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45304 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 45305 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 45306 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 45307 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 45308 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 45309 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP |
|---|
| 45310 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 45311 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 45312 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 45313 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 45314 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 45315 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 45316 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL |
|---|
| 45317 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 45318 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 45319 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 45320 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 45321 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST |
|---|
| 45322 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45323 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 45324 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 45325 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 45326 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 45327 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 45328 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP |
|---|
| 45329 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 45330 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 45331 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 45332 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 45333 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 45334 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 45335 | //BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL |
|---|
| 45336 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 45337 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 45338 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 45339 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 45340 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 45341 | #define BIF_CFG_DEV0_EPF0_VF23_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 45342 | |
|---|
| 45343 | |
|---|
| 45344 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp |
|---|
| 45345 | //BIF_CFG_DEV0_EPF0_VF24_VENDOR_ID |
|---|
| 45346 | #define BIF_CFG_DEV0_EPF0_VF24_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 45347 | #define BIF_CFG_DEV0_EPF0_VF24_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 45348 | //BIF_CFG_DEV0_EPF0_VF24_DEVICE_ID |
|---|
| 45349 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 45350 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 45351 | //BIF_CFG_DEV0_EPF0_VF24_COMMAND |
|---|
| 45352 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 45353 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 45354 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 45355 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 45356 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 45357 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 45358 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 45359 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 45360 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 45361 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 45362 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 45363 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 45364 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 45365 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 45366 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 45367 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 45368 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 45369 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 45370 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 45371 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 45372 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 45373 | #define BIF_CFG_DEV0_EPF0_VF24_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 45374 | //BIF_CFG_DEV0_EPF0_VF24_STATUS |
|---|
| 45375 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 45376 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 45377 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 45378 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 45379 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 45380 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 45381 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 45382 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 45383 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 45384 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 45385 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 45386 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 45387 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 45388 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 45389 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 45390 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 45391 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 45392 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 45393 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 45394 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 45395 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 45396 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 45397 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 45398 | #define BIF_CFG_DEV0_EPF0_VF24_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 45399 | //BIF_CFG_DEV0_EPF0_VF24_REVISION_ID |
|---|
| 45400 | #define BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 45401 | #define BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 45402 | #define BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 45403 | #define BIF_CFG_DEV0_EPF0_VF24_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 45404 | //BIF_CFG_DEV0_EPF0_VF24_PROG_INTERFACE |
|---|
| 45405 | #define BIF_CFG_DEV0_EPF0_VF24_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 45406 | #define BIF_CFG_DEV0_EPF0_VF24_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 45407 | //BIF_CFG_DEV0_EPF0_VF24_SUB_CLASS |
|---|
| 45408 | #define BIF_CFG_DEV0_EPF0_VF24_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 45409 | #define BIF_CFG_DEV0_EPF0_VF24_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 45410 | //BIF_CFG_DEV0_EPF0_VF24_BASE_CLASS |
|---|
| 45411 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 45412 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 45413 | //BIF_CFG_DEV0_EPF0_VF24_CACHE_LINE |
|---|
| 45414 | #define BIF_CFG_DEV0_EPF0_VF24_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 45415 | #define BIF_CFG_DEV0_EPF0_VF24_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 45416 | //BIF_CFG_DEV0_EPF0_VF24_LATENCY |
|---|
| 45417 | #define BIF_CFG_DEV0_EPF0_VF24_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 45418 | #define BIF_CFG_DEV0_EPF0_VF24_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 45419 | //BIF_CFG_DEV0_EPF0_VF24_HEADER |
|---|
| 45420 | #define 0x0 |
|---|
| 45421 | #define 0x7 |
|---|
| 45422 | #define 0x7FL |
|---|
| 45423 | #define 0x80L |
|---|
| 45424 | //BIF_CFG_DEV0_EPF0_VF24_BIST |
|---|
| 45425 | #define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 45426 | #define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 45427 | #define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 45428 | #define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 45429 | #define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_STRT_MASK 0x40L |
|---|
| 45430 | #define BIF_CFG_DEV0_EPF0_VF24_BIST__BIST_CAP_MASK 0x80L |
|---|
| 45431 | //BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_1 |
|---|
| 45432 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 45433 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 45434 | //BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_2 |
|---|
| 45435 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 45436 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 45437 | //BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_3 |
|---|
| 45438 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 45439 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 45440 | //BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_4 |
|---|
| 45441 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 45442 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 45443 | //BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_5 |
|---|
| 45444 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 45445 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 45446 | //BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_6 |
|---|
| 45447 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 45448 | #define BIF_CFG_DEV0_EPF0_VF24_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 45449 | //BIF_CFG_DEV0_EPF0_VF24_CARDBUS_CIS_PTR |
|---|
| 45450 | #define BIF_CFG_DEV0_EPF0_VF24_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 45451 | #define BIF_CFG_DEV0_EPF0_VF24_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 45452 | //BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID |
|---|
| 45453 | #define BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 45454 | #define BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 45455 | #define BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 45456 | #define BIF_CFG_DEV0_EPF0_VF24_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 45457 | //BIF_CFG_DEV0_EPF0_VF24_ROM_BASE_ADDR |
|---|
| 45458 | #define BIF_CFG_DEV0_EPF0_VF24_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 45459 | #define BIF_CFG_DEV0_EPF0_VF24_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 45460 | //BIF_CFG_DEV0_EPF0_VF24_CAP_PTR |
|---|
| 45461 | #define BIF_CFG_DEV0_EPF0_VF24_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 45462 | #define BIF_CFG_DEV0_EPF0_VF24_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 45463 | //BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_LINE |
|---|
| 45464 | #define BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 45465 | #define BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 45466 | //BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_PIN |
|---|
| 45467 | #define BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 45468 | #define BIF_CFG_DEV0_EPF0_VF24_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 45469 | //BIF_CFG_DEV0_EPF0_VF24_MIN_GRANT |
|---|
| 45470 | #define BIF_CFG_DEV0_EPF0_VF24_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 45471 | #define BIF_CFG_DEV0_EPF0_VF24_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 45472 | //BIF_CFG_DEV0_EPF0_VF24_MAX_LATENCY |
|---|
| 45473 | #define BIF_CFG_DEV0_EPF0_VF24_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 45474 | #define BIF_CFG_DEV0_EPF0_VF24_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 45475 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST |
|---|
| 45476 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45477 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 45478 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 45479 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 45480 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP |
|---|
| 45481 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 45482 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 45483 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 45484 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 45485 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 45486 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 45487 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 45488 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 45489 | //BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP |
|---|
| 45490 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 45491 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 45492 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 45493 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 45494 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 45495 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 45496 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 45497 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 45498 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 45499 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 45500 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 45501 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 45502 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 45503 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 45504 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 45505 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 45506 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 45507 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 45508 | //BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL |
|---|
| 45509 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 45510 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 45511 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 45512 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 45513 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 45514 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 45515 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 45516 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 45517 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 45518 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 45519 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 45520 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 45521 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 45522 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 45523 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 45524 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 45525 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 45526 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 45527 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 45528 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 45529 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 45530 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 45531 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 45532 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 45533 | //BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS |
|---|
| 45534 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 45535 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 45536 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 45537 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 45538 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 45539 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 45540 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 45541 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 45542 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 45543 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 45544 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 45545 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 45546 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 45547 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 45548 | //BIF_CFG_DEV0_EPF0_VF24_LINK_CAP |
|---|
| 45549 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 45550 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 45551 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 45552 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 45553 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 45554 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 45555 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 45556 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 45557 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 45558 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 45559 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 45560 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 45561 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 45562 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 45563 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 45564 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 45565 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 45566 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 45567 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 45568 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 45569 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 45570 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 45571 | //BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL |
|---|
| 45572 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 45573 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 45574 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 45575 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 45576 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 45577 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 45578 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 45579 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 45580 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 45581 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 45582 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 45583 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 45584 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 45585 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 45586 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 45587 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 45588 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 45589 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 45590 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 45591 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 45592 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 45593 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 45594 | //BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS |
|---|
| 45595 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 45596 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 45597 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 45598 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 45599 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 45600 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 45601 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 45602 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 45603 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 45604 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 45605 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 45606 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 45607 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 45608 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 45609 | //BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2 |
|---|
| 45610 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 45611 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 45612 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 45613 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 45614 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 45615 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 45616 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 45617 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 45618 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 45619 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 45620 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 45621 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 45622 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 45623 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 45624 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 45625 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 45626 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 45627 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 45628 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 45629 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 45630 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 45631 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 45632 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 45633 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 45634 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 45635 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 45636 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 45637 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 45638 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 45639 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 45640 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 45641 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 45642 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 45643 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 45644 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 45645 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 45646 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 45647 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 45648 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 45649 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 45650 | //BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2 |
|---|
| 45651 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 45652 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 45653 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 45654 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 45655 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 45656 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 45657 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 45658 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 45659 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 45660 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 45661 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 45662 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 45663 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 45664 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 45665 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 45666 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 45667 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 45668 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 45669 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 45670 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 45671 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 45672 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 45673 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 45674 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 45675 | //BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS2 |
|---|
| 45676 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 45677 | #define BIF_CFG_DEV0_EPF0_VF24_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 45678 | //BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2 |
|---|
| 45679 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 45680 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 45681 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 45682 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 45683 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 45684 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 45685 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 45686 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 45687 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 45688 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 45689 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 45690 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 45691 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 45692 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 45693 | //BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2 |
|---|
| 45694 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 45695 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 45696 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 45697 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 45698 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 45699 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 45700 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 45701 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 45702 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 45703 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 45704 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 45705 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 45706 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 45707 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 45708 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 45709 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 45710 | //BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2 |
|---|
| 45711 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 45712 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 45713 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 45714 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 45715 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 45716 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 45717 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 45718 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 45719 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 45720 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 45721 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 45722 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 45723 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 45724 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 45725 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 45726 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 45727 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 45728 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 45729 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 45730 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 45731 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 45732 | #define BIF_CFG_DEV0_EPF0_VF24_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 45733 | //BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST |
|---|
| 45734 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45735 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 45736 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 45737 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 45738 | //BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL |
|---|
| 45739 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 45740 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 45741 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 45742 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 45743 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 45744 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 45745 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 45746 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 45747 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 45748 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 45749 | //BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_LO |
|---|
| 45750 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 45751 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 45752 | //BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_HI |
|---|
| 45753 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 45754 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 45755 | //BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA |
|---|
| 45756 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 45757 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 45758 | //BIF_CFG_DEV0_EPF0_VF24_MSI_MASK |
|---|
| 45759 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 45760 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 45761 | //BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_64 |
|---|
| 45762 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 45763 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 45764 | //BIF_CFG_DEV0_EPF0_VF24_MSI_MASK_64 |
|---|
| 45765 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 45766 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 45767 | //BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING |
|---|
| 45768 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 45769 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 45770 | //BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_64 |
|---|
| 45771 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 45772 | #define BIF_CFG_DEV0_EPF0_VF24_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 45773 | //BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST |
|---|
| 45774 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45775 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 45776 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 45777 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 45778 | //BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL |
|---|
| 45779 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 45780 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 45781 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 45782 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 45783 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 45784 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 45785 | //BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE |
|---|
| 45786 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 45787 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 45788 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 45789 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 45790 | //BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA |
|---|
| 45791 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 45792 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 45793 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 45794 | #define BIF_CFG_DEV0_EPF0_VF24_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 45795 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 45796 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45797 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 45798 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 45799 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 45800 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 45801 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 45802 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 45803 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 45804 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 45805 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 45806 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 45807 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 45808 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 45809 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC1 |
|---|
| 45810 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 45811 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 45812 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC2 |
|---|
| 45813 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 45814 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 45815 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 45816 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 45817 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 45818 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 45819 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 45820 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 45821 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 45822 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS |
|---|
| 45823 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 45824 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 45825 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 45826 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 45827 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 45828 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 45829 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 45830 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 45831 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 45832 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 45833 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 45834 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 45835 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 45836 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 45837 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 45838 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 45839 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 45840 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 45841 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 45842 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 45843 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 45844 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 45845 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 45846 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 45847 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 45848 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 45849 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 45850 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 45851 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 45852 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 45853 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 45854 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 45855 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK |
|---|
| 45856 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 45857 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 45858 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 45859 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 45860 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 45861 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 45862 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 45863 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 45864 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 45865 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 45866 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 45867 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 45868 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 45869 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 45870 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 45871 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 45872 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 45873 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 45874 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 45875 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 45876 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 45877 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 45878 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 45879 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 45880 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 45881 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 45882 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 45883 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 45884 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 45885 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 45886 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 45887 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 45888 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 45889 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 45890 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 45891 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 45892 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 45893 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 45894 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 45895 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 45896 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 45897 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 45898 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 45899 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 45900 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 45901 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 45902 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 45903 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 45904 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 45905 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 45906 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 45907 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 45908 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 45909 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 45910 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 45911 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 45912 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 45913 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 45914 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 45915 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 45916 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 45917 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 45918 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 45919 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 45920 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 45921 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS |
|---|
| 45922 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 45923 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 45924 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 45925 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 45926 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 45927 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 45928 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 45929 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 45930 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 45931 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 45932 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 45933 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 45934 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 45935 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 45936 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 45937 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 45938 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK |
|---|
| 45939 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 45940 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 45941 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 45942 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 45943 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 45944 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 45945 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 45946 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 45947 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 45948 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 45949 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 45950 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 45951 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 45952 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 45953 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 45954 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 45955 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 45956 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 45957 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 45958 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 45959 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 45960 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 45961 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 45962 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 45963 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 45964 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 45965 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 45966 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 45967 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 45968 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 45969 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 45970 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 45971 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 45972 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 45973 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 45974 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG0 |
|---|
| 45975 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 45976 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 45977 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG1 |
|---|
| 45978 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 45979 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 45980 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG2 |
|---|
| 45981 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 45982 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 45983 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG3 |
|---|
| 45984 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 45985 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 45986 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG0 |
|---|
| 45987 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 45988 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 45989 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG1 |
|---|
| 45990 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 45991 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 45992 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG2 |
|---|
| 45993 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 45994 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 45995 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG3 |
|---|
| 45996 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 45997 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 45998 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST |
|---|
| 45999 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 46000 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 46001 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 46002 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 46003 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 46004 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 46005 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP |
|---|
| 46006 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 46007 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 46008 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 46009 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 46010 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 46011 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 46012 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL |
|---|
| 46013 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 46014 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 46015 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 46016 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 46017 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST |
|---|
| 46018 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 46019 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 46020 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 46021 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 46022 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 46023 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 46024 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP |
|---|
| 46025 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 46026 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 46027 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 46028 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 46029 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 46030 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 46031 | //BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL |
|---|
| 46032 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 46033 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 46034 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 46035 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 46036 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 46037 | #define BIF_CFG_DEV0_EPF0_VF24_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 46038 | |
|---|
| 46039 | |
|---|
| 46040 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp |
|---|
| 46041 | //BIF_CFG_DEV0_EPF0_VF25_VENDOR_ID |
|---|
| 46042 | #define BIF_CFG_DEV0_EPF0_VF25_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 46043 | #define BIF_CFG_DEV0_EPF0_VF25_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 46044 | //BIF_CFG_DEV0_EPF0_VF25_DEVICE_ID |
|---|
| 46045 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 46046 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 46047 | //BIF_CFG_DEV0_EPF0_VF25_COMMAND |
|---|
| 46048 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 46049 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 46050 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 46051 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 46052 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 46053 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 46054 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 46055 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 46056 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 46057 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 46058 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 46059 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 46060 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 46061 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 46062 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 46063 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 46064 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 46065 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 46066 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 46067 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 46068 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 46069 | #define BIF_CFG_DEV0_EPF0_VF25_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 46070 | //BIF_CFG_DEV0_EPF0_VF25_STATUS |
|---|
| 46071 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 46072 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 46073 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 46074 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 46075 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 46076 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 46077 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 46078 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 46079 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 46080 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 46081 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 46082 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 46083 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 46084 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 46085 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 46086 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 46087 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 46088 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 46089 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 46090 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 46091 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 46092 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 46093 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 46094 | #define BIF_CFG_DEV0_EPF0_VF25_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 46095 | //BIF_CFG_DEV0_EPF0_VF25_REVISION_ID |
|---|
| 46096 | #define BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 46097 | #define BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 46098 | #define BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 46099 | #define BIF_CFG_DEV0_EPF0_VF25_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 46100 | //BIF_CFG_DEV0_EPF0_VF25_PROG_INTERFACE |
|---|
| 46101 | #define BIF_CFG_DEV0_EPF0_VF25_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 46102 | #define BIF_CFG_DEV0_EPF0_VF25_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 46103 | //BIF_CFG_DEV0_EPF0_VF25_SUB_CLASS |
|---|
| 46104 | #define BIF_CFG_DEV0_EPF0_VF25_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 46105 | #define BIF_CFG_DEV0_EPF0_VF25_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 46106 | //BIF_CFG_DEV0_EPF0_VF25_BASE_CLASS |
|---|
| 46107 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 46108 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 46109 | //BIF_CFG_DEV0_EPF0_VF25_CACHE_LINE |
|---|
| 46110 | #define BIF_CFG_DEV0_EPF0_VF25_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 46111 | #define BIF_CFG_DEV0_EPF0_VF25_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 46112 | //BIF_CFG_DEV0_EPF0_VF25_LATENCY |
|---|
| 46113 | #define BIF_CFG_DEV0_EPF0_VF25_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 46114 | #define BIF_CFG_DEV0_EPF0_VF25_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 46115 | //BIF_CFG_DEV0_EPF0_VF25_HEADER |
|---|
| 46116 | #define 0x0 |
|---|
| 46117 | #define 0x7 |
|---|
| 46118 | #define 0x7FL |
|---|
| 46119 | #define 0x80L |
|---|
| 46120 | //BIF_CFG_DEV0_EPF0_VF25_BIST |
|---|
| 46121 | #define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 46122 | #define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 46123 | #define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 46124 | #define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 46125 | #define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_STRT_MASK 0x40L |
|---|
| 46126 | #define BIF_CFG_DEV0_EPF0_VF25_BIST__BIST_CAP_MASK 0x80L |
|---|
| 46127 | //BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_1 |
|---|
| 46128 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 46129 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46130 | //BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_2 |
|---|
| 46131 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 46132 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46133 | //BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_3 |
|---|
| 46134 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 46135 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46136 | //BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_4 |
|---|
| 46137 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 46138 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46139 | //BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_5 |
|---|
| 46140 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 46141 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46142 | //BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_6 |
|---|
| 46143 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 46144 | #define BIF_CFG_DEV0_EPF0_VF25_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46145 | //BIF_CFG_DEV0_EPF0_VF25_CARDBUS_CIS_PTR |
|---|
| 46146 | #define BIF_CFG_DEV0_EPF0_VF25_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 46147 | #define BIF_CFG_DEV0_EPF0_VF25_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 46148 | //BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID |
|---|
| 46149 | #define BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 46150 | #define BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 46151 | #define BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 46152 | #define BIF_CFG_DEV0_EPF0_VF25_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 46153 | //BIF_CFG_DEV0_EPF0_VF25_ROM_BASE_ADDR |
|---|
| 46154 | #define BIF_CFG_DEV0_EPF0_VF25_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 46155 | #define BIF_CFG_DEV0_EPF0_VF25_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46156 | //BIF_CFG_DEV0_EPF0_VF25_CAP_PTR |
|---|
| 46157 | #define BIF_CFG_DEV0_EPF0_VF25_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 46158 | #define BIF_CFG_DEV0_EPF0_VF25_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 46159 | //BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_LINE |
|---|
| 46160 | #define BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 46161 | #define BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 46162 | //BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_PIN |
|---|
| 46163 | #define BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 46164 | #define BIF_CFG_DEV0_EPF0_VF25_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 46165 | //BIF_CFG_DEV0_EPF0_VF25_MIN_GRANT |
|---|
| 46166 | #define BIF_CFG_DEV0_EPF0_VF25_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 46167 | #define BIF_CFG_DEV0_EPF0_VF25_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 46168 | //BIF_CFG_DEV0_EPF0_VF25_MAX_LATENCY |
|---|
| 46169 | #define BIF_CFG_DEV0_EPF0_VF25_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 46170 | #define BIF_CFG_DEV0_EPF0_VF25_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 46171 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST |
|---|
| 46172 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 46173 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 46174 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 46175 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 46176 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP |
|---|
| 46177 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 46178 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 46179 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 46180 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 46181 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 46182 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 46183 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 46184 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 46185 | //BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP |
|---|
| 46186 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 46187 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 46188 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 46189 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 46190 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 46191 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 46192 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 46193 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 46194 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 46195 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 46196 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 46197 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 46198 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 46199 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 46200 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 46201 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 46202 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 46203 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 46204 | //BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL |
|---|
| 46205 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 46206 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 46207 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 46208 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 46209 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 46210 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 46211 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 46212 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 46213 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 46214 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 46215 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 46216 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 46217 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 46218 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 46219 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 46220 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 46221 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 46222 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 46223 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 46224 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 46225 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 46226 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 46227 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 46228 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 46229 | //BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS |
|---|
| 46230 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 46231 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 46232 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 46233 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 46234 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 46235 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 46236 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 46237 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 46238 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 46239 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 46240 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 46241 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 46242 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 46243 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 46244 | //BIF_CFG_DEV0_EPF0_VF25_LINK_CAP |
|---|
| 46245 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 46246 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 46247 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 46248 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 46249 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 46250 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 46251 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 46252 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 46253 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 46254 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 46255 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 46256 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 46257 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 46258 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 46259 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 46260 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 46261 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 46262 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 46263 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 46264 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 46265 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 46266 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 46267 | //BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL |
|---|
| 46268 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 46269 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 46270 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 46271 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 46272 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 46273 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 46274 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 46275 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 46276 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 46277 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 46278 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 46279 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 46280 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 46281 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 46282 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 46283 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 46284 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 46285 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 46286 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 46287 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 46288 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 46289 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 46290 | //BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS |
|---|
| 46291 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 46292 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 46293 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 46294 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 46295 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 46296 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 46297 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 46298 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 46299 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 46300 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 46301 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 46302 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 46303 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 46304 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 46305 | //BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2 |
|---|
| 46306 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 46307 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 46308 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 46309 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 46310 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 46311 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 46312 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 46313 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 46314 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 46315 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 46316 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 46317 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 46318 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 46319 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 46320 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 46321 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 46322 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 46323 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 46324 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 46325 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 46326 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 46327 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 46328 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 46329 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 46330 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 46331 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 46332 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 46333 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 46334 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 46335 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 46336 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 46337 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 46338 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 46339 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 46340 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 46341 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 46342 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 46343 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 46344 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 46345 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 46346 | //BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2 |
|---|
| 46347 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 46348 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 46349 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 46350 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 46351 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 46352 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 46353 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 46354 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 46355 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 46356 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 46357 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 46358 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 46359 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 46360 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 46361 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 46362 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 46363 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 46364 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 46365 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 46366 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 46367 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 46368 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 46369 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 46370 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 46371 | //BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS2 |
|---|
| 46372 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 46373 | #define BIF_CFG_DEV0_EPF0_VF25_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 46374 | //BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2 |
|---|
| 46375 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 46376 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 46377 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 46378 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 46379 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 46380 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 46381 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 46382 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 46383 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 46384 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 46385 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 46386 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 46387 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 46388 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 46389 | //BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2 |
|---|
| 46390 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 46391 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 46392 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 46393 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 46394 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 46395 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 46396 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 46397 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 46398 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 46399 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 46400 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 46401 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 46402 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 46403 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 46404 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 46405 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 46406 | //BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2 |
|---|
| 46407 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 46408 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 46409 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 46410 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 46411 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 46412 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 46413 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 46414 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 46415 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 46416 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 46417 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 46418 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 46419 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 46420 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 46421 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 46422 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 46423 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 46424 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 46425 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 46426 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 46427 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 46428 | #define BIF_CFG_DEV0_EPF0_VF25_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 46429 | //BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST |
|---|
| 46430 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 46431 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 46432 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 46433 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 46434 | //BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL |
|---|
| 46435 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 46436 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 46437 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 46438 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 46439 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 46440 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 46441 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 46442 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 46443 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 46444 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 46445 | //BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_LO |
|---|
| 46446 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 46447 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 46448 | //BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_HI |
|---|
| 46449 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 46450 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 46451 | //BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA |
|---|
| 46452 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 46453 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 46454 | //BIF_CFG_DEV0_EPF0_VF25_MSI_MASK |
|---|
| 46455 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 46456 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 46457 | //BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_64 |
|---|
| 46458 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 46459 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 46460 | //BIF_CFG_DEV0_EPF0_VF25_MSI_MASK_64 |
|---|
| 46461 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 46462 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 46463 | //BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING |
|---|
| 46464 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 46465 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 46466 | //BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_64 |
|---|
| 46467 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 46468 | #define BIF_CFG_DEV0_EPF0_VF25_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 46469 | //BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST |
|---|
| 46470 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 46471 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 46472 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 46473 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 46474 | //BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL |
|---|
| 46475 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 46476 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 46477 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 46478 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 46479 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 46480 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 46481 | //BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE |
|---|
| 46482 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 46483 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 46484 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 46485 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 46486 | //BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA |
|---|
| 46487 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 46488 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 46489 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 46490 | #define BIF_CFG_DEV0_EPF0_VF25_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 46491 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 46492 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 46493 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 46494 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 46495 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 46496 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 46497 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 46498 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 46499 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 46500 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 46501 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 46502 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 46503 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 46504 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 46505 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC1 |
|---|
| 46506 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 46507 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 46508 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC2 |
|---|
| 46509 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 46510 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 46511 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 46512 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 46513 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 46514 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 46515 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 46516 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 46517 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 46518 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS |
|---|
| 46519 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 46520 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 46521 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 46522 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 46523 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 46524 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 46525 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 46526 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 46527 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 46528 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 46529 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 46530 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 46531 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 46532 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 46533 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 46534 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 46535 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 46536 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 46537 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 46538 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 46539 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 46540 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 46541 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 46542 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 46543 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 46544 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 46545 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 46546 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 46547 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 46548 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 46549 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 46550 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 46551 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK |
|---|
| 46552 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 46553 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 46554 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 46555 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 46556 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 46557 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 46558 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 46559 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 46560 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 46561 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 46562 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 46563 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 46564 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 46565 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 46566 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 46567 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 46568 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 46569 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 46570 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 46571 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 46572 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 46573 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 46574 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 46575 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 46576 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 46577 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 46578 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 46579 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 46580 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 46581 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 46582 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 46583 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 46584 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 46585 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 46586 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 46587 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 46588 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 46589 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 46590 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 46591 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 46592 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 46593 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 46594 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 46595 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 46596 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 46597 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 46598 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 46599 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 46600 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 46601 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 46602 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 46603 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 46604 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 46605 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 46606 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 46607 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 46608 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 46609 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 46610 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 46611 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 46612 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 46613 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 46614 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 46615 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 46616 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 46617 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS |
|---|
| 46618 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 46619 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 46620 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 46621 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 46622 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 46623 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 46624 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 46625 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 46626 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 46627 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 46628 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 46629 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 46630 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 46631 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 46632 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 46633 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 46634 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK |
|---|
| 46635 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 46636 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 46637 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 46638 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 46639 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 46640 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 46641 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 46642 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 46643 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 46644 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 46645 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 46646 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 46647 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 46648 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 46649 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 46650 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 46651 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 46652 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 46653 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 46654 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 46655 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 46656 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 46657 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 46658 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 46659 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 46660 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 46661 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 46662 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 46663 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 46664 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 46665 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 46666 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 46667 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 46668 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 46669 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 46670 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG0 |
|---|
| 46671 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 46672 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 46673 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG1 |
|---|
| 46674 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 46675 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 46676 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG2 |
|---|
| 46677 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 46678 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 46679 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG3 |
|---|
| 46680 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 46681 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 46682 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG0 |
|---|
| 46683 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 46684 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 46685 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG1 |
|---|
| 46686 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 46687 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 46688 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG2 |
|---|
| 46689 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 46690 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 46691 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG3 |
|---|
| 46692 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 46693 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 46694 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST |
|---|
| 46695 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 46696 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 46697 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 46698 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 46699 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 46700 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 46701 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP |
|---|
| 46702 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 46703 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 46704 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 46705 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 46706 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 46707 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 46708 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL |
|---|
| 46709 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 46710 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 46711 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 46712 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 46713 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST |
|---|
| 46714 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 46715 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 46716 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 46717 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 46718 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 46719 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 46720 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP |
|---|
| 46721 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 46722 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 46723 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 46724 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 46725 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 46726 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 46727 | //BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL |
|---|
| 46728 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 46729 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 46730 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 46731 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 46732 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 46733 | #define BIF_CFG_DEV0_EPF0_VF25_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 46734 | |
|---|
| 46735 | |
|---|
| 46736 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp |
|---|
| 46737 | //BIF_CFG_DEV0_EPF0_VF26_VENDOR_ID |
|---|
| 46738 | #define BIF_CFG_DEV0_EPF0_VF26_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 46739 | #define BIF_CFG_DEV0_EPF0_VF26_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 46740 | //BIF_CFG_DEV0_EPF0_VF26_DEVICE_ID |
|---|
| 46741 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 46742 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 46743 | //BIF_CFG_DEV0_EPF0_VF26_COMMAND |
|---|
| 46744 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 46745 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 46746 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 46747 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 46748 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 46749 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 46750 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 46751 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 46752 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 46753 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 46754 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 46755 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 46756 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 46757 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 46758 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 46759 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 46760 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 46761 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 46762 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 46763 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 46764 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 46765 | #define BIF_CFG_DEV0_EPF0_VF26_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 46766 | //BIF_CFG_DEV0_EPF0_VF26_STATUS |
|---|
| 46767 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 46768 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 46769 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 46770 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 46771 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 46772 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 46773 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 46774 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 46775 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 46776 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 46777 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 46778 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 46779 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 46780 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 46781 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 46782 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 46783 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 46784 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 46785 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 46786 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 46787 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 46788 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 46789 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 46790 | #define BIF_CFG_DEV0_EPF0_VF26_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 46791 | //BIF_CFG_DEV0_EPF0_VF26_REVISION_ID |
|---|
| 46792 | #define BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 46793 | #define BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 46794 | #define BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 46795 | #define BIF_CFG_DEV0_EPF0_VF26_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 46796 | //BIF_CFG_DEV0_EPF0_VF26_PROG_INTERFACE |
|---|
| 46797 | #define BIF_CFG_DEV0_EPF0_VF26_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 46798 | #define BIF_CFG_DEV0_EPF0_VF26_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 46799 | //BIF_CFG_DEV0_EPF0_VF26_SUB_CLASS |
|---|
| 46800 | #define BIF_CFG_DEV0_EPF0_VF26_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 46801 | #define BIF_CFG_DEV0_EPF0_VF26_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 46802 | //BIF_CFG_DEV0_EPF0_VF26_BASE_CLASS |
|---|
| 46803 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 46804 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 46805 | //BIF_CFG_DEV0_EPF0_VF26_CACHE_LINE |
|---|
| 46806 | #define BIF_CFG_DEV0_EPF0_VF26_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 46807 | #define BIF_CFG_DEV0_EPF0_VF26_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 46808 | //BIF_CFG_DEV0_EPF0_VF26_LATENCY |
|---|
| 46809 | #define BIF_CFG_DEV0_EPF0_VF26_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 46810 | #define BIF_CFG_DEV0_EPF0_VF26_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 46811 | //BIF_CFG_DEV0_EPF0_VF26_HEADER |
|---|
| 46812 | #define 0x0 |
|---|
| 46813 | #define 0x7 |
|---|
| 46814 | #define 0x7FL |
|---|
| 46815 | #define 0x80L |
|---|
| 46816 | //BIF_CFG_DEV0_EPF0_VF26_BIST |
|---|
| 46817 | #define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 46818 | #define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 46819 | #define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 46820 | #define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 46821 | #define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_STRT_MASK 0x40L |
|---|
| 46822 | #define BIF_CFG_DEV0_EPF0_VF26_BIST__BIST_CAP_MASK 0x80L |
|---|
| 46823 | //BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_1 |
|---|
| 46824 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 46825 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46826 | //BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_2 |
|---|
| 46827 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 46828 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46829 | //BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_3 |
|---|
| 46830 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 46831 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46832 | //BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_4 |
|---|
| 46833 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 46834 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46835 | //BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_5 |
|---|
| 46836 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 46837 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46838 | //BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_6 |
|---|
| 46839 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 46840 | #define BIF_CFG_DEV0_EPF0_VF26_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46841 | //BIF_CFG_DEV0_EPF0_VF26_CARDBUS_CIS_PTR |
|---|
| 46842 | #define BIF_CFG_DEV0_EPF0_VF26_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 46843 | #define BIF_CFG_DEV0_EPF0_VF26_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 46844 | //BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID |
|---|
| 46845 | #define BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 46846 | #define BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 46847 | #define BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 46848 | #define BIF_CFG_DEV0_EPF0_VF26_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 46849 | //BIF_CFG_DEV0_EPF0_VF26_ROM_BASE_ADDR |
|---|
| 46850 | #define BIF_CFG_DEV0_EPF0_VF26_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 46851 | #define BIF_CFG_DEV0_EPF0_VF26_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 46852 | //BIF_CFG_DEV0_EPF0_VF26_CAP_PTR |
|---|
| 46853 | #define BIF_CFG_DEV0_EPF0_VF26_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 46854 | #define BIF_CFG_DEV0_EPF0_VF26_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 46855 | //BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_LINE |
|---|
| 46856 | #define BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 46857 | #define BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 46858 | //BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_PIN |
|---|
| 46859 | #define BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 46860 | #define BIF_CFG_DEV0_EPF0_VF26_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 46861 | //BIF_CFG_DEV0_EPF0_VF26_MIN_GRANT |
|---|
| 46862 | #define BIF_CFG_DEV0_EPF0_VF26_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 46863 | #define BIF_CFG_DEV0_EPF0_VF26_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 46864 | //BIF_CFG_DEV0_EPF0_VF26_MAX_LATENCY |
|---|
| 46865 | #define BIF_CFG_DEV0_EPF0_VF26_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 46866 | #define BIF_CFG_DEV0_EPF0_VF26_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 46867 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST |
|---|
| 46868 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 46869 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 46870 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 46871 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 46872 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP |
|---|
| 46873 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 46874 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 46875 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 46876 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 46877 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 46878 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 46879 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 46880 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 46881 | //BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP |
|---|
| 46882 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 46883 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 46884 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 46885 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 46886 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 46887 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 46888 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 46889 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 46890 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 46891 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 46892 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 46893 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 46894 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 46895 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 46896 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 46897 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 46898 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 46899 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 46900 | //BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL |
|---|
| 46901 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 46902 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 46903 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 46904 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 46905 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 46906 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 46907 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 46908 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 46909 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 46910 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 46911 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 46912 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 46913 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 46914 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 46915 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 46916 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 46917 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 46918 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 46919 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 46920 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 46921 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 46922 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 46923 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 46924 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 46925 | //BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS |
|---|
| 46926 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 46927 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 46928 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 46929 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 46930 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 46931 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 46932 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 46933 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 46934 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 46935 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 46936 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 46937 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 46938 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 46939 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 46940 | //BIF_CFG_DEV0_EPF0_VF26_LINK_CAP |
|---|
| 46941 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 46942 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 46943 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 46944 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 46945 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 46946 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 46947 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 46948 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 46949 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 46950 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 46951 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 46952 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 46953 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 46954 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 46955 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 46956 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 46957 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 46958 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 46959 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 46960 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 46961 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 46962 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 46963 | //BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL |
|---|
| 46964 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 46965 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 46966 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 46967 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 46968 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 46969 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 46970 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 46971 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 46972 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 46973 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 46974 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 46975 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 46976 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 46977 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 46978 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 46979 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 46980 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 46981 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 46982 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 46983 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 46984 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 46985 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 46986 | //BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS |
|---|
| 46987 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 46988 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 46989 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 46990 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 46991 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 46992 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 46993 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 46994 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 46995 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 46996 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 46997 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 46998 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 46999 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 47000 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 47001 | //BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2 |
|---|
| 47002 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 47003 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 47004 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 47005 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 47006 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 47007 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 47008 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 47009 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 47010 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 47011 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 47012 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 47013 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 47014 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 47015 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 47016 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 47017 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 47018 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 47019 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 47020 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 47021 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 47022 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 47023 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 47024 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 47025 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 47026 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 47027 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 47028 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 47029 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 47030 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 47031 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 47032 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 47033 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 47034 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 47035 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 47036 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 47037 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 47038 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 47039 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 47040 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 47041 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 47042 | //BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2 |
|---|
| 47043 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 47044 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 47045 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 47046 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 47047 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 47048 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 47049 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 47050 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 47051 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 47052 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 47053 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 47054 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 47055 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 47056 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 47057 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 47058 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 47059 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 47060 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 47061 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 47062 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 47063 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 47064 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 47065 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 47066 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 47067 | //BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS2 |
|---|
| 47068 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 47069 | #define BIF_CFG_DEV0_EPF0_VF26_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
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| 47070 | //BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2 |
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| 47071 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 47072 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
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| 47073 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 47074 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
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| 47075 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
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| 47076 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
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| 47077 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
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| 47078 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 47079 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 47080 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 47081 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 47082 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 47083 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 47084 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
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| 47085 | //BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2 |
|---|
| 47086 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
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| 47087 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
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| 47088 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
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| 47089 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 47090 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 47091 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 47092 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
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| 47093 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 47094 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 47095 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 47096 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 47097 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 47098 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 47099 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 47100 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 47101 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
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| 47102 | //BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2 |
|---|
| 47103 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 47104 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
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| 47105 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 47106 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 47107 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 47108 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 47109 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 47110 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 47111 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 47112 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 47113 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 47114 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 47115 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 47116 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 47117 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 47118 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 47119 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 47120 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 47121 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 47122 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 47123 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 47124 | #define BIF_CFG_DEV0_EPF0_VF26_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 47125 | //BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST |
|---|
| 47126 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 47127 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 47128 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 47129 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 47130 | //BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL |
|---|
| 47131 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 47132 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
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| 47133 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 47134 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 47135 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 47136 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 47137 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
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| 47138 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 47139 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 47140 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 47141 | //BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_LO |
|---|
| 47142 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 47143 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
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| 47144 | //BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_HI |
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| 47145 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
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| 47146 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 47147 | //BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA |
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| 47148 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 47149 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
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| 47150 | //BIF_CFG_DEV0_EPF0_VF26_MSI_MASK |
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| 47151 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MASK__MSI_MASK__SHIFT 0x0 |
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| 47152 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
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| 47153 | //BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_64 |
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| 47154 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
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| 47155 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
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| 47156 | //BIF_CFG_DEV0_EPF0_VF26_MSI_MASK_64 |
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| 47157 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
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| 47158 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
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| 47159 | //BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING |
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| 47160 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 47161 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
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| 47162 | //BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_64 |
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| 47163 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
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| 47164 | #define BIF_CFG_DEV0_EPF0_VF26_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
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| 47165 | //BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST |
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| 47166 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 47167 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 47168 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 47169 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 47170 | //BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL |
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| 47171 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
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| 47172 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
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| 47173 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
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| 47174 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
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| 47175 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
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| 47176 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
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| 47177 | //BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE |
|---|
| 47178 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 47179 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
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| 47180 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
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| 47181 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
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| 47182 | //BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA |
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| 47183 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
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| 47184 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 47185 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
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| 47186 | #define BIF_CFG_DEV0_EPF0_VF26_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
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| 47187 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 47188 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 47189 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 47190 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 47191 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 47192 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 47193 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 47194 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 47195 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 47196 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 47197 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
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| 47198 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 47199 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 47200 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 47201 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC1 |
|---|
| 47202 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 47203 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 47204 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC2 |
|---|
| 47205 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 47206 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 47207 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 47208 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 47209 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 47210 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 47211 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 47212 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 47213 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 47214 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS |
|---|
| 47215 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 47216 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 47217 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 47218 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 47219 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 47220 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 47221 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 47222 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 47223 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 47224 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 47225 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 47226 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 47227 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 47228 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 47229 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 47230 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 47231 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 47232 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 47233 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 47234 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 47235 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 47236 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 47237 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 47238 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 47239 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 47240 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 47241 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 47242 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 47243 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 47244 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 47245 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 47246 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 47247 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK |
|---|
| 47248 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 47249 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 47250 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 47251 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 47252 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 47253 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 47254 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 47255 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 47256 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 47257 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 47258 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 47259 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 47260 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 47261 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 47262 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 47263 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 47264 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 47265 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 47266 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 47267 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 47268 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 47269 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 47270 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 47271 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 47272 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 47273 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 47274 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 47275 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 47276 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 47277 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 47278 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 47279 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 47280 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 47281 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 47282 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 47283 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 47284 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 47285 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 47286 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 47287 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 47288 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 47289 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 47290 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 47291 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 47292 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 47293 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 47294 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 47295 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 47296 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 47297 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 47298 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 47299 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 47300 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 47301 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 47302 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 47303 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 47304 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 47305 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 47306 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 47307 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 47308 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 47309 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 47310 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 47311 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 47312 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 47313 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS |
|---|
| 47314 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 47315 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 47316 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 47317 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 47318 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 47319 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 47320 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 47321 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 47322 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 47323 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 47324 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 47325 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 47326 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 47327 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 47328 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 47329 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 47330 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK |
|---|
| 47331 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 47332 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 47333 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 47334 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 47335 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 47336 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 47337 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 47338 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 47339 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 47340 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 47341 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 47342 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 47343 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 47344 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 47345 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 47346 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 47347 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 47348 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 47349 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 47350 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 47351 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 47352 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 47353 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 47354 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 47355 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 47356 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 47357 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 47358 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 47359 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 47360 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 47361 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 47362 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 47363 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 47364 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 47365 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 47366 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG0 |
|---|
| 47367 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 47368 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 47369 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG1 |
|---|
| 47370 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 47371 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 47372 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG2 |
|---|
| 47373 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 47374 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 47375 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG3 |
|---|
| 47376 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 47377 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 47378 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG0 |
|---|
| 47379 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 47380 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 47381 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG1 |
|---|
| 47382 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 47383 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 47384 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG2 |
|---|
| 47385 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 47386 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 47387 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG3 |
|---|
| 47388 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 47389 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 47390 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST |
|---|
| 47391 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 47392 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 47393 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 47394 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 47395 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 47396 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 47397 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP |
|---|
| 47398 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 47399 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 47400 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 47401 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 47402 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 47403 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 47404 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL |
|---|
| 47405 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 47406 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 47407 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 47408 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 47409 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST |
|---|
| 47410 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 47411 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 47412 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 47413 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 47414 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 47415 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 47416 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP |
|---|
| 47417 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 47418 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 47419 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 47420 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 47421 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 47422 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 47423 | //BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL |
|---|
| 47424 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 47425 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 47426 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 47427 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 47428 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 47429 | #define BIF_CFG_DEV0_EPF0_VF26_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 47430 | |
|---|
| 47431 | |
|---|
| 47432 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp |
|---|
| 47433 | //BIF_CFG_DEV0_EPF0_VF27_VENDOR_ID |
|---|
| 47434 | #define BIF_CFG_DEV0_EPF0_VF27_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 47435 | #define BIF_CFG_DEV0_EPF0_VF27_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 47436 | //BIF_CFG_DEV0_EPF0_VF27_DEVICE_ID |
|---|
| 47437 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 47438 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 47439 | //BIF_CFG_DEV0_EPF0_VF27_COMMAND |
|---|
| 47440 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 47441 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 47442 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 47443 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 47444 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 47445 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 47446 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 47447 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 47448 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 47449 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 47450 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 47451 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 47452 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 47453 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 47454 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 47455 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 47456 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 47457 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 47458 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 47459 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 47460 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 47461 | #define BIF_CFG_DEV0_EPF0_VF27_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 47462 | //BIF_CFG_DEV0_EPF0_VF27_STATUS |
|---|
| 47463 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 47464 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 47465 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 47466 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 47467 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 47468 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 47469 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 47470 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 47471 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 47472 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 47473 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 47474 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 47475 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 47476 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 47477 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 47478 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 47479 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 47480 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 47481 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 47482 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 47483 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 47484 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 47485 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 47486 | #define BIF_CFG_DEV0_EPF0_VF27_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 47487 | //BIF_CFG_DEV0_EPF0_VF27_REVISION_ID |
|---|
| 47488 | #define BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 47489 | #define BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 47490 | #define BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 47491 | #define BIF_CFG_DEV0_EPF0_VF27_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 47492 | //BIF_CFG_DEV0_EPF0_VF27_PROG_INTERFACE |
|---|
| 47493 | #define BIF_CFG_DEV0_EPF0_VF27_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 47494 | #define BIF_CFG_DEV0_EPF0_VF27_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 47495 | //BIF_CFG_DEV0_EPF0_VF27_SUB_CLASS |
|---|
| 47496 | #define BIF_CFG_DEV0_EPF0_VF27_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 47497 | #define BIF_CFG_DEV0_EPF0_VF27_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 47498 | //BIF_CFG_DEV0_EPF0_VF27_BASE_CLASS |
|---|
| 47499 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 47500 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 47501 | //BIF_CFG_DEV0_EPF0_VF27_CACHE_LINE |
|---|
| 47502 | #define BIF_CFG_DEV0_EPF0_VF27_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 47503 | #define BIF_CFG_DEV0_EPF0_VF27_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 47504 | //BIF_CFG_DEV0_EPF0_VF27_LATENCY |
|---|
| 47505 | #define BIF_CFG_DEV0_EPF0_VF27_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 47506 | #define BIF_CFG_DEV0_EPF0_VF27_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 47507 | //BIF_CFG_DEV0_EPF0_VF27_HEADER |
|---|
| 47508 | #define 0x0 |
|---|
| 47509 | #define 0x7 |
|---|
| 47510 | #define 0x7FL |
|---|
| 47511 | #define 0x80L |
|---|
| 47512 | //BIF_CFG_DEV0_EPF0_VF27_BIST |
|---|
| 47513 | #define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 47514 | #define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 47515 | #define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 47516 | #define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 47517 | #define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_STRT_MASK 0x40L |
|---|
| 47518 | #define BIF_CFG_DEV0_EPF0_VF27_BIST__BIST_CAP_MASK 0x80L |
|---|
| 47519 | //BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_1 |
|---|
| 47520 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 47521 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 47522 | //BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_2 |
|---|
| 47523 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 47524 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 47525 | //BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_3 |
|---|
| 47526 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 47527 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 47528 | //BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_4 |
|---|
| 47529 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 47530 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 47531 | //BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_5 |
|---|
| 47532 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 47533 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 47534 | //BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_6 |
|---|
| 47535 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 47536 | #define BIF_CFG_DEV0_EPF0_VF27_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 47537 | //BIF_CFG_DEV0_EPF0_VF27_CARDBUS_CIS_PTR |
|---|
| 47538 | #define BIF_CFG_DEV0_EPF0_VF27_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 47539 | #define BIF_CFG_DEV0_EPF0_VF27_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 47540 | //BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID |
|---|
| 47541 | #define BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 47542 | #define BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 47543 | #define BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 47544 | #define BIF_CFG_DEV0_EPF0_VF27_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 47545 | //BIF_CFG_DEV0_EPF0_VF27_ROM_BASE_ADDR |
|---|
| 47546 | #define BIF_CFG_DEV0_EPF0_VF27_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 47547 | #define BIF_CFG_DEV0_EPF0_VF27_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 47548 | //BIF_CFG_DEV0_EPF0_VF27_CAP_PTR |
|---|
| 47549 | #define BIF_CFG_DEV0_EPF0_VF27_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 47550 | #define BIF_CFG_DEV0_EPF0_VF27_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 47551 | //BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_LINE |
|---|
| 47552 | #define BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 47553 | #define BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 47554 | //BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_PIN |
|---|
| 47555 | #define BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 47556 | #define BIF_CFG_DEV0_EPF0_VF27_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 47557 | //BIF_CFG_DEV0_EPF0_VF27_MIN_GRANT |
|---|
| 47558 | #define BIF_CFG_DEV0_EPF0_VF27_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 47559 | #define BIF_CFG_DEV0_EPF0_VF27_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 47560 | //BIF_CFG_DEV0_EPF0_VF27_MAX_LATENCY |
|---|
| 47561 | #define BIF_CFG_DEV0_EPF0_VF27_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 47562 | #define BIF_CFG_DEV0_EPF0_VF27_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 47563 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST |
|---|
| 47564 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 47565 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 47566 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 47567 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 47568 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP |
|---|
| 47569 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 47570 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 47571 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 47572 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 47573 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 47574 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 47575 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 47576 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 47577 | //BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP |
|---|
| 47578 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 47579 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 47580 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 47581 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 47582 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 47583 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 47584 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 47585 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 47586 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 47587 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 47588 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 47589 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 47590 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 47591 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 47592 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 47593 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 47594 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 47595 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 47596 | //BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL |
|---|
| 47597 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 47598 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 47599 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 47600 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 47601 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 47602 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 47603 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 47604 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 47605 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 47606 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 47607 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 47608 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 47609 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 47610 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 47611 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 47612 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 47613 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 47614 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 47615 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 47616 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 47617 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 47618 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 47619 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 47620 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 47621 | //BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS |
|---|
| 47622 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 47623 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 47624 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 47625 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 47626 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 47627 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 47628 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 47629 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 47630 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 47631 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 47632 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 47633 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 47634 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 47635 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 47636 | //BIF_CFG_DEV0_EPF0_VF27_LINK_CAP |
|---|
| 47637 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 47638 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 47639 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 47640 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 47641 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 47642 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 47643 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 47644 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 47645 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 47646 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 47647 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 47648 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 47649 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 47650 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 47651 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 47652 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 47653 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 47654 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 47655 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 47656 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 47657 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 47658 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 47659 | //BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL |
|---|
| 47660 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 47661 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 47662 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 47663 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 47664 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 47665 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 47666 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 47667 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 47668 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 47669 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 47670 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 47671 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 47672 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 47673 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 47674 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 47675 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 47676 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 47677 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 47678 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 47679 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 47680 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 47681 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 47682 | //BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS |
|---|
| 47683 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 47684 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 47685 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 47686 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 47687 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 47688 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 47689 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 47690 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 47691 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 47692 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 47693 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 47694 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 47695 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 47696 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 47697 | //BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2 |
|---|
| 47698 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 47699 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 47700 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 47701 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 47702 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 47703 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 47704 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 47705 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 47706 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 47707 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 47708 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 47709 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 47710 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 47711 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 47712 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 47713 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 47714 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 47715 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 47716 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 47717 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 47718 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 47719 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 47720 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 47721 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 47722 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 47723 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 47724 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 47725 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 47726 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 47727 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 47728 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 47729 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 47730 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 47731 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 47732 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 47733 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 47734 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 47735 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 47736 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 47737 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 47738 | //BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2 |
|---|
| 47739 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 47740 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 47741 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 47742 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 47743 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 47744 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 47745 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 47746 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 47747 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 47748 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 47749 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 47750 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 47751 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 47752 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 47753 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 47754 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 47755 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 47756 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 47757 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 47758 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 47759 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 47760 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 47761 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 47762 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 47763 | //BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS2 |
|---|
| 47764 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 47765 | #define BIF_CFG_DEV0_EPF0_VF27_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 47766 | //BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2 |
|---|
| 47767 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 47768 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 47769 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 47770 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 47771 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 47772 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 47773 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 47774 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 47775 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 47776 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 47777 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 47778 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 47779 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 47780 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 47781 | //BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2 |
|---|
| 47782 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 47783 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 47784 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 47785 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 47786 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 47787 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 47788 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 47789 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 47790 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 47791 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 47792 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 47793 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 47794 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 47795 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 47796 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 47797 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 47798 | //BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2 |
|---|
| 47799 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 47800 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 47801 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 47802 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 47803 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 47804 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 47805 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 47806 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 47807 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 47808 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 47809 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 47810 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 47811 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 47812 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 47813 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 47814 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 47815 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 47816 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 47817 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 47818 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 47819 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 47820 | #define BIF_CFG_DEV0_EPF0_VF27_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 47821 | //BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST |
|---|
| 47822 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 47823 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 47824 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 47825 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 47826 | //BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL |
|---|
| 47827 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 47828 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 47829 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 47830 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 47831 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 47832 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 47833 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 47834 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 47835 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 47836 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 47837 | //BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_LO |
|---|
| 47838 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 47839 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 47840 | //BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_HI |
|---|
| 47841 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 47842 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 47843 | //BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA |
|---|
| 47844 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 47845 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 47846 | //BIF_CFG_DEV0_EPF0_VF27_MSI_MASK |
|---|
| 47847 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 47848 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 47849 | //BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_64 |
|---|
| 47850 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 47851 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 47852 | //BIF_CFG_DEV0_EPF0_VF27_MSI_MASK_64 |
|---|
| 47853 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 47854 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 47855 | //BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING |
|---|
| 47856 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 47857 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 47858 | //BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_64 |
|---|
| 47859 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 47860 | #define BIF_CFG_DEV0_EPF0_VF27_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 47861 | //BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST |
|---|
| 47862 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 47863 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 47864 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 47865 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 47866 | //BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL |
|---|
| 47867 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 47868 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 47869 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 47870 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 47871 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 47872 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 47873 | //BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE |
|---|
| 47874 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 47875 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 47876 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 47877 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 47878 | //BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA |
|---|
| 47879 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 47880 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 47881 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 47882 | #define BIF_CFG_DEV0_EPF0_VF27_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 47883 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 47884 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 47885 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 47886 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 47887 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 47888 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 47889 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 47890 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 47891 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 47892 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 47893 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 47894 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 47895 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 47896 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 47897 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC1 |
|---|
| 47898 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 47899 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 47900 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC2 |
|---|
| 47901 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 47902 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 47903 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 47904 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 47905 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 47906 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 47907 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 47908 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 47909 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 47910 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS |
|---|
| 47911 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 47912 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 47913 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 47914 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 47915 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 47916 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 47917 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 47918 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 47919 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 47920 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 47921 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 47922 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 47923 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 47924 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 47925 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 47926 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 47927 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 47928 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 47929 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 47930 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 47931 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 47932 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 47933 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 47934 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 47935 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 47936 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 47937 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 47938 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 47939 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 47940 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 47941 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 47942 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 47943 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK |
|---|
| 47944 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 47945 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 47946 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 47947 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 47948 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 47949 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 47950 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 47951 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 47952 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 47953 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 47954 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 47955 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 47956 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 47957 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 47958 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 47959 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 47960 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 47961 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 47962 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 47963 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 47964 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 47965 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 47966 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 47967 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 47968 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 47969 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 47970 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 47971 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 47972 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 47973 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 47974 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 47975 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 47976 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 47977 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 47978 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 47979 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 47980 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 47981 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 47982 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 47983 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 47984 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 47985 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 47986 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 47987 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 47988 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 47989 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 47990 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 47991 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 47992 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 47993 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 47994 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 47995 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 47996 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 47997 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 47998 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 47999 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 48000 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 48001 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 48002 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 48003 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 48004 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 48005 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 48006 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 48007 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 48008 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 48009 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS |
|---|
| 48010 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 48011 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 48012 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 48013 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 48014 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 48015 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 48016 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 48017 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 48018 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 48019 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 48020 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 48021 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 48022 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 48023 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 48024 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 48025 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 48026 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK |
|---|
| 48027 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 48028 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 48029 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 48030 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 48031 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 48032 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 48033 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 48034 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 48035 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 48036 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 48037 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 48038 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 48039 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 48040 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 48041 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 48042 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 48043 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 48044 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 48045 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 48046 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 48047 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 48048 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 48049 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 48050 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 48051 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 48052 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 48053 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 48054 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 48055 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 48056 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 48057 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 48058 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 48059 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 48060 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 48061 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 48062 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG0 |
|---|
| 48063 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 48064 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 48065 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG1 |
|---|
| 48066 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 48067 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 48068 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG2 |
|---|
| 48069 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 48070 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 48071 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG3 |
|---|
| 48072 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 48073 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 48074 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG0 |
|---|
| 48075 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 48076 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 48077 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG1 |
|---|
| 48078 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 48079 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 48080 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG2 |
|---|
| 48081 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 48082 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 48083 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG3 |
|---|
| 48084 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 48085 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 48086 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST |
|---|
| 48087 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 48088 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 48089 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 48090 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 48091 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 48092 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 48093 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP |
|---|
| 48094 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 48095 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 48096 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 48097 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 48098 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 48099 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 48100 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL |
|---|
| 48101 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 48102 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 48103 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 48104 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 48105 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST |
|---|
| 48106 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 48107 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 48108 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 48109 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 48110 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 48111 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 48112 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP |
|---|
| 48113 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 48114 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 48115 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 48116 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 48117 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 48118 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 48119 | //BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL |
|---|
| 48120 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 48121 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 48122 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 48123 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 48124 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 48125 | #define BIF_CFG_DEV0_EPF0_VF27_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 48126 | |
|---|
| 48127 | |
|---|
| 48128 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp |
|---|
| 48129 | //BIF_CFG_DEV0_EPF0_VF28_VENDOR_ID |
|---|
| 48130 | #define BIF_CFG_DEV0_EPF0_VF28_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 48131 | #define BIF_CFG_DEV0_EPF0_VF28_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 48132 | //BIF_CFG_DEV0_EPF0_VF28_DEVICE_ID |
|---|
| 48133 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 48134 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 48135 | //BIF_CFG_DEV0_EPF0_VF28_COMMAND |
|---|
| 48136 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 48137 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 48138 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 48139 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 48140 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 48141 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 48142 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 48143 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 48144 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 48145 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 48146 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 48147 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 48148 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 48149 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 48150 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 48151 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 48152 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 48153 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 48154 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 48155 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 48156 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 48157 | #define BIF_CFG_DEV0_EPF0_VF28_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 48158 | //BIF_CFG_DEV0_EPF0_VF28_STATUS |
|---|
| 48159 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 48160 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 48161 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 48162 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 48163 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 48164 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 48165 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 48166 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 48167 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 48168 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 48169 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 48170 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 48171 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 48172 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 48173 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 48174 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 48175 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 48176 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 48177 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 48178 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 48179 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 48180 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 48181 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 48182 | #define BIF_CFG_DEV0_EPF0_VF28_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 48183 | //BIF_CFG_DEV0_EPF0_VF28_REVISION_ID |
|---|
| 48184 | #define BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 48185 | #define BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 48186 | #define BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 48187 | #define BIF_CFG_DEV0_EPF0_VF28_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 48188 | //BIF_CFG_DEV0_EPF0_VF28_PROG_INTERFACE |
|---|
| 48189 | #define BIF_CFG_DEV0_EPF0_VF28_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 48190 | #define BIF_CFG_DEV0_EPF0_VF28_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 48191 | //BIF_CFG_DEV0_EPF0_VF28_SUB_CLASS |
|---|
| 48192 | #define BIF_CFG_DEV0_EPF0_VF28_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 48193 | #define BIF_CFG_DEV0_EPF0_VF28_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 48194 | //BIF_CFG_DEV0_EPF0_VF28_BASE_CLASS |
|---|
| 48195 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 48196 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 48197 | //BIF_CFG_DEV0_EPF0_VF28_CACHE_LINE |
|---|
| 48198 | #define BIF_CFG_DEV0_EPF0_VF28_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 48199 | #define BIF_CFG_DEV0_EPF0_VF28_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 48200 | //BIF_CFG_DEV0_EPF0_VF28_LATENCY |
|---|
| 48201 | #define BIF_CFG_DEV0_EPF0_VF28_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 48202 | #define BIF_CFG_DEV0_EPF0_VF28_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 48203 | //BIF_CFG_DEV0_EPF0_VF28_HEADER |
|---|
| 48204 | #define 0x0 |
|---|
| 48205 | #define 0x7 |
|---|
| 48206 | #define 0x7FL |
|---|
| 48207 | #define 0x80L |
|---|
| 48208 | //BIF_CFG_DEV0_EPF0_VF28_BIST |
|---|
| 48209 | #define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 48210 | #define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 48211 | #define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 48212 | #define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 48213 | #define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_STRT_MASK 0x40L |
|---|
| 48214 | #define BIF_CFG_DEV0_EPF0_VF28_BIST__BIST_CAP_MASK 0x80L |
|---|
| 48215 | //BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_1 |
|---|
| 48216 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 48217 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48218 | //BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_2 |
|---|
| 48219 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 48220 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48221 | //BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_3 |
|---|
| 48222 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 48223 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48224 | //BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_4 |
|---|
| 48225 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 48226 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48227 | //BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_5 |
|---|
| 48228 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 48229 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48230 | //BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_6 |
|---|
| 48231 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 48232 | #define BIF_CFG_DEV0_EPF0_VF28_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48233 | //BIF_CFG_DEV0_EPF0_VF28_CARDBUS_CIS_PTR |
|---|
| 48234 | #define BIF_CFG_DEV0_EPF0_VF28_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 48235 | #define BIF_CFG_DEV0_EPF0_VF28_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 48236 | //BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID |
|---|
| 48237 | #define BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 48238 | #define BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 48239 | #define BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 48240 | #define BIF_CFG_DEV0_EPF0_VF28_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 48241 | //BIF_CFG_DEV0_EPF0_VF28_ROM_BASE_ADDR |
|---|
| 48242 | #define BIF_CFG_DEV0_EPF0_VF28_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 48243 | #define BIF_CFG_DEV0_EPF0_VF28_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48244 | //BIF_CFG_DEV0_EPF0_VF28_CAP_PTR |
|---|
| 48245 | #define BIF_CFG_DEV0_EPF0_VF28_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 48246 | #define BIF_CFG_DEV0_EPF0_VF28_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 48247 | //BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_LINE |
|---|
| 48248 | #define BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 48249 | #define BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 48250 | //BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_PIN |
|---|
| 48251 | #define BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 48252 | #define BIF_CFG_DEV0_EPF0_VF28_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 48253 | //BIF_CFG_DEV0_EPF0_VF28_MIN_GRANT |
|---|
| 48254 | #define BIF_CFG_DEV0_EPF0_VF28_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 48255 | #define BIF_CFG_DEV0_EPF0_VF28_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 48256 | //BIF_CFG_DEV0_EPF0_VF28_MAX_LATENCY |
|---|
| 48257 | #define BIF_CFG_DEV0_EPF0_VF28_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 48258 | #define BIF_CFG_DEV0_EPF0_VF28_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 48259 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST |
|---|
| 48260 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 48261 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 48262 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 48263 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 48264 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP |
|---|
| 48265 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 48266 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 48267 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 48268 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 48269 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 48270 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 48271 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 48272 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 48273 | //BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP |
|---|
| 48274 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 48275 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 48276 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 48277 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 48278 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 48279 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 48280 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 48281 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 48282 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 48283 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 48284 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 48285 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 48286 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 48287 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 48288 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 48289 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 48290 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 48291 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 48292 | //BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL |
|---|
| 48293 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 48294 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 48295 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 48296 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 48297 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 48298 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 48299 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 48300 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 48301 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 48302 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 48303 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 48304 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 48305 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 48306 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 48307 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 48308 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 48309 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 48310 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 48311 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 48312 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 48313 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 48314 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 48315 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 48316 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 48317 | //BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS |
|---|
| 48318 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 48319 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 48320 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 48321 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 48322 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 48323 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 48324 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 48325 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 48326 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 48327 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 48328 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 48329 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 48330 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 48331 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 48332 | //BIF_CFG_DEV0_EPF0_VF28_LINK_CAP |
|---|
| 48333 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 48334 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 48335 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 48336 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 48337 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 48338 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 48339 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 48340 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 48341 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 48342 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 48343 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 48344 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 48345 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 48346 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 48347 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 48348 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 48349 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 48350 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 48351 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 48352 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 48353 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 48354 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 48355 | //BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL |
|---|
| 48356 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 48357 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 48358 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 48359 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 48360 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 48361 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 48362 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 48363 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 48364 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 48365 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 48366 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 48367 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 48368 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 48369 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 48370 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 48371 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 48372 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 48373 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 48374 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 48375 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 48376 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 48377 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 48378 | //BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS |
|---|
| 48379 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 48380 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 48381 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 48382 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 48383 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 48384 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 48385 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 48386 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 48387 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 48388 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 48389 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 48390 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 48391 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 48392 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 48393 | //BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2 |
|---|
| 48394 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 48395 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 48396 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 48397 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 48398 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 48399 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 48400 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 48401 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 48402 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 48403 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 48404 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 48405 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 48406 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 48407 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 48408 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 48409 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 48410 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 48411 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 48412 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 48413 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 48414 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 48415 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 48416 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 48417 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 48418 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 48419 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 48420 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 48421 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 48422 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 48423 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 48424 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 48425 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 48426 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 48427 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 48428 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 48429 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 48430 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 48431 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 48432 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 48433 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 48434 | //BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2 |
|---|
| 48435 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 48436 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 48437 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 48438 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 48439 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 48440 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 48441 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 48442 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 48443 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 48444 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 48445 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 48446 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 48447 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 48448 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 48449 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 48450 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 48451 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 48452 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 48453 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 48454 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 48455 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 48456 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 48457 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 48458 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 48459 | //BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS2 |
|---|
| 48460 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 48461 | #define BIF_CFG_DEV0_EPF0_VF28_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 48462 | //BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2 |
|---|
| 48463 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 48464 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 48465 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 48466 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 48467 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 48468 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 48469 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 48470 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 48471 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 48472 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 48473 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 48474 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 48475 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 48476 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 48477 | //BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2 |
|---|
| 48478 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 48479 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 48480 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 48481 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 48482 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 48483 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 48484 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 48485 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 48486 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 48487 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 48488 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 48489 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 48490 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 48491 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 48492 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 48493 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 48494 | //BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2 |
|---|
| 48495 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 48496 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 48497 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 48498 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 48499 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 48500 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 48501 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 48502 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 48503 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 48504 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 48505 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 48506 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 48507 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 48508 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 48509 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 48510 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 48511 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 48512 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 48513 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 48514 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 48515 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 48516 | #define BIF_CFG_DEV0_EPF0_VF28_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 48517 | //BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST |
|---|
| 48518 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 48519 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 48520 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 48521 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 48522 | //BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL |
|---|
| 48523 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 48524 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 48525 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 48526 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 48527 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 48528 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 48529 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 48530 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 48531 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 48532 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 48533 | //BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_LO |
|---|
| 48534 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 48535 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 48536 | //BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_HI |
|---|
| 48537 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 48538 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 48539 | //BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA |
|---|
| 48540 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 48541 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 48542 | //BIF_CFG_DEV0_EPF0_VF28_MSI_MASK |
|---|
| 48543 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 48544 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 48545 | //BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_64 |
|---|
| 48546 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 48547 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 48548 | //BIF_CFG_DEV0_EPF0_VF28_MSI_MASK_64 |
|---|
| 48549 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 48550 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 48551 | //BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING |
|---|
| 48552 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 48553 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 48554 | //BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_64 |
|---|
| 48555 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 48556 | #define BIF_CFG_DEV0_EPF0_VF28_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 48557 | //BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST |
|---|
| 48558 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 48559 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 48560 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 48561 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 48562 | //BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL |
|---|
| 48563 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 48564 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 48565 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 48566 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 48567 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 48568 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 48569 | //BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE |
|---|
| 48570 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 48571 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 48572 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 48573 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 48574 | //BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA |
|---|
| 48575 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 48576 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 48577 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 48578 | #define BIF_CFG_DEV0_EPF0_VF28_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 48579 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 48580 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 48581 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 48582 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 48583 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 48584 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 48585 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 48586 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 48587 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 48588 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 48589 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 48590 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 48591 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 48592 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 48593 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC1 |
|---|
| 48594 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 48595 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 48596 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC2 |
|---|
| 48597 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 48598 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 48599 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 48600 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 48601 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 48602 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 48603 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 48604 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 48605 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 48606 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS |
|---|
| 48607 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 48608 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 48609 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 48610 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 48611 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 48612 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 48613 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 48614 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 48615 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 48616 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 48617 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 48618 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 48619 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 48620 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 48621 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 48622 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 48623 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 48624 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 48625 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 48626 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 48627 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 48628 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 48629 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 48630 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 48631 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 48632 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 48633 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 48634 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 48635 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 48636 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 48637 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 48638 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 48639 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK |
|---|
| 48640 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 48641 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 48642 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 48643 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 48644 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 48645 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 48646 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 48647 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 48648 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 48649 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 48650 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 48651 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 48652 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 48653 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 48654 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 48655 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 48656 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 48657 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 48658 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 48659 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 48660 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 48661 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 48662 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 48663 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 48664 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 48665 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 48666 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 48667 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 48668 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 48669 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 48670 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 48671 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 48672 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 48673 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 48674 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 48675 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 48676 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 48677 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 48678 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 48679 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 48680 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 48681 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 48682 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 48683 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 48684 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 48685 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 48686 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 48687 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 48688 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 48689 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 48690 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 48691 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 48692 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 48693 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 48694 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 48695 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 48696 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 48697 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 48698 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 48699 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 48700 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 48701 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 48702 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 48703 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 48704 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 48705 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS |
|---|
| 48706 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 48707 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 48708 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 48709 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 48710 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 48711 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 48712 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 48713 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 48714 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 48715 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 48716 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 48717 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 48718 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 48719 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 48720 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 48721 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 48722 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK |
|---|
| 48723 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 48724 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 48725 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 48726 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 48727 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 48728 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 48729 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 48730 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 48731 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 48732 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 48733 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 48734 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 48735 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 48736 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 48737 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 48738 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 48739 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 48740 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 48741 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 48742 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 48743 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 48744 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 48745 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 48746 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 48747 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 48748 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 48749 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 48750 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 48751 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 48752 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 48753 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 48754 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 48755 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 48756 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 48757 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 48758 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG0 |
|---|
| 48759 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 48760 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 48761 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG1 |
|---|
| 48762 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 48763 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 48764 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG2 |
|---|
| 48765 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 48766 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 48767 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG3 |
|---|
| 48768 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 48769 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 48770 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG0 |
|---|
| 48771 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 48772 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 48773 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG1 |
|---|
| 48774 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 48775 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 48776 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG2 |
|---|
| 48777 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 48778 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 48779 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG3 |
|---|
| 48780 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 48781 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 48782 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST |
|---|
| 48783 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 48784 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 48785 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 48786 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 48787 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 48788 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 48789 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP |
|---|
| 48790 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 48791 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 48792 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 48793 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 48794 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 48795 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 48796 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL |
|---|
| 48797 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 48798 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 48799 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 48800 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 48801 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST |
|---|
| 48802 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 48803 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 48804 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 48805 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 48806 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 48807 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 48808 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP |
|---|
| 48809 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 48810 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 48811 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 48812 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 48813 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 48814 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 48815 | //BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL |
|---|
| 48816 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 48817 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 48818 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 48819 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 48820 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 48821 | #define BIF_CFG_DEV0_EPF0_VF28_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 48822 | |
|---|
| 48823 | |
|---|
| 48824 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp |
|---|
| 48825 | //BIF_CFG_DEV0_EPF0_VF29_VENDOR_ID |
|---|
| 48826 | #define BIF_CFG_DEV0_EPF0_VF29_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 48827 | #define BIF_CFG_DEV0_EPF0_VF29_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 48828 | //BIF_CFG_DEV0_EPF0_VF29_DEVICE_ID |
|---|
| 48829 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 48830 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 48831 | //BIF_CFG_DEV0_EPF0_VF29_COMMAND |
|---|
| 48832 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 48833 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 48834 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 48835 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 48836 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 48837 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 48838 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 48839 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 48840 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 48841 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 48842 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 48843 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 48844 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 48845 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 48846 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 48847 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 48848 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 48849 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 48850 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 48851 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 48852 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 48853 | #define BIF_CFG_DEV0_EPF0_VF29_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 48854 | //BIF_CFG_DEV0_EPF0_VF29_STATUS |
|---|
| 48855 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 48856 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 48857 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 48858 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 48859 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 48860 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 48861 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 48862 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 48863 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 48864 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 48865 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 48866 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 48867 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 48868 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 48869 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 48870 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 48871 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 48872 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 48873 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 48874 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 48875 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 48876 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 48877 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 48878 | #define BIF_CFG_DEV0_EPF0_VF29_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 48879 | //BIF_CFG_DEV0_EPF0_VF29_REVISION_ID |
|---|
| 48880 | #define BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 48881 | #define BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 48882 | #define BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 48883 | #define BIF_CFG_DEV0_EPF0_VF29_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 48884 | //BIF_CFG_DEV0_EPF0_VF29_PROG_INTERFACE |
|---|
| 48885 | #define BIF_CFG_DEV0_EPF0_VF29_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 48886 | #define BIF_CFG_DEV0_EPF0_VF29_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 48887 | //BIF_CFG_DEV0_EPF0_VF29_SUB_CLASS |
|---|
| 48888 | #define BIF_CFG_DEV0_EPF0_VF29_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 48889 | #define BIF_CFG_DEV0_EPF0_VF29_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 48890 | //BIF_CFG_DEV0_EPF0_VF29_BASE_CLASS |
|---|
| 48891 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 48892 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 48893 | //BIF_CFG_DEV0_EPF0_VF29_CACHE_LINE |
|---|
| 48894 | #define BIF_CFG_DEV0_EPF0_VF29_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 48895 | #define BIF_CFG_DEV0_EPF0_VF29_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 48896 | //BIF_CFG_DEV0_EPF0_VF29_LATENCY |
|---|
| 48897 | #define BIF_CFG_DEV0_EPF0_VF29_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 48898 | #define BIF_CFG_DEV0_EPF0_VF29_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 48899 | //BIF_CFG_DEV0_EPF0_VF29_HEADER |
|---|
| 48900 | #define 0x0 |
|---|
| 48901 | #define 0x7 |
|---|
| 48902 | #define 0x7FL |
|---|
| 48903 | #define 0x80L |
|---|
| 48904 | //BIF_CFG_DEV0_EPF0_VF29_BIST |
|---|
| 48905 | #define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 48906 | #define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 48907 | #define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 48908 | #define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 48909 | #define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_STRT_MASK 0x40L |
|---|
| 48910 | #define BIF_CFG_DEV0_EPF0_VF29_BIST__BIST_CAP_MASK 0x80L |
|---|
| 48911 | //BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_1 |
|---|
| 48912 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 48913 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48914 | //BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_2 |
|---|
| 48915 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 48916 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48917 | //BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_3 |
|---|
| 48918 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 48919 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48920 | //BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_4 |
|---|
| 48921 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 48922 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48923 | //BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_5 |
|---|
| 48924 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 48925 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48926 | //BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_6 |
|---|
| 48927 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 48928 | #define BIF_CFG_DEV0_EPF0_VF29_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48929 | //BIF_CFG_DEV0_EPF0_VF29_CARDBUS_CIS_PTR |
|---|
| 48930 | #define BIF_CFG_DEV0_EPF0_VF29_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 48931 | #define BIF_CFG_DEV0_EPF0_VF29_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 48932 | //BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID |
|---|
| 48933 | #define BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 48934 | #define BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 48935 | #define BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 48936 | #define BIF_CFG_DEV0_EPF0_VF29_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 48937 | //BIF_CFG_DEV0_EPF0_VF29_ROM_BASE_ADDR |
|---|
| 48938 | #define BIF_CFG_DEV0_EPF0_VF29_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 48939 | #define BIF_CFG_DEV0_EPF0_VF29_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 48940 | //BIF_CFG_DEV0_EPF0_VF29_CAP_PTR |
|---|
| 48941 | #define BIF_CFG_DEV0_EPF0_VF29_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 48942 | #define BIF_CFG_DEV0_EPF0_VF29_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 48943 | //BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_LINE |
|---|
| 48944 | #define BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 48945 | #define BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 48946 | //BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_PIN |
|---|
| 48947 | #define BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 48948 | #define BIF_CFG_DEV0_EPF0_VF29_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 48949 | //BIF_CFG_DEV0_EPF0_VF29_MIN_GRANT |
|---|
| 48950 | #define BIF_CFG_DEV0_EPF0_VF29_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 48951 | #define BIF_CFG_DEV0_EPF0_VF29_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 48952 | //BIF_CFG_DEV0_EPF0_VF29_MAX_LATENCY |
|---|
| 48953 | #define BIF_CFG_DEV0_EPF0_VF29_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 48954 | #define BIF_CFG_DEV0_EPF0_VF29_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 48955 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST |
|---|
| 48956 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 48957 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 48958 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 48959 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 48960 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP |
|---|
| 48961 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 48962 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 48963 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 48964 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 48965 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 48966 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 48967 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 48968 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 48969 | //BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP |
|---|
| 48970 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 48971 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 48972 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 48973 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 48974 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 48975 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 48976 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 48977 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 48978 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 48979 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 48980 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 48981 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 48982 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 48983 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 48984 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 48985 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 48986 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 48987 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 48988 | //BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL |
|---|
| 48989 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 48990 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 48991 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 48992 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 48993 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 48994 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 48995 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 48996 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 48997 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 48998 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 48999 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 49000 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 49001 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 49002 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 49003 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 49004 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 49005 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 49006 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 49007 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 49008 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 49009 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 49010 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 49011 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 49012 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 49013 | //BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS |
|---|
| 49014 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 49015 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 49016 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 49017 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 49018 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 49019 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 49020 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 49021 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 49022 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 49023 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 49024 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 49025 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 49026 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 49027 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 49028 | //BIF_CFG_DEV0_EPF0_VF29_LINK_CAP |
|---|
| 49029 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 49030 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 49031 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 49032 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 49033 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 49034 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 49035 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 49036 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 49037 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 49038 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 49039 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 49040 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 49041 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 49042 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 49043 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 49044 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 49045 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 49046 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 49047 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 49048 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 49049 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 49050 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 49051 | //BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL |
|---|
| 49052 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 49053 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 49054 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 49055 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 49056 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 49057 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 49058 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 49059 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 49060 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 49061 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 49062 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 49063 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 49064 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 49065 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 49066 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 49067 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 49068 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 49069 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 49070 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 49071 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 49072 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 49073 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 49074 | //BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS |
|---|
| 49075 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 49076 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 49077 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 49078 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 49079 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 49080 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 49081 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 49082 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 49083 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 49084 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 49085 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 49086 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 49087 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 49088 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 49089 | //BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2 |
|---|
| 49090 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 49091 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 49092 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 49093 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 49094 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 49095 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 49096 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 49097 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 49098 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 49099 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 49100 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 49101 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 49102 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 49103 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 49104 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 49105 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 49106 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 49107 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 49108 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 49109 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 49110 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 49111 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 49112 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 49113 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 49114 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 49115 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 49116 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 49117 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 49118 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 49119 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 49120 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 49121 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 49122 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 49123 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 49124 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 49125 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 49126 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 49127 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 49128 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 49129 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 49130 | //BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2 |
|---|
| 49131 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 49132 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 49133 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 49134 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 49135 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 49136 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 49137 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 49138 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 49139 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 49140 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 49141 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 49142 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 49143 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 49144 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 49145 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 49146 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 49147 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 49148 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 49149 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 49150 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 49151 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 49152 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 49153 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 49154 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 49155 | //BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS2 |
|---|
| 49156 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 49157 | #define BIF_CFG_DEV0_EPF0_VF29_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 49158 | //BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2 |
|---|
| 49159 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 49160 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 49161 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 49162 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 49163 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 49164 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 49165 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 49166 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 49167 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 49168 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 49169 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 49170 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 49171 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 49172 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 49173 | //BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2 |
|---|
| 49174 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 49175 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 49176 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 49177 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 49178 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 49179 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 49180 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 49181 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 49182 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 49183 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 49184 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 49185 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 49186 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 49187 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 49188 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 49189 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 49190 | //BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2 |
|---|
| 49191 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 49192 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 49193 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 49194 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 49195 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 49196 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 49197 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 49198 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 49199 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 49200 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 49201 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 49202 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 49203 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 49204 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 49205 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 49206 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 49207 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 49208 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 49209 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 49210 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 49211 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 49212 | #define BIF_CFG_DEV0_EPF0_VF29_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 49213 | //BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST |
|---|
| 49214 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49215 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 49216 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 49217 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 49218 | //BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL |
|---|
| 49219 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 49220 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 49221 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 49222 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 49223 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 49224 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 49225 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 49226 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 49227 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 49228 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 49229 | //BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_LO |
|---|
| 49230 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 49231 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 49232 | //BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_HI |
|---|
| 49233 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 49234 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 49235 | //BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA |
|---|
| 49236 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 49237 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 49238 | //BIF_CFG_DEV0_EPF0_VF29_MSI_MASK |
|---|
| 49239 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 49240 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 49241 | //BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_64 |
|---|
| 49242 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 49243 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 49244 | //BIF_CFG_DEV0_EPF0_VF29_MSI_MASK_64 |
|---|
| 49245 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 49246 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 49247 | //BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING |
|---|
| 49248 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 49249 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 49250 | //BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_64 |
|---|
| 49251 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 49252 | #define BIF_CFG_DEV0_EPF0_VF29_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 49253 | //BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST |
|---|
| 49254 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49255 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 49256 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 49257 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 49258 | //BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL |
|---|
| 49259 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 49260 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 49261 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 49262 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 49263 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 49264 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 49265 | //BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE |
|---|
| 49266 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 49267 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 49268 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 49269 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 49270 | //BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA |
|---|
| 49271 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 49272 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 49273 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 49274 | #define BIF_CFG_DEV0_EPF0_VF29_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 49275 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 49276 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49277 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 49278 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 49279 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 49280 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 49281 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 49282 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 49283 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 49284 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 49285 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 49286 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 49287 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 49288 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 49289 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC1 |
|---|
| 49290 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 49291 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 49292 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC2 |
|---|
| 49293 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 49294 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 49295 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 49296 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49297 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 49298 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 49299 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 49300 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 49301 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 49302 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS |
|---|
| 49303 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 49304 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 49305 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 49306 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 49307 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 49308 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 49309 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 49310 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 49311 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 49312 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 49313 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 49314 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 49315 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 49316 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 49317 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 49318 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 49319 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 49320 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 49321 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 49322 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 49323 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 49324 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 49325 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 49326 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 49327 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 49328 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 49329 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 49330 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 49331 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 49332 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 49333 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 49334 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 49335 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK |
|---|
| 49336 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 49337 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 49338 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 49339 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 49340 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 49341 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 49342 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 49343 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 49344 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 49345 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 49346 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 49347 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 49348 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 49349 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 49350 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 49351 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 49352 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 49353 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 49354 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 49355 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 49356 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 49357 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 49358 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 49359 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 49360 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 49361 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 49362 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 49363 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 49364 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 49365 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 49366 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 49367 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 49368 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 49369 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 49370 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 49371 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 49372 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 49373 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 49374 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 49375 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 49376 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 49377 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 49378 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 49379 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 49380 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 49381 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 49382 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 49383 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 49384 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 49385 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 49386 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 49387 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 49388 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 49389 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 49390 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 49391 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 49392 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 49393 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 49394 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 49395 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 49396 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 49397 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 49398 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 49399 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 49400 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 49401 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS |
|---|
| 49402 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 49403 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 49404 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 49405 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 49406 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 49407 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 49408 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 49409 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 49410 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 49411 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 49412 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 49413 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 49414 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 49415 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 49416 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 49417 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 49418 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK |
|---|
| 49419 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 49420 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 49421 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 49422 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 49423 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 49424 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 49425 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 49426 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 49427 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 49428 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 49429 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 49430 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 49431 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 49432 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 49433 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 49434 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 49435 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 49436 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 49437 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 49438 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 49439 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 49440 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 49441 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 49442 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 49443 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 49444 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 49445 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 49446 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 49447 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 49448 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 49449 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 49450 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 49451 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 49452 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 49453 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 49454 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG0 |
|---|
| 49455 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 49456 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 49457 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG1 |
|---|
| 49458 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 49459 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 49460 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG2 |
|---|
| 49461 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 49462 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 49463 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG3 |
|---|
| 49464 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 49465 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 49466 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG0 |
|---|
| 49467 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 49468 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 49469 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG1 |
|---|
| 49470 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 49471 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 49472 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG2 |
|---|
| 49473 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 49474 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 49475 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG3 |
|---|
| 49476 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 49477 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 49478 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST |
|---|
| 49479 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49480 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 49481 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 49482 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 49483 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 49484 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 49485 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP |
|---|
| 49486 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 49487 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 49488 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 49489 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 49490 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 49491 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 49492 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL |
|---|
| 49493 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 49494 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 49495 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 49496 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 49497 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST |
|---|
| 49498 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49499 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 49500 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 49501 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 49502 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 49503 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 49504 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP |
|---|
| 49505 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 49506 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 49507 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 49508 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 49509 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 49510 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 49511 | //BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL |
|---|
| 49512 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 49513 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 49514 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 49515 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 49516 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 49517 | #define BIF_CFG_DEV0_EPF0_VF29_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 49518 | |
|---|
| 49519 | |
|---|
| 49520 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp |
|---|
| 49521 | //BIF_CFG_DEV0_EPF0_VF30_VENDOR_ID |
|---|
| 49522 | #define BIF_CFG_DEV0_EPF0_VF30_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 49523 | #define BIF_CFG_DEV0_EPF0_VF30_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 49524 | //BIF_CFG_DEV0_EPF0_VF30_DEVICE_ID |
|---|
| 49525 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 49526 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 49527 | //BIF_CFG_DEV0_EPF0_VF30_COMMAND |
|---|
| 49528 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 49529 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 49530 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 49531 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 49532 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 49533 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 49534 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 49535 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 49536 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 49537 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 49538 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 49539 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 49540 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 49541 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 49542 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 49543 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 49544 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 49545 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 49546 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 49547 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 49548 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 49549 | #define BIF_CFG_DEV0_EPF0_VF30_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 49550 | //BIF_CFG_DEV0_EPF0_VF30_STATUS |
|---|
| 49551 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 49552 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 49553 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 49554 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 49555 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 49556 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 49557 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 49558 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 49559 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 49560 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 49561 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 49562 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 49563 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 49564 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 49565 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 49566 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 49567 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 49568 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 49569 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 49570 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 49571 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 49572 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 49573 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 49574 | #define BIF_CFG_DEV0_EPF0_VF30_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 49575 | //BIF_CFG_DEV0_EPF0_VF30_REVISION_ID |
|---|
| 49576 | #define BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 49577 | #define BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 49578 | #define BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 49579 | #define BIF_CFG_DEV0_EPF0_VF30_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 49580 | //BIF_CFG_DEV0_EPF0_VF30_PROG_INTERFACE |
|---|
| 49581 | #define BIF_CFG_DEV0_EPF0_VF30_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 49582 | #define BIF_CFG_DEV0_EPF0_VF30_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 49583 | //BIF_CFG_DEV0_EPF0_VF30_SUB_CLASS |
|---|
| 49584 | #define BIF_CFG_DEV0_EPF0_VF30_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 49585 | #define BIF_CFG_DEV0_EPF0_VF30_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 49586 | //BIF_CFG_DEV0_EPF0_VF30_BASE_CLASS |
|---|
| 49587 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 49588 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 49589 | //BIF_CFG_DEV0_EPF0_VF30_CACHE_LINE |
|---|
| 49590 | #define BIF_CFG_DEV0_EPF0_VF30_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 49591 | #define BIF_CFG_DEV0_EPF0_VF30_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 49592 | //BIF_CFG_DEV0_EPF0_VF30_LATENCY |
|---|
| 49593 | #define BIF_CFG_DEV0_EPF0_VF30_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 49594 | #define BIF_CFG_DEV0_EPF0_VF30_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 49595 | //BIF_CFG_DEV0_EPF0_VF30_HEADER |
|---|
| 49596 | #define 0x0 |
|---|
| 49597 | #define 0x7 |
|---|
| 49598 | #define 0x7FL |
|---|
| 49599 | #define 0x80L |
|---|
| 49600 | //BIF_CFG_DEV0_EPF0_VF30_BIST |
|---|
| 49601 | #define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 49602 | #define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 49603 | #define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 49604 | #define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 49605 | #define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_STRT_MASK 0x40L |
|---|
| 49606 | #define BIF_CFG_DEV0_EPF0_VF30_BIST__BIST_CAP_MASK 0x80L |
|---|
| 49607 | //BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_1 |
|---|
| 49608 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 49609 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 49610 | //BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_2 |
|---|
| 49611 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 49612 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 49613 | //BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_3 |
|---|
| 49614 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 49615 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 49616 | //BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_4 |
|---|
| 49617 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 49618 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 49619 | //BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_5 |
|---|
| 49620 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 49621 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 49622 | //BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_6 |
|---|
| 49623 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 49624 | #define BIF_CFG_DEV0_EPF0_VF30_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 49625 | //BIF_CFG_DEV0_EPF0_VF30_CARDBUS_CIS_PTR |
|---|
| 49626 | #define BIF_CFG_DEV0_EPF0_VF30_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 49627 | #define BIF_CFG_DEV0_EPF0_VF30_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 49628 | //BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID |
|---|
| 49629 | #define BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 49630 | #define BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 49631 | #define BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 49632 | #define BIF_CFG_DEV0_EPF0_VF30_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 49633 | //BIF_CFG_DEV0_EPF0_VF30_ROM_BASE_ADDR |
|---|
| 49634 | #define BIF_CFG_DEV0_EPF0_VF30_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 49635 | #define BIF_CFG_DEV0_EPF0_VF30_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 49636 | //BIF_CFG_DEV0_EPF0_VF30_CAP_PTR |
|---|
| 49637 | #define BIF_CFG_DEV0_EPF0_VF30_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 49638 | #define BIF_CFG_DEV0_EPF0_VF30_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 49639 | //BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_LINE |
|---|
| 49640 | #define BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 49641 | #define BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 49642 | //BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_PIN |
|---|
| 49643 | #define BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 49644 | #define BIF_CFG_DEV0_EPF0_VF30_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 49645 | //BIF_CFG_DEV0_EPF0_VF30_MIN_GRANT |
|---|
| 49646 | #define BIF_CFG_DEV0_EPF0_VF30_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 49647 | #define BIF_CFG_DEV0_EPF0_VF30_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 49648 | //BIF_CFG_DEV0_EPF0_VF30_MAX_LATENCY |
|---|
| 49649 | #define BIF_CFG_DEV0_EPF0_VF30_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 49650 | #define BIF_CFG_DEV0_EPF0_VF30_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 49651 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST |
|---|
| 49652 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49653 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 49654 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 49655 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 49656 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP |
|---|
| 49657 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 49658 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 49659 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 49660 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 49661 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 49662 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 49663 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 49664 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 49665 | //BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP |
|---|
| 49666 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 49667 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 49668 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 49669 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 49670 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 49671 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 49672 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 49673 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 49674 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 49675 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 49676 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 49677 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 49678 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 49679 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 49680 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 49681 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 49682 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 49683 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 49684 | //BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL |
|---|
| 49685 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 49686 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 49687 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 49688 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 49689 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 49690 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 49691 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 49692 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 49693 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 49694 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 49695 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 49696 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 49697 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 49698 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 49699 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 49700 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 49701 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 49702 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 49703 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 49704 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 49705 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 49706 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 49707 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 49708 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 49709 | //BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS |
|---|
| 49710 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 49711 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 49712 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 49713 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 49714 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 49715 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 49716 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 49717 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 49718 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 49719 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 49720 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 49721 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 49722 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 49723 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 49724 | //BIF_CFG_DEV0_EPF0_VF30_LINK_CAP |
|---|
| 49725 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 49726 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 49727 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 49728 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 49729 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 49730 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 49731 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 49732 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 49733 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 49734 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 49735 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 49736 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 49737 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 49738 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 49739 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 49740 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 49741 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 49742 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 49743 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 49744 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 49745 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 49746 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 49747 | //BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL |
|---|
| 49748 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 49749 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 49750 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 49751 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 49752 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 49753 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 49754 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 49755 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 49756 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 49757 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 49758 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 49759 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 49760 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 49761 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 49762 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 49763 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 49764 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 49765 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 49766 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 49767 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 49768 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 49769 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 49770 | //BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS |
|---|
| 49771 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 49772 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 49773 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 49774 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 49775 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 49776 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 49777 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 49778 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 49779 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 49780 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 49781 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 49782 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 49783 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 49784 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 49785 | //BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2 |
|---|
| 49786 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 49787 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 49788 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 49789 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 49790 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 49791 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 49792 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 49793 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 49794 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 49795 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 49796 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 49797 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 49798 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 49799 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 49800 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 49801 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 49802 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 49803 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 49804 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 49805 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 49806 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 49807 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 49808 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 49809 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 49810 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 49811 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 49812 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 49813 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 49814 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 49815 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 49816 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 49817 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 49818 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 49819 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 49820 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 49821 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 49822 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 49823 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 49824 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 49825 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 49826 | //BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2 |
|---|
| 49827 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 49828 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 49829 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 49830 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 49831 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 49832 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 49833 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 49834 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 49835 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 49836 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 49837 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 49838 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 49839 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 49840 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 49841 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 49842 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 49843 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 49844 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 49845 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 49846 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 49847 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 49848 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 49849 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 49850 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 49851 | //BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS2 |
|---|
| 49852 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 49853 | #define BIF_CFG_DEV0_EPF0_VF30_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 49854 | //BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2 |
|---|
| 49855 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 49856 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 49857 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 49858 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 49859 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 49860 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 49861 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 49862 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 49863 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 49864 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 49865 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 49866 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 49867 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 49868 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 49869 | //BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2 |
|---|
| 49870 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 49871 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 49872 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 49873 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 49874 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 49875 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 49876 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 49877 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 49878 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 49879 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 49880 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 49881 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 49882 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 49883 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 49884 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 49885 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 49886 | //BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2 |
|---|
| 49887 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 49888 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 49889 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 49890 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 49891 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 49892 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 49893 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 49894 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 49895 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 49896 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 49897 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 49898 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 49899 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 49900 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 49901 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 49902 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 49903 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 49904 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 49905 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 49906 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 49907 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 49908 | #define BIF_CFG_DEV0_EPF0_VF30_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 49909 | //BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST |
|---|
| 49910 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49911 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 49912 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 49913 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 49914 | //BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL |
|---|
| 49915 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 49916 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 49917 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 49918 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 49919 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 49920 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 49921 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 49922 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 49923 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 49924 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 49925 | //BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_LO |
|---|
| 49926 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 49927 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 49928 | //BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_HI |
|---|
| 49929 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 49930 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 49931 | //BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA |
|---|
| 49932 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 49933 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 49934 | //BIF_CFG_DEV0_EPF0_VF30_MSI_MASK |
|---|
| 49935 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 49936 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 49937 | //BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_64 |
|---|
| 49938 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 49939 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 49940 | //BIF_CFG_DEV0_EPF0_VF30_MSI_MASK_64 |
|---|
| 49941 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 49942 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 49943 | //BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING |
|---|
| 49944 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 49945 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 49946 | //BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_64 |
|---|
| 49947 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 49948 | #define BIF_CFG_DEV0_EPF0_VF30_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 49949 | //BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST |
|---|
| 49950 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49951 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 49952 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 49953 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 49954 | //BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL |
|---|
| 49955 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 49956 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 49957 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 49958 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 49959 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 49960 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 49961 | //BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE |
|---|
| 49962 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 49963 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 49964 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 49965 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 49966 | //BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA |
|---|
| 49967 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 49968 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 49969 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 49970 | #define BIF_CFG_DEV0_EPF0_VF30_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 49971 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 49972 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49973 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 49974 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 49975 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 49976 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 49977 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 49978 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 49979 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 49980 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 49981 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 49982 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 49983 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 49984 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 49985 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC1 |
|---|
| 49986 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 49987 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 49988 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC2 |
|---|
| 49989 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 49990 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 49991 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 49992 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 49993 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 49994 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 49995 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 49996 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 49997 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 49998 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS |
|---|
| 49999 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 50000 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 50001 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 50002 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 50003 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 50004 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 50005 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 50006 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 50007 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 50008 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 50009 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 50010 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 50011 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 50012 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 50013 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 50014 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 50015 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 50016 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 50017 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 50018 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 50019 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 50020 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 50021 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 50022 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 50023 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 50024 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 50025 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 50026 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 50027 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 50028 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 50029 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 50030 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 50031 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK |
|---|
| 50032 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 50033 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 50034 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 50035 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 50036 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 50037 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 50038 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 50039 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 50040 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 50041 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 50042 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 50043 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 50044 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 50045 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 50046 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 50047 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 50048 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 50049 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 50050 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 50051 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 50052 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 50053 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 50054 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 50055 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 50056 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 50057 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 50058 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 50059 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 50060 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 50061 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 50062 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 50063 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 50064 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 50065 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 50066 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 50067 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 50068 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 50069 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 50070 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 50071 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 50072 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 50073 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 50074 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 50075 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 50076 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 50077 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 50078 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 50079 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 50080 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 50081 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 50082 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 50083 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 50084 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 50085 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 50086 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 50087 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 50088 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 50089 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 50090 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 50091 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 50092 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 50093 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 50094 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 50095 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 50096 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 50097 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS |
|---|
| 50098 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 50099 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 50100 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 50101 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 50102 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 50103 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 50104 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 50105 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 50106 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 50107 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 50108 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 50109 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 50110 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 50111 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 50112 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 50113 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 50114 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK |
|---|
| 50115 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 50116 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 50117 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 50118 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 50119 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 50120 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 50121 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 50122 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 50123 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 50124 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 50125 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 50126 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 50127 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 50128 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 50129 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 50130 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 50131 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 50132 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 50133 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 50134 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 50135 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 50136 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 50137 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 50138 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 50139 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 50140 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 50141 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 50142 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 50143 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 50144 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 50145 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 50146 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 50147 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 50148 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 50149 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 50150 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG0 |
|---|
| 50151 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 50152 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 50153 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG1 |
|---|
| 50154 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 50155 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 50156 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG2 |
|---|
| 50157 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 50158 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 50159 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG3 |
|---|
| 50160 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 50161 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 50162 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG0 |
|---|
| 50163 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 50164 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 50165 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG1 |
|---|
| 50166 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 50167 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 50168 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG2 |
|---|
| 50169 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 50170 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 50171 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG3 |
|---|
| 50172 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 50173 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 50174 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST |
|---|
| 50175 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 50176 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 50177 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 50178 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 50179 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 50180 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 50181 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP |
|---|
| 50182 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 50183 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 50184 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 50185 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 50186 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 50187 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 50188 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL |
|---|
| 50189 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 50190 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 50191 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 50192 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 50193 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST |
|---|
| 50194 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 50195 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 50196 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 50197 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 50198 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 50199 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 50200 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP |
|---|
| 50201 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 50202 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 50203 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 50204 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 50205 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 50206 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 50207 | //BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL |
|---|
| 50208 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 50209 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 50210 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 50211 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 50212 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 50213 | #define BIF_CFG_DEV0_EPF0_VF30_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 50214 | |
|---|
| 50215 | |
|---|
| 50216 | // addressBlock: nbio_nbif0_pciemsix_0_usb_MSIXTDEC |
|---|
| 50217 | //PCIEMSIX_VECT0_ADDR_LO |
|---|
| 50218 | #define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50219 | #define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50220 | //PCIEMSIX_VECT0_ADDR_HI |
|---|
| 50221 | #define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50222 | #define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50223 | //PCIEMSIX_VECT0_MSG_DATA |
|---|
| 50224 | #define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50225 | #define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50226 | //PCIEMSIX_VECT0_CONTROL |
|---|
| 50227 | #define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50228 | #define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50229 | //PCIEMSIX_VECT1_ADDR_LO |
|---|
| 50230 | #define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50231 | #define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50232 | //PCIEMSIX_VECT1_ADDR_HI |
|---|
| 50233 | #define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50234 | #define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50235 | //PCIEMSIX_VECT1_MSG_DATA |
|---|
| 50236 | #define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50237 | #define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50238 | //PCIEMSIX_VECT1_CONTROL |
|---|
| 50239 | #define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50240 | #define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50241 | //PCIEMSIX_VECT2_ADDR_LO |
|---|
| 50242 | #define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50243 | #define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50244 | //PCIEMSIX_VECT2_ADDR_HI |
|---|
| 50245 | #define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50246 | #define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50247 | //PCIEMSIX_VECT2_MSG_DATA |
|---|
| 50248 | #define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50249 | #define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50250 | //PCIEMSIX_VECT2_CONTROL |
|---|
| 50251 | #define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50252 | #define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50253 | //PCIEMSIX_VECT3_ADDR_LO |
|---|
| 50254 | #define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50255 | #define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50256 | //PCIEMSIX_VECT3_ADDR_HI |
|---|
| 50257 | #define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50258 | #define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50259 | //PCIEMSIX_VECT3_MSG_DATA |
|---|
| 50260 | #define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50261 | #define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50262 | //PCIEMSIX_VECT3_CONTROL |
|---|
| 50263 | #define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50264 | #define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50265 | //PCIEMSIX_VECT4_ADDR_LO |
|---|
| 50266 | #define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50267 | #define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50268 | //PCIEMSIX_VECT4_ADDR_HI |
|---|
| 50269 | #define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50270 | #define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50271 | //PCIEMSIX_VECT4_MSG_DATA |
|---|
| 50272 | #define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50273 | #define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50274 | //PCIEMSIX_VECT4_CONTROL |
|---|
| 50275 | #define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50276 | #define PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50277 | //PCIEMSIX_VECT5_ADDR_LO |
|---|
| 50278 | #define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50279 | #define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50280 | //PCIEMSIX_VECT5_ADDR_HI |
|---|
| 50281 | #define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50282 | #define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50283 | //PCIEMSIX_VECT5_MSG_DATA |
|---|
| 50284 | #define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50285 | #define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50286 | //PCIEMSIX_VECT5_CONTROL |
|---|
| 50287 | #define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50288 | #define PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50289 | //PCIEMSIX_VECT6_ADDR_LO |
|---|
| 50290 | #define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50291 | #define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50292 | //PCIEMSIX_VECT6_ADDR_HI |
|---|
| 50293 | #define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50294 | #define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50295 | //PCIEMSIX_VECT6_MSG_DATA |
|---|
| 50296 | #define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50297 | #define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50298 | //PCIEMSIX_VECT6_CONTROL |
|---|
| 50299 | #define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50300 | #define PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50301 | //PCIEMSIX_VECT7_ADDR_LO |
|---|
| 50302 | #define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50303 | #define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50304 | //PCIEMSIX_VECT7_ADDR_HI |
|---|
| 50305 | #define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50306 | #define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50307 | //PCIEMSIX_VECT7_MSG_DATA |
|---|
| 50308 | #define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50309 | #define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50310 | //PCIEMSIX_VECT7_CONTROL |
|---|
| 50311 | #define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50312 | #define PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50313 | //PCIEMSIX_VECT8_ADDR_LO |
|---|
| 50314 | #define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50315 | #define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50316 | //PCIEMSIX_VECT8_ADDR_HI |
|---|
| 50317 | #define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50318 | #define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50319 | //PCIEMSIX_VECT8_MSG_DATA |
|---|
| 50320 | #define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50321 | #define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50322 | //PCIEMSIX_VECT8_CONTROL |
|---|
| 50323 | #define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50324 | #define PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50325 | //PCIEMSIX_VECT9_ADDR_LO |
|---|
| 50326 | #define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50327 | #define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50328 | //PCIEMSIX_VECT9_ADDR_HI |
|---|
| 50329 | #define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50330 | #define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50331 | //PCIEMSIX_VECT9_MSG_DATA |
|---|
| 50332 | #define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50333 | #define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50334 | //PCIEMSIX_VECT9_CONTROL |
|---|
| 50335 | #define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50336 | #define PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50337 | //PCIEMSIX_VECT10_ADDR_LO |
|---|
| 50338 | #define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50339 | #define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50340 | //PCIEMSIX_VECT10_ADDR_HI |
|---|
| 50341 | #define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50342 | #define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50343 | //PCIEMSIX_VECT10_MSG_DATA |
|---|
| 50344 | #define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50345 | #define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50346 | //PCIEMSIX_VECT10_CONTROL |
|---|
| 50347 | #define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50348 | #define PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50349 | //PCIEMSIX_VECT11_ADDR_LO |
|---|
| 50350 | #define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50351 | #define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50352 | //PCIEMSIX_VECT11_ADDR_HI |
|---|
| 50353 | #define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50354 | #define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50355 | //PCIEMSIX_VECT11_MSG_DATA |
|---|
| 50356 | #define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50357 | #define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50358 | //PCIEMSIX_VECT11_CONTROL |
|---|
| 50359 | #define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50360 | #define PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50361 | //PCIEMSIX_VECT12_ADDR_LO |
|---|
| 50362 | #define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50363 | #define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50364 | //PCIEMSIX_VECT12_ADDR_HI |
|---|
| 50365 | #define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50366 | #define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50367 | //PCIEMSIX_VECT12_MSG_DATA |
|---|
| 50368 | #define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50369 | #define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50370 | //PCIEMSIX_VECT12_CONTROL |
|---|
| 50371 | #define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50372 | #define PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50373 | //PCIEMSIX_VECT13_ADDR_LO |
|---|
| 50374 | #define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50375 | #define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50376 | //PCIEMSIX_VECT13_ADDR_HI |
|---|
| 50377 | #define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50378 | #define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50379 | //PCIEMSIX_VECT13_MSG_DATA |
|---|
| 50380 | #define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50381 | #define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50382 | //PCIEMSIX_VECT13_CONTROL |
|---|
| 50383 | #define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50384 | #define PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50385 | //PCIEMSIX_VECT14_ADDR_LO |
|---|
| 50386 | #define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50387 | #define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50388 | //PCIEMSIX_VECT14_ADDR_HI |
|---|
| 50389 | #define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50390 | #define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50391 | //PCIEMSIX_VECT14_MSG_DATA |
|---|
| 50392 | #define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50393 | #define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50394 | //PCIEMSIX_VECT14_CONTROL |
|---|
| 50395 | #define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50396 | #define PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50397 | //PCIEMSIX_VECT15_ADDR_LO |
|---|
| 50398 | #define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50399 | #define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50400 | //PCIEMSIX_VECT15_ADDR_HI |
|---|
| 50401 | #define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50402 | #define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50403 | //PCIEMSIX_VECT15_MSG_DATA |
|---|
| 50404 | #define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50405 | #define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50406 | //PCIEMSIX_VECT15_CONTROL |
|---|
| 50407 | #define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50408 | #define PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50409 | //PCIEMSIX_VECT16_ADDR_LO |
|---|
| 50410 | #define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50411 | #define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50412 | //PCIEMSIX_VECT16_ADDR_HI |
|---|
| 50413 | #define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50414 | #define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50415 | //PCIEMSIX_VECT16_MSG_DATA |
|---|
| 50416 | #define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50417 | #define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50418 | //PCIEMSIX_VECT16_CONTROL |
|---|
| 50419 | #define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50420 | #define PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50421 | //PCIEMSIX_VECT17_ADDR_LO |
|---|
| 50422 | #define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50423 | #define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50424 | //PCIEMSIX_VECT17_ADDR_HI |
|---|
| 50425 | #define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50426 | #define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50427 | //PCIEMSIX_VECT17_MSG_DATA |
|---|
| 50428 | #define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50429 | #define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50430 | //PCIEMSIX_VECT17_CONTROL |
|---|
| 50431 | #define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50432 | #define PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50433 | //PCIEMSIX_VECT18_ADDR_LO |
|---|
| 50434 | #define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50435 | #define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50436 | //PCIEMSIX_VECT18_ADDR_HI |
|---|
| 50437 | #define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50438 | #define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50439 | //PCIEMSIX_VECT18_MSG_DATA |
|---|
| 50440 | #define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50441 | #define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50442 | //PCIEMSIX_VECT18_CONTROL |
|---|
| 50443 | #define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50444 | #define PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50445 | //PCIEMSIX_VECT19_ADDR_LO |
|---|
| 50446 | #define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50447 | #define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50448 | //PCIEMSIX_VECT19_ADDR_HI |
|---|
| 50449 | #define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50450 | #define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50451 | //PCIEMSIX_VECT19_MSG_DATA |
|---|
| 50452 | #define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50453 | #define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50454 | //PCIEMSIX_VECT19_CONTROL |
|---|
| 50455 | #define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50456 | #define PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50457 | //PCIEMSIX_VECT20_ADDR_LO |
|---|
| 50458 | #define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50459 | #define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50460 | //PCIEMSIX_VECT20_ADDR_HI |
|---|
| 50461 | #define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50462 | #define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50463 | //PCIEMSIX_VECT20_MSG_DATA |
|---|
| 50464 | #define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50465 | #define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50466 | //PCIEMSIX_VECT20_CONTROL |
|---|
| 50467 | #define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50468 | #define PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50469 | //PCIEMSIX_VECT21_ADDR_LO |
|---|
| 50470 | #define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50471 | #define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50472 | //PCIEMSIX_VECT21_ADDR_HI |
|---|
| 50473 | #define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50474 | #define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50475 | //PCIEMSIX_VECT21_MSG_DATA |
|---|
| 50476 | #define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50477 | #define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50478 | //PCIEMSIX_VECT21_CONTROL |
|---|
| 50479 | #define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50480 | #define PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50481 | //PCIEMSIX_VECT22_ADDR_LO |
|---|
| 50482 | #define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50483 | #define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50484 | //PCIEMSIX_VECT22_ADDR_HI |
|---|
| 50485 | #define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50486 | #define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50487 | //PCIEMSIX_VECT22_MSG_DATA |
|---|
| 50488 | #define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50489 | #define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50490 | //PCIEMSIX_VECT22_CONTROL |
|---|
| 50491 | #define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50492 | #define PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50493 | //PCIEMSIX_VECT23_ADDR_LO |
|---|
| 50494 | #define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50495 | #define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50496 | //PCIEMSIX_VECT23_ADDR_HI |
|---|
| 50497 | #define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50498 | #define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50499 | //PCIEMSIX_VECT23_MSG_DATA |
|---|
| 50500 | #define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50501 | #define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50502 | //PCIEMSIX_VECT23_CONTROL |
|---|
| 50503 | #define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50504 | #define PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50505 | //PCIEMSIX_VECT24_ADDR_LO |
|---|
| 50506 | #define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50507 | #define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50508 | //PCIEMSIX_VECT24_ADDR_HI |
|---|
| 50509 | #define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50510 | #define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50511 | //PCIEMSIX_VECT24_MSG_DATA |
|---|
| 50512 | #define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50513 | #define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50514 | //PCIEMSIX_VECT24_CONTROL |
|---|
| 50515 | #define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50516 | #define PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50517 | //PCIEMSIX_VECT25_ADDR_LO |
|---|
| 50518 | #define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50519 | #define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50520 | //PCIEMSIX_VECT25_ADDR_HI |
|---|
| 50521 | #define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50522 | #define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50523 | //PCIEMSIX_VECT25_MSG_DATA |
|---|
| 50524 | #define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50525 | #define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50526 | //PCIEMSIX_VECT25_CONTROL |
|---|
| 50527 | #define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50528 | #define PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50529 | //PCIEMSIX_VECT26_ADDR_LO |
|---|
| 50530 | #define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50531 | #define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50532 | //PCIEMSIX_VECT26_ADDR_HI |
|---|
| 50533 | #define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50534 | #define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50535 | //PCIEMSIX_VECT26_MSG_DATA |
|---|
| 50536 | #define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50537 | #define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50538 | //PCIEMSIX_VECT26_CONTROL |
|---|
| 50539 | #define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50540 | #define PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50541 | //PCIEMSIX_VECT27_ADDR_LO |
|---|
| 50542 | #define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50543 | #define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50544 | //PCIEMSIX_VECT27_ADDR_HI |
|---|
| 50545 | #define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50546 | #define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50547 | //PCIEMSIX_VECT27_MSG_DATA |
|---|
| 50548 | #define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50549 | #define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50550 | //PCIEMSIX_VECT27_CONTROL |
|---|
| 50551 | #define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50552 | #define PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50553 | //PCIEMSIX_VECT28_ADDR_LO |
|---|
| 50554 | #define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50555 | #define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50556 | //PCIEMSIX_VECT28_ADDR_HI |
|---|
| 50557 | #define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50558 | #define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50559 | //PCIEMSIX_VECT28_MSG_DATA |
|---|
| 50560 | #define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50561 | #define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50562 | //PCIEMSIX_VECT28_CONTROL |
|---|
| 50563 | #define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50564 | #define PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50565 | //PCIEMSIX_VECT29_ADDR_LO |
|---|
| 50566 | #define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50567 | #define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50568 | //PCIEMSIX_VECT29_ADDR_HI |
|---|
| 50569 | #define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50570 | #define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50571 | //PCIEMSIX_VECT29_MSG_DATA |
|---|
| 50572 | #define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50573 | #define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50574 | //PCIEMSIX_VECT29_CONTROL |
|---|
| 50575 | #define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50576 | #define PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50577 | //PCIEMSIX_VECT30_ADDR_LO |
|---|
| 50578 | #define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50579 | #define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50580 | //PCIEMSIX_VECT30_ADDR_HI |
|---|
| 50581 | #define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50582 | #define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50583 | //PCIEMSIX_VECT30_MSG_DATA |
|---|
| 50584 | #define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50585 | #define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50586 | //PCIEMSIX_VECT30_CONTROL |
|---|
| 50587 | #define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50588 | #define PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50589 | //PCIEMSIX_VECT31_ADDR_LO |
|---|
| 50590 | #define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50591 | #define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50592 | //PCIEMSIX_VECT31_ADDR_HI |
|---|
| 50593 | #define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50594 | #define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50595 | //PCIEMSIX_VECT31_MSG_DATA |
|---|
| 50596 | #define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50597 | #define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50598 | //PCIEMSIX_VECT31_CONTROL |
|---|
| 50599 | #define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50600 | #define PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50601 | //PCIEMSIX_VECT32_ADDR_LO |
|---|
| 50602 | #define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50603 | #define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50604 | //PCIEMSIX_VECT32_ADDR_HI |
|---|
| 50605 | #define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50606 | #define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50607 | //PCIEMSIX_VECT32_MSG_DATA |
|---|
| 50608 | #define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50609 | #define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50610 | //PCIEMSIX_VECT32_CONTROL |
|---|
| 50611 | #define PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50612 | #define PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50613 | //PCIEMSIX_VECT33_ADDR_LO |
|---|
| 50614 | #define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50615 | #define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50616 | //PCIEMSIX_VECT33_ADDR_HI |
|---|
| 50617 | #define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50618 | #define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50619 | //PCIEMSIX_VECT33_MSG_DATA |
|---|
| 50620 | #define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50621 | #define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50622 | //PCIEMSIX_VECT33_CONTROL |
|---|
| 50623 | #define PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50624 | #define PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50625 | //PCIEMSIX_VECT34_ADDR_LO |
|---|
| 50626 | #define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50627 | #define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50628 | //PCIEMSIX_VECT34_ADDR_HI |
|---|
| 50629 | #define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50630 | #define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50631 | //PCIEMSIX_VECT34_MSG_DATA |
|---|
| 50632 | #define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50633 | #define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50634 | //PCIEMSIX_VECT34_CONTROL |
|---|
| 50635 | #define PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50636 | #define PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50637 | //PCIEMSIX_VECT35_ADDR_LO |
|---|
| 50638 | #define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50639 | #define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50640 | //PCIEMSIX_VECT35_ADDR_HI |
|---|
| 50641 | #define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50642 | #define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50643 | //PCIEMSIX_VECT35_MSG_DATA |
|---|
| 50644 | #define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50645 | #define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50646 | //PCIEMSIX_VECT35_CONTROL |
|---|
| 50647 | #define PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50648 | #define PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50649 | //PCIEMSIX_VECT36_ADDR_LO |
|---|
| 50650 | #define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50651 | #define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50652 | //PCIEMSIX_VECT36_ADDR_HI |
|---|
| 50653 | #define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50654 | #define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50655 | //PCIEMSIX_VECT36_MSG_DATA |
|---|
| 50656 | #define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50657 | #define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50658 | //PCIEMSIX_VECT36_CONTROL |
|---|
| 50659 | #define PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50660 | #define PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50661 | //PCIEMSIX_VECT37_ADDR_LO |
|---|
| 50662 | #define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50663 | #define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50664 | //PCIEMSIX_VECT37_ADDR_HI |
|---|
| 50665 | #define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50666 | #define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50667 | //PCIEMSIX_VECT37_MSG_DATA |
|---|
| 50668 | #define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50669 | #define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50670 | //PCIEMSIX_VECT37_CONTROL |
|---|
| 50671 | #define PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50672 | #define PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50673 | //PCIEMSIX_VECT38_ADDR_LO |
|---|
| 50674 | #define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50675 | #define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50676 | //PCIEMSIX_VECT38_ADDR_HI |
|---|
| 50677 | #define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50678 | #define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50679 | //PCIEMSIX_VECT38_MSG_DATA |
|---|
| 50680 | #define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50681 | #define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50682 | //PCIEMSIX_VECT38_CONTROL |
|---|
| 50683 | #define PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50684 | #define PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50685 | //PCIEMSIX_VECT39_ADDR_LO |
|---|
| 50686 | #define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50687 | #define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50688 | //PCIEMSIX_VECT39_ADDR_HI |
|---|
| 50689 | #define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50690 | #define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50691 | //PCIEMSIX_VECT39_MSG_DATA |
|---|
| 50692 | #define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50693 | #define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50694 | //PCIEMSIX_VECT39_CONTROL |
|---|
| 50695 | #define PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50696 | #define PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50697 | //PCIEMSIX_VECT40_ADDR_LO |
|---|
| 50698 | #define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50699 | #define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50700 | //PCIEMSIX_VECT40_ADDR_HI |
|---|
| 50701 | #define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50702 | #define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50703 | //PCIEMSIX_VECT40_MSG_DATA |
|---|
| 50704 | #define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50705 | #define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50706 | //PCIEMSIX_VECT40_CONTROL |
|---|
| 50707 | #define PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50708 | #define PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50709 | //PCIEMSIX_VECT41_ADDR_LO |
|---|
| 50710 | #define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50711 | #define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50712 | //PCIEMSIX_VECT41_ADDR_HI |
|---|
| 50713 | #define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50714 | #define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50715 | //PCIEMSIX_VECT41_MSG_DATA |
|---|
| 50716 | #define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50717 | #define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50718 | //PCIEMSIX_VECT41_CONTROL |
|---|
| 50719 | #define PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50720 | #define PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50721 | //PCIEMSIX_VECT42_ADDR_LO |
|---|
| 50722 | #define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50723 | #define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50724 | //PCIEMSIX_VECT42_ADDR_HI |
|---|
| 50725 | #define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50726 | #define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50727 | //PCIEMSIX_VECT42_MSG_DATA |
|---|
| 50728 | #define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50729 | #define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50730 | //PCIEMSIX_VECT42_CONTROL |
|---|
| 50731 | #define PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50732 | #define PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50733 | //PCIEMSIX_VECT43_ADDR_LO |
|---|
| 50734 | #define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50735 | #define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50736 | //PCIEMSIX_VECT43_ADDR_HI |
|---|
| 50737 | #define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50738 | #define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50739 | //PCIEMSIX_VECT43_MSG_DATA |
|---|
| 50740 | #define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50741 | #define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50742 | //PCIEMSIX_VECT43_CONTROL |
|---|
| 50743 | #define PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50744 | #define PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50745 | //PCIEMSIX_VECT44_ADDR_LO |
|---|
| 50746 | #define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50747 | #define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50748 | //PCIEMSIX_VECT44_ADDR_HI |
|---|
| 50749 | #define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50750 | #define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50751 | //PCIEMSIX_VECT44_MSG_DATA |
|---|
| 50752 | #define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50753 | #define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50754 | //PCIEMSIX_VECT44_CONTROL |
|---|
| 50755 | #define PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50756 | #define PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50757 | //PCIEMSIX_VECT45_ADDR_LO |
|---|
| 50758 | #define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50759 | #define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50760 | //PCIEMSIX_VECT45_ADDR_HI |
|---|
| 50761 | #define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50762 | #define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50763 | //PCIEMSIX_VECT45_MSG_DATA |
|---|
| 50764 | #define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50765 | #define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50766 | //PCIEMSIX_VECT45_CONTROL |
|---|
| 50767 | #define PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50768 | #define PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50769 | //PCIEMSIX_VECT46_ADDR_LO |
|---|
| 50770 | #define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50771 | #define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50772 | //PCIEMSIX_VECT46_ADDR_HI |
|---|
| 50773 | #define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50774 | #define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50775 | //PCIEMSIX_VECT46_MSG_DATA |
|---|
| 50776 | #define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50777 | #define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50778 | //PCIEMSIX_VECT46_CONTROL |
|---|
| 50779 | #define PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50780 | #define PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50781 | //PCIEMSIX_VECT47_ADDR_LO |
|---|
| 50782 | #define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50783 | #define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50784 | //PCIEMSIX_VECT47_ADDR_HI |
|---|
| 50785 | #define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50786 | #define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50787 | //PCIEMSIX_VECT47_MSG_DATA |
|---|
| 50788 | #define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50789 | #define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50790 | //PCIEMSIX_VECT47_CONTROL |
|---|
| 50791 | #define PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50792 | #define PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50793 | //PCIEMSIX_VECT48_ADDR_LO |
|---|
| 50794 | #define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50795 | #define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50796 | //PCIEMSIX_VECT48_ADDR_HI |
|---|
| 50797 | #define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50798 | #define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50799 | //PCIEMSIX_VECT48_MSG_DATA |
|---|
| 50800 | #define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50801 | #define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50802 | //PCIEMSIX_VECT48_CONTROL |
|---|
| 50803 | #define PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50804 | #define PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50805 | //PCIEMSIX_VECT49_ADDR_LO |
|---|
| 50806 | #define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50807 | #define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50808 | //PCIEMSIX_VECT49_ADDR_HI |
|---|
| 50809 | #define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50810 | #define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50811 | //PCIEMSIX_VECT49_MSG_DATA |
|---|
| 50812 | #define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50813 | #define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50814 | //PCIEMSIX_VECT49_CONTROL |
|---|
| 50815 | #define PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50816 | #define PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50817 | //PCIEMSIX_VECT50_ADDR_LO |
|---|
| 50818 | #define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50819 | #define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50820 | //PCIEMSIX_VECT50_ADDR_HI |
|---|
| 50821 | #define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50822 | #define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50823 | //PCIEMSIX_VECT50_MSG_DATA |
|---|
| 50824 | #define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50825 | #define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50826 | //PCIEMSIX_VECT50_CONTROL |
|---|
| 50827 | #define PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50828 | #define PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50829 | //PCIEMSIX_VECT51_ADDR_LO |
|---|
| 50830 | #define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50831 | #define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50832 | //PCIEMSIX_VECT51_ADDR_HI |
|---|
| 50833 | #define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50834 | #define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50835 | //PCIEMSIX_VECT51_MSG_DATA |
|---|
| 50836 | #define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50837 | #define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50838 | //PCIEMSIX_VECT51_CONTROL |
|---|
| 50839 | #define PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50840 | #define PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50841 | //PCIEMSIX_VECT52_ADDR_LO |
|---|
| 50842 | #define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50843 | #define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50844 | //PCIEMSIX_VECT52_ADDR_HI |
|---|
| 50845 | #define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50846 | #define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50847 | //PCIEMSIX_VECT52_MSG_DATA |
|---|
| 50848 | #define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50849 | #define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50850 | //PCIEMSIX_VECT52_CONTROL |
|---|
| 50851 | #define PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50852 | #define PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50853 | //PCIEMSIX_VECT53_ADDR_LO |
|---|
| 50854 | #define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50855 | #define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50856 | //PCIEMSIX_VECT53_ADDR_HI |
|---|
| 50857 | #define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50858 | #define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50859 | //PCIEMSIX_VECT53_MSG_DATA |
|---|
| 50860 | #define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50861 | #define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50862 | //PCIEMSIX_VECT53_CONTROL |
|---|
| 50863 | #define PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50864 | #define PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50865 | //PCIEMSIX_VECT54_ADDR_LO |
|---|
| 50866 | #define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50867 | #define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50868 | //PCIEMSIX_VECT54_ADDR_HI |
|---|
| 50869 | #define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50870 | #define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50871 | //PCIEMSIX_VECT54_MSG_DATA |
|---|
| 50872 | #define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50873 | #define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50874 | //PCIEMSIX_VECT54_CONTROL |
|---|
| 50875 | #define PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50876 | #define PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50877 | //PCIEMSIX_VECT55_ADDR_LO |
|---|
| 50878 | #define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50879 | #define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50880 | //PCIEMSIX_VECT55_ADDR_HI |
|---|
| 50881 | #define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50882 | #define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50883 | //PCIEMSIX_VECT55_MSG_DATA |
|---|
| 50884 | #define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50885 | #define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50886 | //PCIEMSIX_VECT55_CONTROL |
|---|
| 50887 | #define PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50888 | #define PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50889 | //PCIEMSIX_VECT56_ADDR_LO |
|---|
| 50890 | #define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50891 | #define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50892 | //PCIEMSIX_VECT56_ADDR_HI |
|---|
| 50893 | #define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50894 | #define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50895 | //PCIEMSIX_VECT56_MSG_DATA |
|---|
| 50896 | #define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50897 | #define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50898 | //PCIEMSIX_VECT56_CONTROL |
|---|
| 50899 | #define PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50900 | #define PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50901 | //PCIEMSIX_VECT57_ADDR_LO |
|---|
| 50902 | #define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50903 | #define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50904 | //PCIEMSIX_VECT57_ADDR_HI |
|---|
| 50905 | #define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50906 | #define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50907 | //PCIEMSIX_VECT57_MSG_DATA |
|---|
| 50908 | #define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50909 | #define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50910 | //PCIEMSIX_VECT57_CONTROL |
|---|
| 50911 | #define PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50912 | #define PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50913 | //PCIEMSIX_VECT58_ADDR_LO |
|---|
| 50914 | #define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50915 | #define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50916 | //PCIEMSIX_VECT58_ADDR_HI |
|---|
| 50917 | #define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50918 | #define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50919 | //PCIEMSIX_VECT58_MSG_DATA |
|---|
| 50920 | #define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50921 | #define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50922 | //PCIEMSIX_VECT58_CONTROL |
|---|
| 50923 | #define PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50924 | #define PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50925 | //PCIEMSIX_VECT59_ADDR_LO |
|---|
| 50926 | #define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50927 | #define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50928 | //PCIEMSIX_VECT59_ADDR_HI |
|---|
| 50929 | #define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50930 | #define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50931 | //PCIEMSIX_VECT59_MSG_DATA |
|---|
| 50932 | #define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50933 | #define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50934 | //PCIEMSIX_VECT59_CONTROL |
|---|
| 50935 | #define PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50936 | #define PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50937 | //PCIEMSIX_VECT60_ADDR_LO |
|---|
| 50938 | #define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50939 | #define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50940 | //PCIEMSIX_VECT60_ADDR_HI |
|---|
| 50941 | #define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50942 | #define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50943 | //PCIEMSIX_VECT60_MSG_DATA |
|---|
| 50944 | #define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50945 | #define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50946 | //PCIEMSIX_VECT60_CONTROL |
|---|
| 50947 | #define PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50948 | #define PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50949 | //PCIEMSIX_VECT61_ADDR_LO |
|---|
| 50950 | #define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50951 | #define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50952 | //PCIEMSIX_VECT61_ADDR_HI |
|---|
| 50953 | #define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50954 | #define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50955 | //PCIEMSIX_VECT61_MSG_DATA |
|---|
| 50956 | #define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50957 | #define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50958 | //PCIEMSIX_VECT61_CONTROL |
|---|
| 50959 | #define PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50960 | #define PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50961 | //PCIEMSIX_VECT62_ADDR_LO |
|---|
| 50962 | #define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50963 | #define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50964 | //PCIEMSIX_VECT62_ADDR_HI |
|---|
| 50965 | #define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50966 | #define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50967 | //PCIEMSIX_VECT62_MSG_DATA |
|---|
| 50968 | #define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50969 | #define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50970 | //PCIEMSIX_VECT62_CONTROL |
|---|
| 50971 | #define PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50972 | #define PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50973 | //PCIEMSIX_VECT63_ADDR_LO |
|---|
| 50974 | #define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50975 | #define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50976 | //PCIEMSIX_VECT63_ADDR_HI |
|---|
| 50977 | #define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50978 | #define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50979 | //PCIEMSIX_VECT63_MSG_DATA |
|---|
| 50980 | #define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50981 | #define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50982 | //PCIEMSIX_VECT63_CONTROL |
|---|
| 50983 | #define PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50984 | #define PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50985 | //PCIEMSIX_VECT64_ADDR_LO |
|---|
| 50986 | #define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50987 | #define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 50988 | //PCIEMSIX_VECT64_ADDR_HI |
|---|
| 50989 | #define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 50990 | #define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 50991 | //PCIEMSIX_VECT64_MSG_DATA |
|---|
| 50992 | #define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 50993 | #define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 50994 | //PCIEMSIX_VECT64_CONTROL |
|---|
| 50995 | #define PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 50996 | #define PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 50997 | //PCIEMSIX_VECT65_ADDR_LO |
|---|
| 50998 | #define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 50999 | #define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51000 | //PCIEMSIX_VECT65_ADDR_HI |
|---|
| 51001 | #define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51002 | #define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51003 | //PCIEMSIX_VECT65_MSG_DATA |
|---|
| 51004 | #define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51005 | #define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51006 | //PCIEMSIX_VECT65_CONTROL |
|---|
| 51007 | #define PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51008 | #define PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51009 | //PCIEMSIX_VECT66_ADDR_LO |
|---|
| 51010 | #define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51011 | #define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51012 | //PCIEMSIX_VECT66_ADDR_HI |
|---|
| 51013 | #define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51014 | #define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51015 | //PCIEMSIX_VECT66_MSG_DATA |
|---|
| 51016 | #define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51017 | #define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51018 | //PCIEMSIX_VECT66_CONTROL |
|---|
| 51019 | #define PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51020 | #define PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51021 | //PCIEMSIX_VECT67_ADDR_LO |
|---|
| 51022 | #define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51023 | #define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51024 | //PCIEMSIX_VECT67_ADDR_HI |
|---|
| 51025 | #define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51026 | #define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51027 | //PCIEMSIX_VECT67_MSG_DATA |
|---|
| 51028 | #define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51029 | #define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51030 | //PCIEMSIX_VECT67_CONTROL |
|---|
| 51031 | #define PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51032 | #define PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51033 | //PCIEMSIX_VECT68_ADDR_LO |
|---|
| 51034 | #define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51035 | #define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51036 | //PCIEMSIX_VECT68_ADDR_HI |
|---|
| 51037 | #define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51038 | #define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51039 | //PCIEMSIX_VECT68_MSG_DATA |
|---|
| 51040 | #define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51041 | #define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51042 | //PCIEMSIX_VECT68_CONTROL |
|---|
| 51043 | #define PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51044 | #define PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51045 | //PCIEMSIX_VECT69_ADDR_LO |
|---|
| 51046 | #define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51047 | #define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51048 | //PCIEMSIX_VECT69_ADDR_HI |
|---|
| 51049 | #define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51050 | #define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51051 | //PCIEMSIX_VECT69_MSG_DATA |
|---|
| 51052 | #define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51053 | #define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51054 | //PCIEMSIX_VECT69_CONTROL |
|---|
| 51055 | #define PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51056 | #define PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51057 | //PCIEMSIX_VECT70_ADDR_LO |
|---|
| 51058 | #define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51059 | #define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51060 | //PCIEMSIX_VECT70_ADDR_HI |
|---|
| 51061 | #define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51062 | #define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51063 | //PCIEMSIX_VECT70_MSG_DATA |
|---|
| 51064 | #define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51065 | #define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51066 | //PCIEMSIX_VECT70_CONTROL |
|---|
| 51067 | #define PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51068 | #define PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51069 | //PCIEMSIX_VECT71_ADDR_LO |
|---|
| 51070 | #define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51071 | #define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51072 | //PCIEMSIX_VECT71_ADDR_HI |
|---|
| 51073 | #define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51074 | #define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51075 | //PCIEMSIX_VECT71_MSG_DATA |
|---|
| 51076 | #define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51077 | #define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51078 | //PCIEMSIX_VECT71_CONTROL |
|---|
| 51079 | #define PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51080 | #define PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51081 | //PCIEMSIX_VECT72_ADDR_LO |
|---|
| 51082 | #define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51083 | #define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51084 | //PCIEMSIX_VECT72_ADDR_HI |
|---|
| 51085 | #define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51086 | #define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51087 | //PCIEMSIX_VECT72_MSG_DATA |
|---|
| 51088 | #define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51089 | #define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51090 | //PCIEMSIX_VECT72_CONTROL |
|---|
| 51091 | #define PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51092 | #define PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51093 | //PCIEMSIX_VECT73_ADDR_LO |
|---|
| 51094 | #define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51095 | #define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51096 | //PCIEMSIX_VECT73_ADDR_HI |
|---|
| 51097 | #define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51098 | #define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51099 | //PCIEMSIX_VECT73_MSG_DATA |
|---|
| 51100 | #define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51101 | #define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51102 | //PCIEMSIX_VECT73_CONTROL |
|---|
| 51103 | #define PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51104 | #define PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51105 | //PCIEMSIX_VECT74_ADDR_LO |
|---|
| 51106 | #define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51107 | #define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51108 | //PCIEMSIX_VECT74_ADDR_HI |
|---|
| 51109 | #define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51110 | #define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51111 | //PCIEMSIX_VECT74_MSG_DATA |
|---|
| 51112 | #define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51113 | #define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51114 | //PCIEMSIX_VECT74_CONTROL |
|---|
| 51115 | #define PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51116 | #define PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51117 | //PCIEMSIX_VECT75_ADDR_LO |
|---|
| 51118 | #define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51119 | #define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51120 | //PCIEMSIX_VECT75_ADDR_HI |
|---|
| 51121 | #define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51122 | #define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51123 | //PCIEMSIX_VECT75_MSG_DATA |
|---|
| 51124 | #define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51125 | #define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51126 | //PCIEMSIX_VECT75_CONTROL |
|---|
| 51127 | #define PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51128 | #define PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51129 | //PCIEMSIX_VECT76_ADDR_LO |
|---|
| 51130 | #define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51131 | #define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51132 | //PCIEMSIX_VECT76_ADDR_HI |
|---|
| 51133 | #define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51134 | #define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51135 | //PCIEMSIX_VECT76_MSG_DATA |
|---|
| 51136 | #define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51137 | #define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51138 | //PCIEMSIX_VECT76_CONTROL |
|---|
| 51139 | #define PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51140 | #define PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51141 | //PCIEMSIX_VECT77_ADDR_LO |
|---|
| 51142 | #define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51143 | #define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51144 | //PCIEMSIX_VECT77_ADDR_HI |
|---|
| 51145 | #define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51146 | #define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51147 | //PCIEMSIX_VECT77_MSG_DATA |
|---|
| 51148 | #define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51149 | #define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51150 | //PCIEMSIX_VECT77_CONTROL |
|---|
| 51151 | #define PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51152 | #define PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51153 | //PCIEMSIX_VECT78_ADDR_LO |
|---|
| 51154 | #define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51155 | #define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51156 | //PCIEMSIX_VECT78_ADDR_HI |
|---|
| 51157 | #define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51158 | #define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51159 | //PCIEMSIX_VECT78_MSG_DATA |
|---|
| 51160 | #define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51161 | #define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51162 | //PCIEMSIX_VECT78_CONTROL |
|---|
| 51163 | #define PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51164 | #define PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51165 | //PCIEMSIX_VECT79_ADDR_LO |
|---|
| 51166 | #define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51167 | #define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51168 | //PCIEMSIX_VECT79_ADDR_HI |
|---|
| 51169 | #define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51170 | #define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51171 | //PCIEMSIX_VECT79_MSG_DATA |
|---|
| 51172 | #define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51173 | #define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51174 | //PCIEMSIX_VECT79_CONTROL |
|---|
| 51175 | #define PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51176 | #define PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51177 | //PCIEMSIX_VECT80_ADDR_LO |
|---|
| 51178 | #define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51179 | #define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51180 | //PCIEMSIX_VECT80_ADDR_HI |
|---|
| 51181 | #define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51182 | #define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51183 | //PCIEMSIX_VECT80_MSG_DATA |
|---|
| 51184 | #define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51185 | #define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51186 | //PCIEMSIX_VECT80_CONTROL |
|---|
| 51187 | #define PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51188 | #define PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51189 | //PCIEMSIX_VECT81_ADDR_LO |
|---|
| 51190 | #define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51191 | #define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51192 | //PCIEMSIX_VECT81_ADDR_HI |
|---|
| 51193 | #define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51194 | #define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51195 | //PCIEMSIX_VECT81_MSG_DATA |
|---|
| 51196 | #define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51197 | #define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51198 | //PCIEMSIX_VECT81_CONTROL |
|---|
| 51199 | #define PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51200 | #define PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51201 | //PCIEMSIX_VECT82_ADDR_LO |
|---|
| 51202 | #define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51203 | #define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51204 | //PCIEMSIX_VECT82_ADDR_HI |
|---|
| 51205 | #define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51206 | #define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51207 | //PCIEMSIX_VECT82_MSG_DATA |
|---|
| 51208 | #define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51209 | #define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51210 | //PCIEMSIX_VECT82_CONTROL |
|---|
| 51211 | #define PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51212 | #define PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51213 | //PCIEMSIX_VECT83_ADDR_LO |
|---|
| 51214 | #define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51215 | #define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51216 | //PCIEMSIX_VECT83_ADDR_HI |
|---|
| 51217 | #define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51218 | #define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51219 | //PCIEMSIX_VECT83_MSG_DATA |
|---|
| 51220 | #define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51221 | #define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51222 | //PCIEMSIX_VECT83_CONTROL |
|---|
| 51223 | #define PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51224 | #define PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51225 | //PCIEMSIX_VECT84_ADDR_LO |
|---|
| 51226 | #define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51227 | #define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51228 | //PCIEMSIX_VECT84_ADDR_HI |
|---|
| 51229 | #define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51230 | #define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51231 | //PCIEMSIX_VECT84_MSG_DATA |
|---|
| 51232 | #define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51233 | #define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51234 | //PCIEMSIX_VECT84_CONTROL |
|---|
| 51235 | #define PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51236 | #define PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51237 | //PCIEMSIX_VECT85_ADDR_LO |
|---|
| 51238 | #define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51239 | #define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51240 | //PCIEMSIX_VECT85_ADDR_HI |
|---|
| 51241 | #define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51242 | #define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51243 | //PCIEMSIX_VECT85_MSG_DATA |
|---|
| 51244 | #define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51245 | #define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51246 | //PCIEMSIX_VECT85_CONTROL |
|---|
| 51247 | #define PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51248 | #define PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51249 | //PCIEMSIX_VECT86_ADDR_LO |
|---|
| 51250 | #define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51251 | #define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51252 | //PCIEMSIX_VECT86_ADDR_HI |
|---|
| 51253 | #define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51254 | #define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51255 | //PCIEMSIX_VECT86_MSG_DATA |
|---|
| 51256 | #define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51257 | #define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51258 | //PCIEMSIX_VECT86_CONTROL |
|---|
| 51259 | #define PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51260 | #define PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51261 | //PCIEMSIX_VECT87_ADDR_LO |
|---|
| 51262 | #define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51263 | #define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51264 | //PCIEMSIX_VECT87_ADDR_HI |
|---|
| 51265 | #define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51266 | #define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51267 | //PCIEMSIX_VECT87_MSG_DATA |
|---|
| 51268 | #define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51269 | #define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51270 | //PCIEMSIX_VECT87_CONTROL |
|---|
| 51271 | #define PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51272 | #define PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51273 | //PCIEMSIX_VECT88_ADDR_LO |
|---|
| 51274 | #define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51275 | #define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51276 | //PCIEMSIX_VECT88_ADDR_HI |
|---|
| 51277 | #define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51278 | #define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51279 | //PCIEMSIX_VECT88_MSG_DATA |
|---|
| 51280 | #define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51281 | #define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51282 | //PCIEMSIX_VECT88_CONTROL |
|---|
| 51283 | #define PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51284 | #define PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51285 | //PCIEMSIX_VECT89_ADDR_LO |
|---|
| 51286 | #define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51287 | #define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51288 | //PCIEMSIX_VECT89_ADDR_HI |
|---|
| 51289 | #define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51290 | #define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51291 | //PCIEMSIX_VECT89_MSG_DATA |
|---|
| 51292 | #define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51293 | #define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51294 | //PCIEMSIX_VECT89_CONTROL |
|---|
| 51295 | #define PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51296 | #define PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51297 | //PCIEMSIX_VECT90_ADDR_LO |
|---|
| 51298 | #define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51299 | #define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51300 | //PCIEMSIX_VECT90_ADDR_HI |
|---|
| 51301 | #define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51302 | #define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51303 | //PCIEMSIX_VECT90_MSG_DATA |
|---|
| 51304 | #define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51305 | #define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51306 | //PCIEMSIX_VECT90_CONTROL |
|---|
| 51307 | #define PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51308 | #define PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51309 | //PCIEMSIX_VECT91_ADDR_LO |
|---|
| 51310 | #define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51311 | #define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51312 | //PCIEMSIX_VECT91_ADDR_HI |
|---|
| 51313 | #define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51314 | #define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51315 | //PCIEMSIX_VECT91_MSG_DATA |
|---|
| 51316 | #define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51317 | #define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51318 | //PCIEMSIX_VECT91_CONTROL |
|---|
| 51319 | #define PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51320 | #define PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51321 | //PCIEMSIX_VECT92_ADDR_LO |
|---|
| 51322 | #define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51323 | #define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51324 | //PCIEMSIX_VECT92_ADDR_HI |
|---|
| 51325 | #define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51326 | #define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51327 | //PCIEMSIX_VECT92_MSG_DATA |
|---|
| 51328 | #define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51329 | #define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51330 | //PCIEMSIX_VECT92_CONTROL |
|---|
| 51331 | #define PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51332 | #define PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51333 | //PCIEMSIX_VECT93_ADDR_LO |
|---|
| 51334 | #define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51335 | #define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51336 | //PCIEMSIX_VECT93_ADDR_HI |
|---|
| 51337 | #define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51338 | #define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51339 | //PCIEMSIX_VECT93_MSG_DATA |
|---|
| 51340 | #define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51341 | #define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51342 | //PCIEMSIX_VECT93_CONTROL |
|---|
| 51343 | #define PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51344 | #define PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51345 | //PCIEMSIX_VECT94_ADDR_LO |
|---|
| 51346 | #define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51347 | #define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51348 | //PCIEMSIX_VECT94_ADDR_HI |
|---|
| 51349 | #define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51350 | #define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51351 | //PCIEMSIX_VECT94_MSG_DATA |
|---|
| 51352 | #define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51353 | #define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51354 | //PCIEMSIX_VECT94_CONTROL |
|---|
| 51355 | #define PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51356 | #define PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51357 | //PCIEMSIX_VECT95_ADDR_LO |
|---|
| 51358 | #define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51359 | #define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51360 | //PCIEMSIX_VECT95_ADDR_HI |
|---|
| 51361 | #define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51362 | #define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51363 | //PCIEMSIX_VECT95_MSG_DATA |
|---|
| 51364 | #define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51365 | #define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51366 | //PCIEMSIX_VECT95_CONTROL |
|---|
| 51367 | #define PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51368 | #define PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51369 | //PCIEMSIX_VECT96_ADDR_LO |
|---|
| 51370 | #define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51371 | #define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51372 | //PCIEMSIX_VECT96_ADDR_HI |
|---|
| 51373 | #define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51374 | #define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51375 | //PCIEMSIX_VECT96_MSG_DATA |
|---|
| 51376 | #define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51377 | #define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51378 | //PCIEMSIX_VECT96_CONTROL |
|---|
| 51379 | #define PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51380 | #define PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51381 | //PCIEMSIX_VECT97_ADDR_LO |
|---|
| 51382 | #define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51383 | #define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51384 | //PCIEMSIX_VECT97_ADDR_HI |
|---|
| 51385 | #define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51386 | #define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51387 | //PCIEMSIX_VECT97_MSG_DATA |
|---|
| 51388 | #define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51389 | #define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51390 | //PCIEMSIX_VECT97_CONTROL |
|---|
| 51391 | #define PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51392 | #define PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51393 | //PCIEMSIX_VECT98_ADDR_LO |
|---|
| 51394 | #define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51395 | #define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51396 | //PCIEMSIX_VECT98_ADDR_HI |
|---|
| 51397 | #define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51398 | #define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51399 | //PCIEMSIX_VECT98_MSG_DATA |
|---|
| 51400 | #define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51401 | #define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51402 | //PCIEMSIX_VECT98_CONTROL |
|---|
| 51403 | #define PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51404 | #define PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51405 | //PCIEMSIX_VECT99_ADDR_LO |
|---|
| 51406 | #define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51407 | #define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51408 | //PCIEMSIX_VECT99_ADDR_HI |
|---|
| 51409 | #define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51410 | #define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51411 | //PCIEMSIX_VECT99_MSG_DATA |
|---|
| 51412 | #define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51413 | #define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51414 | //PCIEMSIX_VECT99_CONTROL |
|---|
| 51415 | #define PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51416 | #define PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51417 | //PCIEMSIX_VECT100_ADDR_LO |
|---|
| 51418 | #define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51419 | #define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51420 | //PCIEMSIX_VECT100_ADDR_HI |
|---|
| 51421 | #define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51422 | #define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51423 | //PCIEMSIX_VECT100_MSG_DATA |
|---|
| 51424 | #define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51425 | #define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51426 | //PCIEMSIX_VECT100_CONTROL |
|---|
| 51427 | #define PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51428 | #define PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51429 | //PCIEMSIX_VECT101_ADDR_LO |
|---|
| 51430 | #define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51431 | #define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51432 | //PCIEMSIX_VECT101_ADDR_HI |
|---|
| 51433 | #define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51434 | #define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51435 | //PCIEMSIX_VECT101_MSG_DATA |
|---|
| 51436 | #define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51437 | #define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51438 | //PCIEMSIX_VECT101_CONTROL |
|---|
| 51439 | #define PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51440 | #define PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51441 | //PCIEMSIX_VECT102_ADDR_LO |
|---|
| 51442 | #define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51443 | #define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51444 | //PCIEMSIX_VECT102_ADDR_HI |
|---|
| 51445 | #define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51446 | #define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51447 | //PCIEMSIX_VECT102_MSG_DATA |
|---|
| 51448 | #define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51449 | #define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51450 | //PCIEMSIX_VECT102_CONTROL |
|---|
| 51451 | #define PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51452 | #define PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51453 | //PCIEMSIX_VECT103_ADDR_LO |
|---|
| 51454 | #define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51455 | #define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51456 | //PCIEMSIX_VECT103_ADDR_HI |
|---|
| 51457 | #define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51458 | #define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51459 | //PCIEMSIX_VECT103_MSG_DATA |
|---|
| 51460 | #define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51461 | #define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51462 | //PCIEMSIX_VECT103_CONTROL |
|---|
| 51463 | #define PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51464 | #define PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51465 | //PCIEMSIX_VECT104_ADDR_LO |
|---|
| 51466 | #define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51467 | #define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51468 | //PCIEMSIX_VECT104_ADDR_HI |
|---|
| 51469 | #define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51470 | #define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51471 | //PCIEMSIX_VECT104_MSG_DATA |
|---|
| 51472 | #define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51473 | #define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51474 | //PCIEMSIX_VECT104_CONTROL |
|---|
| 51475 | #define PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51476 | #define PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51477 | //PCIEMSIX_VECT105_ADDR_LO |
|---|
| 51478 | #define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51479 | #define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51480 | //PCIEMSIX_VECT105_ADDR_HI |
|---|
| 51481 | #define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51482 | #define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51483 | //PCIEMSIX_VECT105_MSG_DATA |
|---|
| 51484 | #define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51485 | #define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51486 | //PCIEMSIX_VECT105_CONTROL |
|---|
| 51487 | #define PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51488 | #define PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51489 | //PCIEMSIX_VECT106_ADDR_LO |
|---|
| 51490 | #define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51491 | #define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51492 | //PCIEMSIX_VECT106_ADDR_HI |
|---|
| 51493 | #define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51494 | #define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51495 | //PCIEMSIX_VECT106_MSG_DATA |
|---|
| 51496 | #define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51497 | #define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51498 | //PCIEMSIX_VECT106_CONTROL |
|---|
| 51499 | #define PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51500 | #define PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51501 | //PCIEMSIX_VECT107_ADDR_LO |
|---|
| 51502 | #define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51503 | #define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51504 | //PCIEMSIX_VECT107_ADDR_HI |
|---|
| 51505 | #define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51506 | #define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51507 | //PCIEMSIX_VECT107_MSG_DATA |
|---|
| 51508 | #define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51509 | #define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51510 | //PCIEMSIX_VECT107_CONTROL |
|---|
| 51511 | #define PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51512 | #define PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51513 | //PCIEMSIX_VECT108_ADDR_LO |
|---|
| 51514 | #define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51515 | #define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51516 | //PCIEMSIX_VECT108_ADDR_HI |
|---|
| 51517 | #define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51518 | #define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51519 | //PCIEMSIX_VECT108_MSG_DATA |
|---|
| 51520 | #define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51521 | #define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51522 | //PCIEMSIX_VECT108_CONTROL |
|---|
| 51523 | #define PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51524 | #define PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51525 | //PCIEMSIX_VECT109_ADDR_LO |
|---|
| 51526 | #define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51527 | #define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51528 | //PCIEMSIX_VECT109_ADDR_HI |
|---|
| 51529 | #define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51530 | #define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51531 | //PCIEMSIX_VECT109_MSG_DATA |
|---|
| 51532 | #define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51533 | #define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51534 | //PCIEMSIX_VECT109_CONTROL |
|---|
| 51535 | #define PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51536 | #define PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51537 | //PCIEMSIX_VECT110_ADDR_LO |
|---|
| 51538 | #define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51539 | #define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51540 | //PCIEMSIX_VECT110_ADDR_HI |
|---|
| 51541 | #define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51542 | #define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51543 | //PCIEMSIX_VECT110_MSG_DATA |
|---|
| 51544 | #define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51545 | #define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51546 | //PCIEMSIX_VECT110_CONTROL |
|---|
| 51547 | #define PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51548 | #define PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51549 | //PCIEMSIX_VECT111_ADDR_LO |
|---|
| 51550 | #define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51551 | #define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51552 | //PCIEMSIX_VECT111_ADDR_HI |
|---|
| 51553 | #define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51554 | #define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51555 | //PCIEMSIX_VECT111_MSG_DATA |
|---|
| 51556 | #define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51557 | #define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51558 | //PCIEMSIX_VECT111_CONTROL |
|---|
| 51559 | #define PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51560 | #define PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51561 | //PCIEMSIX_VECT112_ADDR_LO |
|---|
| 51562 | #define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51563 | #define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51564 | //PCIEMSIX_VECT112_ADDR_HI |
|---|
| 51565 | #define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51566 | #define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51567 | //PCIEMSIX_VECT112_MSG_DATA |
|---|
| 51568 | #define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51569 | #define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51570 | //PCIEMSIX_VECT112_CONTROL |
|---|
| 51571 | #define PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51572 | #define PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51573 | //PCIEMSIX_VECT113_ADDR_LO |
|---|
| 51574 | #define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51575 | #define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51576 | //PCIEMSIX_VECT113_ADDR_HI |
|---|
| 51577 | #define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51578 | #define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51579 | //PCIEMSIX_VECT113_MSG_DATA |
|---|
| 51580 | #define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51581 | #define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51582 | //PCIEMSIX_VECT113_CONTROL |
|---|
| 51583 | #define PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51584 | #define PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51585 | //PCIEMSIX_VECT114_ADDR_LO |
|---|
| 51586 | #define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51587 | #define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51588 | //PCIEMSIX_VECT114_ADDR_HI |
|---|
| 51589 | #define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51590 | #define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51591 | //PCIEMSIX_VECT114_MSG_DATA |
|---|
| 51592 | #define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51593 | #define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51594 | //PCIEMSIX_VECT114_CONTROL |
|---|
| 51595 | #define PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51596 | #define PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51597 | //PCIEMSIX_VECT115_ADDR_LO |
|---|
| 51598 | #define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51599 | #define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51600 | //PCIEMSIX_VECT115_ADDR_HI |
|---|
| 51601 | #define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51602 | #define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51603 | //PCIEMSIX_VECT115_MSG_DATA |
|---|
| 51604 | #define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51605 | #define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51606 | //PCIEMSIX_VECT115_CONTROL |
|---|
| 51607 | #define PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51608 | #define PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51609 | //PCIEMSIX_VECT116_ADDR_LO |
|---|
| 51610 | #define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51611 | #define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51612 | //PCIEMSIX_VECT116_ADDR_HI |
|---|
| 51613 | #define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51614 | #define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51615 | //PCIEMSIX_VECT116_MSG_DATA |
|---|
| 51616 | #define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51617 | #define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51618 | //PCIEMSIX_VECT116_CONTROL |
|---|
| 51619 | #define PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51620 | #define PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51621 | //PCIEMSIX_VECT117_ADDR_LO |
|---|
| 51622 | #define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51623 | #define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51624 | //PCIEMSIX_VECT117_ADDR_HI |
|---|
| 51625 | #define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51626 | #define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51627 | //PCIEMSIX_VECT117_MSG_DATA |
|---|
| 51628 | #define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51629 | #define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51630 | //PCIEMSIX_VECT117_CONTROL |
|---|
| 51631 | #define PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51632 | #define PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51633 | //PCIEMSIX_VECT118_ADDR_LO |
|---|
| 51634 | #define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51635 | #define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51636 | //PCIEMSIX_VECT118_ADDR_HI |
|---|
| 51637 | #define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51638 | #define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51639 | //PCIEMSIX_VECT118_MSG_DATA |
|---|
| 51640 | #define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51641 | #define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51642 | //PCIEMSIX_VECT118_CONTROL |
|---|
| 51643 | #define PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51644 | #define PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51645 | //PCIEMSIX_VECT119_ADDR_LO |
|---|
| 51646 | #define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51647 | #define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51648 | //PCIEMSIX_VECT119_ADDR_HI |
|---|
| 51649 | #define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51650 | #define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51651 | //PCIEMSIX_VECT119_MSG_DATA |
|---|
| 51652 | #define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51653 | #define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51654 | //PCIEMSIX_VECT119_CONTROL |
|---|
| 51655 | #define PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51656 | #define PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51657 | //PCIEMSIX_VECT120_ADDR_LO |
|---|
| 51658 | #define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51659 | #define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51660 | //PCIEMSIX_VECT120_ADDR_HI |
|---|
| 51661 | #define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51662 | #define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51663 | //PCIEMSIX_VECT120_MSG_DATA |
|---|
| 51664 | #define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51665 | #define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51666 | //PCIEMSIX_VECT120_CONTROL |
|---|
| 51667 | #define PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51668 | #define PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51669 | //PCIEMSIX_VECT121_ADDR_LO |
|---|
| 51670 | #define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51671 | #define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51672 | //PCIEMSIX_VECT121_ADDR_HI |
|---|
| 51673 | #define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51674 | #define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51675 | //PCIEMSIX_VECT121_MSG_DATA |
|---|
| 51676 | #define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51677 | #define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51678 | //PCIEMSIX_VECT121_CONTROL |
|---|
| 51679 | #define PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51680 | #define PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51681 | //PCIEMSIX_VECT122_ADDR_LO |
|---|
| 51682 | #define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51683 | #define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51684 | //PCIEMSIX_VECT122_ADDR_HI |
|---|
| 51685 | #define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51686 | #define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51687 | //PCIEMSIX_VECT122_MSG_DATA |
|---|
| 51688 | #define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51689 | #define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51690 | //PCIEMSIX_VECT122_CONTROL |
|---|
| 51691 | #define PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51692 | #define PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51693 | //PCIEMSIX_VECT123_ADDR_LO |
|---|
| 51694 | #define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51695 | #define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51696 | //PCIEMSIX_VECT123_ADDR_HI |
|---|
| 51697 | #define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51698 | #define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51699 | //PCIEMSIX_VECT123_MSG_DATA |
|---|
| 51700 | #define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51701 | #define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51702 | //PCIEMSIX_VECT123_CONTROL |
|---|
| 51703 | #define PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51704 | #define PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51705 | //PCIEMSIX_VECT124_ADDR_LO |
|---|
| 51706 | #define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51707 | #define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51708 | //PCIEMSIX_VECT124_ADDR_HI |
|---|
| 51709 | #define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51710 | #define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51711 | //PCIEMSIX_VECT124_MSG_DATA |
|---|
| 51712 | #define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51713 | #define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51714 | //PCIEMSIX_VECT124_CONTROL |
|---|
| 51715 | #define PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51716 | #define PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51717 | //PCIEMSIX_VECT125_ADDR_LO |
|---|
| 51718 | #define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51719 | #define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51720 | //PCIEMSIX_VECT125_ADDR_HI |
|---|
| 51721 | #define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51722 | #define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51723 | //PCIEMSIX_VECT125_MSG_DATA |
|---|
| 51724 | #define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51725 | #define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51726 | //PCIEMSIX_VECT125_CONTROL |
|---|
| 51727 | #define PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51728 | #define PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51729 | //PCIEMSIX_VECT126_ADDR_LO |
|---|
| 51730 | #define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51731 | #define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51732 | //PCIEMSIX_VECT126_ADDR_HI |
|---|
| 51733 | #define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51734 | #define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51735 | //PCIEMSIX_VECT126_MSG_DATA |
|---|
| 51736 | #define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51737 | #define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51738 | //PCIEMSIX_VECT126_CONTROL |
|---|
| 51739 | #define PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51740 | #define PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51741 | //PCIEMSIX_VECT127_ADDR_LO |
|---|
| 51742 | #define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51743 | #define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51744 | //PCIEMSIX_VECT127_ADDR_HI |
|---|
| 51745 | #define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51746 | #define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51747 | //PCIEMSIX_VECT127_MSG_DATA |
|---|
| 51748 | #define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51749 | #define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51750 | //PCIEMSIX_VECT127_CONTROL |
|---|
| 51751 | #define PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51752 | #define PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51753 | //PCIEMSIX_VECT128_ADDR_LO |
|---|
| 51754 | #define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51755 | #define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51756 | //PCIEMSIX_VECT128_ADDR_HI |
|---|
| 51757 | #define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51758 | #define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51759 | //PCIEMSIX_VECT128_MSG_DATA |
|---|
| 51760 | #define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51761 | #define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51762 | //PCIEMSIX_VECT128_CONTROL |
|---|
| 51763 | #define PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51764 | #define PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51765 | //PCIEMSIX_VECT129_ADDR_LO |
|---|
| 51766 | #define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51767 | #define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51768 | //PCIEMSIX_VECT129_ADDR_HI |
|---|
| 51769 | #define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51770 | #define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51771 | //PCIEMSIX_VECT129_MSG_DATA |
|---|
| 51772 | #define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51773 | #define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51774 | //PCIEMSIX_VECT129_CONTROL |
|---|
| 51775 | #define PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51776 | #define PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51777 | //PCIEMSIX_VECT130_ADDR_LO |
|---|
| 51778 | #define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51779 | #define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51780 | //PCIEMSIX_VECT130_ADDR_HI |
|---|
| 51781 | #define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51782 | #define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51783 | //PCIEMSIX_VECT130_MSG_DATA |
|---|
| 51784 | #define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51785 | #define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51786 | //PCIEMSIX_VECT130_CONTROL |
|---|
| 51787 | #define PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51788 | #define PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51789 | //PCIEMSIX_VECT131_ADDR_LO |
|---|
| 51790 | #define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51791 | #define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51792 | //PCIEMSIX_VECT131_ADDR_HI |
|---|
| 51793 | #define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51794 | #define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51795 | //PCIEMSIX_VECT131_MSG_DATA |
|---|
| 51796 | #define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51797 | #define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51798 | //PCIEMSIX_VECT131_CONTROL |
|---|
| 51799 | #define PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51800 | #define PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51801 | //PCIEMSIX_VECT132_ADDR_LO |
|---|
| 51802 | #define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51803 | #define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51804 | //PCIEMSIX_VECT132_ADDR_HI |
|---|
| 51805 | #define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51806 | #define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51807 | //PCIEMSIX_VECT132_MSG_DATA |
|---|
| 51808 | #define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51809 | #define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51810 | //PCIEMSIX_VECT132_CONTROL |
|---|
| 51811 | #define PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51812 | #define PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51813 | //PCIEMSIX_VECT133_ADDR_LO |
|---|
| 51814 | #define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51815 | #define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51816 | //PCIEMSIX_VECT133_ADDR_HI |
|---|
| 51817 | #define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51818 | #define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51819 | //PCIEMSIX_VECT133_MSG_DATA |
|---|
| 51820 | #define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51821 | #define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51822 | //PCIEMSIX_VECT133_CONTROL |
|---|
| 51823 | #define PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51824 | #define PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51825 | //PCIEMSIX_VECT134_ADDR_LO |
|---|
| 51826 | #define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51827 | #define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51828 | //PCIEMSIX_VECT134_ADDR_HI |
|---|
| 51829 | #define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51830 | #define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51831 | //PCIEMSIX_VECT134_MSG_DATA |
|---|
| 51832 | #define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51833 | #define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51834 | //PCIEMSIX_VECT134_CONTROL |
|---|
| 51835 | #define PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51836 | #define PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51837 | //PCIEMSIX_VECT135_ADDR_LO |
|---|
| 51838 | #define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51839 | #define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51840 | //PCIEMSIX_VECT135_ADDR_HI |
|---|
| 51841 | #define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51842 | #define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51843 | //PCIEMSIX_VECT135_MSG_DATA |
|---|
| 51844 | #define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51845 | #define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51846 | //PCIEMSIX_VECT135_CONTROL |
|---|
| 51847 | #define PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51848 | #define PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51849 | //PCIEMSIX_VECT136_ADDR_LO |
|---|
| 51850 | #define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51851 | #define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51852 | //PCIEMSIX_VECT136_ADDR_HI |
|---|
| 51853 | #define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51854 | #define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51855 | //PCIEMSIX_VECT136_MSG_DATA |
|---|
| 51856 | #define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51857 | #define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51858 | //PCIEMSIX_VECT136_CONTROL |
|---|
| 51859 | #define PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51860 | #define PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51861 | //PCIEMSIX_VECT137_ADDR_LO |
|---|
| 51862 | #define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51863 | #define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51864 | //PCIEMSIX_VECT137_ADDR_HI |
|---|
| 51865 | #define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51866 | #define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51867 | //PCIEMSIX_VECT137_MSG_DATA |
|---|
| 51868 | #define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51869 | #define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51870 | //PCIEMSIX_VECT137_CONTROL |
|---|
| 51871 | #define PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51872 | #define PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51873 | //PCIEMSIX_VECT138_ADDR_LO |
|---|
| 51874 | #define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51875 | #define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51876 | //PCIEMSIX_VECT138_ADDR_HI |
|---|
| 51877 | #define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51878 | #define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51879 | //PCIEMSIX_VECT138_MSG_DATA |
|---|
| 51880 | #define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51881 | #define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51882 | //PCIEMSIX_VECT138_CONTROL |
|---|
| 51883 | #define PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51884 | #define PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51885 | //PCIEMSIX_VECT139_ADDR_LO |
|---|
| 51886 | #define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51887 | #define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51888 | //PCIEMSIX_VECT139_ADDR_HI |
|---|
| 51889 | #define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51890 | #define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51891 | //PCIEMSIX_VECT139_MSG_DATA |
|---|
| 51892 | #define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51893 | #define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51894 | //PCIEMSIX_VECT139_CONTROL |
|---|
| 51895 | #define PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51896 | #define PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51897 | //PCIEMSIX_VECT140_ADDR_LO |
|---|
| 51898 | #define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51899 | #define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51900 | //PCIEMSIX_VECT140_ADDR_HI |
|---|
| 51901 | #define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51902 | #define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51903 | //PCIEMSIX_VECT140_MSG_DATA |
|---|
| 51904 | #define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51905 | #define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51906 | //PCIEMSIX_VECT140_CONTROL |
|---|
| 51907 | #define PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51908 | #define PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51909 | //PCIEMSIX_VECT141_ADDR_LO |
|---|
| 51910 | #define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51911 | #define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51912 | //PCIEMSIX_VECT141_ADDR_HI |
|---|
| 51913 | #define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51914 | #define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51915 | //PCIEMSIX_VECT141_MSG_DATA |
|---|
| 51916 | #define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51917 | #define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51918 | //PCIEMSIX_VECT141_CONTROL |
|---|
| 51919 | #define PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51920 | #define PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51921 | //PCIEMSIX_VECT142_ADDR_LO |
|---|
| 51922 | #define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51923 | #define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51924 | //PCIEMSIX_VECT142_ADDR_HI |
|---|
| 51925 | #define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51926 | #define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51927 | //PCIEMSIX_VECT142_MSG_DATA |
|---|
| 51928 | #define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51929 | #define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51930 | //PCIEMSIX_VECT142_CONTROL |
|---|
| 51931 | #define PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51932 | #define PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51933 | //PCIEMSIX_VECT143_ADDR_LO |
|---|
| 51934 | #define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51935 | #define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51936 | //PCIEMSIX_VECT143_ADDR_HI |
|---|
| 51937 | #define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51938 | #define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51939 | //PCIEMSIX_VECT143_MSG_DATA |
|---|
| 51940 | #define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51941 | #define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51942 | //PCIEMSIX_VECT143_CONTROL |
|---|
| 51943 | #define PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51944 | #define PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51945 | //PCIEMSIX_VECT144_ADDR_LO |
|---|
| 51946 | #define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51947 | #define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51948 | //PCIEMSIX_VECT144_ADDR_HI |
|---|
| 51949 | #define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51950 | #define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51951 | //PCIEMSIX_VECT144_MSG_DATA |
|---|
| 51952 | #define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51953 | #define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51954 | //PCIEMSIX_VECT144_CONTROL |
|---|
| 51955 | #define PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51956 | #define PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51957 | //PCIEMSIX_VECT145_ADDR_LO |
|---|
| 51958 | #define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51959 | #define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51960 | //PCIEMSIX_VECT145_ADDR_HI |
|---|
| 51961 | #define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51962 | #define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51963 | //PCIEMSIX_VECT145_MSG_DATA |
|---|
| 51964 | #define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51965 | #define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51966 | //PCIEMSIX_VECT145_CONTROL |
|---|
| 51967 | #define PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51968 | #define PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51969 | //PCIEMSIX_VECT146_ADDR_LO |
|---|
| 51970 | #define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51971 | #define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51972 | //PCIEMSIX_VECT146_ADDR_HI |
|---|
| 51973 | #define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51974 | #define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51975 | //PCIEMSIX_VECT146_MSG_DATA |
|---|
| 51976 | #define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51977 | #define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51978 | //PCIEMSIX_VECT146_CONTROL |
|---|
| 51979 | #define PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51980 | #define PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51981 | //PCIEMSIX_VECT147_ADDR_LO |
|---|
| 51982 | #define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51983 | #define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51984 | //PCIEMSIX_VECT147_ADDR_HI |
|---|
| 51985 | #define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51986 | #define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51987 | //PCIEMSIX_VECT147_MSG_DATA |
|---|
| 51988 | #define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 51989 | #define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 51990 | //PCIEMSIX_VECT147_CONTROL |
|---|
| 51991 | #define PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 51992 | #define PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 51993 | //PCIEMSIX_VECT148_ADDR_LO |
|---|
| 51994 | #define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 51995 | #define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 51996 | //PCIEMSIX_VECT148_ADDR_HI |
|---|
| 51997 | #define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 51998 | #define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 51999 | //PCIEMSIX_VECT148_MSG_DATA |
|---|
| 52000 | #define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52001 | #define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52002 | //PCIEMSIX_VECT148_CONTROL |
|---|
| 52003 | #define PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52004 | #define PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52005 | //PCIEMSIX_VECT149_ADDR_LO |
|---|
| 52006 | #define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52007 | #define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52008 | //PCIEMSIX_VECT149_ADDR_HI |
|---|
| 52009 | #define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52010 | #define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52011 | //PCIEMSIX_VECT149_MSG_DATA |
|---|
| 52012 | #define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52013 | #define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52014 | //PCIEMSIX_VECT149_CONTROL |
|---|
| 52015 | #define PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52016 | #define PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52017 | //PCIEMSIX_VECT150_ADDR_LO |
|---|
| 52018 | #define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52019 | #define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52020 | //PCIEMSIX_VECT150_ADDR_HI |
|---|
| 52021 | #define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52022 | #define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52023 | //PCIEMSIX_VECT150_MSG_DATA |
|---|
| 52024 | #define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52025 | #define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52026 | //PCIEMSIX_VECT150_CONTROL |
|---|
| 52027 | #define PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52028 | #define PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52029 | //PCIEMSIX_VECT151_ADDR_LO |
|---|
| 52030 | #define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52031 | #define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52032 | //PCIEMSIX_VECT151_ADDR_HI |
|---|
| 52033 | #define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52034 | #define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52035 | //PCIEMSIX_VECT151_MSG_DATA |
|---|
| 52036 | #define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52037 | #define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52038 | //PCIEMSIX_VECT151_CONTROL |
|---|
| 52039 | #define PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52040 | #define PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52041 | //PCIEMSIX_VECT152_ADDR_LO |
|---|
| 52042 | #define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52043 | #define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52044 | //PCIEMSIX_VECT152_ADDR_HI |
|---|
| 52045 | #define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52046 | #define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52047 | //PCIEMSIX_VECT152_MSG_DATA |
|---|
| 52048 | #define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52049 | #define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52050 | //PCIEMSIX_VECT152_CONTROL |
|---|
| 52051 | #define PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52052 | #define PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52053 | //PCIEMSIX_VECT153_ADDR_LO |
|---|
| 52054 | #define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52055 | #define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52056 | //PCIEMSIX_VECT153_ADDR_HI |
|---|
| 52057 | #define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52058 | #define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52059 | //PCIEMSIX_VECT153_MSG_DATA |
|---|
| 52060 | #define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52061 | #define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52062 | //PCIEMSIX_VECT153_CONTROL |
|---|
| 52063 | #define PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52064 | #define PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52065 | //PCIEMSIX_VECT154_ADDR_LO |
|---|
| 52066 | #define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52067 | #define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52068 | //PCIEMSIX_VECT154_ADDR_HI |
|---|
| 52069 | #define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52070 | #define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52071 | //PCIEMSIX_VECT154_MSG_DATA |
|---|
| 52072 | #define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52073 | #define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52074 | //PCIEMSIX_VECT154_CONTROL |
|---|
| 52075 | #define PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52076 | #define PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52077 | //PCIEMSIX_VECT155_ADDR_LO |
|---|
| 52078 | #define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52079 | #define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52080 | //PCIEMSIX_VECT155_ADDR_HI |
|---|
| 52081 | #define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52082 | #define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52083 | //PCIEMSIX_VECT155_MSG_DATA |
|---|
| 52084 | #define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52085 | #define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52086 | //PCIEMSIX_VECT155_CONTROL |
|---|
| 52087 | #define PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52088 | #define PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52089 | //PCIEMSIX_VECT156_ADDR_LO |
|---|
| 52090 | #define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52091 | #define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52092 | //PCIEMSIX_VECT156_ADDR_HI |
|---|
| 52093 | #define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52094 | #define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52095 | //PCIEMSIX_VECT156_MSG_DATA |
|---|
| 52096 | #define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52097 | #define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52098 | //PCIEMSIX_VECT156_CONTROL |
|---|
| 52099 | #define PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52100 | #define PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52101 | //PCIEMSIX_VECT157_ADDR_LO |
|---|
| 52102 | #define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52103 | #define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52104 | //PCIEMSIX_VECT157_ADDR_HI |
|---|
| 52105 | #define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52106 | #define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52107 | //PCIEMSIX_VECT157_MSG_DATA |
|---|
| 52108 | #define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52109 | #define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52110 | //PCIEMSIX_VECT157_CONTROL |
|---|
| 52111 | #define PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52112 | #define PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52113 | //PCIEMSIX_VECT158_ADDR_LO |
|---|
| 52114 | #define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52115 | #define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52116 | //PCIEMSIX_VECT158_ADDR_HI |
|---|
| 52117 | #define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52118 | #define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52119 | //PCIEMSIX_VECT158_MSG_DATA |
|---|
| 52120 | #define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52121 | #define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52122 | //PCIEMSIX_VECT158_CONTROL |
|---|
| 52123 | #define PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52124 | #define PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52125 | //PCIEMSIX_VECT159_ADDR_LO |
|---|
| 52126 | #define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52127 | #define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52128 | //PCIEMSIX_VECT159_ADDR_HI |
|---|
| 52129 | #define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52130 | #define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52131 | //PCIEMSIX_VECT159_MSG_DATA |
|---|
| 52132 | #define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52133 | #define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52134 | //PCIEMSIX_VECT159_CONTROL |
|---|
| 52135 | #define PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52136 | #define PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52137 | //PCIEMSIX_VECT160_ADDR_LO |
|---|
| 52138 | #define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52139 | #define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52140 | //PCIEMSIX_VECT160_ADDR_HI |
|---|
| 52141 | #define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52142 | #define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52143 | //PCIEMSIX_VECT160_MSG_DATA |
|---|
| 52144 | #define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52145 | #define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52146 | //PCIEMSIX_VECT160_CONTROL |
|---|
| 52147 | #define PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52148 | #define PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52149 | //PCIEMSIX_VECT161_ADDR_LO |
|---|
| 52150 | #define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52151 | #define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52152 | //PCIEMSIX_VECT161_ADDR_HI |
|---|
| 52153 | #define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52154 | #define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52155 | //PCIEMSIX_VECT161_MSG_DATA |
|---|
| 52156 | #define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52157 | #define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52158 | //PCIEMSIX_VECT161_CONTROL |
|---|
| 52159 | #define PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52160 | #define PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52161 | //PCIEMSIX_VECT162_ADDR_LO |
|---|
| 52162 | #define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52163 | #define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52164 | //PCIEMSIX_VECT162_ADDR_HI |
|---|
| 52165 | #define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52166 | #define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52167 | //PCIEMSIX_VECT162_MSG_DATA |
|---|
| 52168 | #define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52169 | #define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52170 | //PCIEMSIX_VECT162_CONTROL |
|---|
| 52171 | #define PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52172 | #define PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52173 | //PCIEMSIX_VECT163_ADDR_LO |
|---|
| 52174 | #define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52175 | #define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52176 | //PCIEMSIX_VECT163_ADDR_HI |
|---|
| 52177 | #define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52178 | #define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52179 | //PCIEMSIX_VECT163_MSG_DATA |
|---|
| 52180 | #define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52181 | #define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52182 | //PCIEMSIX_VECT163_CONTROL |
|---|
| 52183 | #define PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52184 | #define PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52185 | //PCIEMSIX_VECT164_ADDR_LO |
|---|
| 52186 | #define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52187 | #define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52188 | //PCIEMSIX_VECT164_ADDR_HI |
|---|
| 52189 | #define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52190 | #define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52191 | //PCIEMSIX_VECT164_MSG_DATA |
|---|
| 52192 | #define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52193 | #define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52194 | //PCIEMSIX_VECT164_CONTROL |
|---|
| 52195 | #define PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52196 | #define PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52197 | //PCIEMSIX_VECT165_ADDR_LO |
|---|
| 52198 | #define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52199 | #define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52200 | //PCIEMSIX_VECT165_ADDR_HI |
|---|
| 52201 | #define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52202 | #define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52203 | //PCIEMSIX_VECT165_MSG_DATA |
|---|
| 52204 | #define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52205 | #define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52206 | //PCIEMSIX_VECT165_CONTROL |
|---|
| 52207 | #define PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52208 | #define PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52209 | //PCIEMSIX_VECT166_ADDR_LO |
|---|
| 52210 | #define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52211 | #define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52212 | //PCIEMSIX_VECT166_ADDR_HI |
|---|
| 52213 | #define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52214 | #define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52215 | //PCIEMSIX_VECT166_MSG_DATA |
|---|
| 52216 | #define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52217 | #define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52218 | //PCIEMSIX_VECT166_CONTROL |
|---|
| 52219 | #define PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52220 | #define PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52221 | //PCIEMSIX_VECT167_ADDR_LO |
|---|
| 52222 | #define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52223 | #define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52224 | //PCIEMSIX_VECT167_ADDR_HI |
|---|
| 52225 | #define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52226 | #define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52227 | //PCIEMSIX_VECT167_MSG_DATA |
|---|
| 52228 | #define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52229 | #define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52230 | //PCIEMSIX_VECT167_CONTROL |
|---|
| 52231 | #define PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52232 | #define PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52233 | //PCIEMSIX_VECT168_ADDR_LO |
|---|
| 52234 | #define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52235 | #define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52236 | //PCIEMSIX_VECT168_ADDR_HI |
|---|
| 52237 | #define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52238 | #define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52239 | //PCIEMSIX_VECT168_MSG_DATA |
|---|
| 52240 | #define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52241 | #define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52242 | //PCIEMSIX_VECT168_CONTROL |
|---|
| 52243 | #define PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52244 | #define PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52245 | //PCIEMSIX_VECT169_ADDR_LO |
|---|
| 52246 | #define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52247 | #define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52248 | //PCIEMSIX_VECT169_ADDR_HI |
|---|
| 52249 | #define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52250 | #define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52251 | //PCIEMSIX_VECT169_MSG_DATA |
|---|
| 52252 | #define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52253 | #define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52254 | //PCIEMSIX_VECT169_CONTROL |
|---|
| 52255 | #define PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52256 | #define PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52257 | //PCIEMSIX_VECT170_ADDR_LO |
|---|
| 52258 | #define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52259 | #define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52260 | //PCIEMSIX_VECT170_ADDR_HI |
|---|
| 52261 | #define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52262 | #define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52263 | //PCIEMSIX_VECT170_MSG_DATA |
|---|
| 52264 | #define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52265 | #define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52266 | //PCIEMSIX_VECT170_CONTROL |
|---|
| 52267 | #define PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52268 | #define PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52269 | //PCIEMSIX_VECT171_ADDR_LO |
|---|
| 52270 | #define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52271 | #define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52272 | //PCIEMSIX_VECT171_ADDR_HI |
|---|
| 52273 | #define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52274 | #define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52275 | //PCIEMSIX_VECT171_MSG_DATA |
|---|
| 52276 | #define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52277 | #define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52278 | //PCIEMSIX_VECT171_CONTROL |
|---|
| 52279 | #define PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52280 | #define PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52281 | //PCIEMSIX_VECT172_ADDR_LO |
|---|
| 52282 | #define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52283 | #define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52284 | //PCIEMSIX_VECT172_ADDR_HI |
|---|
| 52285 | #define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52286 | #define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52287 | //PCIEMSIX_VECT172_MSG_DATA |
|---|
| 52288 | #define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52289 | #define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52290 | //PCIEMSIX_VECT172_CONTROL |
|---|
| 52291 | #define PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52292 | #define PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52293 | //PCIEMSIX_VECT173_ADDR_LO |
|---|
| 52294 | #define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52295 | #define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52296 | //PCIEMSIX_VECT173_ADDR_HI |
|---|
| 52297 | #define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52298 | #define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52299 | //PCIEMSIX_VECT173_MSG_DATA |
|---|
| 52300 | #define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52301 | #define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52302 | //PCIEMSIX_VECT173_CONTROL |
|---|
| 52303 | #define PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52304 | #define PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52305 | //PCIEMSIX_VECT174_ADDR_LO |
|---|
| 52306 | #define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52307 | #define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52308 | //PCIEMSIX_VECT174_ADDR_HI |
|---|
| 52309 | #define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52310 | #define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52311 | //PCIEMSIX_VECT174_MSG_DATA |
|---|
| 52312 | #define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52313 | #define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52314 | //PCIEMSIX_VECT174_CONTROL |
|---|
| 52315 | #define PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52316 | #define PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52317 | //PCIEMSIX_VECT175_ADDR_LO |
|---|
| 52318 | #define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52319 | #define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52320 | //PCIEMSIX_VECT175_ADDR_HI |
|---|
| 52321 | #define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52322 | #define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52323 | //PCIEMSIX_VECT175_MSG_DATA |
|---|
| 52324 | #define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52325 | #define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52326 | //PCIEMSIX_VECT175_CONTROL |
|---|
| 52327 | #define PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52328 | #define PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52329 | //PCIEMSIX_VECT176_ADDR_LO |
|---|
| 52330 | #define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52331 | #define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52332 | //PCIEMSIX_VECT176_ADDR_HI |
|---|
| 52333 | #define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52334 | #define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52335 | //PCIEMSIX_VECT176_MSG_DATA |
|---|
| 52336 | #define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52337 | #define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52338 | //PCIEMSIX_VECT176_CONTROL |
|---|
| 52339 | #define PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52340 | #define PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52341 | //PCIEMSIX_VECT177_ADDR_LO |
|---|
| 52342 | #define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52343 | #define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52344 | //PCIEMSIX_VECT177_ADDR_HI |
|---|
| 52345 | #define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52346 | #define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52347 | //PCIEMSIX_VECT177_MSG_DATA |
|---|
| 52348 | #define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52349 | #define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52350 | //PCIEMSIX_VECT177_CONTROL |
|---|
| 52351 | #define PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52352 | #define PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52353 | //PCIEMSIX_VECT178_ADDR_LO |
|---|
| 52354 | #define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52355 | #define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52356 | //PCIEMSIX_VECT178_ADDR_HI |
|---|
| 52357 | #define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52358 | #define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52359 | //PCIEMSIX_VECT178_MSG_DATA |
|---|
| 52360 | #define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52361 | #define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52362 | //PCIEMSIX_VECT178_CONTROL |
|---|
| 52363 | #define PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52364 | #define PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52365 | //PCIEMSIX_VECT179_ADDR_LO |
|---|
| 52366 | #define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52367 | #define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52368 | //PCIEMSIX_VECT179_ADDR_HI |
|---|
| 52369 | #define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52370 | #define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52371 | //PCIEMSIX_VECT179_MSG_DATA |
|---|
| 52372 | #define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52373 | #define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52374 | //PCIEMSIX_VECT179_CONTROL |
|---|
| 52375 | #define PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52376 | #define PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52377 | //PCIEMSIX_VECT180_ADDR_LO |
|---|
| 52378 | #define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52379 | #define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52380 | //PCIEMSIX_VECT180_ADDR_HI |
|---|
| 52381 | #define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52382 | #define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52383 | //PCIEMSIX_VECT180_MSG_DATA |
|---|
| 52384 | #define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52385 | #define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52386 | //PCIEMSIX_VECT180_CONTROL |
|---|
| 52387 | #define PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52388 | #define PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52389 | //PCIEMSIX_VECT181_ADDR_LO |
|---|
| 52390 | #define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52391 | #define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52392 | //PCIEMSIX_VECT181_ADDR_HI |
|---|
| 52393 | #define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52394 | #define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52395 | //PCIEMSIX_VECT181_MSG_DATA |
|---|
| 52396 | #define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52397 | #define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52398 | //PCIEMSIX_VECT181_CONTROL |
|---|
| 52399 | #define PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52400 | #define PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52401 | //PCIEMSIX_VECT182_ADDR_LO |
|---|
| 52402 | #define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52403 | #define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52404 | //PCIEMSIX_VECT182_ADDR_HI |
|---|
| 52405 | #define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52406 | #define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52407 | //PCIEMSIX_VECT182_MSG_DATA |
|---|
| 52408 | #define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52409 | #define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52410 | //PCIEMSIX_VECT182_CONTROL |
|---|
| 52411 | #define PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52412 | #define PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52413 | //PCIEMSIX_VECT183_ADDR_LO |
|---|
| 52414 | #define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52415 | #define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52416 | //PCIEMSIX_VECT183_ADDR_HI |
|---|
| 52417 | #define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52418 | #define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52419 | //PCIEMSIX_VECT183_MSG_DATA |
|---|
| 52420 | #define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52421 | #define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52422 | //PCIEMSIX_VECT183_CONTROL |
|---|
| 52423 | #define PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52424 | #define PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52425 | //PCIEMSIX_VECT184_ADDR_LO |
|---|
| 52426 | #define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52427 | #define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52428 | //PCIEMSIX_VECT184_ADDR_HI |
|---|
| 52429 | #define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52430 | #define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52431 | //PCIEMSIX_VECT184_MSG_DATA |
|---|
| 52432 | #define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52433 | #define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52434 | //PCIEMSIX_VECT184_CONTROL |
|---|
| 52435 | #define PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52436 | #define PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52437 | //PCIEMSIX_VECT185_ADDR_LO |
|---|
| 52438 | #define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52439 | #define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52440 | //PCIEMSIX_VECT185_ADDR_HI |
|---|
| 52441 | #define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52442 | #define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52443 | //PCIEMSIX_VECT185_MSG_DATA |
|---|
| 52444 | #define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52445 | #define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52446 | //PCIEMSIX_VECT185_CONTROL |
|---|
| 52447 | #define PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52448 | #define PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52449 | //PCIEMSIX_VECT186_ADDR_LO |
|---|
| 52450 | #define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52451 | #define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52452 | //PCIEMSIX_VECT186_ADDR_HI |
|---|
| 52453 | #define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52454 | #define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52455 | //PCIEMSIX_VECT186_MSG_DATA |
|---|
| 52456 | #define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52457 | #define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52458 | //PCIEMSIX_VECT186_CONTROL |
|---|
| 52459 | #define PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52460 | #define PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52461 | //PCIEMSIX_VECT187_ADDR_LO |
|---|
| 52462 | #define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52463 | #define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52464 | //PCIEMSIX_VECT187_ADDR_HI |
|---|
| 52465 | #define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52466 | #define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52467 | //PCIEMSIX_VECT187_MSG_DATA |
|---|
| 52468 | #define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52469 | #define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52470 | //PCIEMSIX_VECT187_CONTROL |
|---|
| 52471 | #define PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52472 | #define PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52473 | //PCIEMSIX_VECT188_ADDR_LO |
|---|
| 52474 | #define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52475 | #define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52476 | //PCIEMSIX_VECT188_ADDR_HI |
|---|
| 52477 | #define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52478 | #define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52479 | //PCIEMSIX_VECT188_MSG_DATA |
|---|
| 52480 | #define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52481 | #define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52482 | //PCIEMSIX_VECT188_CONTROL |
|---|
| 52483 | #define PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52484 | #define PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52485 | //PCIEMSIX_VECT189_ADDR_LO |
|---|
| 52486 | #define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52487 | #define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52488 | //PCIEMSIX_VECT189_ADDR_HI |
|---|
| 52489 | #define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52490 | #define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52491 | //PCIEMSIX_VECT189_MSG_DATA |
|---|
| 52492 | #define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52493 | #define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52494 | //PCIEMSIX_VECT189_CONTROL |
|---|
| 52495 | #define PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52496 | #define PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52497 | //PCIEMSIX_VECT190_ADDR_LO |
|---|
| 52498 | #define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52499 | #define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52500 | //PCIEMSIX_VECT190_ADDR_HI |
|---|
| 52501 | #define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52502 | #define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52503 | //PCIEMSIX_VECT190_MSG_DATA |
|---|
| 52504 | #define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52505 | #define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52506 | //PCIEMSIX_VECT190_CONTROL |
|---|
| 52507 | #define PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52508 | #define PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52509 | //PCIEMSIX_VECT191_ADDR_LO |
|---|
| 52510 | #define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52511 | #define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52512 | //PCIEMSIX_VECT191_ADDR_HI |
|---|
| 52513 | #define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52514 | #define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52515 | //PCIEMSIX_VECT191_MSG_DATA |
|---|
| 52516 | #define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52517 | #define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52518 | //PCIEMSIX_VECT191_CONTROL |
|---|
| 52519 | #define PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52520 | #define PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52521 | //PCIEMSIX_VECT192_ADDR_LO |
|---|
| 52522 | #define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52523 | #define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52524 | //PCIEMSIX_VECT192_ADDR_HI |
|---|
| 52525 | #define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52526 | #define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52527 | //PCIEMSIX_VECT192_MSG_DATA |
|---|
| 52528 | #define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52529 | #define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52530 | //PCIEMSIX_VECT192_CONTROL |
|---|
| 52531 | #define PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52532 | #define PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52533 | //PCIEMSIX_VECT193_ADDR_LO |
|---|
| 52534 | #define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52535 | #define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52536 | //PCIEMSIX_VECT193_ADDR_HI |
|---|
| 52537 | #define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52538 | #define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52539 | //PCIEMSIX_VECT193_MSG_DATA |
|---|
| 52540 | #define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52541 | #define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52542 | //PCIEMSIX_VECT193_CONTROL |
|---|
| 52543 | #define PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52544 | #define PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52545 | //PCIEMSIX_VECT194_ADDR_LO |
|---|
| 52546 | #define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52547 | #define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52548 | //PCIEMSIX_VECT194_ADDR_HI |
|---|
| 52549 | #define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52550 | #define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52551 | //PCIEMSIX_VECT194_MSG_DATA |
|---|
| 52552 | #define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52553 | #define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52554 | //PCIEMSIX_VECT194_CONTROL |
|---|
| 52555 | #define PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52556 | #define PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52557 | //PCIEMSIX_VECT195_ADDR_LO |
|---|
| 52558 | #define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52559 | #define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52560 | //PCIEMSIX_VECT195_ADDR_HI |
|---|
| 52561 | #define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52562 | #define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52563 | //PCIEMSIX_VECT195_MSG_DATA |
|---|
| 52564 | #define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52565 | #define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52566 | //PCIEMSIX_VECT195_CONTROL |
|---|
| 52567 | #define PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52568 | #define PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52569 | //PCIEMSIX_VECT196_ADDR_LO |
|---|
| 52570 | #define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52571 | #define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52572 | //PCIEMSIX_VECT196_ADDR_HI |
|---|
| 52573 | #define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52574 | #define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52575 | //PCIEMSIX_VECT196_MSG_DATA |
|---|
| 52576 | #define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52577 | #define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52578 | //PCIEMSIX_VECT196_CONTROL |
|---|
| 52579 | #define PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52580 | #define PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52581 | //PCIEMSIX_VECT197_ADDR_LO |
|---|
| 52582 | #define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52583 | #define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52584 | //PCIEMSIX_VECT197_ADDR_HI |
|---|
| 52585 | #define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52586 | #define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52587 | //PCIEMSIX_VECT197_MSG_DATA |
|---|
| 52588 | #define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52589 | #define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52590 | //PCIEMSIX_VECT197_CONTROL |
|---|
| 52591 | #define PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52592 | #define PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52593 | //PCIEMSIX_VECT198_ADDR_LO |
|---|
| 52594 | #define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52595 | #define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52596 | //PCIEMSIX_VECT198_ADDR_HI |
|---|
| 52597 | #define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52598 | #define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52599 | //PCIEMSIX_VECT198_MSG_DATA |
|---|
| 52600 | #define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52601 | #define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52602 | //PCIEMSIX_VECT198_CONTROL |
|---|
| 52603 | #define PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52604 | #define PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52605 | //PCIEMSIX_VECT199_ADDR_LO |
|---|
| 52606 | #define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52607 | #define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52608 | //PCIEMSIX_VECT199_ADDR_HI |
|---|
| 52609 | #define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52610 | #define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52611 | //PCIEMSIX_VECT199_MSG_DATA |
|---|
| 52612 | #define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52613 | #define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52614 | //PCIEMSIX_VECT199_CONTROL |
|---|
| 52615 | #define PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52616 | #define PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52617 | //PCIEMSIX_VECT200_ADDR_LO |
|---|
| 52618 | #define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52619 | #define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52620 | //PCIEMSIX_VECT200_ADDR_HI |
|---|
| 52621 | #define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52622 | #define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52623 | //PCIEMSIX_VECT200_MSG_DATA |
|---|
| 52624 | #define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52625 | #define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52626 | //PCIEMSIX_VECT200_CONTROL |
|---|
| 52627 | #define PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52628 | #define PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52629 | //PCIEMSIX_VECT201_ADDR_LO |
|---|
| 52630 | #define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52631 | #define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52632 | //PCIEMSIX_VECT201_ADDR_HI |
|---|
| 52633 | #define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52634 | #define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52635 | //PCIEMSIX_VECT201_MSG_DATA |
|---|
| 52636 | #define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52637 | #define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52638 | //PCIEMSIX_VECT201_CONTROL |
|---|
| 52639 | #define PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52640 | #define PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52641 | //PCIEMSIX_VECT202_ADDR_LO |
|---|
| 52642 | #define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52643 | #define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52644 | //PCIEMSIX_VECT202_ADDR_HI |
|---|
| 52645 | #define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52646 | #define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52647 | //PCIEMSIX_VECT202_MSG_DATA |
|---|
| 52648 | #define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52649 | #define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52650 | //PCIEMSIX_VECT202_CONTROL |
|---|
| 52651 | #define PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52652 | #define PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52653 | //PCIEMSIX_VECT203_ADDR_LO |
|---|
| 52654 | #define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52655 | #define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52656 | //PCIEMSIX_VECT203_ADDR_HI |
|---|
| 52657 | #define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52658 | #define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52659 | //PCIEMSIX_VECT203_MSG_DATA |
|---|
| 52660 | #define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52661 | #define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52662 | //PCIEMSIX_VECT203_CONTROL |
|---|
| 52663 | #define PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52664 | #define PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52665 | //PCIEMSIX_VECT204_ADDR_LO |
|---|
| 52666 | #define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52667 | #define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52668 | //PCIEMSIX_VECT204_ADDR_HI |
|---|
| 52669 | #define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52670 | #define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52671 | //PCIEMSIX_VECT204_MSG_DATA |
|---|
| 52672 | #define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52673 | #define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52674 | //PCIEMSIX_VECT204_CONTROL |
|---|
| 52675 | #define PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52676 | #define PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52677 | //PCIEMSIX_VECT205_ADDR_LO |
|---|
| 52678 | #define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52679 | #define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52680 | //PCIEMSIX_VECT205_ADDR_HI |
|---|
| 52681 | #define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52682 | #define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52683 | //PCIEMSIX_VECT205_MSG_DATA |
|---|
| 52684 | #define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52685 | #define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52686 | //PCIEMSIX_VECT205_CONTROL |
|---|
| 52687 | #define PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52688 | #define PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52689 | //PCIEMSIX_VECT206_ADDR_LO |
|---|
| 52690 | #define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52691 | #define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52692 | //PCIEMSIX_VECT206_ADDR_HI |
|---|
| 52693 | #define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52694 | #define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52695 | //PCIEMSIX_VECT206_MSG_DATA |
|---|
| 52696 | #define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52697 | #define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52698 | //PCIEMSIX_VECT206_CONTROL |
|---|
| 52699 | #define PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52700 | #define PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52701 | //PCIEMSIX_VECT207_ADDR_LO |
|---|
| 52702 | #define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52703 | #define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52704 | //PCIEMSIX_VECT207_ADDR_HI |
|---|
| 52705 | #define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52706 | #define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52707 | //PCIEMSIX_VECT207_MSG_DATA |
|---|
| 52708 | #define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52709 | #define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52710 | //PCIEMSIX_VECT207_CONTROL |
|---|
| 52711 | #define PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52712 | #define PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52713 | //PCIEMSIX_VECT208_ADDR_LO |
|---|
| 52714 | #define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52715 | #define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52716 | //PCIEMSIX_VECT208_ADDR_HI |
|---|
| 52717 | #define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52718 | #define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52719 | //PCIEMSIX_VECT208_MSG_DATA |
|---|
| 52720 | #define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52721 | #define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52722 | //PCIEMSIX_VECT208_CONTROL |
|---|
| 52723 | #define PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52724 | #define PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52725 | //PCIEMSIX_VECT209_ADDR_LO |
|---|
| 52726 | #define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52727 | #define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52728 | //PCIEMSIX_VECT209_ADDR_HI |
|---|
| 52729 | #define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52730 | #define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52731 | //PCIEMSIX_VECT209_MSG_DATA |
|---|
| 52732 | #define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52733 | #define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52734 | //PCIEMSIX_VECT209_CONTROL |
|---|
| 52735 | #define PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52736 | #define PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52737 | //PCIEMSIX_VECT210_ADDR_LO |
|---|
| 52738 | #define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52739 | #define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52740 | //PCIEMSIX_VECT210_ADDR_HI |
|---|
| 52741 | #define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52742 | #define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52743 | //PCIEMSIX_VECT210_MSG_DATA |
|---|
| 52744 | #define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52745 | #define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52746 | //PCIEMSIX_VECT210_CONTROL |
|---|
| 52747 | #define PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52748 | #define PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52749 | //PCIEMSIX_VECT211_ADDR_LO |
|---|
| 52750 | #define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52751 | #define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52752 | //PCIEMSIX_VECT211_ADDR_HI |
|---|
| 52753 | #define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52754 | #define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52755 | //PCIEMSIX_VECT211_MSG_DATA |
|---|
| 52756 | #define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52757 | #define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52758 | //PCIEMSIX_VECT211_CONTROL |
|---|
| 52759 | #define PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52760 | #define PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52761 | //PCIEMSIX_VECT212_ADDR_LO |
|---|
| 52762 | #define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52763 | #define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52764 | //PCIEMSIX_VECT212_ADDR_HI |
|---|
| 52765 | #define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52766 | #define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52767 | //PCIEMSIX_VECT212_MSG_DATA |
|---|
| 52768 | #define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52769 | #define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52770 | //PCIEMSIX_VECT212_CONTROL |
|---|
| 52771 | #define PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52772 | #define PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52773 | //PCIEMSIX_VECT213_ADDR_LO |
|---|
| 52774 | #define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52775 | #define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52776 | //PCIEMSIX_VECT213_ADDR_HI |
|---|
| 52777 | #define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52778 | #define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52779 | //PCIEMSIX_VECT213_MSG_DATA |
|---|
| 52780 | #define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52781 | #define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52782 | //PCIEMSIX_VECT213_CONTROL |
|---|
| 52783 | #define PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52784 | #define PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52785 | //PCIEMSIX_VECT214_ADDR_LO |
|---|
| 52786 | #define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52787 | #define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52788 | //PCIEMSIX_VECT214_ADDR_HI |
|---|
| 52789 | #define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52790 | #define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52791 | //PCIEMSIX_VECT214_MSG_DATA |
|---|
| 52792 | #define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52793 | #define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52794 | //PCIEMSIX_VECT214_CONTROL |
|---|
| 52795 | #define PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52796 | #define PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52797 | //PCIEMSIX_VECT215_ADDR_LO |
|---|
| 52798 | #define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52799 | #define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52800 | //PCIEMSIX_VECT215_ADDR_HI |
|---|
| 52801 | #define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52802 | #define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52803 | //PCIEMSIX_VECT215_MSG_DATA |
|---|
| 52804 | #define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52805 | #define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52806 | //PCIEMSIX_VECT215_CONTROL |
|---|
| 52807 | #define PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52808 | #define PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52809 | //PCIEMSIX_VECT216_ADDR_LO |
|---|
| 52810 | #define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52811 | #define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52812 | //PCIEMSIX_VECT216_ADDR_HI |
|---|
| 52813 | #define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52814 | #define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52815 | //PCIEMSIX_VECT216_MSG_DATA |
|---|
| 52816 | #define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52817 | #define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52818 | //PCIEMSIX_VECT216_CONTROL |
|---|
| 52819 | #define PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52820 | #define PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52821 | //PCIEMSIX_VECT217_ADDR_LO |
|---|
| 52822 | #define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52823 | #define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52824 | //PCIEMSIX_VECT217_ADDR_HI |
|---|
| 52825 | #define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52826 | #define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52827 | //PCIEMSIX_VECT217_MSG_DATA |
|---|
| 52828 | #define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52829 | #define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52830 | //PCIEMSIX_VECT217_CONTROL |
|---|
| 52831 | #define PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52832 | #define PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52833 | //PCIEMSIX_VECT218_ADDR_LO |
|---|
| 52834 | #define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52835 | #define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52836 | //PCIEMSIX_VECT218_ADDR_HI |
|---|
| 52837 | #define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52838 | #define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52839 | //PCIEMSIX_VECT218_MSG_DATA |
|---|
| 52840 | #define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52841 | #define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52842 | //PCIEMSIX_VECT218_CONTROL |
|---|
| 52843 | #define PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52844 | #define PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52845 | //PCIEMSIX_VECT219_ADDR_LO |
|---|
| 52846 | #define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52847 | #define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52848 | //PCIEMSIX_VECT219_ADDR_HI |
|---|
| 52849 | #define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52850 | #define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52851 | //PCIEMSIX_VECT219_MSG_DATA |
|---|
| 52852 | #define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52853 | #define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52854 | //PCIEMSIX_VECT219_CONTROL |
|---|
| 52855 | #define PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52856 | #define PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52857 | //PCIEMSIX_VECT220_ADDR_LO |
|---|
| 52858 | #define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52859 | #define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52860 | //PCIEMSIX_VECT220_ADDR_HI |
|---|
| 52861 | #define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52862 | #define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52863 | //PCIEMSIX_VECT220_MSG_DATA |
|---|
| 52864 | #define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52865 | #define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52866 | //PCIEMSIX_VECT220_CONTROL |
|---|
| 52867 | #define PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52868 | #define PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52869 | //PCIEMSIX_VECT221_ADDR_LO |
|---|
| 52870 | #define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52871 | #define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52872 | //PCIEMSIX_VECT221_ADDR_HI |
|---|
| 52873 | #define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52874 | #define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52875 | //PCIEMSIX_VECT221_MSG_DATA |
|---|
| 52876 | #define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52877 | #define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52878 | //PCIEMSIX_VECT221_CONTROL |
|---|
| 52879 | #define PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52880 | #define PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52881 | //PCIEMSIX_VECT222_ADDR_LO |
|---|
| 52882 | #define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52883 | #define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52884 | //PCIEMSIX_VECT222_ADDR_HI |
|---|
| 52885 | #define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52886 | #define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52887 | //PCIEMSIX_VECT222_MSG_DATA |
|---|
| 52888 | #define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52889 | #define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52890 | //PCIEMSIX_VECT222_CONTROL |
|---|
| 52891 | #define PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52892 | #define PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52893 | //PCIEMSIX_VECT223_ADDR_LO |
|---|
| 52894 | #define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52895 | #define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52896 | //PCIEMSIX_VECT223_ADDR_HI |
|---|
| 52897 | #define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52898 | #define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52899 | //PCIEMSIX_VECT223_MSG_DATA |
|---|
| 52900 | #define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52901 | #define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52902 | //PCIEMSIX_VECT223_CONTROL |
|---|
| 52903 | #define PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52904 | #define PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52905 | //PCIEMSIX_VECT224_ADDR_LO |
|---|
| 52906 | #define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52907 | #define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52908 | //PCIEMSIX_VECT224_ADDR_HI |
|---|
| 52909 | #define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52910 | #define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52911 | //PCIEMSIX_VECT224_MSG_DATA |
|---|
| 52912 | #define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52913 | #define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52914 | //PCIEMSIX_VECT224_CONTROL |
|---|
| 52915 | #define PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52916 | #define PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52917 | //PCIEMSIX_VECT225_ADDR_LO |
|---|
| 52918 | #define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52919 | #define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52920 | //PCIEMSIX_VECT225_ADDR_HI |
|---|
| 52921 | #define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52922 | #define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52923 | //PCIEMSIX_VECT225_MSG_DATA |
|---|
| 52924 | #define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52925 | #define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52926 | //PCIEMSIX_VECT225_CONTROL |
|---|
| 52927 | #define PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52928 | #define PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52929 | //PCIEMSIX_VECT226_ADDR_LO |
|---|
| 52930 | #define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52931 | #define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52932 | //PCIEMSIX_VECT226_ADDR_HI |
|---|
| 52933 | #define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52934 | #define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52935 | //PCIEMSIX_VECT226_MSG_DATA |
|---|
| 52936 | #define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52937 | #define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52938 | //PCIEMSIX_VECT226_CONTROL |
|---|
| 52939 | #define PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52940 | #define PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52941 | //PCIEMSIX_VECT227_ADDR_LO |
|---|
| 52942 | #define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52943 | #define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52944 | //PCIEMSIX_VECT227_ADDR_HI |
|---|
| 52945 | #define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52946 | #define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52947 | //PCIEMSIX_VECT227_MSG_DATA |
|---|
| 52948 | #define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52949 | #define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52950 | //PCIEMSIX_VECT227_CONTROL |
|---|
| 52951 | #define PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52952 | #define PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52953 | //PCIEMSIX_VECT228_ADDR_LO |
|---|
| 52954 | #define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52955 | #define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52956 | //PCIEMSIX_VECT228_ADDR_HI |
|---|
| 52957 | #define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52958 | #define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52959 | //PCIEMSIX_VECT228_MSG_DATA |
|---|
| 52960 | #define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52961 | #define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52962 | //PCIEMSIX_VECT228_CONTROL |
|---|
| 52963 | #define PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52964 | #define PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52965 | //PCIEMSIX_VECT229_ADDR_LO |
|---|
| 52966 | #define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52967 | #define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52968 | //PCIEMSIX_VECT229_ADDR_HI |
|---|
| 52969 | #define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52970 | #define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52971 | //PCIEMSIX_VECT229_MSG_DATA |
|---|
| 52972 | #define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52973 | #define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52974 | //PCIEMSIX_VECT229_CONTROL |
|---|
| 52975 | #define PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52976 | #define PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52977 | //PCIEMSIX_VECT230_ADDR_LO |
|---|
| 52978 | #define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52979 | #define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52980 | //PCIEMSIX_VECT230_ADDR_HI |
|---|
| 52981 | #define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52982 | #define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52983 | //PCIEMSIX_VECT230_MSG_DATA |
|---|
| 52984 | #define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52985 | #define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52986 | //PCIEMSIX_VECT230_CONTROL |
|---|
| 52987 | #define PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 52988 | #define PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 52989 | //PCIEMSIX_VECT231_ADDR_LO |
|---|
| 52990 | #define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 52991 | #define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 52992 | //PCIEMSIX_VECT231_ADDR_HI |
|---|
| 52993 | #define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 52994 | #define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 52995 | //PCIEMSIX_VECT231_MSG_DATA |
|---|
| 52996 | #define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 52997 | #define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 52998 | //PCIEMSIX_VECT231_CONTROL |
|---|
| 52999 | #define PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53000 | #define PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53001 | //PCIEMSIX_VECT232_ADDR_LO |
|---|
| 53002 | #define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53003 | #define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53004 | //PCIEMSIX_VECT232_ADDR_HI |
|---|
| 53005 | #define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53006 | #define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53007 | //PCIEMSIX_VECT232_MSG_DATA |
|---|
| 53008 | #define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53009 | #define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53010 | //PCIEMSIX_VECT232_CONTROL |
|---|
| 53011 | #define PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53012 | #define PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53013 | //PCIEMSIX_VECT233_ADDR_LO |
|---|
| 53014 | #define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53015 | #define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53016 | //PCIEMSIX_VECT233_ADDR_HI |
|---|
| 53017 | #define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53018 | #define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53019 | //PCIEMSIX_VECT233_MSG_DATA |
|---|
| 53020 | #define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53021 | #define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53022 | //PCIEMSIX_VECT233_CONTROL |
|---|
| 53023 | #define PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53024 | #define PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53025 | //PCIEMSIX_VECT234_ADDR_LO |
|---|
| 53026 | #define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53027 | #define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53028 | //PCIEMSIX_VECT234_ADDR_HI |
|---|
| 53029 | #define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53030 | #define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53031 | //PCIEMSIX_VECT234_MSG_DATA |
|---|
| 53032 | #define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53033 | #define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53034 | //PCIEMSIX_VECT234_CONTROL |
|---|
| 53035 | #define PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53036 | #define PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53037 | //PCIEMSIX_VECT235_ADDR_LO |
|---|
| 53038 | #define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53039 | #define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53040 | //PCIEMSIX_VECT235_ADDR_HI |
|---|
| 53041 | #define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53042 | #define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53043 | //PCIEMSIX_VECT235_MSG_DATA |
|---|
| 53044 | #define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53045 | #define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53046 | //PCIEMSIX_VECT235_CONTROL |
|---|
| 53047 | #define PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53048 | #define PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53049 | //PCIEMSIX_VECT236_ADDR_LO |
|---|
| 53050 | #define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53051 | #define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53052 | //PCIEMSIX_VECT236_ADDR_HI |
|---|
| 53053 | #define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53054 | #define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53055 | //PCIEMSIX_VECT236_MSG_DATA |
|---|
| 53056 | #define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53057 | #define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53058 | //PCIEMSIX_VECT236_CONTROL |
|---|
| 53059 | #define PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53060 | #define PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53061 | //PCIEMSIX_VECT237_ADDR_LO |
|---|
| 53062 | #define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53063 | #define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53064 | //PCIEMSIX_VECT237_ADDR_HI |
|---|
| 53065 | #define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53066 | #define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53067 | //PCIEMSIX_VECT237_MSG_DATA |
|---|
| 53068 | #define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53069 | #define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53070 | //PCIEMSIX_VECT237_CONTROL |
|---|
| 53071 | #define PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53072 | #define PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53073 | //PCIEMSIX_VECT238_ADDR_LO |
|---|
| 53074 | #define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53075 | #define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53076 | //PCIEMSIX_VECT238_ADDR_HI |
|---|
| 53077 | #define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53078 | #define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53079 | //PCIEMSIX_VECT238_MSG_DATA |
|---|
| 53080 | #define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53081 | #define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53082 | //PCIEMSIX_VECT238_CONTROL |
|---|
| 53083 | #define PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53084 | #define PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53085 | //PCIEMSIX_VECT239_ADDR_LO |
|---|
| 53086 | #define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53087 | #define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53088 | //PCIEMSIX_VECT239_ADDR_HI |
|---|
| 53089 | #define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53090 | #define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53091 | //PCIEMSIX_VECT239_MSG_DATA |
|---|
| 53092 | #define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53093 | #define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53094 | //PCIEMSIX_VECT239_CONTROL |
|---|
| 53095 | #define PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53096 | #define PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53097 | //PCIEMSIX_VECT240_ADDR_LO |
|---|
| 53098 | #define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53099 | #define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53100 | //PCIEMSIX_VECT240_ADDR_HI |
|---|
| 53101 | #define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53102 | #define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53103 | //PCIEMSIX_VECT240_MSG_DATA |
|---|
| 53104 | #define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53105 | #define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53106 | //PCIEMSIX_VECT240_CONTROL |
|---|
| 53107 | #define PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53108 | #define PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53109 | //PCIEMSIX_VECT241_ADDR_LO |
|---|
| 53110 | #define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53111 | #define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53112 | //PCIEMSIX_VECT241_ADDR_HI |
|---|
| 53113 | #define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53114 | #define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53115 | //PCIEMSIX_VECT241_MSG_DATA |
|---|
| 53116 | #define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53117 | #define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53118 | //PCIEMSIX_VECT241_CONTROL |
|---|
| 53119 | #define PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53120 | #define PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53121 | //PCIEMSIX_VECT242_ADDR_LO |
|---|
| 53122 | #define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53123 | #define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53124 | //PCIEMSIX_VECT242_ADDR_HI |
|---|
| 53125 | #define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53126 | #define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53127 | //PCIEMSIX_VECT242_MSG_DATA |
|---|
| 53128 | #define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53129 | #define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53130 | //PCIEMSIX_VECT242_CONTROL |
|---|
| 53131 | #define PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53132 | #define PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53133 | //PCIEMSIX_VECT243_ADDR_LO |
|---|
| 53134 | #define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53135 | #define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53136 | //PCIEMSIX_VECT243_ADDR_HI |
|---|
| 53137 | #define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53138 | #define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53139 | //PCIEMSIX_VECT243_MSG_DATA |
|---|
| 53140 | #define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53141 | #define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53142 | //PCIEMSIX_VECT243_CONTROL |
|---|
| 53143 | #define PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53144 | #define PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53145 | //PCIEMSIX_VECT244_ADDR_LO |
|---|
| 53146 | #define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53147 | #define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53148 | //PCIEMSIX_VECT244_ADDR_HI |
|---|
| 53149 | #define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53150 | #define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53151 | //PCIEMSIX_VECT244_MSG_DATA |
|---|
| 53152 | #define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53153 | #define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53154 | //PCIEMSIX_VECT244_CONTROL |
|---|
| 53155 | #define PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53156 | #define PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53157 | //PCIEMSIX_VECT245_ADDR_LO |
|---|
| 53158 | #define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53159 | #define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53160 | //PCIEMSIX_VECT245_ADDR_HI |
|---|
| 53161 | #define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53162 | #define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53163 | //PCIEMSIX_VECT245_MSG_DATA |
|---|
| 53164 | #define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53165 | #define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53166 | //PCIEMSIX_VECT245_CONTROL |
|---|
| 53167 | #define PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53168 | #define PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53169 | //PCIEMSIX_VECT246_ADDR_LO |
|---|
| 53170 | #define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53171 | #define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53172 | //PCIEMSIX_VECT246_ADDR_HI |
|---|
| 53173 | #define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53174 | #define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53175 | //PCIEMSIX_VECT246_MSG_DATA |
|---|
| 53176 | #define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53177 | #define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53178 | //PCIEMSIX_VECT246_CONTROL |
|---|
| 53179 | #define PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53180 | #define PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53181 | //PCIEMSIX_VECT247_ADDR_LO |
|---|
| 53182 | #define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53183 | #define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53184 | //PCIEMSIX_VECT247_ADDR_HI |
|---|
| 53185 | #define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53186 | #define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53187 | //PCIEMSIX_VECT247_MSG_DATA |
|---|
| 53188 | #define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53189 | #define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53190 | //PCIEMSIX_VECT247_CONTROL |
|---|
| 53191 | #define PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53192 | #define PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53193 | //PCIEMSIX_VECT248_ADDR_LO |
|---|
| 53194 | #define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53195 | #define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53196 | //PCIEMSIX_VECT248_ADDR_HI |
|---|
| 53197 | #define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53198 | #define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53199 | //PCIEMSIX_VECT248_MSG_DATA |
|---|
| 53200 | #define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53201 | #define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53202 | //PCIEMSIX_VECT248_CONTROL |
|---|
| 53203 | #define PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53204 | #define PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53205 | //PCIEMSIX_VECT249_ADDR_LO |
|---|
| 53206 | #define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53207 | #define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53208 | //PCIEMSIX_VECT249_ADDR_HI |
|---|
| 53209 | #define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53210 | #define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53211 | //PCIEMSIX_VECT249_MSG_DATA |
|---|
| 53212 | #define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53213 | #define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53214 | //PCIEMSIX_VECT249_CONTROL |
|---|
| 53215 | #define PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53216 | #define PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53217 | //PCIEMSIX_VECT250_ADDR_LO |
|---|
| 53218 | #define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53219 | #define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53220 | //PCIEMSIX_VECT250_ADDR_HI |
|---|
| 53221 | #define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53222 | #define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53223 | //PCIEMSIX_VECT250_MSG_DATA |
|---|
| 53224 | #define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53225 | #define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53226 | //PCIEMSIX_VECT250_CONTROL |
|---|
| 53227 | #define PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53228 | #define PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53229 | //PCIEMSIX_VECT251_ADDR_LO |
|---|
| 53230 | #define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53231 | #define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53232 | //PCIEMSIX_VECT251_ADDR_HI |
|---|
| 53233 | #define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53234 | #define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53235 | //PCIEMSIX_VECT251_MSG_DATA |
|---|
| 53236 | #define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53237 | #define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53238 | //PCIEMSIX_VECT251_CONTROL |
|---|
| 53239 | #define PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53240 | #define PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53241 | //PCIEMSIX_VECT252_ADDR_LO |
|---|
| 53242 | #define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53243 | #define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53244 | //PCIEMSIX_VECT252_ADDR_HI |
|---|
| 53245 | #define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53246 | #define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53247 | //PCIEMSIX_VECT252_MSG_DATA |
|---|
| 53248 | #define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53249 | #define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53250 | //PCIEMSIX_VECT252_CONTROL |
|---|
| 53251 | #define PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53252 | #define PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53253 | //PCIEMSIX_VECT253_ADDR_LO |
|---|
| 53254 | #define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53255 | #define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53256 | //PCIEMSIX_VECT253_ADDR_HI |
|---|
| 53257 | #define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53258 | #define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53259 | //PCIEMSIX_VECT253_MSG_DATA |
|---|
| 53260 | #define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53261 | #define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53262 | //PCIEMSIX_VECT253_CONTROL |
|---|
| 53263 | #define PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53264 | #define PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53265 | //PCIEMSIX_VECT254_ADDR_LO |
|---|
| 53266 | #define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53267 | #define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53268 | //PCIEMSIX_VECT254_ADDR_HI |
|---|
| 53269 | #define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53270 | #define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53271 | //PCIEMSIX_VECT254_MSG_DATA |
|---|
| 53272 | #define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53273 | #define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53274 | //PCIEMSIX_VECT254_CONTROL |
|---|
| 53275 | #define PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53276 | #define PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53277 | //PCIEMSIX_VECT255_ADDR_LO |
|---|
| 53278 | #define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 53279 | #define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 53280 | //PCIEMSIX_VECT255_ADDR_HI |
|---|
| 53281 | #define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 53282 | #define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 53283 | //PCIEMSIX_VECT255_MSG_DATA |
|---|
| 53284 | #define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 53285 | #define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 53286 | //PCIEMSIX_VECT255_CONTROL |
|---|
| 53287 | #define PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 53288 | #define PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 53289 | |
|---|
| 53290 | |
|---|
| 53291 | // addressBlock: nbio_nbif0_pciemsix_0_usb_MSIXPDEC |
|---|
| 53292 | //PCIEMSIX_PBA_0 |
|---|
| 53293 | #define PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT 0x0 |
|---|
| 53294 | #define PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
|---|
| 53295 | //PCIEMSIX_PBA_1 |
|---|
| 53296 | #define PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT 0x0 |
|---|
| 53297 | #define PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
|---|
| 53298 | //PCIEMSIX_PBA_2 |
|---|
| 53299 | #define PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT 0x0 |
|---|
| 53300 | #define PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
|---|
| 53301 | //PCIEMSIX_PBA_3 |
|---|
| 53302 | #define PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT 0x0 |
|---|
| 53303 | #define PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
|---|
| 53304 | //PCIEMSIX_PBA_4 |
|---|
| 53305 | #define PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT 0x0 |
|---|
| 53306 | #define PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
|---|
| 53307 | //PCIEMSIX_PBA_5 |
|---|
| 53308 | #define PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT 0x0 |
|---|
| 53309 | #define PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
|---|
| 53310 | //PCIEMSIX_PBA_6 |
|---|
| 53311 | #define PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT 0x0 |
|---|
| 53312 | #define PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
|---|
| 53313 | //PCIEMSIX_PBA_7 |
|---|
| 53314 | #define PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT 0x0 |
|---|
| 53315 | #define PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL |
|---|
| 53316 | |
|---|
| 53317 | |
|---|
| 53318 | // addressBlock: nbio_pcie0_pswusp0_pciedir_p |
|---|
| 53319 | //PCIEP_RESERVED |
|---|
| 53320 | #define PCIEP_RESERVED__RESERVED__SHIFT 0x0 |
|---|
| 53321 | #define PCIEP_RESERVED__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 53322 | //PCIEP_SCRATCH |
|---|
| 53323 | #define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 |
|---|
| 53324 | #define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 53325 | //PCIEP_PORT_CNTL |
|---|
| 53326 | #define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 |
|---|
| 53327 | #define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 |
|---|
| 53328 | #define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 |
|---|
| 53329 | #define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 |
|---|
| 53330 | #define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 |
|---|
| 53331 | #define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 |
|---|
| 53332 | #define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 |
|---|
| 53333 | #define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 |
|---|
| 53334 | #define PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18 |
|---|
| 53335 | #define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x1a |
|---|
| 53336 | #define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L |
|---|
| 53337 | #define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L |
|---|
| 53338 | #define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L |
|---|
| 53339 | #define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L |
|---|
| 53340 | #define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L |
|---|
| 53341 | #define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L |
|---|
| 53342 | #define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x0003FF00L |
|---|
| 53343 | #define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L |
|---|
| 53344 | #define PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L |
|---|
| 53345 | #define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x0C000000L |
|---|
| 53346 | //PCIE_TX_CNTL |
|---|
| 53347 | #define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa |
|---|
| 53348 | #define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc |
|---|
| 53349 | #define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe |
|---|
| 53350 | #define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf |
|---|
| 53351 | #define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 |
|---|
| 53352 | #define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 |
|---|
| 53353 | #define 0x16 |
|---|
| 53354 | #define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 |
|---|
| 53355 | #define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 |
|---|
| 53356 | #define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 |
|---|
| 53357 | #define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a |
|---|
| 53358 | #define PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT 0x1b |
|---|
| 53359 | #define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L |
|---|
| 53360 | #define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L |
|---|
| 53361 | #define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L |
|---|
| 53362 | #define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L |
|---|
| 53363 | #define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L |
|---|
| 53364 | #define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L |
|---|
| 53365 | #define 0x00400000L |
|---|
| 53366 | #define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L |
|---|
| 53367 | #define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L |
|---|
| 53368 | #define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L |
|---|
| 53369 | #define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L |
|---|
| 53370 | #define PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK 0x08000000L |
|---|
| 53371 | //PCIE_TX_REQUESTER_ID |
|---|
| 53372 | #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 |
|---|
| 53373 | #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 |
|---|
| 53374 | #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 |
|---|
| 53375 | #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L |
|---|
| 53376 | #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L |
|---|
| 53377 | #define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L |
|---|
| 53378 | //PCIE_TX_VENDOR_SPECIFIC |
|---|
| 53379 | #define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 |
|---|
| 53380 | #define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT 0x18 |
|---|
| 53381 | #define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL |
|---|
| 53382 | #define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK 0x01000000L |
|---|
| 53383 | //PCIE_TX_REQUEST_NUM_CNTL |
|---|
| 53384 | #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 |
|---|
| 53385 | #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e |
|---|
| 53386 | #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f |
|---|
| 53387 | #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L |
|---|
| 53388 | #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L |
|---|
| 53389 | #define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L |
|---|
| 53390 | //PCIE_TX_SEQ |
|---|
| 53391 | #define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 |
|---|
| 53392 | #define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 |
|---|
| 53393 | #define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL |
|---|
| 53394 | #define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L |
|---|
| 53395 | //PCIE_TX_REPLAY |
|---|
| 53396 | #define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 |
|---|
| 53397 | #define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf |
|---|
| 53398 | #define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 |
|---|
| 53399 | #define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L |
|---|
| 53400 | #define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L |
|---|
| 53401 | #define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L |
|---|
| 53402 | //PCIE_TX_ACK_LATENCY_LIMIT |
|---|
| 53403 | #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 |
|---|
| 53404 | #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc |
|---|
| 53405 | #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL |
|---|
| 53406 | #define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L |
|---|
| 53407 | //PCIE_TX_NOP_DLLP |
|---|
| 53408 | #define PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT 0x0 |
|---|
| 53409 | #define PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT 0x18 |
|---|
| 53410 | #define PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK 0x00FFFFFFL |
|---|
| 53411 | #define PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK 0x01000000L |
|---|
| 53412 | //PCIE_TX_CNTL_2 |
|---|
| 53413 | #define PCIE_TX_CNTL_2__TX_SKID_CREDIT_LIMIT__SHIFT 0x0 |
|---|
| 53414 | #define PCIE_TX_CNTL_2__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT 0x4 |
|---|
| 53415 | #define PCIE_TX_CNTL_2__TX_SKID_CREDIT_LIMIT_MASK 0x0000000FL |
|---|
| 53416 | #define PCIE_TX_CNTL_2__TX_SKID_CREDIT_OVERRIDE_EN_MASK 0x00000010L |
|---|
| 53417 | //PCIE_TX_CREDITS_ADVT_P |
|---|
| 53418 | #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 |
|---|
| 53419 | #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 |
|---|
| 53420 | #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00003FFFL |
|---|
| 53421 | #define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x03FF0000L |
|---|
| 53422 | //PCIE_TX_CREDITS_ADVT_NP |
|---|
| 53423 | #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 |
|---|
| 53424 | #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 |
|---|
| 53425 | #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00003FFFL |
|---|
| 53426 | #define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x03FF0000L |
|---|
| 53427 | //PCIE_TX_CREDITS_ADVT_CPL |
|---|
| 53428 | #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 |
|---|
| 53429 | #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 |
|---|
| 53430 | #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00003FFFL |
|---|
| 53431 | #define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x03FF0000L |
|---|
| 53432 | //PCIE_TX_CREDITS_INIT_P |
|---|
| 53433 | #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 |
|---|
| 53434 | #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 |
|---|
| 53435 | #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL |
|---|
| 53436 | #define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L |
|---|
| 53437 | //PCIE_TX_CREDITS_INIT_NP |
|---|
| 53438 | #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 |
|---|
| 53439 | #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 |
|---|
| 53440 | #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL |
|---|
| 53441 | #define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L |
|---|
| 53442 | //PCIE_TX_CREDITS_INIT_CPL |
|---|
| 53443 | #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 |
|---|
| 53444 | #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 |
|---|
| 53445 | #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL |
|---|
| 53446 | #define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L |
|---|
| 53447 | //PCIE_TX_CREDITS_STATUS |
|---|
| 53448 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 |
|---|
| 53449 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 |
|---|
| 53450 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 |
|---|
| 53451 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 |
|---|
| 53452 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 |
|---|
| 53453 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 |
|---|
| 53454 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 |
|---|
| 53455 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 |
|---|
| 53456 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 |
|---|
| 53457 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 |
|---|
| 53458 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 |
|---|
| 53459 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 |
|---|
| 53460 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L |
|---|
| 53461 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L |
|---|
| 53462 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L |
|---|
| 53463 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L |
|---|
| 53464 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L |
|---|
| 53465 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L |
|---|
| 53466 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L |
|---|
| 53467 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L |
|---|
| 53468 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L |
|---|
| 53469 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L |
|---|
| 53470 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L |
|---|
| 53471 | #define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L |
|---|
| 53472 | //PCIE_TX_CREDITS_FCU_THRESHOLD |
|---|
| 53473 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 |
|---|
| 53474 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 |
|---|
| 53475 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 |
|---|
| 53476 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 |
|---|
| 53477 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 |
|---|
| 53478 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 |
|---|
| 53479 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L |
|---|
| 53480 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L |
|---|
| 53481 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L |
|---|
| 53482 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L |
|---|
| 53483 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L |
|---|
| 53484 | #define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L |
|---|
| 53485 | //PCIE_P_PORT_LANE_STATUS |
|---|
| 53486 | #define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 |
|---|
| 53487 | #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 |
|---|
| 53488 | #define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L |
|---|
| 53489 | #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL |
|---|
| 53490 | //PCIE_FC_P |
|---|
| 53491 | #define PCIE_FC_P__PD_CREDITS__SHIFT 0x0 |
|---|
| 53492 | #define PCIE_FC_P__PH_CREDITS__SHIFT 0x10 |
|---|
| 53493 | #define PCIE_FC_P__PD_CREDITS_MASK 0x0000FFFFL |
|---|
| 53494 | #define PCIE_FC_P__PH_CREDITS_MASK 0x0FFF0000L |
|---|
| 53495 | //PCIE_FC_NP |
|---|
| 53496 | #define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 |
|---|
| 53497 | #define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x10 |
|---|
| 53498 | #define PCIE_FC_NP__NPD_CREDITS_MASK 0x0000FFFFL |
|---|
| 53499 | #define PCIE_FC_NP__NPH_CREDITS_MASK 0x0FFF0000L |
|---|
| 53500 | //PCIE_FC_CPL |
|---|
| 53501 | #define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 |
|---|
| 53502 | #define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x10 |
|---|
| 53503 | #define PCIE_FC_CPL__CPLD_CREDITS_MASK 0x0000FFFFL |
|---|
| 53504 | #define PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0FFF0000L |
|---|
| 53505 | //PCIE_FC_P_VC1 |
|---|
| 53506 | #define PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT 0x0 |
|---|
| 53507 | #define PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT 0x10 |
|---|
| 53508 | #define PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK 0x0000FFFFL |
|---|
| 53509 | #define PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK 0x0FFF0000L |
|---|
| 53510 | //PCIE_FC_NP_VC1 |
|---|
| 53511 | #define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT 0x0 |
|---|
| 53512 | #define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT 0x10 |
|---|
| 53513 | #define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK 0x0000FFFFL |
|---|
| 53514 | #define PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK 0x0FFF0000L |
|---|
| 53515 | //PCIE_FC_CPL_VC1 |
|---|
| 53516 | #define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT 0x0 |
|---|
| 53517 | #define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT 0x10 |
|---|
| 53518 | #define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK 0x0000FFFFL |
|---|
| 53519 | #define PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK 0x0FFF0000L |
|---|
| 53520 | //PSWUSP0_PCIE_ERR_CNTL |
|---|
| 53521 | #define PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 |
|---|
| 53522 | #define PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 |
|---|
| 53523 | #define PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 |
|---|
| 53524 | #define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 |
|---|
| 53525 | #define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 |
|---|
| 53526 | #define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 |
|---|
| 53527 | #define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 |
|---|
| 53528 | #define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 |
|---|
| 53529 | #define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb |
|---|
| 53530 | #define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc |
|---|
| 53531 | #define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd |
|---|
| 53532 | #define PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe |
|---|
| 53533 | #define PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf |
|---|
| 53534 | #define PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 |
|---|
| 53535 | #define PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 |
|---|
| 53536 | #define PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 |
|---|
| 53537 | #define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT 0x13 |
|---|
| 53538 | #define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT 0x14 |
|---|
| 53539 | #define PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L |
|---|
| 53540 | #define PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L |
|---|
| 53541 | #define PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L |
|---|
| 53542 | #define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L |
|---|
| 53543 | #define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L |
|---|
| 53544 | #define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L |
|---|
| 53545 | #define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L |
|---|
| 53546 | #define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L |
|---|
| 53547 | #define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L |
|---|
| 53548 | #define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x00001000L |
|---|
| 53549 | #define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x00002000L |
|---|
| 53550 | #define PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L |
|---|
| 53551 | #define PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L |
|---|
| 53552 | #define PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L |
|---|
| 53553 | #define PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L |
|---|
| 53554 | #define PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L |
|---|
| 53555 | #define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK 0x00080000L |
|---|
| 53556 | #define PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK 0x00100000L |
|---|
| 53557 | //PSWUSP0_PCIE_RX_CNTL |
|---|
| 53558 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 |
|---|
| 53559 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 |
|---|
| 53560 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 |
|---|
| 53561 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 |
|---|
| 53562 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 |
|---|
| 53563 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 |
|---|
| 53564 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 |
|---|
| 53565 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 |
|---|
| 53566 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 |
|---|
| 53567 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 |
|---|
| 53568 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa |
|---|
| 53569 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb |
|---|
| 53570 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc |
|---|
| 53571 | #define PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd |
|---|
| 53572 | #define PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe |
|---|
| 53573 | #define PSWUSP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf |
|---|
| 53574 | #define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 |
|---|
| 53575 | #define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 |
|---|
| 53576 | #define PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 |
|---|
| 53577 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 |
|---|
| 53578 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 |
|---|
| 53579 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 |
|---|
| 53580 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 |
|---|
| 53581 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 |
|---|
| 53582 | #define PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a |
|---|
| 53583 | #define PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b |
|---|
| 53584 | #define PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT 0x1c |
|---|
| 53585 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L |
|---|
| 53586 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L |
|---|
| 53587 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L |
|---|
| 53588 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L |
|---|
| 53589 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L |
|---|
| 53590 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L |
|---|
| 53591 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L |
|---|
| 53592 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L |
|---|
| 53593 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L |
|---|
| 53594 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L |
|---|
| 53595 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L |
|---|
| 53596 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L |
|---|
| 53597 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L |
|---|
| 53598 | #define PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L |
|---|
| 53599 | #define PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x00004000L |
|---|
| 53600 | #define PSWUSP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L |
|---|
| 53601 | #define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L |
|---|
| 53602 | #define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L |
|---|
| 53603 | #define PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L |
|---|
| 53604 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L |
|---|
| 53605 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L |
|---|
| 53606 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L |
|---|
| 53607 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L |
|---|
| 53608 | #define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L |
|---|
| 53609 | #define PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L |
|---|
| 53610 | #define PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L |
|---|
| 53611 | #define PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK 0x10000000L |
|---|
| 53612 | //PCIE_RX_EXPECTED_SEQNUM |
|---|
| 53613 | #define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 |
|---|
| 53614 | #define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL |
|---|
| 53615 | //PCIE_RX_VENDOR_SPECIFIC |
|---|
| 53616 | #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 |
|---|
| 53617 | #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 |
|---|
| 53618 | #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL |
|---|
| 53619 | #define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L |
|---|
| 53620 | //PCIE_RX_CNTL3 |
|---|
| 53621 | #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 |
|---|
| 53622 | #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 |
|---|
| 53623 | #define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 |
|---|
| 53624 | #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 |
|---|
| 53625 | #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 |
|---|
| 53626 | #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L |
|---|
| 53627 | #define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L |
|---|
| 53628 | #define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L |
|---|
| 53629 | #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L |
|---|
| 53630 | #define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L |
|---|
| 53631 | //PCIE_RX_CREDITS_ALLOCATED_P |
|---|
| 53632 | #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 |
|---|
| 53633 | #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 |
|---|
| 53634 | #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL |
|---|
| 53635 | #define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L |
|---|
| 53636 | //PCIE_RX_CREDITS_ALLOCATED_NP |
|---|
| 53637 | #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 |
|---|
| 53638 | #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 |
|---|
| 53639 | #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL |
|---|
| 53640 | #define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L |
|---|
| 53641 | //PCIE_RX_CREDITS_ALLOCATED_CPL |
|---|
| 53642 | #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 |
|---|
| 53643 | #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 |
|---|
| 53644 | #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL |
|---|
| 53645 | #define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L |
|---|
| 53646 | //PCIEP_ERROR_INJECT_PHYSICAL |
|---|
| 53647 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 |
|---|
| 53648 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 |
|---|
| 53649 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 |
|---|
| 53650 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 |
|---|
| 53651 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 |
|---|
| 53652 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa |
|---|
| 53653 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc |
|---|
| 53654 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe |
|---|
| 53655 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 |
|---|
| 53656 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 |
|---|
| 53657 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 |
|---|
| 53658 | #define 0x16 |
|---|
| 53659 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L |
|---|
| 53660 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL |
|---|
| 53661 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L |
|---|
| 53662 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L |
|---|
| 53663 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L |
|---|
| 53664 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L |
|---|
| 53665 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L |
|---|
| 53666 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L |
|---|
| 53667 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L |
|---|
| 53668 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L |
|---|
| 53669 | #define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L |
|---|
| 53670 | #define 0x00C00000L |
|---|
| 53671 | //PCIEP_ERROR_INJECT_TRANSACTION |
|---|
| 53672 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 |
|---|
| 53673 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 |
|---|
| 53674 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 |
|---|
| 53675 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 |
|---|
| 53676 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 |
|---|
| 53677 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa |
|---|
| 53678 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc |
|---|
| 53679 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe |
|---|
| 53680 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 |
|---|
| 53681 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 |
|---|
| 53682 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L |
|---|
| 53683 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL |
|---|
| 53684 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L |
|---|
| 53685 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L |
|---|
| 53686 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L |
|---|
| 53687 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L |
|---|
| 53688 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L |
|---|
| 53689 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L |
|---|
| 53690 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L |
|---|
| 53691 | #define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L |
|---|
| 53692 | //PCIEP_SRIOV_PRIV_CTRL |
|---|
| 53693 | #define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE__SHIFT 0x0 |
|---|
| 53694 | #define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x2 |
|---|
| 53695 | #define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE_MASK 0x00000003L |
|---|
| 53696 | #define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x0000000CL |
|---|
| 53697 | //PCIEP_NAK_COUNTER |
|---|
| 53698 | #define PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0 |
|---|
| 53699 | #define PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10 |
|---|
| 53700 | #define PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL |
|---|
| 53701 | #define PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L |
|---|
| 53702 | //PCIE_LC_CNTL |
|---|
| 53703 | #define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 |
|---|
| 53704 | #define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 |
|---|
| 53705 | #define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 |
|---|
| 53706 | #define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 |
|---|
| 53707 | #define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 |
|---|
| 53708 | #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc |
|---|
| 53709 | #define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 |
|---|
| 53710 | #define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 |
|---|
| 53711 | #define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 |
|---|
| 53712 | #define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 |
|---|
| 53713 | #define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 |
|---|
| 53714 | #define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 |
|---|
| 53715 | #define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 |
|---|
| 53716 | #define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 |
|---|
| 53717 | #define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 |
|---|
| 53718 | #define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b |
|---|
| 53719 | #define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c |
|---|
| 53720 | #define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d |
|---|
| 53721 | #define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e |
|---|
| 53722 | #define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f |
|---|
| 53723 | #define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L |
|---|
| 53724 | #define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L |
|---|
| 53725 | #define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L |
|---|
| 53726 | #define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L |
|---|
| 53727 | #define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L |
|---|
| 53728 | #define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L |
|---|
| 53729 | #define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L |
|---|
| 53730 | #define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L |
|---|
| 53731 | #define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L |
|---|
| 53732 | #define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L |
|---|
| 53733 | #define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L |
|---|
| 53734 | #define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L |
|---|
| 53735 | #define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L |
|---|
| 53736 | #define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L |
|---|
| 53737 | #define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L |
|---|
| 53738 | #define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L |
|---|
| 53739 | #define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L |
|---|
| 53740 | #define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L |
|---|
| 53741 | #define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L |
|---|
| 53742 | #define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L |
|---|
| 53743 | //PCIE_LC_TRAINING_CNTL |
|---|
| 53744 | #define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 |
|---|
| 53745 | #define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 |
|---|
| 53746 | #define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 |
|---|
| 53747 | #define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 |
|---|
| 53748 | #define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 |
|---|
| 53749 | #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 |
|---|
| 53750 | #define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb |
|---|
| 53751 | #define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc |
|---|
| 53752 | #define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd |
|---|
| 53753 | #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe |
|---|
| 53754 | #define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf |
|---|
| 53755 | #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 |
|---|
| 53756 | #define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 |
|---|
| 53757 | #define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 |
|---|
| 53758 | #define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 |
|---|
| 53759 | #define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 |
|---|
| 53760 | #define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 |
|---|
| 53761 | #define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 |
|---|
| 53762 | #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 |
|---|
| 53763 | #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 |
|---|
| 53764 | #define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a |
|---|
| 53765 | #define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b |
|---|
| 53766 | #define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c |
|---|
| 53767 | #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d |
|---|
| 53768 | #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e |
|---|
| 53769 | #define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL |
|---|
| 53770 | #define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L |
|---|
| 53771 | #define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L |
|---|
| 53772 | #define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L |
|---|
| 53773 | #define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L |
|---|
| 53774 | #define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L |
|---|
| 53775 | #define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L |
|---|
| 53776 | #define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L |
|---|
| 53777 | #define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L |
|---|
| 53778 | #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L |
|---|
| 53779 | #define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L |
|---|
| 53780 | #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L |
|---|
| 53781 | #define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L |
|---|
| 53782 | #define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L |
|---|
| 53783 | #define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L |
|---|
| 53784 | #define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L |
|---|
| 53785 | #define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L |
|---|
| 53786 | #define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L |
|---|
| 53787 | #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L |
|---|
| 53788 | #define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L |
|---|
| 53789 | #define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L |
|---|
| 53790 | #define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L |
|---|
| 53791 | #define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L |
|---|
| 53792 | #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L |
|---|
| 53793 | #define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L |
|---|
| 53794 | //PCIE_LC_LINK_WIDTH_CNTL |
|---|
| 53795 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 |
|---|
| 53796 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 |
|---|
| 53797 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 |
|---|
| 53798 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 |
|---|
| 53799 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 |
|---|
| 53800 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa |
|---|
| 53801 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb |
|---|
| 53802 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc |
|---|
| 53803 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd |
|---|
| 53804 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe |
|---|
| 53805 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf |
|---|
| 53806 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 |
|---|
| 53807 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 |
|---|
| 53808 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 |
|---|
| 53809 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 |
|---|
| 53810 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 |
|---|
| 53811 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 |
|---|
| 53812 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 |
|---|
| 53813 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 |
|---|
| 53814 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 |
|---|
| 53815 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a |
|---|
| 53816 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b |
|---|
| 53817 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c |
|---|
| 53818 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d |
|---|
| 53819 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e |
|---|
| 53820 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f |
|---|
| 53821 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L |
|---|
| 53822 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L |
|---|
| 53823 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L |
|---|
| 53824 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L |
|---|
| 53825 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L |
|---|
| 53826 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L |
|---|
| 53827 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L |
|---|
| 53828 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L |
|---|
| 53829 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L |
|---|
| 53830 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L |
|---|
| 53831 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L |
|---|
| 53832 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x00010000L |
|---|
| 53833 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L |
|---|
| 53834 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L |
|---|
| 53835 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L |
|---|
| 53836 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L |
|---|
| 53837 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L |
|---|
| 53838 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L |
|---|
| 53839 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L |
|---|
| 53840 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L |
|---|
| 53841 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L |
|---|
| 53842 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L |
|---|
| 53843 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L |
|---|
| 53844 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L |
|---|
| 53845 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L |
|---|
| 53846 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L |
|---|
| 53847 | //PCIE_LC_N_FTS_CNTL |
|---|
| 53848 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 |
|---|
| 53849 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 |
|---|
| 53850 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 |
|---|
| 53851 | #define PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT 0xa |
|---|
| 53852 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xe |
|---|
| 53853 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT 0xf |
|---|
| 53854 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 |
|---|
| 53855 | #define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 |
|---|
| 53856 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL |
|---|
| 53857 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L |
|---|
| 53858 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L |
|---|
| 53859 | #define PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK 0x00000400L |
|---|
| 53860 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00004000L |
|---|
| 53861 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK 0x00008000L |
|---|
| 53862 | #define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L |
|---|
| 53863 | #define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L |
|---|
| 53864 | //PSWUSP0_PCIE_LC_SPEED_CNTL |
|---|
| 53865 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 |
|---|
| 53866 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 |
|---|
| 53867 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 |
|---|
| 53868 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x3 |
|---|
| 53869 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x4 |
|---|
| 53870 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x6 |
|---|
| 53871 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x7 |
|---|
| 53872 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x8 |
|---|
| 53873 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x9 |
|---|
| 53874 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0xa |
|---|
| 53875 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xb |
|---|
| 53876 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xd |
|---|
| 53877 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xe |
|---|
| 53878 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x10 |
|---|
| 53879 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x11 |
|---|
| 53880 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x12 |
|---|
| 53881 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x13 |
|---|
| 53882 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x14 |
|---|
| 53883 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x15 |
|---|
| 53884 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x16 |
|---|
| 53885 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT 0x17 |
|---|
| 53886 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT 0x18 |
|---|
| 53887 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x19 |
|---|
| 53888 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x1a |
|---|
| 53889 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1c |
|---|
| 53890 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1d |
|---|
| 53891 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1e |
|---|
| 53892 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1f |
|---|
| 53893 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L |
|---|
| 53894 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L |
|---|
| 53895 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L |
|---|
| 53896 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000008L |
|---|
| 53897 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000030L |
|---|
| 53898 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000040L |
|---|
| 53899 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000080L |
|---|
| 53900 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000100L |
|---|
| 53901 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000200L |
|---|
| 53902 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000400L |
|---|
| 53903 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00001800L |
|---|
| 53904 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00002000L |
|---|
| 53905 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x0000C000L |
|---|
| 53906 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00010000L |
|---|
| 53907 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00020000L |
|---|
| 53908 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00040000L |
|---|
| 53909 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00080000L |
|---|
| 53910 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00100000L |
|---|
| 53911 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00200000L |
|---|
| 53912 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00400000L |
|---|
| 53913 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK 0x00800000L |
|---|
| 53914 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK 0x01000000L |
|---|
| 53915 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x02000000L |
|---|
| 53916 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x0C000000L |
|---|
| 53917 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x10000000L |
|---|
| 53918 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x20000000L |
|---|
| 53919 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x40000000L |
|---|
| 53920 | #define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x80000000L |
|---|
| 53921 | //PCIE_LC_STATE0 |
|---|
| 53922 | #define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 |
|---|
| 53923 | #define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 |
|---|
| 53924 | #define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 |
|---|
| 53925 | #define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 |
|---|
| 53926 | #define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL |
|---|
| 53927 | #define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L |
|---|
| 53928 | #define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L |
|---|
| 53929 | #define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L |
|---|
| 53930 | //PCIE_LC_STATE1 |
|---|
| 53931 | #define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 |
|---|
| 53932 | #define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 |
|---|
| 53933 | #define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 |
|---|
| 53934 | #define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 |
|---|
| 53935 | #define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL |
|---|
| 53936 | #define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L |
|---|
| 53937 | #define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L |
|---|
| 53938 | #define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L |
|---|
| 53939 | //PCIE_LC_STATE2 |
|---|
| 53940 | #define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 |
|---|
| 53941 | #define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 |
|---|
| 53942 | #define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 |
|---|
| 53943 | #define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 |
|---|
| 53944 | #define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL |
|---|
| 53945 | #define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L |
|---|
| 53946 | #define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L |
|---|
| 53947 | #define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L |
|---|
| 53948 | //PCIE_LC_STATE3 |
|---|
| 53949 | #define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 |
|---|
| 53950 | #define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 |
|---|
| 53951 | #define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 |
|---|
| 53952 | #define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 |
|---|
| 53953 | #define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL |
|---|
| 53954 | #define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L |
|---|
| 53955 | #define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L |
|---|
| 53956 | #define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L |
|---|
| 53957 | //PCIE_LC_STATE4 |
|---|
| 53958 | #define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 |
|---|
| 53959 | #define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 |
|---|
| 53960 | #define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 |
|---|
| 53961 | #define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 |
|---|
| 53962 | #define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL |
|---|
| 53963 | #define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L |
|---|
| 53964 | #define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L |
|---|
| 53965 | #define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L |
|---|
| 53966 | //PCIE_LC_STATE5 |
|---|
| 53967 | #define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 |
|---|
| 53968 | #define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 |
|---|
| 53969 | #define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 |
|---|
| 53970 | #define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 |
|---|
| 53971 | #define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL |
|---|
| 53972 | #define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L |
|---|
| 53973 | #define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L |
|---|
| 53974 | #define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L |
|---|
| 53975 | //PCIE_LINK_MANAGEMENT_CNTL2 |
|---|
| 53976 | #define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0 |
|---|
| 53977 | #define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1 |
|---|
| 53978 | #define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2 |
|---|
| 53979 | #define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3 |
|---|
| 53980 | #define PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4 |
|---|
| 53981 | #define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7 |
|---|
| 53982 | #define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb |
|---|
| 53983 | #define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf |
|---|
| 53984 | #define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13 |
|---|
| 53985 | #define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT 0x17 |
|---|
| 53986 | #define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT 0x1b |
|---|
| 53987 | #define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L |
|---|
| 53988 | #define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L |
|---|
| 53989 | #define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L |
|---|
| 53990 | #define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L |
|---|
| 53991 | #define PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000070L |
|---|
| 53992 | #define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L |
|---|
| 53993 | #define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L |
|---|
| 53994 | #define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L |
|---|
| 53995 | #define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L |
|---|
| 53996 | #define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK 0x07800000L |
|---|
| 53997 | #define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK 0x78000000L |
|---|
| 53998 | //PSWUSP0_PCIE_LC_CNTL2 |
|---|
| 53999 | #define PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 |
|---|
| 54000 | #define PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 |
|---|
| 54001 | #define PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 |
|---|
| 54002 | #define PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 |
|---|
| 54003 | #define PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 |
|---|
| 54004 | #define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa |
|---|
| 54005 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb |
|---|
| 54006 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc |
|---|
| 54007 | #define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd |
|---|
| 54008 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe |
|---|
| 54009 | #define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 |
|---|
| 54010 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 |
|---|
| 54011 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 |
|---|
| 54012 | #define PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x13 |
|---|
| 54013 | #define PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 |
|---|
| 54014 | #define PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 |
|---|
| 54015 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 |
|---|
| 54016 | #define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 |
|---|
| 54017 | #define PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 |
|---|
| 54018 | #define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a |
|---|
| 54019 | #define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b |
|---|
| 54020 | #define PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c |
|---|
| 54021 | #define PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d |
|---|
| 54022 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f |
|---|
| 54023 | #define PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL |
|---|
| 54024 | #define PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L |
|---|
| 54025 | #define PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L |
|---|
| 54026 | #define PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L |
|---|
| 54027 | #define PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L |
|---|
| 54028 | #define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L |
|---|
| 54029 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L |
|---|
| 54030 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L |
|---|
| 54031 | #define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L |
|---|
| 54032 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L |
|---|
| 54033 | #define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L |
|---|
| 54034 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L |
|---|
| 54035 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L |
|---|
| 54036 | #define PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x00080000L |
|---|
| 54037 | #define PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L |
|---|
| 54038 | #define PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L |
|---|
| 54039 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L |
|---|
| 54040 | #define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L |
|---|
| 54041 | #define PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L |
|---|
| 54042 | #define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L |
|---|
| 54043 | #define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L |
|---|
| 54044 | #define PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L |
|---|
| 54045 | #define PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L |
|---|
| 54046 | #define PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L |
|---|
| 54047 | //PCIE_LC_BW_CHANGE_CNTL |
|---|
| 54048 | #define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 |
|---|
| 54049 | #define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 |
|---|
| 54050 | #define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 |
|---|
| 54051 | #define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 |
|---|
| 54052 | #define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 |
|---|
| 54053 | #define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 |
|---|
| 54054 | #define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 |
|---|
| 54055 | #define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 |
|---|
| 54056 | #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 |
|---|
| 54057 | #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 |
|---|
| 54058 | #define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa |
|---|
| 54059 | #define PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb |
|---|
| 54060 | #define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L |
|---|
| 54061 | #define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L |
|---|
| 54062 | #define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L |
|---|
| 54063 | #define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L |
|---|
| 54064 | #define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L |
|---|
| 54065 | #define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L |
|---|
| 54066 | #define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L |
|---|
| 54067 | #define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L |
|---|
| 54068 | #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L |
|---|
| 54069 | #define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L |
|---|
| 54070 | #define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L |
|---|
| 54071 | #define PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L |
|---|
| 54072 | //PCIE_LC_CDR_CNTL |
|---|
| 54073 | #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 |
|---|
| 54074 | #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc |
|---|
| 54075 | #define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 |
|---|
| 54076 | #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL |
|---|
| 54077 | #define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L |
|---|
| 54078 | #define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L |
|---|
| 54079 | //PCIE_LC_LANE_CNTL |
|---|
| 54080 | #define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 |
|---|
| 54081 | #define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL |
|---|
| 54082 | //PCIE_LC_CNTL3 |
|---|
| 54083 | #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 |
|---|
| 54084 | #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 |
|---|
| 54085 | #define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 |
|---|
| 54086 | #define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 |
|---|
| 54087 | #define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 |
|---|
| 54088 | #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 |
|---|
| 54089 | #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 |
|---|
| 54090 | #define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 |
|---|
| 54091 | #define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa |
|---|
| 54092 | #define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb |
|---|
| 54093 | #define PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT 0xc |
|---|
| 54094 | #define PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT 0xd |
|---|
| 54095 | #define PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT 0xe |
|---|
| 54096 | #define PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT 0xf |
|---|
| 54097 | #define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 |
|---|
| 54098 | #define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 |
|---|
| 54099 | #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 |
|---|
| 54100 | #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 |
|---|
| 54101 | #define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 |
|---|
| 54102 | #define PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT 0x16 |
|---|
| 54103 | #define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 |
|---|
| 54104 | #define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 |
|---|
| 54105 | #define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a |
|---|
| 54106 | #define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e |
|---|
| 54107 | #define PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT 0x1f |
|---|
| 54108 | #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L |
|---|
| 54109 | #define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L |
|---|
| 54110 | #define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L |
|---|
| 54111 | #define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L |
|---|
| 54112 | #define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L |
|---|
| 54113 | #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L |
|---|
| 54114 | #define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L |
|---|
| 54115 | #define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L |
|---|
| 54116 | #define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L |
|---|
| 54117 | #define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L |
|---|
| 54118 | #define PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK 0x00001000L |
|---|
| 54119 | #define PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK 0x00002000L |
|---|
| 54120 | #define PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK 0x00004000L |
|---|
| 54121 | #define PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK 0x00008000L |
|---|
| 54122 | #define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x00010000L |
|---|
| 54123 | #define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L |
|---|
| 54124 | #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L |
|---|
| 54125 | #define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L |
|---|
| 54126 | #define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L |
|---|
| 54127 | #define PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK 0x00400000L |
|---|
| 54128 | #define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L |
|---|
| 54129 | #define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L |
|---|
| 54130 | #define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L |
|---|
| 54131 | #define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L |
|---|
| 54132 | #define PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK 0x80000000L |
|---|
| 54133 | //PCIE_LC_CNTL4 |
|---|
| 54134 | #define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 |
|---|
| 54135 | #define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 |
|---|
| 54136 | #define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 |
|---|
| 54137 | #define PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT 0x4 |
|---|
| 54138 | #define PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT 0x5 |
|---|
| 54139 | #define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 |
|---|
| 54140 | #define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 |
|---|
| 54141 | #define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT 0x8 |
|---|
| 54142 | #define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa |
|---|
| 54143 | #define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT 0xb |
|---|
| 54144 | #define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT 0xc |
|---|
| 54145 | #define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd |
|---|
| 54146 | #define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe |
|---|
| 54147 | #define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT 0xf |
|---|
| 54148 | #define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT 0x10 |
|---|
| 54149 | #define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT 0x11 |
|---|
| 54150 | #define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT 0x12 |
|---|
| 54151 | #define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 |
|---|
| 54152 | #define PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17 |
|---|
| 54153 | #define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 |
|---|
| 54154 | #define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 |
|---|
| 54155 | #define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a |
|---|
| 54156 | #define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L |
|---|
| 54157 | #define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L |
|---|
| 54158 | #define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L |
|---|
| 54159 | #define PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK 0x00000010L |
|---|
| 54160 | #define PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK 0x00000020L |
|---|
| 54161 | #define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L |
|---|
| 54162 | #define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L |
|---|
| 54163 | #define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK 0x00000300L |
|---|
| 54164 | #define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L |
|---|
| 54165 | #define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK 0x00000800L |
|---|
| 54166 | #define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK 0x00001000L |
|---|
| 54167 | #define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L |
|---|
| 54168 | #define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L |
|---|
| 54169 | #define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK 0x00008000L |
|---|
| 54170 | #define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK 0x00010000L |
|---|
| 54171 | #define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK 0x00020000L |
|---|
| 54172 | #define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK 0x003C0000L |
|---|
| 54173 | #define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L |
|---|
| 54174 | #define PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L |
|---|
| 54175 | #define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L |
|---|
| 54176 | #define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L |
|---|
| 54177 | #define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L |
|---|
| 54178 | //PCIE_LC_CNTL5 |
|---|
| 54179 | #define PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT 0x0 |
|---|
| 54180 | #define PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT 0x2 |
|---|
| 54181 | #define PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT 0x6 |
|---|
| 54182 | #define PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT 0xa |
|---|
| 54183 | #define PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT 0x10 |
|---|
| 54184 | #define PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT 0x15 |
|---|
| 54185 | #define PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT 0x16 |
|---|
| 54186 | #define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 |
|---|
| 54187 | #define PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19 |
|---|
| 54188 | #define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a |
|---|
| 54189 | #define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b |
|---|
| 54190 | #define PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c |
|---|
| 54191 | #define PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d |
|---|
| 54192 | #define PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK 0x00000003L |
|---|
| 54193 | #define PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK 0x0000003CL |
|---|
| 54194 | #define PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK 0x000003C0L |
|---|
| 54195 | #define PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK 0x0000FC00L |
|---|
| 54196 | #define PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK 0x001F0000L |
|---|
| 54197 | #define PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK 0x00200000L |
|---|
| 54198 | #define PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK 0x00C00000L |
|---|
| 54199 | #define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L |
|---|
| 54200 | #define PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L |
|---|
| 54201 | #define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L |
|---|
| 54202 | #define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L |
|---|
| 54203 | #define PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L |
|---|
| 54204 | #define PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L |
|---|
| 54205 | //PCIE_LC_FORCE_COEFF |
|---|
| 54206 | #define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT 0x0 |
|---|
| 54207 | #define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT 0x1 |
|---|
| 54208 | #define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT 0x7 |
|---|
| 54209 | #define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT 0xd |
|---|
| 54210 | #define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT 0x13 |
|---|
| 54211 | #define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 |
|---|
| 54212 | #define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK 0x00000001L |
|---|
| 54213 | #define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK 0x0000007EL |
|---|
| 54214 | #define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK 0x00001F80L |
|---|
| 54215 | #define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK 0x0007E000L |
|---|
| 54216 | #define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK 0x00080000L |
|---|
| 54217 | #define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L |
|---|
| 54218 | //PCIE_LC_BEST_EQ_SETTINGS |
|---|
| 54219 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 |
|---|
| 54220 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 |
|---|
| 54221 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa |
|---|
| 54222 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 |
|---|
| 54223 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 |
|---|
| 54224 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT 0x1e |
|---|
| 54225 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL |
|---|
| 54226 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L |
|---|
| 54227 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L |
|---|
| 54228 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L |
|---|
| 54229 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L |
|---|
| 54230 | #define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK 0x40000000L |
|---|
| 54231 | //PCIE_LC_FORCE_EQ_REQ_COEFF |
|---|
| 54232 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT 0x0 |
|---|
| 54233 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT 0x1 |
|---|
| 54234 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT 0x7 |
|---|
| 54235 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT 0xd |
|---|
| 54236 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT 0x13 |
|---|
| 54237 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT 0x19 |
|---|
| 54238 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK 0x00000001L |
|---|
| 54239 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK 0x0000007EL |
|---|
| 54240 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK 0x00001F80L |
|---|
| 54241 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK 0x0007E000L |
|---|
| 54242 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK 0x01F80000L |
|---|
| 54243 | #define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK 0x7E000000L |
|---|
| 54244 | //PCIE_LC_CNTL6 |
|---|
| 54245 | #define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 |
|---|
| 54246 | #define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 |
|---|
| 54247 | #define PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 |
|---|
| 54248 | #define PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT 0x6 |
|---|
| 54249 | #define PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8 |
|---|
| 54250 | #define PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9 |
|---|
| 54251 | #define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd |
|---|
| 54252 | #define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe |
|---|
| 54253 | #define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10 |
|---|
| 54254 | #define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12 |
|---|
| 54255 | #define PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13 |
|---|
| 54256 | #define PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14 |
|---|
| 54257 | #define PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15 |
|---|
| 54258 | #define PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16 |
|---|
| 54259 | #define PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17 |
|---|
| 54260 | #define PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18 |
|---|
| 54261 | #define PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f |
|---|
| 54262 | #define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000003L |
|---|
| 54263 | #define PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x0000000CL |
|---|
| 54264 | #define PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000030L |
|---|
| 54265 | #define PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK 0x000000C0L |
|---|
| 54266 | #define PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L |
|---|
| 54267 | #define PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L |
|---|
| 54268 | #define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L |
|---|
| 54269 | #define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L |
|---|
| 54270 | #define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L |
|---|
| 54271 | #define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L |
|---|
| 54272 | #define PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L |
|---|
| 54273 | #define PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L |
|---|
| 54274 | #define PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L |
|---|
| 54275 | #define PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L |
|---|
| 54276 | #define PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L |
|---|
| 54277 | #define PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L |
|---|
| 54278 | #define PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L |
|---|
| 54279 | //PCIE_LC_CNTL7 |
|---|
| 54280 | #define PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0 |
|---|
| 54281 | #define PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1 |
|---|
| 54282 | #define PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2 |
|---|
| 54283 | #define PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3 |
|---|
| 54284 | #define PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4 |
|---|
| 54285 | #define PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5 |
|---|
| 54286 | #define PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6 |
|---|
| 54287 | #define PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7 |
|---|
| 54288 | #define PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8 |
|---|
| 54289 | #define PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9 |
|---|
| 54290 | #define PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa |
|---|
| 54291 | #define PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb |
|---|
| 54292 | #define PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc |
|---|
| 54293 | #define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd |
|---|
| 54294 | #define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15 |
|---|
| 54295 | #define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16 |
|---|
| 54296 | #define PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17 |
|---|
| 54297 | #define PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT 0x18 |
|---|
| 54298 | #define PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT 0x19 |
|---|
| 54299 | #define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b |
|---|
| 54300 | #define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c |
|---|
| 54301 | #define PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d |
|---|
| 54302 | #define PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e |
|---|
| 54303 | #define PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT 0x1f |
|---|
| 54304 | #define PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L |
|---|
| 54305 | #define PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L |
|---|
| 54306 | #define PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L |
|---|
| 54307 | #define PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L |
|---|
| 54308 | #define PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L |
|---|
| 54309 | #define PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L |
|---|
| 54310 | #define PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L |
|---|
| 54311 | #define PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L |
|---|
| 54312 | #define PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L |
|---|
| 54313 | #define PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L |
|---|
| 54314 | #define PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L |
|---|
| 54315 | #define PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L |
|---|
| 54316 | #define PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L |
|---|
| 54317 | #define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L |
|---|
| 54318 | #define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L |
|---|
| 54319 | #define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L |
|---|
| 54320 | #define PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L |
|---|
| 54321 | #define PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK 0x01000000L |
|---|
| 54322 | #define PCIE_LC_CNTL7__LC_ESM_RATES_MASK 0x06000000L |
|---|
| 54323 | #define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L |
|---|
| 54324 | #define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L |
|---|
| 54325 | #define PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L |
|---|
| 54326 | #define PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L |
|---|
| 54327 | #define PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK 0x80000000L |
|---|
| 54328 | //PCIE_LINK_MANAGEMENT_STATUS |
|---|
| 54329 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0 |
|---|
| 54330 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1 |
|---|
| 54331 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2 |
|---|
| 54332 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3 |
|---|
| 54333 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4 |
|---|
| 54334 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5 |
|---|
| 54335 | #define PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6 |
|---|
| 54336 | #define PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7 |
|---|
| 54337 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8 |
|---|
| 54338 | #define PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9 |
|---|
| 54339 | #define PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa |
|---|
| 54340 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb |
|---|
| 54341 | #define PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc |
|---|
| 54342 | #define PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd |
|---|
| 54343 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L |
|---|
| 54344 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L |
|---|
| 54345 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L |
|---|
| 54346 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L |
|---|
| 54347 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L |
|---|
| 54348 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L |
|---|
| 54349 | #define PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L |
|---|
| 54350 | #define PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L |
|---|
| 54351 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L |
|---|
| 54352 | #define PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L |
|---|
| 54353 | #define PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L |
|---|
| 54354 | #define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L |
|---|
| 54355 | #define PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L |
|---|
| 54356 | #define PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L |
|---|
| 54357 | //PCIE_LINK_MANAGEMENT_MASK |
|---|
| 54358 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0 |
|---|
| 54359 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1 |
|---|
| 54360 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2 |
|---|
| 54361 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3 |
|---|
| 54362 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4 |
|---|
| 54363 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5 |
|---|
| 54364 | #define PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6 |
|---|
| 54365 | #define PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7 |
|---|
| 54366 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8 |
|---|
| 54367 | #define PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9 |
|---|
| 54368 | #define PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa |
|---|
| 54369 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb |
|---|
| 54370 | #define PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc |
|---|
| 54371 | #define PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd |
|---|
| 54372 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L |
|---|
| 54373 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L |
|---|
| 54374 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L |
|---|
| 54375 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L |
|---|
| 54376 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L |
|---|
| 54377 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L |
|---|
| 54378 | #define PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L |
|---|
| 54379 | #define PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L |
|---|
| 54380 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L |
|---|
| 54381 | #define PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L |
|---|
| 54382 | #define PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L |
|---|
| 54383 | #define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L |
|---|
| 54384 | #define PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L |
|---|
| 54385 | #define PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L |
|---|
| 54386 | //PCIE_LINK_MANAGEMENT_CNTL |
|---|
| 54387 | #define PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0 |
|---|
| 54388 | #define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3 |
|---|
| 54389 | #define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7 |
|---|
| 54390 | #define PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb |
|---|
| 54391 | #define PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc |
|---|
| 54392 | #define PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd |
|---|
| 54393 | #define PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf |
|---|
| 54394 | #define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11 |
|---|
| 54395 | #define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12 |
|---|
| 54396 | #define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13 |
|---|
| 54397 | #define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17 |
|---|
| 54398 | #define PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b |
|---|
| 54399 | #define PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT 0x1e |
|---|
| 54400 | #define PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT 0x1f |
|---|
| 54401 | #define PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L |
|---|
| 54402 | #define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L |
|---|
| 54403 | #define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L |
|---|
| 54404 | #define PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L |
|---|
| 54405 | #define PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L |
|---|
| 54406 | #define PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L |
|---|
| 54407 | #define PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L |
|---|
| 54408 | #define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L |
|---|
| 54409 | #define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L |
|---|
| 54410 | #define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L |
|---|
| 54411 | #define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L |
|---|
| 54412 | #define PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L |
|---|
| 54413 | #define PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK 0x40000000L |
|---|
| 54414 | #define PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK 0x80000000L |
|---|
| 54415 | //PCIEP_STRAP_LC |
|---|
| 54416 | #define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 |
|---|
| 54417 | #define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 |
|---|
| 54418 | #define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 |
|---|
| 54419 | #define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 |
|---|
| 54420 | #define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 |
|---|
| 54421 | #define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb |
|---|
| 54422 | #define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc |
|---|
| 54423 | #define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd |
|---|
| 54424 | #define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe |
|---|
| 54425 | #define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf |
|---|
| 54426 | #define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 |
|---|
| 54427 | #define PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x13 |
|---|
| 54428 | #define PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT 0x14 |
|---|
| 54429 | #define PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT 0x15 |
|---|
| 54430 | #define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L |
|---|
| 54431 | #define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL |
|---|
| 54432 | #define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L |
|---|
| 54433 | #define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L |
|---|
| 54434 | #define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L |
|---|
| 54435 | #define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L |
|---|
| 54436 | #define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L |
|---|
| 54437 | #define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L |
|---|
| 54438 | #define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L |
|---|
| 54439 | #define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L |
|---|
| 54440 | #define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L |
|---|
| 54441 | #define PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00080000L |
|---|
| 54442 | #define PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK 0x00100000L |
|---|
| 54443 | #define PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK 0x00200000L |
|---|
| 54444 | //PSWUSP0_PCIEP_STRAP_MISC |
|---|
| 54445 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 |
|---|
| 54446 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 |
|---|
| 54447 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 |
|---|
| 54448 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 |
|---|
| 54449 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 |
|---|
| 54450 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT 0x6 |
|---|
| 54451 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT 0x7 |
|---|
| 54452 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L |
|---|
| 54453 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L |
|---|
| 54454 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L |
|---|
| 54455 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L |
|---|
| 54456 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L |
|---|
| 54457 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK 0x00000040L |
|---|
| 54458 | #define PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK 0x00000080L |
|---|
| 54459 | //PCIEP_STRAP_LC2 |
|---|
| 54460 | #define PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 54461 | #define PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT 0x1 |
|---|
| 54462 | #define PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT 0x3 |
|---|
| 54463 | #define PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT 0x4 |
|---|
| 54464 | #define PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT 0x7 |
|---|
| 54465 | #define PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 54466 | #define PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK 0x00000006L |
|---|
| 54467 | #define PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK 0x00000008L |
|---|
| 54468 | #define PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK 0x00000070L |
|---|
| 54469 | #define PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK 0x00000380L |
|---|
| 54470 | //PCIE_LC_L1_PM_SUBSTATE |
|---|
| 54471 | #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0 |
|---|
| 54472 | #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1 |
|---|
| 54473 | #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2 |
|---|
| 54474 | #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3 |
|---|
| 54475 | #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4 |
|---|
| 54476 | #define PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT 0x5 |
|---|
| 54477 | #define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6 |
|---|
| 54478 | #define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8 |
|---|
| 54479 | #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10 |
|---|
| 54480 | #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14 |
|---|
| 54481 | #define PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17 |
|---|
| 54482 | #define PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT 0x1a |
|---|
| 54483 | #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L |
|---|
| 54484 | #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L |
|---|
| 54485 | #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L |
|---|
| 54486 | #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L |
|---|
| 54487 | #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L |
|---|
| 54488 | #define PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK 0x00000020L |
|---|
| 54489 | #define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L |
|---|
| 54490 | #define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L |
|---|
| 54491 | #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L |
|---|
| 54492 | #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L |
|---|
| 54493 | #define PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L |
|---|
| 54494 | #define PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK 0x04000000L |
|---|
| 54495 | //PCIE_LC_L1_PM_SUBSTATE2 |
|---|
| 54496 | #define PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0 |
|---|
| 54497 | #define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8 |
|---|
| 54498 | #define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10 |
|---|
| 54499 | #define PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL |
|---|
| 54500 | #define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L |
|---|
| 54501 | #define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L |
|---|
| 54502 | //PCIE_LC_PORT_ORDER |
|---|
| 54503 | #define PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0 |
|---|
| 54504 | #define PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL |
|---|
| 54505 | //PCIEP_BCH_ECC_CNTL |
|---|
| 54506 | #define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 |
|---|
| 54507 | #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 |
|---|
| 54508 | #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 |
|---|
| 54509 | #define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L |
|---|
| 54510 | #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L |
|---|
| 54511 | #define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L |
|---|
| 54512 | //PCIE_LC_CNTL8 |
|---|
| 54513 | #define PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT 0x0 |
|---|
| 54514 | #define PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT 0x2 |
|---|
| 54515 | #define PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT 0x3 |
|---|
| 54516 | #define PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT 0x7 |
|---|
| 54517 | #define PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT 0x8 |
|---|
| 54518 | #define PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT 0x9 |
|---|
| 54519 | #define PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT 0xa |
|---|
| 54520 | #define PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT 0xb |
|---|
| 54521 | #define PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT 0xc |
|---|
| 54522 | #define PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT 0xd |
|---|
| 54523 | #define PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT 0x11 |
|---|
| 54524 | #define PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT 0x12 |
|---|
| 54525 | #define PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT 0x16 |
|---|
| 54526 | #define PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT 0x17 |
|---|
| 54527 | #define PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT 0x19 |
|---|
| 54528 | #define PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1a |
|---|
| 54529 | #define PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1b |
|---|
| 54530 | #define PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT 0x1c |
|---|
| 54531 | #define PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x1d |
|---|
| 54532 | #define PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x1e |
|---|
| 54533 | #define PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK 0x00000003L |
|---|
| 54534 | #define PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK 0x00000004L |
|---|
| 54535 | #define PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK 0x00000078L |
|---|
| 54536 | #define PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK 0x00000080L |
|---|
| 54537 | #define PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK 0x00000100L |
|---|
| 54538 | #define PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK 0x00000200L |
|---|
| 54539 | #define PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK 0x00000400L |
|---|
| 54540 | #define PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK 0x00000800L |
|---|
| 54541 | #define PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK 0x00001000L |
|---|
| 54542 | #define PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK 0x0001E000L |
|---|
| 54543 | #define PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK 0x00020000L |
|---|
| 54544 | #define PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK 0x003C0000L |
|---|
| 54545 | #define PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK 0x00400000L |
|---|
| 54546 | #define PCIE_LC_CNTL8__LC_FOM_TIME_MASK 0x01800000L |
|---|
| 54547 | #define PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK 0x02000000L |
|---|
| 54548 | #define PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x04000000L |
|---|
| 54549 | #define PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x08000000L |
|---|
| 54550 | #define PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK 0x10000000L |
|---|
| 54551 | #define PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x20000000L |
|---|
| 54552 | #define PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0xC0000000L |
|---|
| 54553 | //PCIE_LC_CNTL9 |
|---|
| 54554 | #define PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT 0x0 |
|---|
| 54555 | #define PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT 0x1 |
|---|
| 54556 | #define PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT 0x3 |
|---|
| 54557 | #define PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT 0x4 |
|---|
| 54558 | #define PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT 0x6 |
|---|
| 54559 | #define PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT 0x8 |
|---|
| 54560 | #define PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT 0xa |
|---|
| 54561 | #define PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT 0xb |
|---|
| 54562 | #define PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT 0xc |
|---|
| 54563 | #define PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT 0xd |
|---|
| 54564 | #define PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT 0xe |
|---|
| 54565 | #define PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT 0x18 |
|---|
| 54566 | #define PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT 0x19 |
|---|
| 54567 | #define PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT 0x1a |
|---|
| 54568 | #define PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT 0x1b |
|---|
| 54569 | #define PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT 0x1c |
|---|
| 54570 | #define PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT 0x1d |
|---|
| 54571 | #define PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT 0x1f |
|---|
| 54572 | #define PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK 0x00000001L |
|---|
| 54573 | #define PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK 0x00000006L |
|---|
| 54574 | #define PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK 0x00000008L |
|---|
| 54575 | #define PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK 0x00000030L |
|---|
| 54576 | #define PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK 0x000000C0L |
|---|
| 54577 | #define PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK 0x00000300L |
|---|
| 54578 | #define PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK 0x00000400L |
|---|
| 54579 | #define PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK 0x00000800L |
|---|
| 54580 | #define PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK 0x00001000L |
|---|
| 54581 | #define PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK 0x00002000L |
|---|
| 54582 | #define PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK 0x00FFC000L |
|---|
| 54583 | #define PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK 0x01000000L |
|---|
| 54584 | #define PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK 0x02000000L |
|---|
| 54585 | #define PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK 0x04000000L |
|---|
| 54586 | #define PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK 0x08000000L |
|---|
| 54587 | #define PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK 0x10000000L |
|---|
| 54588 | #define PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK 0x20000000L |
|---|
| 54589 | #define PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK 0x80000000L |
|---|
| 54590 | //PCIE_LC_FORCE_COEFF2 |
|---|
| 54591 | #define PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT 0x0 |
|---|
| 54592 | #define PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT 0x1 |
|---|
| 54593 | #define PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT 0x7 |
|---|
| 54594 | #define PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT 0xd |
|---|
| 54595 | #define PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT 0x13 |
|---|
| 54596 | #define PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK 0x00000001L |
|---|
| 54597 | #define PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK 0x0000007EL |
|---|
| 54598 | #define PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK 0x00001F80L |
|---|
| 54599 | #define PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK 0x0007E000L |
|---|
| 54600 | #define PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK 0x00080000L |
|---|
| 54601 | //PCIE_LC_FORCE_EQ_REQ_COEFF2 |
|---|
| 54602 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT 0x0 |
|---|
| 54603 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT 0x1 |
|---|
| 54604 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT 0x7 |
|---|
| 54605 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT 0xd |
|---|
| 54606 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT 0x13 |
|---|
| 54607 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT 0x19 |
|---|
| 54608 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK 0x00000001L |
|---|
| 54609 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK 0x0000007EL |
|---|
| 54610 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK 0x00001F80L |
|---|
| 54611 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK 0x0007E000L |
|---|
| 54612 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK 0x01F80000L |
|---|
| 54613 | #define PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK 0x7E000000L |
|---|
| 54614 | //PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES |
|---|
| 54615 | #define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT 0x0 |
|---|
| 54616 | #define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT 0x1 |
|---|
| 54617 | #define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK 0x00000001L |
|---|
| 54618 | #define PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK 0x00000002L |
|---|
| 54619 | //PCIE_LC_CNTL10 |
|---|
| 54620 | #define PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT 0x0 |
|---|
| 54621 | #define PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT 0x1 |
|---|
| 54622 | #define PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT 0x2 |
|---|
| 54623 | #define PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT 0x4 |
|---|
| 54624 | #define PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT 0x6 |
|---|
| 54625 | #define PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT 0x10 |
|---|
| 54626 | #define PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT 0x1a |
|---|
| 54627 | #define PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT 0x1b |
|---|
| 54628 | #define PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT 0x1d |
|---|
| 54629 | #define PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT 0x1e |
|---|
| 54630 | #define PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT 0x1f |
|---|
| 54631 | #define PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK 0x00000001L |
|---|
| 54632 | #define PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK 0x00000002L |
|---|
| 54633 | #define PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK 0x0000000CL |
|---|
| 54634 | #define PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK 0x00000030L |
|---|
| 54635 | #define PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK 0x0000FFC0L |
|---|
| 54636 | #define PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK 0x03FF0000L |
|---|
| 54637 | #define PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK 0x04000000L |
|---|
| 54638 | #define PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK 0x18000000L |
|---|
| 54639 | #define PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK 0x20000000L |
|---|
| 54640 | #define PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK 0x40000000L |
|---|
| 54641 | #define PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK 0x80000000L |
|---|
| 54642 | //PCIE_LC_CNTL11 |
|---|
| 54643 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT 0x0 |
|---|
| 54644 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT 0x1 |
|---|
| 54645 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT 0x2 |
|---|
| 54646 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT 0x3 |
|---|
| 54647 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT 0x5 |
|---|
| 54648 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT 0x9 |
|---|
| 54649 | #define PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT 0xd |
|---|
| 54650 | #define PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT 0xe |
|---|
| 54651 | #define PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT 0xf |
|---|
| 54652 | #define PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT 0x10 |
|---|
| 54653 | #define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT 0x11 |
|---|
| 54654 | #define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT 0x12 |
|---|
| 54655 | #define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT 0x13 |
|---|
| 54656 | #define PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT 0x14 |
|---|
| 54657 | #define PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT 0x15 |
|---|
| 54658 | #define PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT 0x16 |
|---|
| 54659 | #define PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT 0x17 |
|---|
| 54660 | #define PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT 0x18 |
|---|
| 54661 | #define PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT 0x1a |
|---|
| 54662 | #define PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT 0x1b |
|---|
| 54663 | #define PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT 0x1c |
|---|
| 54664 | #define PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT 0x1e |
|---|
| 54665 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK 0x00000001L |
|---|
| 54666 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK 0x00000002L |
|---|
| 54667 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK 0x00000004L |
|---|
| 54668 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK 0x00000018L |
|---|
| 54669 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK 0x000001E0L |
|---|
| 54670 | #define PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK 0x00001E00L |
|---|
| 54671 | #define PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK 0x00002000L |
|---|
| 54672 | #define PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK 0x00004000L |
|---|
| 54673 | #define PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK 0x00008000L |
|---|
| 54674 | #define PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK 0x00010000L |
|---|
| 54675 | #define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK 0x00020000L |
|---|
| 54676 | #define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK 0x00040000L |
|---|
| 54677 | #define PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK 0x00080000L |
|---|
| 54678 | #define PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK 0x00100000L |
|---|
| 54679 | #define PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK 0x00200000L |
|---|
| 54680 | #define PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK 0x00400000L |
|---|
| 54681 | #define PCIE_LC_CNTL11__LC_LSLD_EN_MASK 0x00800000L |
|---|
| 54682 | #define PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK 0x03000000L |
|---|
| 54683 | #define PCIE_LC_CNTL11__LC_LSLD_MODE_MASK 0x04000000L |
|---|
| 54684 | #define PCIE_LC_CNTL11__LC_LSLD_DONE_MASK 0x08000000L |
|---|
| 54685 | #define PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK 0x30000000L |
|---|
| 54686 | #define PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK 0xC0000000L |
|---|
| 54687 | //PCIE_LC_CNTL12 |
|---|
| 54688 | #define PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT 0x0 |
|---|
| 54689 | #define PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT 0x1 |
|---|
| 54690 | #define PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT 0x2 |
|---|
| 54691 | #define PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT 0x3 |
|---|
| 54692 | #define PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT 0x4 |
|---|
| 54693 | #define PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK 0x00000001L |
|---|
| 54694 | #define PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK 0x00000002L |
|---|
| 54695 | #define PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK 0x00000004L |
|---|
| 54696 | #define PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK 0x00000008L |
|---|
| 54697 | #define PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK 0x00000010L |
|---|
| 54698 | //PCIE_LC_SAVE_RESTORE_1 |
|---|
| 54699 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT 0x0 |
|---|
| 54700 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT 0x1 |
|---|
| 54701 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT 0x2 |
|---|
| 54702 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT 0xa |
|---|
| 54703 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT 0xb |
|---|
| 54704 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT 0xc |
|---|
| 54705 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT 0xd |
|---|
| 54706 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT 0xe |
|---|
| 54707 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT 0x10 |
|---|
| 54708 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK 0x00000001L |
|---|
| 54709 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK 0x00000002L |
|---|
| 54710 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK 0x000003FCL |
|---|
| 54711 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK 0x00000400L |
|---|
| 54712 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK 0x00000800L |
|---|
| 54713 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK 0x00001000L |
|---|
| 54714 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK 0x00002000L |
|---|
| 54715 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK 0x0000C000L |
|---|
| 54716 | #define PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK 0xFFFF0000L |
|---|
| 54717 | //PCIE_LC_SAVE_RESTORE_2 |
|---|
| 54718 | #define PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT 0x0 |
|---|
| 54719 | #define PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK 0xFFFFFFFFL |
|---|
| 54720 | |
|---|
| 54721 | |
|---|
| 54722 | // addressBlock: nbio_pcie0_pciedir |
|---|
| 54723 | //PCIE_RESERVED |
|---|
| 54724 | #define PCIE_RESERVED__RESERVED__SHIFT 0x0 |
|---|
| 54725 | #define PCIE_RESERVED__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 54726 | //PCIE_SCRATCH |
|---|
| 54727 | #define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 |
|---|
| 54728 | #define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 54729 | //PCIE_RX_NUM_NAK |
|---|
| 54730 | #define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 |
|---|
| 54731 | #define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xFFFFFFFFL |
|---|
| 54732 | //PCIE_RX_NUM_NAK_GENERATED |
|---|
| 54733 | #define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 |
|---|
| 54734 | #define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xFFFFFFFFL |
|---|
| 54735 | //PCIE_CNTL |
|---|
| 54736 | #define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 |
|---|
| 54737 | #define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 |
|---|
| 54738 | #define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 |
|---|
| 54739 | #define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 |
|---|
| 54740 | #define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 |
|---|
| 54741 | #define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa |
|---|
| 54742 | #define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf |
|---|
| 54743 | #define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 |
|---|
| 54744 | #define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 |
|---|
| 54745 | #define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 |
|---|
| 54746 | #define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 |
|---|
| 54747 | #define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 |
|---|
| 54748 | #define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 |
|---|
| 54749 | #define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 |
|---|
| 54750 | #define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 |
|---|
| 54751 | #define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 |
|---|
| 54752 | #define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e |
|---|
| 54753 | #define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f |
|---|
| 54754 | #define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L |
|---|
| 54755 | #define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000EL |
|---|
| 54756 | #define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L |
|---|
| 54757 | #define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L |
|---|
| 54758 | #define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L |
|---|
| 54759 | #define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001C00L |
|---|
| 54760 | #define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L |
|---|
| 54761 | #define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L |
|---|
| 54762 | #define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L |
|---|
| 54763 | #define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L |
|---|
| 54764 | #define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L |
|---|
| 54765 | #define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x00100000L |
|---|
| 54766 | #define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L |
|---|
| 54767 | #define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L |
|---|
| 54768 | #define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L |
|---|
| 54769 | #define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3F000000L |
|---|
| 54770 | #define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L |
|---|
| 54771 | #define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L |
|---|
| 54772 | //PCIE_CONFIG_CNTL |
|---|
| 54773 | #define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 |
|---|
| 54774 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x8 |
|---|
| 54775 | #define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x9 |
|---|
| 54776 | #define PCIE_CONFIG_CNTL__CI_10BIT_TAG_EN_OVERRIDE__SHIFT 0xb |
|---|
| 54777 | #define PCIE_CONFIG_CNTL__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT 0xd |
|---|
| 54778 | #define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 |
|---|
| 54779 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 |
|---|
| 54780 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 |
|---|
| 54781 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 |
|---|
| 54782 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 |
|---|
| 54783 | #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 |
|---|
| 54784 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1b |
|---|
| 54785 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT 0x1c |
|---|
| 54786 | #define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x1e |
|---|
| 54787 | #define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000FL |
|---|
| 54788 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK 0x00000100L |
|---|
| 54789 | #define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK 0x00000600L |
|---|
| 54790 | #define PCIE_CONFIG_CNTL__CI_10BIT_TAG_EN_OVERRIDE_MASK 0x00001800L |
|---|
| 54791 | #define PCIE_CONFIG_CNTL__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK 0x00006000L |
|---|
| 54792 | #define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L |
|---|
| 54793 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000E0000L |
|---|
| 54794 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L |
|---|
| 54795 | #define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00E00000L |
|---|
| 54796 | #define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L |
|---|
| 54797 | #define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L |
|---|
| 54798 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK 0x08000000L |
|---|
| 54799 | #define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK 0x30000000L |
|---|
| 54800 | #define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK 0xC0000000L |
|---|
| 54801 | //PCIE_DEBUG_CNTL |
|---|
| 54802 | #define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 |
|---|
| 54803 | #define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 |
|---|
| 54804 | #define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0x000000FFL |
|---|
| 54805 | #define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x00000100L |
|---|
| 54806 | //PCIE_TX_TRACKING_ADDR_LO |
|---|
| 54807 | #define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT 0x2 |
|---|
| 54808 | #define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 54809 | //PCIE_TX_TRACKING_ADDR_HI |
|---|
| 54810 | #define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT 0x0 |
|---|
| 54811 | #define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 54812 | //PCIE_TX_TRACKING_CTRL_STATUS |
|---|
| 54813 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT 0x0 |
|---|
| 54814 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT 0x1 |
|---|
| 54815 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT 0x8 |
|---|
| 54816 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT 0xf |
|---|
| 54817 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK 0x00000001L |
|---|
| 54818 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK 0x0000000EL |
|---|
| 54819 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK 0x00007F00L |
|---|
| 54820 | #define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK 0x00008000L |
|---|
| 54821 | //PCIE_BW_BY_UNITID |
|---|
| 54822 | #define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN__SHIFT 0x0 |
|---|
| 54823 | #define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID__SHIFT 0x8 |
|---|
| 54824 | #define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN_MASK 0x00000001L |
|---|
| 54825 | #define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_MASK 0x00007F00L |
|---|
| 54826 | //PCIE_CNTL2 |
|---|
| 54827 | #define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 |
|---|
| 54828 | #define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 |
|---|
| 54829 | #define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 |
|---|
| 54830 | #define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb |
|---|
| 54831 | #define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc |
|---|
| 54832 | #define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd |
|---|
| 54833 | #define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe |
|---|
| 54834 | #define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 |
|---|
| 54835 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 |
|---|
| 54836 | #define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 |
|---|
| 54837 | #define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 |
|---|
| 54838 | #define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 |
|---|
| 54839 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 |
|---|
| 54840 | #define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 |
|---|
| 54841 | #define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 |
|---|
| 54842 | #define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 |
|---|
| 54843 | #define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d |
|---|
| 54844 | #define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e |
|---|
| 54845 | #define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f |
|---|
| 54846 | #define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L |
|---|
| 54847 | #define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003EL |
|---|
| 54848 | #define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007C0L |
|---|
| 54849 | #define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x00000800L |
|---|
| 54850 | #define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x00001000L |
|---|
| 54851 | #define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x00002000L |
|---|
| 54852 | #define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x00004000L |
|---|
| 54853 | #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L |
|---|
| 54854 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L |
|---|
| 54855 | #define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x00040000L |
|---|
| 54856 | #define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x00080000L |
|---|
| 54857 | #define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L |
|---|
| 54858 | #define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L |
|---|
| 54859 | #define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x00400000L |
|---|
| 54860 | #define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x00800000L |
|---|
| 54861 | #define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1F000000L |
|---|
| 54862 | #define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000L |
|---|
| 54863 | #define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000L |
|---|
| 54864 | #define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000L |
|---|
| 54865 | //PCIE_RX_CNTL2 |
|---|
| 54866 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 |
|---|
| 54867 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 |
|---|
| 54868 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 |
|---|
| 54869 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 |
|---|
| 54870 | #define 0x4 |
|---|
| 54871 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 |
|---|
| 54872 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 |
|---|
| 54873 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 |
|---|
| 54874 | #define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc |
|---|
| 54875 | #define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd |
|---|
| 54876 | #define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe |
|---|
| 54877 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 |
|---|
| 54878 | #define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c |
|---|
| 54879 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L |
|---|
| 54880 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L |
|---|
| 54881 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L |
|---|
| 54882 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L |
|---|
| 54883 | #define 0x00000010L |
|---|
| 54884 | #define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L |
|---|
| 54885 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x00000100L |
|---|
| 54886 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0x00000E00L |
|---|
| 54887 | #define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x00001000L |
|---|
| 54888 | #define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x00002000L |
|---|
| 54889 | #define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x00004000L |
|---|
| 54890 | #define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x03FF0000L |
|---|
| 54891 | #define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L |
|---|
| 54892 | //PCIE_TX_F0_ATTR_CNTL |
|---|
| 54893 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 |
|---|
| 54894 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 |
|---|
| 54895 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 |
|---|
| 54896 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 |
|---|
| 54897 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 |
|---|
| 54898 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa |
|---|
| 54899 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc |
|---|
| 54900 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x00000003L |
|---|
| 54901 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0x0000000CL |
|---|
| 54902 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x00000030L |
|---|
| 54903 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0x000000C0L |
|---|
| 54904 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x00000300L |
|---|
| 54905 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0x00000C00L |
|---|
| 54906 | #define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x00003000L |
|---|
| 54907 | //PCIE_TX_SWUS_ATTR_CNTL |
|---|
| 54908 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT 0x0 |
|---|
| 54909 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT 0x2 |
|---|
| 54910 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT 0x4 |
|---|
| 54911 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT 0x6 |
|---|
| 54912 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT 0x8 |
|---|
| 54913 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT 0xa |
|---|
| 54914 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT 0xc |
|---|
| 54915 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK 0x00000003L |
|---|
| 54916 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK 0x0000000CL |
|---|
| 54917 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK 0x00000030L |
|---|
| 54918 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK 0x000000C0L |
|---|
| 54919 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK 0x00000300L |
|---|
| 54920 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK 0x00000C00L |
|---|
| 54921 | #define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK 0x00003000L |
|---|
| 54922 | //PCIE_CI_CNTL |
|---|
| 54923 | #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 |
|---|
| 54924 | #define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 |
|---|
| 54925 | #define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 |
|---|
| 54926 | #define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 |
|---|
| 54927 | #define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 |
|---|
| 54928 | #define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 |
|---|
| 54929 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa |
|---|
| 54930 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb |
|---|
| 54931 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc |
|---|
| 54932 | #define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT 0x10 |
|---|
| 54933 | #define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS__SHIFT 0x11 |
|---|
| 54934 | #define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS__SHIFT 0x12 |
|---|
| 54935 | #define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS__SHIFT 0x13 |
|---|
| 54936 | #define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS__SHIFT 0x14 |
|---|
| 54937 | #define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG__SHIFT 0x15 |
|---|
| 54938 | #define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT 0x16 |
|---|
| 54939 | #define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT 0x17 |
|---|
| 54940 | #define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT 0x18 |
|---|
| 54941 | #define PCIE_CI_CNTL__CI_MSTSPLIT_DIS__SHIFT 0x19 |
|---|
| 54942 | #define PCIE_CI_CNTL__CI_MSTSPLIT_REQ_CHAIN_DIS__SHIFT 0x1a |
|---|
| 54943 | #define PCIE_CI_CNTL__TX_MWR_SPLIT_QW_PKT_SAFE_MODE__SHIFT 0x1b |
|---|
| 54944 | #define PCIE_CI_CNTL__CI_MST_TAG_BORROWING_DIS__SHIFT 0x1c |
|---|
| 54945 | #define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN__SHIFT 0x1d |
|---|
| 54946 | #define PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN__SHIFT 0x1e |
|---|
| 54947 | #define PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN__SHIFT 0x1f |
|---|
| 54948 | #define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L |
|---|
| 54949 | #define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x00000008L |
|---|
| 54950 | #define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L |
|---|
| 54951 | #define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000C0L |
|---|
| 54952 | #define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L |
|---|
| 54953 | #define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L |
|---|
| 54954 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L |
|---|
| 54955 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L |
|---|
| 54956 | #define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L |
|---|
| 54957 | #define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK 0x00010000L |
|---|
| 54958 | #define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS_MASK 0x00020000L |
|---|
| 54959 | #define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS_MASK 0x00040000L |
|---|
| 54960 | #define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS_MASK 0x00080000L |
|---|
| 54961 | #define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS_MASK 0x00100000L |
|---|
| 54962 | #define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG_MASK 0x00200000L |
|---|
| 54963 | #define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK 0x00400000L |
|---|
| 54964 | #define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK 0x00800000L |
|---|
| 54965 | #define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK 0x01000000L |
|---|
| 54966 | #define PCIE_CI_CNTL__CI_MSTSPLIT_DIS_MASK 0x02000000L |
|---|
| 54967 | #define PCIE_CI_CNTL__CI_MSTSPLIT_REQ_CHAIN_DIS_MASK 0x04000000L |
|---|
| 54968 | #define PCIE_CI_CNTL__TX_MWR_SPLIT_QW_PKT_SAFE_MODE_MASK 0x08000000L |
|---|
| 54969 | #define PCIE_CI_CNTL__CI_MST_TAG_BORROWING_DIS_MASK 0x10000000L |
|---|
| 54970 | #define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN_MASK 0x20000000L |
|---|
| 54971 | #define PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN_MASK 0x40000000L |
|---|
| 54972 | #define PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN_MASK 0x80000000L |
|---|
| 54973 | //PCIE_BUS_CNTL |
|---|
| 54974 | #define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 |
|---|
| 54975 | #define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 |
|---|
| 54976 | #define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc |
|---|
| 54977 | #define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L |
|---|
| 54978 | #define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L |
|---|
| 54979 | #define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x00001000L |
|---|
| 54980 | //PCIE_LC_STATE6 |
|---|
| 54981 | #define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 |
|---|
| 54982 | #define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 |
|---|
| 54983 | #define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 |
|---|
| 54984 | #define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 |
|---|
| 54985 | #define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003FL |
|---|
| 54986 | #define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003F00L |
|---|
| 54987 | #define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003F0000L |
|---|
| 54988 | #define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3F000000L |
|---|
| 54989 | //PCIE_LC_STATE7 |
|---|
| 54990 | #define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 |
|---|
| 54991 | #define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 |
|---|
| 54992 | #define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 |
|---|
| 54993 | #define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 |
|---|
| 54994 | #define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003FL |
|---|
| 54995 | #define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003F00L |
|---|
| 54996 | #define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003F0000L |
|---|
| 54997 | #define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3F000000L |
|---|
| 54998 | //PCIE_LC_STATE8 |
|---|
| 54999 | #define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 |
|---|
| 55000 | #define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 |
|---|
| 55001 | #define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 |
|---|
| 55002 | #define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 |
|---|
| 55003 | #define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003FL |
|---|
| 55004 | #define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003F00L |
|---|
| 55005 | #define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003F0000L |
|---|
| 55006 | #define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3F000000L |
|---|
| 55007 | //PCIE_LC_STATE9 |
|---|
| 55008 | #define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 |
|---|
| 55009 | #define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 |
|---|
| 55010 | #define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 |
|---|
| 55011 | #define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 |
|---|
| 55012 | #define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003FL |
|---|
| 55013 | #define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003F00L |
|---|
| 55014 | #define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003F0000L |
|---|
| 55015 | #define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3F000000L |
|---|
| 55016 | //PCIE_LC_STATE10 |
|---|
| 55017 | #define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 |
|---|
| 55018 | #define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 |
|---|
| 55019 | #define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 |
|---|
| 55020 | #define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 |
|---|
| 55021 | #define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003FL |
|---|
| 55022 | #define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003F00L |
|---|
| 55023 | #define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003F0000L |
|---|
| 55024 | #define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3F000000L |
|---|
| 55025 | //PCIE_LC_STATE11 |
|---|
| 55026 | #define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 |
|---|
| 55027 | #define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 |
|---|
| 55028 | #define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 |
|---|
| 55029 | #define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 |
|---|
| 55030 | #define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003FL |
|---|
| 55031 | #define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003F00L |
|---|
| 55032 | #define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003F0000L |
|---|
| 55033 | #define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3F000000L |
|---|
| 55034 | //PCIE_LC_STATUS1 |
|---|
| 55035 | #define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 |
|---|
| 55036 | #define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 |
|---|
| 55037 | #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 |
|---|
| 55038 | #define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 |
|---|
| 55039 | #define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L |
|---|
| 55040 | #define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L |
|---|
| 55041 | #define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001CL |
|---|
| 55042 | #define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L |
|---|
| 55043 | //PCIE_LC_STATUS2 |
|---|
| 55044 | #define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 |
|---|
| 55045 | #define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 |
|---|
| 55046 | #define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000FFFFL |
|---|
| 55047 | #define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xFFFF0000L |
|---|
| 55048 | //PCIE_TX_CNTL3 |
|---|
| 55049 | #define PCIE_TX_CNTL3__TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS__SHIFT 0x0 |
|---|
| 55050 | #define PCIE_TX_CNTL3__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE__SHIFT 0x1 |
|---|
| 55051 | #define PCIE_TX_CNTL3__TX_STOP_TLP2_IN_REPLAY_DIS__SHIFT 0x4 |
|---|
| 55052 | #define PCIE_TX_CNTL3__TX_PDAT_CREDIT_RELEASE_FIX_DIS__SHIFT 0x5 |
|---|
| 55053 | #define PCIE_TX_CNTL3__TX_ARB_P_AFTER_NP_EN__SHIFT 0x6 |
|---|
| 55054 | #define PCIE_TX_CNTL3__TX_RBUF_DELAY_2HDR_MWR_EN__SHIFT 0x7 |
|---|
| 55055 | #define PCIE_TX_CNTL3__TX_RBUF_DELAY_MWR_SIZE__SHIFT 0x8 |
|---|
| 55056 | #define PCIE_TX_CNTL3__TX_ATOMIC_ORD_HASH_MODE__SHIFT 0x10 |
|---|
| 55057 | #define PCIE_TX_CNTL3__TX_ENCMSG_HDR_FROM_SDP_REQ_EN__SHIFT 0x13 |
|---|
| 55058 | #define PCIE_TX_CNTL3__TX_DROP_REQ_TARGETING_BAD_PORT_EN__SHIFT 0x14 |
|---|
| 55059 | #define PCIE_TX_CNTL3__MCA_CLKGATE_DIS__SHIFT 0x15 |
|---|
| 55060 | #define PCIE_TX_CNTL3__TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS_MASK 0x00000001L |
|---|
| 55061 | #define PCIE_TX_CNTL3__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE_MASK 0x0000000EL |
|---|
| 55062 | #define PCIE_TX_CNTL3__TX_STOP_TLP2_IN_REPLAY_DIS_MASK 0x00000010L |
|---|
| 55063 | #define PCIE_TX_CNTL3__TX_PDAT_CREDIT_RELEASE_FIX_DIS_MASK 0x00000020L |
|---|
| 55064 | #define PCIE_TX_CNTL3__TX_ARB_P_AFTER_NP_EN_MASK 0x00000040L |
|---|
| 55065 | #define PCIE_TX_CNTL3__TX_RBUF_DELAY_2HDR_MWR_EN_MASK 0x00000080L |
|---|
| 55066 | #define PCIE_TX_CNTL3__TX_RBUF_DELAY_MWR_SIZE_MASK 0x0000FF00L |
|---|
| 55067 | #define PCIE_TX_CNTL3__TX_ATOMIC_ORD_HASH_MODE_MASK 0x00070000L |
|---|
| 55068 | #define PCIE_TX_CNTL3__TX_ENCMSG_HDR_FROM_SDP_REQ_EN_MASK 0x00080000L |
|---|
| 55069 | #define PCIE_TX_CNTL3__TX_DROP_REQ_TARGETING_BAD_PORT_EN_MASK 0x00100000L |
|---|
| 55070 | #define PCIE_TX_CNTL3__MCA_CLKGATE_DIS_MASK 0x00200000L |
|---|
| 55071 | //PCIE_TX_STATUS |
|---|
| 55072 | #define PCIE_TX_STATUS__TX_MST_MEM_READY__SHIFT 0x0 |
|---|
| 55073 | #define PCIE_TX_STATUS__CI_MST_REQ_IDLE__SHIFT 0x1 |
|---|
| 55074 | #define PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD__SHIFT 0x2 |
|---|
| 55075 | #define PCIE_TX_STATUS__CI_MST_WRRSP_IDLE__SHIFT 0x3 |
|---|
| 55076 | #define PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE__SHIFT 0x4 |
|---|
| 55077 | #define PCIE_TX_STATUS__CI_MST_TX_IDLE__SHIFT 0x5 |
|---|
| 55078 | #define PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE__SHIFT 0x6 |
|---|
| 55079 | #define PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE__SHIFT 0x7 |
|---|
| 55080 | #define PCIE_TX_STATUS__TX_P_HDR_EMPTY__SHIFT 0x8 |
|---|
| 55081 | #define PCIE_TX_STATUS__TX_NP_HDR_EMPTY__SHIFT 0x9 |
|---|
| 55082 | #define PCIE_TX_STATUS__TX_P_DAT_EMPTY__SHIFT 0xa |
|---|
| 55083 | #define PCIE_TX_STATUS__TX_NP_DAT_EMPTY__SHIFT 0xb |
|---|
| 55084 | #define PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS__SHIFT 0xc |
|---|
| 55085 | #define PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS__SHIFT 0xd |
|---|
| 55086 | #define PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS__SHIFT 0xe |
|---|
| 55087 | #define PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS__SHIFT 0xf |
|---|
| 55088 | #define PCIE_TX_STATUS__TX_MST_MEM_READY_MASK 0x00000001L |
|---|
| 55089 | #define PCIE_TX_STATUS__CI_MST_REQ_IDLE_MASK 0x00000002L |
|---|
| 55090 | #define PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD_MASK 0x00000004L |
|---|
| 55091 | #define PCIE_TX_STATUS__CI_MST_WRRSP_IDLE_MASK 0x00000008L |
|---|
| 55092 | #define PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE_MASK 0x00000010L |
|---|
| 55093 | #define PCIE_TX_STATUS__CI_MST_TX_IDLE_MASK 0x00000020L |
|---|
| 55094 | #define PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE_MASK 0x00000040L |
|---|
| 55095 | #define PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE_MASK 0x00000080L |
|---|
| 55096 | #define PCIE_TX_STATUS__TX_P_HDR_EMPTY_MASK 0x00000100L |
|---|
| 55097 | #define PCIE_TX_STATUS__TX_NP_HDR_EMPTY_MASK 0x00000200L |
|---|
| 55098 | #define PCIE_TX_STATUS__TX_P_DAT_EMPTY_MASK 0x00000400L |
|---|
| 55099 | #define PCIE_TX_STATUS__TX_NP_DAT_EMPTY_MASK 0x00000800L |
|---|
| 55100 | #define PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS_MASK 0x00001000L |
|---|
| 55101 | #define PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS_MASK 0x00002000L |
|---|
| 55102 | #define PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS_MASK 0x00004000L |
|---|
| 55103 | #define PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS_MASK 0x00008000L |
|---|
| 55104 | //PCIE_WPR_CNTL |
|---|
| 55105 | #define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 |
|---|
| 55106 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 |
|---|
| 55107 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 |
|---|
| 55108 | #define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 |
|---|
| 55109 | #define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 |
|---|
| 55110 | #define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 |
|---|
| 55111 | #define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 |
|---|
| 55112 | #define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L |
|---|
| 55113 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L |
|---|
| 55114 | #define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L |
|---|
| 55115 | #define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L |
|---|
| 55116 | #define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L |
|---|
| 55117 | #define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L |
|---|
| 55118 | #define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L |
|---|
| 55119 | //PCIE_RX_LAST_TLP0 |
|---|
| 55120 | #define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 |
|---|
| 55121 | #define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xFFFFFFFFL |
|---|
| 55122 | //PCIE_RX_LAST_TLP1 |
|---|
| 55123 | #define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 |
|---|
| 55124 | #define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xFFFFFFFFL |
|---|
| 55125 | //PCIE_RX_LAST_TLP2 |
|---|
| 55126 | #define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 |
|---|
| 55127 | #define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xFFFFFFFFL |
|---|
| 55128 | //PCIE_RX_LAST_TLP3 |
|---|
| 55129 | #define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 |
|---|
| 55130 | #define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xFFFFFFFFL |
|---|
| 55131 | //PCIE_TX_LAST_TLP0 |
|---|
| 55132 | #define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 |
|---|
| 55133 | #define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xFFFFFFFFL |
|---|
| 55134 | //PCIE_TX_LAST_TLP1 |
|---|
| 55135 | #define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 |
|---|
| 55136 | #define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xFFFFFFFFL |
|---|
| 55137 | //PCIE_TX_LAST_TLP2 |
|---|
| 55138 | #define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 |
|---|
| 55139 | #define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xFFFFFFFFL |
|---|
| 55140 | //PCIE_TX_LAST_TLP3 |
|---|
| 55141 | #define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 |
|---|
| 55142 | #define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xFFFFFFFFL |
|---|
| 55143 | //PCIE_I2C_REG_ADDR_EXPAND |
|---|
| 55144 | #define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 |
|---|
| 55145 | #define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001FFFFL |
|---|
| 55146 | //PCIE_I2C_REG_DATA |
|---|
| 55147 | #define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 |
|---|
| 55148 | #define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xFFFFFFFFL |
|---|
| 55149 | //PCIE_CFG_CNTL |
|---|
| 55150 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 |
|---|
| 55151 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 |
|---|
| 55152 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 |
|---|
| 55153 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L |
|---|
| 55154 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L |
|---|
| 55155 | #define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L |
|---|
| 55156 | //PCIE_LC_PM_CNTL |
|---|
| 55157 | #define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT 0x0 |
|---|
| 55158 | #define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT 0x4 |
|---|
| 55159 | #define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT 0x8 |
|---|
| 55160 | #define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT 0xc |
|---|
| 55161 | #define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT 0x10 |
|---|
| 55162 | #define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT 0x14 |
|---|
| 55163 | #define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT 0x18 |
|---|
| 55164 | #define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT 0x1c |
|---|
| 55165 | #define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK 0x0000000FL |
|---|
| 55166 | #define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK 0x000000F0L |
|---|
| 55167 | #define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK 0x00000F00L |
|---|
| 55168 | #define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK 0x0000F000L |
|---|
| 55169 | #define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK 0x000F0000L |
|---|
| 55170 | #define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK 0x00F00000L |
|---|
| 55171 | #define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK 0x0F000000L |
|---|
| 55172 | #define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK 0xF0000000L |
|---|
| 55173 | //PCIE_LC_PORT_ORDER_CNTL |
|---|
| 55174 | #define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN__SHIFT 0x0 |
|---|
| 55175 | #define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN_MASK 0x00000001L |
|---|
| 55176 | //PCIE_P_CNTL |
|---|
| 55177 | #define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 |
|---|
| 55178 | #define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 |
|---|
| 55179 | #define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 |
|---|
| 55180 | #define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 |
|---|
| 55181 | #define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 |
|---|
| 55182 | #define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 |
|---|
| 55183 | #define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 |
|---|
| 55184 | #define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc |
|---|
| 55185 | #define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd |
|---|
| 55186 | #define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe |
|---|
| 55187 | #define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 |
|---|
| 55188 | #define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT 0x11 |
|---|
| 55189 | #define PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT__SHIFT 0x12 |
|---|
| 55190 | #define PCIE_P_CNTL__MASTER_PLL_LANE_NUM__SHIFT 0x13 |
|---|
| 55191 | #define PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN__SHIFT 0x17 |
|---|
| 55192 | #define PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL__SHIFT 0x18 |
|---|
| 55193 | #define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L |
|---|
| 55194 | #define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L |
|---|
| 55195 | #define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L |
|---|
| 55196 | #define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L |
|---|
| 55197 | #define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L |
|---|
| 55198 | #define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L |
|---|
| 55199 | #define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L |
|---|
| 55200 | #define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L |
|---|
| 55201 | #define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L |
|---|
| 55202 | #define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000C000L |
|---|
| 55203 | #define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x00010000L |
|---|
| 55204 | #define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK 0x00020000L |
|---|
| 55205 | #define PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT_MASK 0x00040000L |
|---|
| 55206 | #define PCIE_P_CNTL__MASTER_PLL_LANE_NUM_MASK 0x00780000L |
|---|
| 55207 | #define PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN_MASK 0x00800000L |
|---|
| 55208 | #define PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL_MASK 0x01000000L |
|---|
| 55209 | //PCIE_P_BUF_STATUS |
|---|
| 55210 | #define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 |
|---|
| 55211 | #define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 |
|---|
| 55212 | #define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000FFFFL |
|---|
| 55213 | #define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xFFFF0000L |
|---|
| 55214 | //PCIE_P_DECODER_STATUS |
|---|
| 55215 | #define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 |
|---|
| 55216 | #define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000FFFFL |
|---|
| 55217 | //PCIE_P_MISC_STATUS |
|---|
| 55218 | #define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 |
|---|
| 55219 | #define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 |
|---|
| 55220 | #define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000000FFL |
|---|
| 55221 | #define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xFFFF0000L |
|---|
| 55222 | //PCIE_P_RCV_L0S_FTS_DET |
|---|
| 55223 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 |
|---|
| 55224 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 |
|---|
| 55225 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000FFL |
|---|
| 55226 | #define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000FF00L |
|---|
| 55227 | //PCIE_RX_AD |
|---|
| 55228 | #define PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT 0x0 |
|---|
| 55229 | #define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT 0x1 |
|---|
| 55230 | #define PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT 0x2 |
|---|
| 55231 | #define PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT 0x3 |
|---|
| 55232 | #define PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT 0x4 |
|---|
| 55233 | #define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT 0x5 |
|---|
| 55234 | #define PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT 0x8 |
|---|
| 55235 | #define PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT 0x9 |
|---|
| 55236 | #define PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT 0xa |
|---|
| 55237 | #define PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT 0xb |
|---|
| 55238 | #define PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT 0xc |
|---|
| 55239 | #define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT 0xd |
|---|
| 55240 | #define PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT 0xe |
|---|
| 55241 | #define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT 0xf |
|---|
| 55242 | #define PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN__SHIFT 0x10 |
|---|
| 55243 | #define PCIE_RX_AD__RX_RC_UR_POIS_ATOP__SHIFT 0x11 |
|---|
| 55244 | #define PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK 0x00000001L |
|---|
| 55245 | #define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK 0x00000002L |
|---|
| 55246 | #define PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK 0x00000004L |
|---|
| 55247 | #define PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK 0x00000008L |
|---|
| 55248 | #define PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK 0x00000010L |
|---|
| 55249 | #define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK 0x00000020L |
|---|
| 55250 | #define PCIE_RX_AD__RX_RC_DROP_VDM0_MASK 0x00000100L |
|---|
| 55251 | #define PCIE_RX_AD__RX_RC_UR_VDM0_MASK 0x00000200L |
|---|
| 55252 | #define PCIE_RX_AD__RX_RC_DROP_VDM1_MASK 0x00000400L |
|---|
| 55253 | #define PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK 0x00000800L |
|---|
| 55254 | #define PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK 0x00001000L |
|---|
| 55255 | #define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK 0x00002000L |
|---|
| 55256 | #define PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK 0x00004000L |
|---|
| 55257 | #define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK 0x00008000L |
|---|
| 55258 | #define PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN_MASK 0x00010000L |
|---|
| 55259 | #define PCIE_RX_AD__RX_RC_UR_POIS_ATOP_MASK 0x00020000L |
|---|
| 55260 | //PCIE_SDP_CTRL |
|---|
| 55261 | #define PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT 0x0 |
|---|
| 55262 | #define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT 0x4 |
|---|
| 55263 | #define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT 0x5 |
|---|
| 55264 | #define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE__SHIFT 0x6 |
|---|
| 55265 | #define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS__SHIFT 0x7 |
|---|
| 55266 | #define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS__SHIFT 0x8 |
|---|
| 55267 | #define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT 0x9 |
|---|
| 55268 | #define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT 0xa |
|---|
| 55269 | #define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT 0xb |
|---|
| 55270 | #define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT 0xc |
|---|
| 55271 | #define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN__SHIFT 0xd |
|---|
| 55272 | #define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL__SHIFT 0xe |
|---|
| 55273 | #define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT 0xf |
|---|
| 55274 | #define PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN__SHIFT 0x10 |
|---|
| 55275 | #define PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN__SHIFT 0x11 |
|---|
| 55276 | #define PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN__SHIFT 0x12 |
|---|
| 55277 | #define PCIE_SDP_CTRL__TX_ENCMSG_USE_SDP_EP_DIS__SHIFT 0x13 |
|---|
| 55278 | #define PCIE_SDP_CTRL__TX_IGNORE_POISON_BIT_EN__SHIFT 0x14 |
|---|
| 55279 | #define PCIE_SDP_CTRL__TX_RBUF_WRITE_2HDR_DIS__SHIFT 0x15 |
|---|
| 55280 | #define PCIE_SDP_CTRL__TX_RBUF_READ_2HDR_DIS__SHIFT 0x16 |
|---|
| 55281 | #define PCIE_SDP_CTRL__TX_RBUF_END_TLP2_DIS__SHIFT 0x17 |
|---|
| 55282 | #define PCIE_SDP_CTRL__TX_MULTICYCLE_DLLP_DIS__SHIFT 0x18 |
|---|
| 55283 | #define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE__SHIFT 0x19 |
|---|
| 55284 | #define PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER__SHIFT 0x1a |
|---|
| 55285 | #define PCIE_SDP_CTRL__SDP_UNIT_ID_MASK 0x0000000FL |
|---|
| 55286 | #define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK 0x00000010L |
|---|
| 55287 | #define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK 0x00000020L |
|---|
| 55288 | #define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE_MASK 0x00000040L |
|---|
| 55289 | #define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS_MASK 0x00000080L |
|---|
| 55290 | #define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS_MASK 0x00000100L |
|---|
| 55291 | #define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK 0x00000200L |
|---|
| 55292 | #define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK 0x00000400L |
|---|
| 55293 | #define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK 0x00000800L |
|---|
| 55294 | #define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK 0x00001000L |
|---|
| 55295 | #define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN_MASK 0x00002000L |
|---|
| 55296 | #define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL_MASK 0x00004000L |
|---|
| 55297 | #define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK 0x00008000L |
|---|
| 55298 | #define PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN_MASK 0x00010000L |
|---|
| 55299 | #define PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN_MASK 0x00020000L |
|---|
| 55300 | #define PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN_MASK 0x00040000L |
|---|
| 55301 | #define PCIE_SDP_CTRL__TX_ENCMSG_USE_SDP_EP_DIS_MASK 0x00080000L |
|---|
| 55302 | #define PCIE_SDP_CTRL__TX_IGNORE_POISON_BIT_EN_MASK 0x00100000L |
|---|
| 55303 | #define PCIE_SDP_CTRL__TX_RBUF_WRITE_2HDR_DIS_MASK 0x00200000L |
|---|
| 55304 | #define PCIE_SDP_CTRL__TX_RBUF_READ_2HDR_DIS_MASK 0x00400000L |
|---|
| 55305 | #define PCIE_SDP_CTRL__TX_RBUF_END_TLP2_DIS_MASK 0x00800000L |
|---|
| 55306 | #define PCIE_SDP_CTRL__TX_MULTICYCLE_DLLP_DIS_MASK 0x01000000L |
|---|
| 55307 | #define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE_MASK 0x02000000L |
|---|
| 55308 | #define PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER_MASK 0x1C000000L |
|---|
| 55309 | //PCIE_SDP_SWUS_SLV_ATTR_CTRL |
|---|
| 55310 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0 |
|---|
| 55311 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2 |
|---|
| 55312 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4 |
|---|
| 55313 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6 |
|---|
| 55314 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8 |
|---|
| 55315 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa |
|---|
| 55316 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc |
|---|
| 55317 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe |
|---|
| 55318 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10 |
|---|
| 55319 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L |
|---|
| 55320 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL |
|---|
| 55321 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L |
|---|
| 55322 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L |
|---|
| 55323 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L |
|---|
| 55324 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L |
|---|
| 55325 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L |
|---|
| 55326 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L |
|---|
| 55327 | #define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L |
|---|
| 55328 | //PCIE_PERF_COUNT_CNTL |
|---|
| 55329 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 |
|---|
| 55330 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 |
|---|
| 55331 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 |
|---|
| 55332 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L |
|---|
| 55333 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L |
|---|
| 55334 | #define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L |
|---|
| 55335 | //PCIE_PERF_CNTL_TXCLK1 |
|---|
| 55336 | #define PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL__SHIFT 0x0 |
|---|
| 55337 | #define PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL__SHIFT 0x8 |
|---|
| 55338 | #define PCIE_PERF_CNTL_TXCLK1__COUNTER0_UPPER__SHIFT 0x10 |
|---|
| 55339 | #define PCIE_PERF_CNTL_TXCLK1__COUNTER1_UPPER__SHIFT 0x18 |
|---|
| 55340 | #define PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL_MASK 0x000000FFL |
|---|
| 55341 | #define PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL_MASK 0x0000FF00L |
|---|
| 55342 | #define PCIE_PERF_CNTL_TXCLK1__COUNTER0_UPPER_MASK 0x00FF0000L |
|---|
| 55343 | #define PCIE_PERF_CNTL_TXCLK1__COUNTER1_UPPER_MASK 0xFF000000L |
|---|
| 55344 | //PCIE_PERF_COUNT0_TXCLK1 |
|---|
| 55345 | #define PCIE_PERF_COUNT0_TXCLK1__COUNTER0__SHIFT 0x0 |
|---|
| 55346 | #define PCIE_PERF_COUNT0_TXCLK1__COUNTER0_MASK 0xFFFFFFFFL |
|---|
| 55347 | //PCIE_PERF_COUNT1_TXCLK1 |
|---|
| 55348 | #define PCIE_PERF_COUNT1_TXCLK1__COUNTER1__SHIFT 0x0 |
|---|
| 55349 | #define PCIE_PERF_COUNT1_TXCLK1__COUNTER1_MASK 0xFFFFFFFFL |
|---|
| 55350 | //PCIE_PERF_CNTL_TXCLK2 |
|---|
| 55351 | #define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 |
|---|
| 55352 | #define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 |
|---|
| 55353 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 |
|---|
| 55354 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 |
|---|
| 55355 | #define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000FFL |
|---|
| 55356 | #define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000FF00L |
|---|
| 55357 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00FF0000L |
|---|
| 55358 | #define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xFF000000L |
|---|
| 55359 | //PCIE_PERF_COUNT0_TXCLK2 |
|---|
| 55360 | #define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 |
|---|
| 55361 | #define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xFFFFFFFFL |
|---|
| 55362 | //PCIE_PERF_COUNT1_TXCLK2 |
|---|
| 55363 | #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 |
|---|
| 55364 | #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL |
|---|
| 55365 | //PCIE_PERF_CNTL_TXCLK3 |
|---|
| 55366 | #define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT 0x0 |
|---|
| 55367 | #define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT 0x8 |
|---|
| 55368 | #define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT 0x10 |
|---|
| 55369 | #define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT 0x18 |
|---|
| 55370 | #define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK 0x000000FFL |
|---|
| 55371 | #define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK 0x0000FF00L |
|---|
| 55372 | #define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK 0x00FF0000L |
|---|
| 55373 | #define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK 0xFF000000L |
|---|
| 55374 | //PCIE_PERF_COUNT0_TXCLK3 |
|---|
| 55375 | #define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT 0x0 |
|---|
| 55376 | #define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK 0xFFFFFFFFL |
|---|
| 55377 | //PCIE_PERF_COUNT1_TXCLK3 |
|---|
| 55378 | #define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT 0x0 |
|---|
| 55379 | #define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK 0xFFFFFFFFL |
|---|
| 55380 | //PCIE_PERF_CNTL_TXCLK4 |
|---|
| 55381 | #define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT 0x0 |
|---|
| 55382 | #define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT 0x8 |
|---|
| 55383 | #define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT 0x10 |
|---|
| 55384 | #define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT 0x18 |
|---|
| 55385 | #define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK 0x000000FFL |
|---|
| 55386 | #define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK 0x0000FF00L |
|---|
| 55387 | #define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK 0x00FF0000L |
|---|
| 55388 | #define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK 0xFF000000L |
|---|
| 55389 | //PCIE_PERF_COUNT0_TXCLK4 |
|---|
| 55390 | #define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT 0x0 |
|---|
| 55391 | #define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK 0xFFFFFFFFL |
|---|
| 55392 | //PCIE_PERF_COUNT1_TXCLK4 |
|---|
| 55393 | #define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT 0x0 |
|---|
| 55394 | #define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK 0xFFFFFFFFL |
|---|
| 55395 | //PCIE_PERF_CNTL_SCLK1 |
|---|
| 55396 | #define PCIE_PERF_CNTL_SCLK1__EVENT0_SEL__SHIFT 0x0 |
|---|
| 55397 | #define PCIE_PERF_CNTL_SCLK1__EVENT1_SEL__SHIFT 0x8 |
|---|
| 55398 | #define PCIE_PERF_CNTL_SCLK1__COUNTER0_UPPER__SHIFT 0x10 |
|---|
| 55399 | #define PCIE_PERF_CNTL_SCLK1__COUNTER1_UPPER__SHIFT 0x18 |
|---|
| 55400 | #define PCIE_PERF_CNTL_SCLK1__EVENT0_SEL_MASK 0x000000FFL |
|---|
| 55401 | #define PCIE_PERF_CNTL_SCLK1__EVENT1_SEL_MASK 0x0000FF00L |
|---|
| 55402 | #define PCIE_PERF_CNTL_SCLK1__COUNTER0_UPPER_MASK 0x00FF0000L |
|---|
| 55403 | #define PCIE_PERF_CNTL_SCLK1__COUNTER1_UPPER_MASK 0xFF000000L |
|---|
| 55404 | //PCIE_PERF_COUNT0_SCLK1 |
|---|
| 55405 | #define PCIE_PERF_COUNT0_SCLK1__COUNTER0__SHIFT 0x0 |
|---|
| 55406 | #define PCIE_PERF_COUNT0_SCLK1__COUNTER0_MASK 0xFFFFFFFFL |
|---|
| 55407 | //PCIE_PERF_COUNT1_SCLK1 |
|---|
| 55408 | #define PCIE_PERF_COUNT1_SCLK1__COUNTER1__SHIFT 0x0 |
|---|
| 55409 | #define PCIE_PERF_COUNT1_SCLK1__COUNTER1_MASK 0xFFFFFFFFL |
|---|
| 55410 | //PCIE_PERF_CNTL_SCLK2 |
|---|
| 55411 | #define PCIE_PERF_CNTL_SCLK2__EVENT0_SEL__SHIFT 0x0 |
|---|
| 55412 | #define PCIE_PERF_CNTL_SCLK2__EVENT1_SEL__SHIFT 0x8 |
|---|
| 55413 | #define PCIE_PERF_CNTL_SCLK2__COUNTER0_UPPER__SHIFT 0x10 |
|---|
| 55414 | #define PCIE_PERF_CNTL_SCLK2__COUNTER1_UPPER__SHIFT 0x18 |
|---|
| 55415 | #define PCIE_PERF_CNTL_SCLK2__EVENT0_SEL_MASK 0x000000FFL |
|---|
| 55416 | #define PCIE_PERF_CNTL_SCLK2__EVENT1_SEL_MASK 0x0000FF00L |
|---|
| 55417 | #define PCIE_PERF_CNTL_SCLK2__COUNTER0_UPPER_MASK 0x00FF0000L |
|---|
| 55418 | #define PCIE_PERF_CNTL_SCLK2__COUNTER1_UPPER_MASK 0xFF000000L |
|---|
| 55419 | //PCIE_PERF_COUNT0_SCLK2 |
|---|
| 55420 | #define PCIE_PERF_COUNT0_SCLK2__COUNTER0__SHIFT 0x0 |
|---|
| 55421 | #define PCIE_PERF_COUNT0_SCLK2__COUNTER0_MASK 0xFFFFFFFFL |
|---|
| 55422 | //PCIE_PERF_COUNT1_SCLK2 |
|---|
| 55423 | #define PCIE_PERF_COUNT1_SCLK2__COUNTER1__SHIFT 0x0 |
|---|
| 55424 | #define PCIE_PERF_COUNT1_SCLK2__COUNTER1_MASK 0xFFFFFFFFL |
|---|
| 55425 | //PCIE_PERF_CNTL_EVENT_LC_PORT_SEL |
|---|
| 55426 | #define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1__SHIFT 0x0 |
|---|
| 55427 | #define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1__SHIFT 0x4 |
|---|
| 55428 | #define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x8 |
|---|
| 55429 | #define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0xc |
|---|
| 55430 | #define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1_MASK 0x0000000FL |
|---|
| 55431 | #define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1_MASK 0x000000F0L |
|---|
| 55432 | #define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x00000F00L |
|---|
| 55433 | #define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0000F000L |
|---|
| 55434 | //PCIE_PERF_CNTL_EVENT_CI_PORT_SEL |
|---|
| 55435 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3__SHIFT 0x0 |
|---|
| 55436 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3__SHIFT 0x4 |
|---|
| 55437 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4__SHIFT 0x8 |
|---|
| 55438 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4__SHIFT 0xc |
|---|
| 55439 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK1__SHIFT 0x10 |
|---|
| 55440 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK1__SHIFT 0x14 |
|---|
| 55441 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK2__SHIFT 0x18 |
|---|
| 55442 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK2__SHIFT 0x1c |
|---|
| 55443 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3_MASK 0x0000000FL |
|---|
| 55444 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3_MASK 0x000000F0L |
|---|
| 55445 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4_MASK 0x00000F00L |
|---|
| 55446 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4_MASK 0x0000F000L |
|---|
| 55447 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK1_MASK 0x000F0000L |
|---|
| 55448 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK1_MASK 0x00F00000L |
|---|
| 55449 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK2_MASK 0x0F000000L |
|---|
| 55450 | #define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK2_MASK 0xF0000000L |
|---|
| 55451 | //PCIE_HIP_REG0 |
|---|
| 55452 | #define PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI__SHIFT 0x0 |
|---|
| 55453 | #define PCIE_HIP_REG0__CI_HIP_APT0_ENABLE__SHIFT 0x18 |
|---|
| 55454 | #define PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE__SHIFT 0x19 |
|---|
| 55455 | #define PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE__SHIFT 0x1a |
|---|
| 55456 | #define PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE__SHIFT 0x1d |
|---|
| 55457 | #define PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI_MASK 0x000FFFFFL |
|---|
| 55458 | #define PCIE_HIP_REG0__CI_HIP_APT0_ENABLE_MASK 0x01000000L |
|---|
| 55459 | #define PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE_MASK 0x02000000L |
|---|
| 55460 | #define PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE_MASK 0x1C000000L |
|---|
| 55461 | #define PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE_MASK 0x60000000L |
|---|
| 55462 | //PCIE_HIP_REG1 |
|---|
| 55463 | #define PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO__SHIFT 0x0 |
|---|
| 55464 | #define PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO_MASK 0xFFFFFFFFL |
|---|
| 55465 | //PCIE_HIP_REG2 |
|---|
| 55466 | #define PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI__SHIFT 0x0 |
|---|
| 55467 | #define PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI_MASK 0x000FFFFFL |
|---|
| 55468 | //PCIE_HIP_REG3 |
|---|
| 55469 | #define PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO__SHIFT 0x0 |
|---|
| 55470 | #define PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO_MASK 0xFFFFFFFFL |
|---|
| 55471 | //PCIE_HIP_REG4 |
|---|
| 55472 | #define PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI__SHIFT 0x0 |
|---|
| 55473 | #define PCIE_HIP_REG4__CI_HIP_APT1_ENABLE__SHIFT 0x18 |
|---|
| 55474 | #define PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE__SHIFT 0x19 |
|---|
| 55475 | #define PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE__SHIFT 0x1a |
|---|
| 55476 | #define PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE__SHIFT 0x1d |
|---|
| 55477 | #define PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI_MASK 0x000FFFFFL |
|---|
| 55478 | #define PCIE_HIP_REG4__CI_HIP_APT1_ENABLE_MASK 0x01000000L |
|---|
| 55479 | #define PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE_MASK 0x02000000L |
|---|
| 55480 | #define PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE_MASK 0x1C000000L |
|---|
| 55481 | #define PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE_MASK 0x60000000L |
|---|
| 55482 | //PCIE_HIP_REG5 |
|---|
| 55483 | #define PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO__SHIFT 0x0 |
|---|
| 55484 | #define PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO_MASK 0xFFFFFFFFL |
|---|
| 55485 | //PCIE_HIP_REG6 |
|---|
| 55486 | #define PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI__SHIFT 0x0 |
|---|
| 55487 | #define PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI_MASK 0x000FFFFFL |
|---|
| 55488 | //PCIE_HIP_REG7 |
|---|
| 55489 | #define PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO__SHIFT 0x0 |
|---|
| 55490 | #define PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO_MASK 0xFFFFFFFFL |
|---|
| 55491 | //PCIE_HIP_REG8 |
|---|
| 55492 | #define PCIE_HIP_REG8__CI_HIP_MASK__SHIFT 0x0 |
|---|
| 55493 | #define PCIE_HIP_REG8__CI_HIP_MASK_MASK 0x000FFFFFL |
|---|
| 55494 | //PCIE_STRAP_F0 |
|---|
| 55495 | #define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 |
|---|
| 55496 | #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 |
|---|
| 55497 | #define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 |
|---|
| 55498 | #define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 |
|---|
| 55499 | #define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 |
|---|
| 55500 | #define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 |
|---|
| 55501 | #define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 |
|---|
| 55502 | #define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 |
|---|
| 55503 | #define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 |
|---|
| 55504 | #define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 |
|---|
| 55505 | #define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa |
|---|
| 55506 | #define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb |
|---|
| 55507 | #define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc |
|---|
| 55508 | #define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd |
|---|
| 55509 | #define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe |
|---|
| 55510 | #define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf |
|---|
| 55511 | #define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 |
|---|
| 55512 | #define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 |
|---|
| 55513 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12 |
|---|
| 55514 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13 |
|---|
| 55515 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14 |
|---|
| 55516 | #define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 |
|---|
| 55517 | #define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18 |
|---|
| 55518 | #define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b |
|---|
| 55519 | #define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c |
|---|
| 55520 | #define PCIE_STRAP_F0__STRAP_SWUS_ARI_EN__SHIFT 0x1d |
|---|
| 55521 | #define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e |
|---|
| 55522 | #define PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN__SHIFT 0x1f |
|---|
| 55523 | #define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L |
|---|
| 55524 | #define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L |
|---|
| 55525 | #define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x00000004L |
|---|
| 55526 | #define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x00000008L |
|---|
| 55527 | #define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x00000010L |
|---|
| 55528 | #define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x00000020L |
|---|
| 55529 | #define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x00000040L |
|---|
| 55530 | #define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x00000080L |
|---|
| 55531 | #define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x00000100L |
|---|
| 55532 | #define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x00000200L |
|---|
| 55533 | #define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x00000400L |
|---|
| 55534 | #define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x00000800L |
|---|
| 55535 | #define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x00001000L |
|---|
| 55536 | #define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x00002000L |
|---|
| 55537 | #define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x00004000L |
|---|
| 55538 | #define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x00008000L |
|---|
| 55539 | #define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x00010000L |
|---|
| 55540 | #define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L |
|---|
| 55541 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x00040000L |
|---|
| 55542 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x00080000L |
|---|
| 55543 | #define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x00100000L |
|---|
| 55544 | #define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L |
|---|
| 55545 | #define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x07000000L |
|---|
| 55546 | #define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x08000000L |
|---|
| 55547 | #define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000L |
|---|
| 55548 | #define PCIE_STRAP_F0__STRAP_SWUS_ARI_EN_MASK 0x20000000L |
|---|
| 55549 | #define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000L |
|---|
| 55550 | #define PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN_MASK 0x80000000L |
|---|
| 55551 | //PCIE_STRAP_MISC |
|---|
| 55552 | #define PCIE_STRAP_MISC__STRAP_DLF_EN__SHIFT 0x0 |
|---|
| 55553 | #define PCIE_STRAP_MISC__STRAP_16GT_EN__SHIFT 0x1 |
|---|
| 55554 | #define PCIE_STRAP_MISC__STRAP_MARGINING_EN__SHIFT 0x2 |
|---|
| 55555 | #define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 |
|---|
| 55556 | #define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER__SHIFT 0x6 |
|---|
| 55557 | #define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 |
|---|
| 55558 | #define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a |
|---|
| 55559 | #define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c |
|---|
| 55560 | #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d |
|---|
| 55561 | #define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f |
|---|
| 55562 | #define PCIE_STRAP_MISC__STRAP_DLF_EN_MASK 0x00000001L |
|---|
| 55563 | #define PCIE_STRAP_MISC__STRAP_16GT_EN_MASK 0x00000002L |
|---|
| 55564 | #define PCIE_STRAP_MISC__STRAP_MARGINING_EN_MASK 0x00000004L |
|---|
| 55565 | #define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x00000010L |
|---|
| 55566 | #define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER_MASK 0x00000040L |
|---|
| 55567 | #define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L |
|---|
| 55568 | #define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x04000000L |
|---|
| 55569 | #define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000L |
|---|
| 55570 | #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L |
|---|
| 55571 | #define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000L |
|---|
| 55572 | //PCIE_STRAP_MISC2 |
|---|
| 55573 | #define PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0 |
|---|
| 55574 | #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 |
|---|
| 55575 | #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 |
|---|
| 55576 | #define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 |
|---|
| 55577 | #define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 |
|---|
| 55578 | #define PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE__SHIFT 0x5 |
|---|
| 55579 | #define PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x00000001L |
|---|
| 55580 | #define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x00000002L |
|---|
| 55581 | #define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L |
|---|
| 55582 | #define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x00000008L |
|---|
| 55583 | #define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L |
|---|
| 55584 | #define PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE_MASK 0x00000020L |
|---|
| 55585 | //PCIE_STRAP_PI |
|---|
| 55586 | #define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 |
|---|
| 55587 | #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c |
|---|
| 55588 | #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d |
|---|
| 55589 | #define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x00000001L |
|---|
| 55590 | #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000L |
|---|
| 55591 | #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000L |
|---|
| 55592 | //PCIE_STRAP_I2C_BD |
|---|
| 55593 | #define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 |
|---|
| 55594 | #define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 |
|---|
| 55595 | #define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x0000007FL |
|---|
| 55596 | #define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x00000080L |
|---|
| 55597 | //PCIE_PRBS_CLR |
|---|
| 55598 | #define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 |
|---|
| 55599 | #define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 |
|---|
| 55600 | #define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 |
|---|
| 55601 | #define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000FFFFL |
|---|
| 55602 | #define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0x000F0000L |
|---|
| 55603 | #define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x01000000L |
|---|
| 55604 | //PCIE_PRBS_STATUS1 |
|---|
| 55605 | #define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 |
|---|
| 55606 | #define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 |
|---|
| 55607 | #define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000FFFFL |
|---|
| 55608 | #define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xFFFF0000L |
|---|
| 55609 | //PCIE_PRBS_STATUS2 |
|---|
| 55610 | #define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 |
|---|
| 55611 | #define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000FFFFL |
|---|
| 55612 | //PCIE_PRBS_FREERUN |
|---|
| 55613 | #define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 |
|---|
| 55614 | #define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000FFFFL |
|---|
| 55615 | //PCIE_PRBS_MISC |
|---|
| 55616 | #define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 |
|---|
| 55617 | #define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 |
|---|
| 55618 | #define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 |
|---|
| 55619 | #define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 |
|---|
| 55620 | #define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 |
|---|
| 55621 | #define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 |
|---|
| 55622 | #define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe |
|---|
| 55623 | #define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 |
|---|
| 55624 | #define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L |
|---|
| 55625 | #define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x0000000EL |
|---|
| 55626 | #define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000010L |
|---|
| 55627 | #define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000020L |
|---|
| 55628 | #define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x000000C0L |
|---|
| 55629 | #define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00001F00L |
|---|
| 55630 | #define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000C000L |
|---|
| 55631 | #define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xFFFF0000L |
|---|
| 55632 | //PCIE_PRBS_USER_PATTERN |
|---|
| 55633 | #define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 |
|---|
| 55634 | #define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3FFFFFFFL |
|---|
| 55635 | //PCIE_PRBS_LO_BITCNT |
|---|
| 55636 | #define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 |
|---|
| 55637 | #define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xFFFFFFFFL |
|---|
| 55638 | //PCIE_PRBS_HI_BITCNT |
|---|
| 55639 | #define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 |
|---|
| 55640 | #define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000FFL |
|---|
| 55641 | //PCIE_PRBS_ERRCNT_0 |
|---|
| 55642 | #define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 |
|---|
| 55643 | #define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xFFFFFFFFL |
|---|
| 55644 | //PCIE_PRBS_ERRCNT_1 |
|---|
| 55645 | #define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 |
|---|
| 55646 | #define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xFFFFFFFFL |
|---|
| 55647 | //PCIE_PRBS_ERRCNT_2 |
|---|
| 55648 | #define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 |
|---|
| 55649 | #define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xFFFFFFFFL |
|---|
| 55650 | //PCIE_PRBS_ERRCNT_3 |
|---|
| 55651 | #define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 |
|---|
| 55652 | #define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xFFFFFFFFL |
|---|
| 55653 | //PCIE_PRBS_ERRCNT_4 |
|---|
| 55654 | #define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 |
|---|
| 55655 | #define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xFFFFFFFFL |
|---|
| 55656 | //PCIE_PRBS_ERRCNT_5 |
|---|
| 55657 | #define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 |
|---|
| 55658 | #define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xFFFFFFFFL |
|---|
| 55659 | //PCIE_PRBS_ERRCNT_6 |
|---|
| 55660 | #define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 |
|---|
| 55661 | #define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xFFFFFFFFL |
|---|
| 55662 | //PCIE_PRBS_ERRCNT_7 |
|---|
| 55663 | #define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 |
|---|
| 55664 | #define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xFFFFFFFFL |
|---|
| 55665 | //PCIE_PRBS_ERRCNT_8 |
|---|
| 55666 | #define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 |
|---|
| 55667 | #define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xFFFFFFFFL |
|---|
| 55668 | //PCIE_PRBS_ERRCNT_9 |
|---|
| 55669 | #define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 |
|---|
| 55670 | #define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xFFFFFFFFL |
|---|
| 55671 | //PCIE_PRBS_ERRCNT_10 |
|---|
| 55672 | #define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 |
|---|
| 55673 | #define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xFFFFFFFFL |
|---|
| 55674 | //PCIE_PRBS_ERRCNT_11 |
|---|
| 55675 | #define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 |
|---|
| 55676 | #define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xFFFFFFFFL |
|---|
| 55677 | //PCIE_PRBS_ERRCNT_12 |
|---|
| 55678 | #define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 |
|---|
| 55679 | #define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xFFFFFFFFL |
|---|
| 55680 | //PCIE_PRBS_ERRCNT_13 |
|---|
| 55681 | #define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 |
|---|
| 55682 | #define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xFFFFFFFFL |
|---|
| 55683 | //PCIE_PRBS_ERRCNT_14 |
|---|
| 55684 | #define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 |
|---|
| 55685 | #define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xFFFFFFFFL |
|---|
| 55686 | //PCIE_PRBS_ERRCNT_15 |
|---|
| 55687 | #define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 |
|---|
| 55688 | #define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xFFFFFFFFL |
|---|
| 55689 | //SWRST_COMMAND_STATUS |
|---|
| 55690 | #define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 |
|---|
| 55691 | #define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 |
|---|
| 55692 | #define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 |
|---|
| 55693 | #define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 |
|---|
| 55694 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT 0x18 |
|---|
| 55695 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT 0x19 |
|---|
| 55696 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT 0x1a |
|---|
| 55697 | #define SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT 0x1b |
|---|
| 55698 | #define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT 0x1c |
|---|
| 55699 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT 0x1d |
|---|
| 55700 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT 0x1e |
|---|
| 55701 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT 0x1f |
|---|
| 55702 | #define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x00000001L |
|---|
| 55703 | #define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x00000002L |
|---|
| 55704 | #define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x00010000L |
|---|
| 55705 | #define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x00020000L |
|---|
| 55706 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK 0x01000000L |
|---|
| 55707 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK 0x02000000L |
|---|
| 55708 | #define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK 0x04000000L |
|---|
| 55709 | #define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK 0x08000000L |
|---|
| 55710 | #define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK 0x10000000L |
|---|
| 55711 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK 0x20000000L |
|---|
| 55712 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK 0x40000000L |
|---|
| 55713 | #define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK 0x80000000L |
|---|
| 55714 | //SWRST_GENERAL_CONTROL |
|---|
| 55715 | #define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 |
|---|
| 55716 | #define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 |
|---|
| 55717 | #define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 |
|---|
| 55718 | #define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 |
|---|
| 55719 | #define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 |
|---|
| 55720 | #define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa |
|---|
| 55721 | #define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc |
|---|
| 55722 | #define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x18 |
|---|
| 55723 | #define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT 0x19 |
|---|
| 55724 | #define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x00000001L |
|---|
| 55725 | #define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x00000002L |
|---|
| 55726 | #define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x0000001CL |
|---|
| 55727 | #define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x00000100L |
|---|
| 55728 | #define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x00000200L |
|---|
| 55729 | #define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x00000400L |
|---|
| 55730 | #define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x00001000L |
|---|
| 55731 | #define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x01000000L |
|---|
| 55732 | #define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK 0x02000000L |
|---|
| 55733 | //SWRST_COMMAND_0 |
|---|
| 55734 | #define SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT 0x0 |
|---|
| 55735 | #define SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT 0x8 |
|---|
| 55736 | #define SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT 0x9 |
|---|
| 55737 | #define SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT 0xa |
|---|
| 55738 | #define SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT 0xb |
|---|
| 55739 | #define SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT 0xc |
|---|
| 55740 | #define SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT 0xd |
|---|
| 55741 | #define SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT 0xe |
|---|
| 55742 | #define SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT 0xf |
|---|
| 55743 | #define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x18 |
|---|
| 55744 | #define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x19 |
|---|
| 55745 | #define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x1a |
|---|
| 55746 | #define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x1b |
|---|
| 55747 | #define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x1c |
|---|
| 55748 | #define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x1d |
|---|
| 55749 | #define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x1e |
|---|
| 55750 | #define SWRST_COMMAND_0__PORT0_COR_RESET_MASK 0x00000001L |
|---|
| 55751 | #define SWRST_COMMAND_0__PORT0_CFG_RESET_MASK 0x00000100L |
|---|
| 55752 | #define SWRST_COMMAND_0__PORT1_CFG_RESET_MASK 0x00000200L |
|---|
| 55753 | #define SWRST_COMMAND_0__PORT2_CFG_RESET_MASK 0x00000400L |
|---|
| 55754 | #define SWRST_COMMAND_0__PORT3_CFG_RESET_MASK 0x00000800L |
|---|
| 55755 | #define SWRST_COMMAND_0__PORT4_CFG_RESET_MASK 0x00001000L |
|---|
| 55756 | #define SWRST_COMMAND_0__PORT5_CFG_RESET_MASK 0x00002000L |
|---|
| 55757 | #define SWRST_COMMAND_0__PORT6_CFG_RESET_MASK 0x00004000L |
|---|
| 55758 | #define SWRST_COMMAND_0__PORT7_CFG_RESET_MASK 0x00008000L |
|---|
| 55759 | #define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x01000000L |
|---|
| 55760 | #define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x02000000L |
|---|
| 55761 | #define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x04000000L |
|---|
| 55762 | #define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x08000000L |
|---|
| 55763 | #define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x10000000L |
|---|
| 55764 | #define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x20000000L |
|---|
| 55765 | #define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x40000000L |
|---|
| 55766 | //SWRST_COMMAND_1 |
|---|
| 55767 | #define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x15 |
|---|
| 55768 | #define SWRST_COMMAND_1__RESETAXIMST__SHIFT 0x16 |
|---|
| 55769 | #define SWRST_COMMAND_1__RESETAXISLV__SHIFT 0x17 |
|---|
| 55770 | #define SWRST_COMMAND_1__RESETAXIINT__SHIFT 0x18 |
|---|
| 55771 | #define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x19 |
|---|
| 55772 | #define SWRST_COMMAND_1__RESETLNCT__SHIFT 0x1a |
|---|
| 55773 | #define SWRST_COMMAND_1__RESETMNTR__SHIFT 0x1b |
|---|
| 55774 | #define SWRST_COMMAND_1__RESETHLTR__SHIFT 0x1c |
|---|
| 55775 | #define SWRST_COMMAND_1__RESETCPM__SHIFT 0x1d |
|---|
| 55776 | #define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x1e |
|---|
| 55777 | #define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1f |
|---|
| 55778 | #define SWRST_COMMAND_1__SWITCHCLK_MASK 0x00200000L |
|---|
| 55779 | #define SWRST_COMMAND_1__RESETAXIMST_MASK 0x00400000L |
|---|
| 55780 | #define SWRST_COMMAND_1__RESETAXISLV_MASK 0x00800000L |
|---|
| 55781 | #define SWRST_COMMAND_1__RESETAXIINT_MASK 0x01000000L |
|---|
| 55782 | #define SWRST_COMMAND_1__RESETPCFG_MASK 0x02000000L |
|---|
| 55783 | #define SWRST_COMMAND_1__RESETLNCT_MASK 0x04000000L |
|---|
| 55784 | #define SWRST_COMMAND_1__RESETMNTR_MASK 0x08000000L |
|---|
| 55785 | #define SWRST_COMMAND_1__RESETHLTR_MASK 0x10000000L |
|---|
| 55786 | #define SWRST_COMMAND_1__RESETCPM_MASK 0x20000000L |
|---|
| 55787 | #define SWRST_COMMAND_1__RESETPHY0_MASK 0x40000000L |
|---|
| 55788 | #define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x80000000L |
|---|
| 55789 | //SWRST_CONTROL_0 |
|---|
| 55790 | #define SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT 0x0 |
|---|
| 55791 | #define SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT 0x8 |
|---|
| 55792 | #define SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT 0x9 |
|---|
| 55793 | #define SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT 0xa |
|---|
| 55794 | #define SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT 0xb |
|---|
| 55795 | #define SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT 0xc |
|---|
| 55796 | #define SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT 0xd |
|---|
| 55797 | #define SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT 0xe |
|---|
| 55798 | #define SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT 0xf |
|---|
| 55799 | #define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x18 |
|---|
| 55800 | #define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x19 |
|---|
| 55801 | #define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x1a |
|---|
| 55802 | #define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x1b |
|---|
| 55803 | #define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x1c |
|---|
| 55804 | #define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x1d |
|---|
| 55805 | #define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x1e |
|---|
| 55806 | #define SWRST_CONTROL_0__PORT0_COR_RCEN_MASK 0x00000001L |
|---|
| 55807 | #define SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK 0x00000100L |
|---|
| 55808 | #define SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK 0x00000200L |
|---|
| 55809 | #define SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK 0x00000400L |
|---|
| 55810 | #define SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK 0x00000800L |
|---|
| 55811 | #define SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK 0x00001000L |
|---|
| 55812 | #define SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK 0x00002000L |
|---|
| 55813 | #define SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK 0x00004000L |
|---|
| 55814 | #define SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK 0x00008000L |
|---|
| 55815 | #define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x01000000L |
|---|
| 55816 | #define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x02000000L |
|---|
| 55817 | #define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x04000000L |
|---|
| 55818 | #define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x08000000L |
|---|
| 55819 | #define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x10000000L |
|---|
| 55820 | #define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x20000000L |
|---|
| 55821 | #define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x40000000L |
|---|
| 55822 | //SWRST_CONTROL_1 |
|---|
| 55823 | #define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x15 |
|---|
| 55824 | #define SWRST_CONTROL_1__RESETAXIMST_RCEN__SHIFT 0x16 |
|---|
| 55825 | #define SWRST_CONTROL_1__RESETAXISLV_RCEN__SHIFT 0x17 |
|---|
| 55826 | #define SWRST_CONTROL_1__RESETAXIINT_RCEN__SHIFT 0x18 |
|---|
| 55827 | #define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x19 |
|---|
| 55828 | #define SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT 0x1a |
|---|
| 55829 | #define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0x1b |
|---|
| 55830 | #define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0x1c |
|---|
| 55831 | #define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0x1d |
|---|
| 55832 | #define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x1e |
|---|
| 55833 | #define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1f |
|---|
| 55834 | #define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x00200000L |
|---|
| 55835 | #define SWRST_CONTROL_1__RESETAXIMST_RCEN_MASK 0x00400000L |
|---|
| 55836 | #define SWRST_CONTROL_1__RESETAXISLV_RCEN_MASK 0x00800000L |
|---|
| 55837 | #define SWRST_CONTROL_1__RESETAXIINT_RCEN_MASK 0x01000000L |
|---|
| 55838 | #define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x02000000L |
|---|
| 55839 | #define SWRST_CONTROL_1__RESETLNCT_RCEN_MASK 0x04000000L |
|---|
| 55840 | #define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x08000000L |
|---|
| 55841 | #define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x10000000L |
|---|
| 55842 | #define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x20000000L |
|---|
| 55843 | #define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x40000000L |
|---|
| 55844 | #define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x80000000L |
|---|
| 55845 | //SWRST_CONTROL_2 |
|---|
| 55846 | #define SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT 0x0 |
|---|
| 55847 | #define SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT 0x8 |
|---|
| 55848 | #define SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT 0x9 |
|---|
| 55849 | #define SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT 0xa |
|---|
| 55850 | #define SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT 0xb |
|---|
| 55851 | #define SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT 0xc |
|---|
| 55852 | #define SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT 0xd |
|---|
| 55853 | #define SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT 0xe |
|---|
| 55854 | #define SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT 0xf |
|---|
| 55855 | #define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x18 |
|---|
| 55856 | #define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x19 |
|---|
| 55857 | #define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x1a |
|---|
| 55858 | #define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x1b |
|---|
| 55859 | #define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x1c |
|---|
| 55860 | #define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x1d |
|---|
| 55861 | #define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x1e |
|---|
| 55862 | #define SWRST_CONTROL_2__PORT0_COR_ATEN_MASK 0x00000001L |
|---|
| 55863 | #define SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK 0x00000100L |
|---|
| 55864 | #define SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK 0x00000200L |
|---|
| 55865 | #define SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK 0x00000400L |
|---|
| 55866 | #define SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK 0x00000800L |
|---|
| 55867 | #define SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK 0x00001000L |
|---|
| 55868 | #define SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK 0x00002000L |
|---|
| 55869 | #define SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK 0x00004000L |
|---|
| 55870 | #define SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK 0x00008000L |
|---|
| 55871 | #define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x01000000L |
|---|
| 55872 | #define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x02000000L |
|---|
| 55873 | #define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x04000000L |
|---|
| 55874 | #define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x08000000L |
|---|
| 55875 | #define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x10000000L |
|---|
| 55876 | #define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x20000000L |
|---|
| 55877 | #define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x40000000L |
|---|
| 55878 | //SWRST_CONTROL_3 |
|---|
| 55879 | #define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x15 |
|---|
| 55880 | #define SWRST_CONTROL_3__RESETAXIMST_ATEN__SHIFT 0x16 |
|---|
| 55881 | #define SWRST_CONTROL_3__RESETAXISLV_ATEN__SHIFT 0x17 |
|---|
| 55882 | #define SWRST_CONTROL_3__RESETAXIINT_ATEN__SHIFT 0x18 |
|---|
| 55883 | #define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x19 |
|---|
| 55884 | #define SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT 0x1a |
|---|
| 55885 | #define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0x1b |
|---|
| 55886 | #define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0x1c |
|---|
| 55887 | #define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0x1d |
|---|
| 55888 | #define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x1e |
|---|
| 55889 | #define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1f |
|---|
| 55890 | #define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x00200000L |
|---|
| 55891 | #define SWRST_CONTROL_3__RESETAXIMST_ATEN_MASK 0x00400000L |
|---|
| 55892 | #define SWRST_CONTROL_3__RESETAXISLV_ATEN_MASK 0x00800000L |
|---|
| 55893 | #define SWRST_CONTROL_3__RESETAXIINT_ATEN_MASK 0x01000000L |
|---|
| 55894 | #define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x02000000L |
|---|
| 55895 | #define SWRST_CONTROL_3__RESETLNCT_ATEN_MASK 0x04000000L |
|---|
| 55896 | #define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x08000000L |
|---|
| 55897 | #define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x10000000L |
|---|
| 55898 | #define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x20000000L |
|---|
| 55899 | #define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x40000000L |
|---|
| 55900 | #define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x80000000L |
|---|
| 55901 | //SWRST_CONTROL_4 |
|---|
| 55902 | #define SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT 0x0 |
|---|
| 55903 | #define SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT 0x8 |
|---|
| 55904 | #define SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT 0x9 |
|---|
| 55905 | #define SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT 0xa |
|---|
| 55906 | #define SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT 0xb |
|---|
| 55907 | #define SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT 0xc |
|---|
| 55908 | #define SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT 0xd |
|---|
| 55909 | #define SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT 0xe |
|---|
| 55910 | #define SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT 0xf |
|---|
| 55911 | #define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x18 |
|---|
| 55912 | #define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x19 |
|---|
| 55913 | #define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x1a |
|---|
| 55914 | #define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x1b |
|---|
| 55915 | #define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x1c |
|---|
| 55916 | #define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x1d |
|---|
| 55917 | #define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x1e |
|---|
| 55918 | #define SWRST_CONTROL_4__PORT0_COR_WREN_MASK 0x00000001L |
|---|
| 55919 | #define SWRST_CONTROL_4__PORT0_CFG_WREN_MASK 0x00000100L |
|---|
| 55920 | #define SWRST_CONTROL_4__PORT1_CFG_WREN_MASK 0x00000200L |
|---|
| 55921 | #define SWRST_CONTROL_4__PORT2_CFG_WREN_MASK 0x00000400L |
|---|
| 55922 | #define SWRST_CONTROL_4__PORT3_CFG_WREN_MASK 0x00000800L |
|---|
| 55923 | #define SWRST_CONTROL_4__PORT4_CFG_WREN_MASK 0x00001000L |
|---|
| 55924 | #define SWRST_CONTROL_4__PORT5_CFG_WREN_MASK 0x00002000L |
|---|
| 55925 | #define SWRST_CONTROL_4__PORT6_CFG_WREN_MASK 0x00004000L |
|---|
| 55926 | #define SWRST_CONTROL_4__PORT7_CFG_WREN_MASK 0x00008000L |
|---|
| 55927 | #define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x01000000L |
|---|
| 55928 | #define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x02000000L |
|---|
| 55929 | #define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x04000000L |
|---|
| 55930 | #define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x08000000L |
|---|
| 55931 | #define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x10000000L |
|---|
| 55932 | #define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x20000000L |
|---|
| 55933 | #define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x40000000L |
|---|
| 55934 | //SWRST_CONTROL_5 |
|---|
| 55935 | #define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x15 |
|---|
| 55936 | #define SWRST_CONTROL_5__WRRESETAXIMST_EN__SHIFT 0x16 |
|---|
| 55937 | #define SWRST_CONTROL_5__WRRESETAXISLV_EN__SHIFT 0x17 |
|---|
| 55938 | #define SWRST_CONTROL_5__WRRESETAXIINT_EN__SHIFT 0x18 |
|---|
| 55939 | #define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x19 |
|---|
| 55940 | #define SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT 0x1a |
|---|
| 55941 | #define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0x1b |
|---|
| 55942 | #define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0x1c |
|---|
| 55943 | #define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0x1d |
|---|
| 55944 | #define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x1e |
|---|
| 55945 | #define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1f |
|---|
| 55946 | #define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x00200000L |
|---|
| 55947 | #define SWRST_CONTROL_5__WRRESETAXIMST_EN_MASK 0x00400000L |
|---|
| 55948 | #define SWRST_CONTROL_5__WRRESETAXISLV_EN_MASK 0x00800000L |
|---|
| 55949 | #define SWRST_CONTROL_5__WRRESETAXIINT_EN_MASK 0x01000000L |
|---|
| 55950 | #define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x02000000L |
|---|
| 55951 | #define SWRST_CONTROL_5__WRRESETLNCT_EN_MASK 0x04000000L |
|---|
| 55952 | #define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x08000000L |
|---|
| 55953 | #define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x10000000L |
|---|
| 55954 | #define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x20000000L |
|---|
| 55955 | #define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x40000000L |
|---|
| 55956 | #define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x80000000L |
|---|
| 55957 | //SWRST_CONTROL_6 |
|---|
| 55958 | #define SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT 0x0 |
|---|
| 55959 | #define SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT 0x1 |
|---|
| 55960 | #define SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT 0x2 |
|---|
| 55961 | #define SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT 0x3 |
|---|
| 55962 | #define SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT 0x4 |
|---|
| 55963 | #define SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT 0x5 |
|---|
| 55964 | #define SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT 0x6 |
|---|
| 55965 | #define SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT 0x7 |
|---|
| 55966 | #define SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT 0x8 |
|---|
| 55967 | #define SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT 0x9 |
|---|
| 55968 | #define SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT 0xa |
|---|
| 55969 | #define SWRST_CONTROL_6__HOLD_TRAINING_A_MASK 0x00000001L |
|---|
| 55970 | #define SWRST_CONTROL_6__HOLD_TRAINING_B_MASK 0x00000002L |
|---|
| 55971 | #define SWRST_CONTROL_6__HOLD_TRAINING_C_MASK 0x00000004L |
|---|
| 55972 | #define SWRST_CONTROL_6__HOLD_TRAINING_D_MASK 0x00000008L |
|---|
| 55973 | #define SWRST_CONTROL_6__HOLD_TRAINING_E_MASK 0x00000010L |
|---|
| 55974 | #define SWRST_CONTROL_6__HOLD_TRAINING_F_MASK 0x00000020L |
|---|
| 55975 | #define SWRST_CONTROL_6__HOLD_TRAINING_G_MASK 0x00000040L |
|---|
| 55976 | #define SWRST_CONTROL_6__HOLD_TRAINING_H_MASK 0x00000080L |
|---|
| 55977 | #define SWRST_CONTROL_6__HOLD_TRAINING_I_MASK 0x00000100L |
|---|
| 55978 | #define SWRST_CONTROL_6__HOLD_TRAINING_J_MASK 0x00000200L |
|---|
| 55979 | #define SWRST_CONTROL_6__HOLD_TRAINING_K_MASK 0x00000400L |
|---|
| 55980 | //SWRST_EP_COMMAND_0 |
|---|
| 55981 | #define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0 |
|---|
| 55982 | #define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8 |
|---|
| 55983 | #define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9 |
|---|
| 55984 | #define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa |
|---|
| 55985 | #define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x00000001L |
|---|
| 55986 | #define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x00000100L |
|---|
| 55987 | #define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x00000200L |
|---|
| 55988 | #define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x00000400L |
|---|
| 55989 | //SWRST_EP_CONTROL_0 |
|---|
| 55990 | #define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0 |
|---|
| 55991 | #define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8 |
|---|
| 55992 | #define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9 |
|---|
| 55993 | #define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa |
|---|
| 55994 | #define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x00000001L |
|---|
| 55995 | #define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x00000100L |
|---|
| 55996 | #define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x00000200L |
|---|
| 55997 | #define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x00000400L |
|---|
| 55998 | //CPM_CONTROL |
|---|
| 55999 | #define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 |
|---|
| 56000 | #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 |
|---|
| 56001 | #define CPM_CONTROL__L1_PWR_GATE_ENABLE__SHIFT 0x2 |
|---|
| 56002 | #define CPM_CONTROL__L1_1_PWR_GATE_ENABLE__SHIFT 0x3 |
|---|
| 56003 | #define CPM_CONTROL__L1_2_PWR_GATE_ENABLE__SHIFT 0x4 |
|---|
| 56004 | #define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 |
|---|
| 56005 | #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 |
|---|
| 56006 | #define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 |
|---|
| 56007 | #define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 |
|---|
| 56008 | #define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 |
|---|
| 56009 | #define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xb |
|---|
| 56010 | #define CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE__SHIFT 0xd |
|---|
| 56011 | #define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xe |
|---|
| 56012 | #define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xf |
|---|
| 56013 | #define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0x10 |
|---|
| 56014 | #define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0x11 |
|---|
| 56015 | #define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x12 |
|---|
| 56016 | #define CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG__SHIFT 0x15 |
|---|
| 56017 | #define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 |
|---|
| 56018 | #define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 |
|---|
| 56019 | #define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT 0x18 |
|---|
| 56020 | #define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1__SHIFT 0x19 |
|---|
| 56021 | #define CPM_CONTROL__PG_EARLY_WAKE_ENABLE__SHIFT 0x1a |
|---|
| 56022 | #define CPM_CONTROL__PCIE_CORE_IDLE__SHIFT 0x1b |
|---|
| 56023 | #define CPM_CONTROL__PCIE_LINK_IDLE__SHIFT 0x1c |
|---|
| 56024 | #define CPM_CONTROL__PCIE_BUFFER_EMPTY__SHIFT 0x1d |
|---|
| 56025 | #define CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY__SHIFT 0x1e |
|---|
| 56026 | #define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L |
|---|
| 56027 | #define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L |
|---|
| 56028 | #define CPM_CONTROL__L1_PWR_GATE_ENABLE_MASK 0x00000004L |
|---|
| 56029 | #define CPM_CONTROL__L1_1_PWR_GATE_ENABLE_MASK 0x00000008L |
|---|
| 56030 | #define CPM_CONTROL__L1_2_PWR_GATE_ENABLE_MASK 0x00000010L |
|---|
| 56031 | #define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L |
|---|
| 56032 | #define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L |
|---|
| 56033 | #define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L |
|---|
| 56034 | #define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L |
|---|
| 56035 | #define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x00000600L |
|---|
| 56036 | #define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x00001800L |
|---|
| 56037 | #define CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE_MASK 0x00002000L |
|---|
| 56038 | #define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x00004000L |
|---|
| 56039 | #define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x00008000L |
|---|
| 56040 | #define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x00010000L |
|---|
| 56041 | #define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x00020000L |
|---|
| 56042 | #define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0x001C0000L |
|---|
| 56043 | #define CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG_MASK 0x00200000L |
|---|
| 56044 | #define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L |
|---|
| 56045 | #define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x00800000L |
|---|
| 56046 | #define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L |
|---|
| 56047 | #define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1_MASK 0x02000000L |
|---|
| 56048 | #define CPM_CONTROL__PG_EARLY_WAKE_ENABLE_MASK 0x04000000L |
|---|
| 56049 | #define CPM_CONTROL__PCIE_CORE_IDLE_MASK 0x08000000L |
|---|
| 56050 | #define CPM_CONTROL__PCIE_LINK_IDLE_MASK 0x10000000L |
|---|
| 56051 | #define CPM_CONTROL__PCIE_BUFFER_EMPTY_MASK 0x20000000L |
|---|
| 56052 | #define CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY_MASK 0xC0000000L |
|---|
| 56053 | //CPM_SPLIT_CONTROL |
|---|
| 56054 | #define CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE__SHIFT 0x0 |
|---|
| 56055 | #define CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE_MASK 0x00000001L |
|---|
| 56056 | //SMN_APERTURE_ID_A |
|---|
| 56057 | #define SMN_APERTURE_ID_A__SMU_APERTURE_ID__SHIFT 0x0 |
|---|
| 56058 | #define SMN_APERTURE_ID_A__SMU_APERTURE_ID_MASK 0x00000FFFL |
|---|
| 56059 | //SMN_APERTURE_ID_B |
|---|
| 56060 | #define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT 0x0 |
|---|
| 56061 | #define SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT 0xc |
|---|
| 56062 | #define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK 0x00000FFFL |
|---|
| 56063 | #define SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK 0x00FFF000L |
|---|
| 56064 | //LNCNT_CONTROL |
|---|
| 56065 | #define LNCNT_CONTROL__CFG_LNC_WINDOW_EN__SHIFT 0x0 |
|---|
| 56066 | #define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT 0x1 |
|---|
| 56067 | #define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT 0x2 |
|---|
| 56068 | #define LNCNT_CONTROL__CFG_LNC_OVRD_EN__SHIFT 0x3 |
|---|
| 56069 | #define LNCNT_CONTROL__CFG_LNC_OVRD_VAL__SHIFT 0x4 |
|---|
| 56070 | #define LNCNT_CONTROL__CFG_LNC_WINDOW_EN_MASK 0x00000001L |
|---|
| 56071 | #define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK 0x00000002L |
|---|
| 56072 | #define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK 0x00000004L |
|---|
| 56073 | #define LNCNT_CONTROL__CFG_LNC_OVRD_EN_MASK 0x00000008L |
|---|
| 56074 | #define LNCNT_CONTROL__CFG_LNC_OVRD_VAL_MASK 0x00000010L |
|---|
| 56075 | //LNCNT_QUAN_THRD |
|---|
| 56076 | #define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD__SHIFT 0x0 |
|---|
| 56077 | #define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD__SHIFT 0x4 |
|---|
| 56078 | #define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD_MASK 0x00000007L |
|---|
| 56079 | #define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD_MASK 0x00000070L |
|---|
| 56080 | //LNCNT_WEIGHT |
|---|
| 56081 | #define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT__SHIFT 0x0 |
|---|
| 56082 | #define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT__SHIFT 0x10 |
|---|
| 56083 | #define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT_MASK 0x0000FFFFL |
|---|
| 56084 | #define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT_MASK 0xFFFF0000L |
|---|
| 56085 | //SMU_INT_PIN_SHARING_PORT_INDICATOR |
|---|
| 56086 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS__SHIFT 0x0 |
|---|
| 56087 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS__SHIFT 0x8 |
|---|
| 56088 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS__SHIFT 0x10 |
|---|
| 56089 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS_MASK 0x000000FFL |
|---|
| 56090 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS_MASK 0x0000FF00L |
|---|
| 56091 | #define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS_MASK 0x00FF0000L |
|---|
| 56092 | //PCIE_PGMST_CNTL |
|---|
| 56093 | #define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0 |
|---|
| 56094 | #define PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8 |
|---|
| 56095 | #define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa |
|---|
| 56096 | #define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT 0xe |
|---|
| 56097 | #define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL |
|---|
| 56098 | #define PCIE_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L |
|---|
| 56099 | #define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L |
|---|
| 56100 | #define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK 0x0000C000L |
|---|
| 56101 | //PCIE_PGSLV_CNTL |
|---|
| 56102 | #define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0 |
|---|
| 56103 | #define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL |
|---|
| 56104 | //LC_CPM_CONTROL_0 |
|---|
| 56105 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE__SHIFT 0x0 |
|---|
| 56106 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE__SHIFT 0x1 |
|---|
| 56107 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE__SHIFT 0x2 |
|---|
| 56108 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE__SHIFT 0x3 |
|---|
| 56109 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE__SHIFT 0x4 |
|---|
| 56110 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE__SHIFT 0x5 |
|---|
| 56111 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE__SHIFT 0x6 |
|---|
| 56112 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE__SHIFT 0x7 |
|---|
| 56113 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE__SHIFT 0x8 |
|---|
| 56114 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE__SHIFT 0x9 |
|---|
| 56115 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE__SHIFT 0xa |
|---|
| 56116 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE__SHIFT 0xb |
|---|
| 56117 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE__SHIFT 0xc |
|---|
| 56118 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE__SHIFT 0xd |
|---|
| 56119 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE__SHIFT 0xe |
|---|
| 56120 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE__SHIFT 0xf |
|---|
| 56121 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE__SHIFT 0x10 |
|---|
| 56122 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE__SHIFT 0x11 |
|---|
| 56123 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE__SHIFT 0x12 |
|---|
| 56124 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE__SHIFT 0x13 |
|---|
| 56125 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE__SHIFT 0x14 |
|---|
| 56126 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE__SHIFT 0x15 |
|---|
| 56127 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE__SHIFT 0x16 |
|---|
| 56128 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE__SHIFT 0x17 |
|---|
| 56129 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE__SHIFT 0x18 |
|---|
| 56130 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE__SHIFT 0x19 |
|---|
| 56131 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE__SHIFT 0x1a |
|---|
| 56132 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE__SHIFT 0x1b |
|---|
| 56133 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE__SHIFT 0x1c |
|---|
| 56134 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE__SHIFT 0x1d |
|---|
| 56135 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE__SHIFT 0x1e |
|---|
| 56136 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE__SHIFT 0x1f |
|---|
| 56137 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE_MASK 0x00000001L |
|---|
| 56138 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE_MASK 0x00000002L |
|---|
| 56139 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE_MASK 0x00000004L |
|---|
| 56140 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE_MASK 0x00000008L |
|---|
| 56141 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE_MASK 0x00000010L |
|---|
| 56142 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE_MASK 0x00000020L |
|---|
| 56143 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE_MASK 0x00000040L |
|---|
| 56144 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE_MASK 0x00000080L |
|---|
| 56145 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE_MASK 0x00000100L |
|---|
| 56146 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE_MASK 0x00000200L |
|---|
| 56147 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE_MASK 0x00000400L |
|---|
| 56148 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE_MASK 0x00000800L |
|---|
| 56149 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE_MASK 0x00001000L |
|---|
| 56150 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE_MASK 0x00002000L |
|---|
| 56151 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE_MASK 0x00004000L |
|---|
| 56152 | #define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE_MASK 0x00008000L |
|---|
| 56153 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE_MASK 0x00010000L |
|---|
| 56154 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE_MASK 0x00020000L |
|---|
| 56155 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE_MASK 0x00040000L |
|---|
| 56156 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE_MASK 0x00080000L |
|---|
| 56157 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE_MASK 0x00100000L |
|---|
| 56158 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE_MASK 0x00200000L |
|---|
| 56159 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE_MASK 0x00400000L |
|---|
| 56160 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE_MASK 0x00800000L |
|---|
| 56161 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE_MASK 0x01000000L |
|---|
| 56162 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE_MASK 0x02000000L |
|---|
| 56163 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE_MASK 0x04000000L |
|---|
| 56164 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE_MASK 0x08000000L |
|---|
| 56165 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE_MASK 0x10000000L |
|---|
| 56166 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE_MASK 0x20000000L |
|---|
| 56167 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE_MASK 0x40000000L |
|---|
| 56168 | #define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE_MASK 0x80000000L |
|---|
| 56169 | //LC_CPM_CONTROL_1 |
|---|
| 56170 | #define LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY__SHIFT 0x0 |
|---|
| 56171 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE__SHIFT 0x10 |
|---|
| 56172 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE__SHIFT 0x11 |
|---|
| 56173 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE__SHIFT 0x12 |
|---|
| 56174 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE__SHIFT 0x13 |
|---|
| 56175 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE__SHIFT 0x14 |
|---|
| 56176 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE__SHIFT 0x15 |
|---|
| 56177 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE__SHIFT 0x16 |
|---|
| 56178 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE__SHIFT 0x17 |
|---|
| 56179 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE__SHIFT 0x18 |
|---|
| 56180 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE__SHIFT 0x19 |
|---|
| 56181 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE__SHIFT 0x1a |
|---|
| 56182 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE__SHIFT 0x1b |
|---|
| 56183 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE__SHIFT 0x1c |
|---|
| 56184 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE__SHIFT 0x1d |
|---|
| 56185 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE__SHIFT 0x1e |
|---|
| 56186 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE__SHIFT 0x1f |
|---|
| 56187 | #define LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY_MASK 0x00000007L |
|---|
| 56188 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE_MASK 0x00010000L |
|---|
| 56189 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE_MASK 0x00020000L |
|---|
| 56190 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE_MASK 0x00040000L |
|---|
| 56191 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE_MASK 0x00080000L |
|---|
| 56192 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE_MASK 0x00100000L |
|---|
| 56193 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE_MASK 0x00200000L |
|---|
| 56194 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE_MASK 0x00400000L |
|---|
| 56195 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE_MASK 0x00800000L |
|---|
| 56196 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE_MASK 0x01000000L |
|---|
| 56197 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE_MASK 0x02000000L |
|---|
| 56198 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE_MASK 0x04000000L |
|---|
| 56199 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE_MASK 0x08000000L |
|---|
| 56200 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE_MASK 0x10000000L |
|---|
| 56201 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE_MASK 0x20000000L |
|---|
| 56202 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE_MASK 0x40000000L |
|---|
| 56203 | #define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE_MASK 0x80000000L |
|---|
| 56204 | //PCIE_RXMARGIN_CONTROL_CAPABILITIES |
|---|
| 56205 | #define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED__SHIFT 0x0 |
|---|
| 56206 | #define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE__SHIFT 0x1 |
|---|
| 56207 | #define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING__SHIFT 0x2 |
|---|
| 56208 | #define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD__SHIFT 0x3 |
|---|
| 56209 | #define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER__SHIFT 0x4 |
|---|
| 56210 | #define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED_MASK 0x00000001L |
|---|
| 56211 | #define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE_MASK 0x00000002L |
|---|
| 56212 | #define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING_MASK 0x00000004L |
|---|
| 56213 | #define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD_MASK 0x00000008L |
|---|
| 56214 | #define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER_MASK 0x00000010L |
|---|
| 56215 | //PCIE_RXMARGIN_1_SETTINGS |
|---|
| 56216 | #define PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS__SHIFT 0x0 |
|---|
| 56217 | #define PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS__SHIFT 0x7 |
|---|
| 56218 | #define PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET__SHIFT 0xd |
|---|
| 56219 | #define PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET__SHIFT 0x14 |
|---|
| 56220 | #define PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS_MASK 0x0000007FL |
|---|
| 56221 | #define PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS_MASK 0x00001F80L |
|---|
| 56222 | #define PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET_MASK 0x000FE000L |
|---|
| 56223 | #define PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET_MASK 0x07F00000L |
|---|
| 56224 | //PCIE_RXMARGIN_2_SETTINGS |
|---|
| 56225 | #define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE__SHIFT 0x0 |
|---|
| 56226 | #define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING__SHIFT 0x6 |
|---|
| 56227 | #define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT__SHIFT 0xc |
|---|
| 56228 | #define PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES__SHIFT 0x13 |
|---|
| 56229 | #define PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT__SHIFT 0x18 |
|---|
| 56230 | #define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE_MASK 0x0000003FL |
|---|
| 56231 | #define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING_MASK 0x00000FC0L |
|---|
| 56232 | #define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT_MASK 0x0007F000L |
|---|
| 56233 | #define PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES_MASK 0x00F80000L |
|---|
| 56234 | #define PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT_MASK 0x3F000000L |
|---|
| 56235 | //PCIE_PRESENCE_DETECT_SELECT |
|---|
| 56236 | #define PCIE_PRESENCE_DETECT_SELECT__PRESENCE_DETECT_SELECT__SHIFT 0x0 |
|---|
| 56237 | #define PCIE_PRESENCE_DETECT_SELECT__PRESENCE_DETECT_SELECT_MASK 0x00000001L |
|---|
| 56238 | //PCIE_LC_DEBUG_CNTL |
|---|
| 56239 | #define PCIE_LC_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 |
|---|
| 56240 | #define PCIE_LC_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xFFFF0000L |
|---|
| 56241 | |
|---|
| 56242 | |
|---|
| 56243 | |
|---|
| 56244 | |
|---|
| 56245 | |
|---|
| 56246 | |
|---|
| 56247 | |
|---|
| 56248 | |
|---|
| 56249 | |
|---|
| 56250 | |
|---|
| 56251 | |
|---|
| 56252 | |
|---|
| 56253 | |
|---|
| 56254 | |
|---|
| 56255 | |
|---|
| 56256 | |
|---|
| 56257 | |
|---|
| 56258 | |
|---|
| 56259 | |
|---|
| 56260 | |
|---|
| 56261 | |
|---|
| 56262 | |
|---|
| 56263 | |
|---|
| 56264 | |
|---|
| 56265 | |
|---|
| 56266 | |
|---|
| 56267 | |
|---|
| 56268 | |
|---|
| 56269 | |
|---|
| 56270 | |
|---|
| 56271 | |
|---|
| 56272 | |
|---|
| 56273 | // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp |
|---|
| 56274 | //BIF_CFG_DEV0_SWDS0_VENDOR_ID |
|---|
| 56275 | #define BIF_CFG_DEV0_SWDS0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 56276 | #define BIF_CFG_DEV0_SWDS0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 56277 | //BIF_CFG_DEV0_SWDS0_DEVICE_ID |
|---|
| 56278 | #define BIF_CFG_DEV0_SWDS0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 56279 | #define BIF_CFG_DEV0_SWDS0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 56280 | //BIF_CFG_DEV0_SWDS0_COMMAND |
|---|
| 56281 | #define BIF_CFG_DEV0_SWDS0_COMMAND__IOEN_DN__SHIFT 0x0 |
|---|
| 56282 | #define BIF_CFG_DEV0_SWDS0_COMMAND__MEMEN_DN__SHIFT 0x1 |
|---|
| 56283 | #define BIF_CFG_DEV0_SWDS0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 56284 | #define BIF_CFG_DEV0_SWDS0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 56285 | #define BIF_CFG_DEV0_SWDS0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 56286 | #define BIF_CFG_DEV0_SWDS0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 56287 | #define BIF_CFG_DEV0_SWDS0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 56288 | #define BIF_CFG_DEV0_SWDS0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 56289 | #define BIF_CFG_DEV0_SWDS0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 56290 | #define BIF_CFG_DEV0_SWDS0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 56291 | #define BIF_CFG_DEV0_SWDS0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 56292 | #define BIF_CFG_DEV0_SWDS0_COMMAND__IOEN_DN_MASK 0x0001L |
|---|
| 56293 | #define BIF_CFG_DEV0_SWDS0_COMMAND__MEMEN_DN_MASK 0x0002L |
|---|
| 56294 | #define BIF_CFG_DEV0_SWDS0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 56295 | #define BIF_CFG_DEV0_SWDS0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 56296 | #define BIF_CFG_DEV0_SWDS0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 56297 | #define BIF_CFG_DEV0_SWDS0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 56298 | #define BIF_CFG_DEV0_SWDS0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 56299 | #define BIF_CFG_DEV0_SWDS0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 56300 | #define BIF_CFG_DEV0_SWDS0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 56301 | #define BIF_CFG_DEV0_SWDS0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 56302 | #define BIF_CFG_DEV0_SWDS0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 56303 | //BIF_CFG_DEV0_SWDS0_STATUS |
|---|
| 56304 | #define BIF_CFG_DEV0_SWDS0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 56305 | #define BIF_CFG_DEV0_SWDS0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 56306 | #define BIF_CFG_DEV0_SWDS0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 56307 | #define BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 56308 | #define BIF_CFG_DEV0_SWDS0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 56309 | #define BIF_CFG_DEV0_SWDS0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 56310 | #define BIF_CFG_DEV0_SWDS0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 56311 | #define BIF_CFG_DEV0_SWDS0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 56312 | #define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 56313 | #define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 56314 | #define BIF_CFG_DEV0_SWDS0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 56315 | #define BIF_CFG_DEV0_SWDS0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 56316 | #define BIF_CFG_DEV0_SWDS0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 56317 | #define BIF_CFG_DEV0_SWDS0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 56318 | #define BIF_CFG_DEV0_SWDS0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 56319 | #define BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 56320 | #define BIF_CFG_DEV0_SWDS0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 56321 | #define BIF_CFG_DEV0_SWDS0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 56322 | #define BIF_CFG_DEV0_SWDS0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 56323 | #define BIF_CFG_DEV0_SWDS0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 56324 | #define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 56325 | #define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 56326 | #define BIF_CFG_DEV0_SWDS0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 56327 | #define BIF_CFG_DEV0_SWDS0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 56328 | //BIF_CFG_DEV0_SWDS0_REVISION_ID |
|---|
| 56329 | #define BIF_CFG_DEV0_SWDS0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 56330 | #define BIF_CFG_DEV0_SWDS0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 56331 | #define BIF_CFG_DEV0_SWDS0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 56332 | #define BIF_CFG_DEV0_SWDS0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 56333 | //BIF_CFG_DEV0_SWDS0_PROG_INTERFACE |
|---|
| 56334 | #define BIF_CFG_DEV0_SWDS0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 56335 | #define BIF_CFG_DEV0_SWDS0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 56336 | //BIF_CFG_DEV0_SWDS0_SUB_CLASS |
|---|
| 56337 | #define BIF_CFG_DEV0_SWDS0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 56338 | #define BIF_CFG_DEV0_SWDS0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 56339 | //BIF_CFG_DEV0_SWDS0_BASE_CLASS |
|---|
| 56340 | #define BIF_CFG_DEV0_SWDS0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 56341 | #define BIF_CFG_DEV0_SWDS0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 56342 | //BIF_CFG_DEV0_SWDS0_CACHE_LINE |
|---|
| 56343 | #define BIF_CFG_DEV0_SWDS0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 56344 | #define BIF_CFG_DEV0_SWDS0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 56345 | //BIF_CFG_DEV0_SWDS0_LATENCY |
|---|
| 56346 | #define BIF_CFG_DEV0_SWDS0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 56347 | #define BIF_CFG_DEV0_SWDS0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 56348 | //BIF_CFG_DEV0_SWDS0_HEADER |
|---|
| 56349 | #define 0x0 |
|---|
| 56350 | #define 0x7 |
|---|
| 56351 | #define 0x7FL |
|---|
| 56352 | #define 0x80L |
|---|
| 56353 | //BIF_CFG_DEV0_SWDS0_BIST |
|---|
| 56354 | #define BIF_CFG_DEV0_SWDS0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 56355 | #define BIF_CFG_DEV0_SWDS0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 56356 | #define BIF_CFG_DEV0_SWDS0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 56357 | #define BIF_CFG_DEV0_SWDS0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 56358 | #define BIF_CFG_DEV0_SWDS0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 56359 | #define BIF_CFG_DEV0_SWDS0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 56360 | //BIF_CFG_DEV0_SWDS0_BASE_ADDR_1 |
|---|
| 56361 | #define BIF_CFG_DEV0_SWDS0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 56362 | #define BIF_CFG_DEV0_SWDS0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 56363 | //BIF_CFG_DEV0_SWDS0_BASE_ADDR_2 |
|---|
| 56364 | #define BIF_CFG_DEV0_SWDS0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 56365 | #define BIF_CFG_DEV0_SWDS0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 56366 | //BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY |
|---|
| 56367 | #define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
|---|
| 56368 | #define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
|---|
| 56369 | #define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
|---|
| 56370 | #define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
|---|
| 56371 | #define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
|---|
| 56372 | #define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
|---|
| 56373 | #define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
|---|
| 56374 | #define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
|---|
| 56375 | //BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT |
|---|
| 56376 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
|---|
| 56377 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
|---|
| 56378 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
|---|
| 56379 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
|---|
| 56380 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
|---|
| 56381 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
|---|
| 56382 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
|---|
| 56383 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
|---|
| 56384 | //BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS |
|---|
| 56385 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 56386 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 56387 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 56388 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 56389 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 56390 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 56391 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 56392 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 56393 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 56394 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 56395 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 56396 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 56397 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 56398 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 56399 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 56400 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 56401 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 56402 | #define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 56403 | //BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT |
|---|
| 56404 | #define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 56405 | #define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
|---|
| 56406 | #define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 56407 | #define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
|---|
| 56408 | #define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 56409 | #define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
|---|
| 56410 | #define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 56411 | #define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
|---|
| 56412 | //BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT |
|---|
| 56413 | #define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 56414 | #define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
|---|
| 56415 | #define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 56416 | #define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
|---|
| 56417 | #define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 56418 | #define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
|---|
| 56419 | #define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 56420 | #define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
|---|
| 56421 | //BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER |
|---|
| 56422 | #define BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
|---|
| 56423 | #define BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
|---|
| 56424 | //BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER |
|---|
| 56425 | #define BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
|---|
| 56426 | #define BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
|---|
| 56427 | //BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI |
|---|
| 56428 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
|---|
| 56429 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
|---|
| 56430 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
|---|
| 56431 | #define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
|---|
| 56432 | //BIF_CFG_DEV0_SWDS0_CAP_PTR |
|---|
| 56433 | #define BIF_CFG_DEV0_SWDS0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 56434 | #define BIF_CFG_DEV0_SWDS0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 56435 | //BIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR |
|---|
| 56436 | #define BIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 56437 | #define BIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 56438 | //BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE |
|---|
| 56439 | #define BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 56440 | #define BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 56441 | //BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN |
|---|
| 56442 | #define BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 56443 | #define BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 56444 | //BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL |
|---|
| 56445 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
|---|
| 56446 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
|---|
| 56447 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
|---|
| 56448 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
|---|
| 56449 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
|---|
| 56450 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
|---|
| 56451 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
|---|
| 56452 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
|---|
| 56453 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
|---|
| 56454 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
|---|
| 56455 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
|---|
| 56456 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
|---|
| 56457 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
|---|
| 56458 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
|---|
| 56459 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
|---|
| 56460 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
|---|
| 56461 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
|---|
| 56462 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
|---|
| 56463 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
|---|
| 56464 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
|---|
| 56465 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
|---|
| 56466 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
|---|
| 56467 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
|---|
| 56468 | #define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
|---|
| 56469 | //BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST |
|---|
| 56470 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 56471 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 56472 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 56473 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 56474 | //BIF_CFG_DEV0_SWDS0_PMI_CAP |
|---|
| 56475 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 56476 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 56477 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 56478 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 56479 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 56480 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 56481 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 56482 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 56483 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 56484 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 56485 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 56486 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 56487 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 56488 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 56489 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 56490 | #define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 56491 | //BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL |
|---|
| 56492 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 56493 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 56494 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 56495 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 56496 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 56497 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 56498 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 56499 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 56500 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 56501 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 56502 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 56503 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 56504 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 56505 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 56506 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 56507 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 56508 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 56509 | #define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 56510 | //BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST |
|---|
| 56511 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 56512 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 56513 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 56514 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 56515 | //BIF_CFG_DEV0_SWDS0_PCIE_CAP |
|---|
| 56516 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 56517 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 56518 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 56519 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 56520 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 56521 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 56522 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 56523 | #define BIF_CFG_DEV0_SWDS0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 56524 | //BIF_CFG_DEV0_SWDS0_DEVICE_CAP |
|---|
| 56525 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 56526 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 56527 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 56528 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 56529 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 56530 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 56531 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 56532 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 56533 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 56534 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 56535 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 56536 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 56537 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 56538 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 56539 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 56540 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 56541 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 56542 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 56543 | //BIF_CFG_DEV0_SWDS0_DEVICE_CNTL |
|---|
| 56544 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 56545 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 56546 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 56547 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 56548 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 56549 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 56550 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 56551 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 56552 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 56553 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 56554 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 56555 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
|---|
| 56556 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 56557 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 56558 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 56559 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 56560 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 56561 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 56562 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 56563 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 56564 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 56565 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 56566 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 56567 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
|---|
| 56568 | //BIF_CFG_DEV0_SWDS0_DEVICE_STATUS |
|---|
| 56569 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 56570 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 56571 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 56572 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 56573 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 56574 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 56575 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 56576 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 56577 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 56578 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 56579 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 56580 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 56581 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 56582 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 56583 | //BIF_CFG_DEV0_SWDS0_LINK_CAP |
|---|
| 56584 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 56585 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 56586 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 56587 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 56588 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 56589 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 56590 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 56591 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 56592 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 56593 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 56594 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 56595 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 56596 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 56597 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 56598 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 56599 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 56600 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 56601 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 56602 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 56603 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 56604 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 56605 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 56606 | //BIF_CFG_DEV0_SWDS0_LINK_CNTL |
|---|
| 56607 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 56608 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 56609 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 56610 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 56611 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 56612 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 56613 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 56614 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 56615 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 56616 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 56617 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 56618 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 56619 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 56620 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 56621 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 56622 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 56623 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 56624 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 56625 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 56626 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 56627 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 56628 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 56629 | //BIF_CFG_DEV0_SWDS0_LINK_STATUS |
|---|
| 56630 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 56631 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 56632 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 56633 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 56634 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 56635 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 56636 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 56637 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 56638 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 56639 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 56640 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 56641 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 56642 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 56643 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 56644 | //BIF_CFG_DEV0_SWDS0_SLOT_CAP |
|---|
| 56645 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
|---|
| 56646 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
|---|
| 56647 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
|---|
| 56648 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
|---|
| 56649 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
|---|
| 56650 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
|---|
| 56651 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
|---|
| 56652 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
|---|
| 56653 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
|---|
| 56654 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
|---|
| 56655 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
|---|
| 56656 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
|---|
| 56657 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
|---|
| 56658 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
|---|
| 56659 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
|---|
| 56660 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
|---|
| 56661 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
|---|
| 56662 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
|---|
| 56663 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
|---|
| 56664 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
|---|
| 56665 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
|---|
| 56666 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
|---|
| 56667 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
|---|
| 56668 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
|---|
| 56669 | //BIF_CFG_DEV0_SWDS0_SLOT_CNTL |
|---|
| 56670 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
|---|
| 56671 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
|---|
| 56672 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
|---|
| 56673 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
|---|
| 56674 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
|---|
| 56675 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
|---|
| 56676 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
|---|
| 56677 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
|---|
| 56678 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
|---|
| 56679 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
|---|
| 56680 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
|---|
| 56681 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
|---|
| 56682 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
|---|
| 56683 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
|---|
| 56684 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
|---|
| 56685 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
|---|
| 56686 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
|---|
| 56687 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
|---|
| 56688 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
|---|
| 56689 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
|---|
| 56690 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
|---|
| 56691 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
|---|
| 56692 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
|---|
| 56693 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
|---|
| 56694 | //BIF_CFG_DEV0_SWDS0_SLOT_STATUS |
|---|
| 56695 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
|---|
| 56696 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
|---|
| 56697 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
|---|
| 56698 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
|---|
| 56699 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
|---|
| 56700 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
|---|
| 56701 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
|---|
| 56702 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
|---|
| 56703 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
|---|
| 56704 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
|---|
| 56705 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
|---|
| 56706 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
|---|
| 56707 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
|---|
| 56708 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
|---|
| 56709 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
|---|
| 56710 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
|---|
| 56711 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
|---|
| 56712 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
|---|
| 56713 | //BIF_CFG_DEV0_SWDS0_DEVICE_CAP2 |
|---|
| 56714 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 56715 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 56716 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 56717 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 56718 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 56719 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 56720 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 56721 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 56722 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 56723 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 56724 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 56725 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 56726 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 56727 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 56728 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 56729 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 56730 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 56731 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 56732 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 56733 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 56734 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 56735 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 56736 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 56737 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 56738 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 56739 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 56740 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 56741 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 56742 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 56743 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 56744 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 56745 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 56746 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 56747 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 56748 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 56749 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 56750 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 56751 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 56752 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 56753 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 56754 | //BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 |
|---|
| 56755 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 56756 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 56757 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 56758 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 56759 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 56760 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 56761 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 56762 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 56763 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 56764 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 56765 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 56766 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 56767 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 56768 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 56769 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 56770 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 56771 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 56772 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 56773 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 56774 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 56775 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 56776 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 56777 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 56778 | #define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 56779 | //BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 |
|---|
| 56780 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 56781 | #define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 56782 | //BIF_CFG_DEV0_SWDS0_LINK_CAP2 |
|---|
| 56783 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 56784 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 56785 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 56786 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 56787 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 56788 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 56789 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 56790 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 56791 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 56792 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 56793 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 56794 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 56795 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 56796 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 56797 | //BIF_CFG_DEV0_SWDS0_LINK_CNTL2 |
|---|
| 56798 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 56799 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 56800 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 56801 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 56802 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 56803 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 56804 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 56805 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 56806 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 56807 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 56808 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 56809 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 56810 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 56811 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 56812 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 56813 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 56814 | //BIF_CFG_DEV0_SWDS0_LINK_STATUS2 |
|---|
| 56815 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 56816 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 56817 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 56818 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 56819 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 56820 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 56821 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 56822 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 56823 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 56824 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 56825 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 56826 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 56827 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 56828 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 56829 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 56830 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 56831 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 56832 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 56833 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 56834 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 56835 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 56836 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 56837 | //BIF_CFG_DEV0_SWDS0_SLOT_CAP2 |
|---|
| 56838 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
|---|
| 56839 | #define BIF_CFG_DEV0_SWDS0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 56840 | //BIF_CFG_DEV0_SWDS0_SLOT_CNTL2 |
|---|
| 56841 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
|---|
| 56842 | #define BIF_CFG_DEV0_SWDS0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
|---|
| 56843 | //BIF_CFG_DEV0_SWDS0_SLOT_STATUS2 |
|---|
| 56844 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 56845 | #define BIF_CFG_DEV0_SWDS0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 56846 | //BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST |
|---|
| 56847 | #define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 56848 | #define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 56849 | #define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 56850 | #define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 56851 | //BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL |
|---|
| 56852 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 56853 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 56854 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 56855 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 56856 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 56857 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 56858 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 56859 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 56860 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 56861 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 56862 | //BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO |
|---|
| 56863 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 56864 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 56865 | //BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI |
|---|
| 56866 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 56867 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 56868 | //BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA |
|---|
| 56869 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 56870 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 56871 | //BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 |
|---|
| 56872 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 56873 | #define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 56874 | //BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST |
|---|
| 56875 | #define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 56876 | #define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 56877 | #define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 56878 | #define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 56879 | //BIF_CFG_DEV0_SWDS0_SSID_CAP |
|---|
| 56880 | #define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 56881 | #define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 56882 | #define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 56883 | #define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 56884 | //BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 56885 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 56886 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 56887 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 56888 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 56889 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 56890 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 56891 | //BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 56892 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 56893 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 56894 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 56895 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 56896 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 56897 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 56898 | //BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 56899 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 56900 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 56901 | //BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 56902 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 56903 | #define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 56904 | //BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST |
|---|
| 56905 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 56906 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 56907 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 56908 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 56909 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 56910 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 56911 | //BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 |
|---|
| 56912 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 56913 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 56914 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 56915 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 56916 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 56917 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 56918 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 56919 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 56920 | //BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 |
|---|
| 56921 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 56922 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 56923 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 56924 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 56925 | //BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL |
|---|
| 56926 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 56927 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 56928 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 56929 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 56930 | //BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS |
|---|
| 56931 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 56932 | #define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 56933 | //BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP |
|---|
| 56934 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 56935 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 56936 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 56937 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 56938 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 56939 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 56940 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 56941 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 56942 | //BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL |
|---|
| 56943 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 56944 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 56945 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 56946 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 56947 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 56948 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 56949 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 56950 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 56951 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 56952 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 56953 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 56954 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 56955 | //BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS |
|---|
| 56956 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 56957 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 56958 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 56959 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 56960 | //BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP |
|---|
| 56961 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 56962 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 56963 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 56964 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 56965 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 56966 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 56967 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 56968 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 56969 | //BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL |
|---|
| 56970 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 56971 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 56972 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 56973 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 56974 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 56975 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 56976 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 56977 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 56978 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 56979 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 56980 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 56981 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 56982 | //BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS |
|---|
| 56983 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 56984 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 56985 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 56986 | #define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 56987 | //BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 56988 | #define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 56989 | #define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 56990 | #define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 56991 | #define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 56992 | #define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 56993 | #define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 56994 | //BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 56995 | #define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 56996 | #define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 56997 | //BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 56998 | #define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 56999 | #define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 57000 | //BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 57001 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 57002 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 57003 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 57004 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 57005 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 57006 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 57007 | //BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS |
|---|
| 57008 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 57009 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 57010 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 57011 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 57012 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 57013 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 57014 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 57015 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 57016 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 57017 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 57018 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 57019 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 57020 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 57021 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 57022 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 57023 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 57024 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 57025 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 57026 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 57027 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 57028 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 57029 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 57030 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 57031 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 57032 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 57033 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 57034 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 57035 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 57036 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 57037 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 57038 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 57039 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 57040 | //BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK |
|---|
| 57041 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 57042 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 57043 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 57044 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 57045 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 57046 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 57047 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 57048 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 57049 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 57050 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 57051 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 57052 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 57053 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 57054 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 57055 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 57056 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 57057 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 57058 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 57059 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 57060 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 57061 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 57062 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 57063 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 57064 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 57065 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 57066 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 57067 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 57068 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 57069 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 57070 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 57071 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 57072 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 57073 | //BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 57074 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 57075 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 57076 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 57077 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 57078 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 57079 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 57080 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 57081 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 57082 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 57083 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 57084 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 57085 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 57086 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 57087 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 57088 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 57089 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 57090 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 57091 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 57092 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 57093 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 57094 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 57095 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 57096 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 57097 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 57098 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 57099 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 57100 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 57101 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 57102 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 57103 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 57104 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 57105 | #define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 57106 | //BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS |
|---|
| 57107 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 57108 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 57109 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 57110 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 57111 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 57112 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 57113 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 57114 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 57115 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 57116 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 57117 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 57118 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 57119 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 57120 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 57121 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 57122 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 57123 | //BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK |
|---|
| 57124 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 57125 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 57126 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 57127 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 57128 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 57129 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 57130 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 57131 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 57132 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 57133 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 57134 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 57135 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 57136 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 57137 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 57138 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 57139 | #define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 57140 | //BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 57141 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 57142 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 57143 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 57144 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 57145 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 57146 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 57147 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 57148 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 57149 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 57150 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 57151 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 57152 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 57153 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 57154 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 57155 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 57156 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 57157 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 57158 | #define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 57159 | //BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 |
|---|
| 57160 | #define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 57161 | #define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 57162 | //BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 |
|---|
| 57163 | #define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 57164 | #define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 57165 | //BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 |
|---|
| 57166 | #define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 57167 | #define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 57168 | //BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 |
|---|
| 57169 | #define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 57170 | #define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 57171 | //BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 57172 | #define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 57173 | #define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 57174 | //BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 57175 | #define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 57176 | #define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 57177 | //BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 57178 | #define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 57179 | #define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 57180 | //BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 57181 | #define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 57182 | #define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 57183 | //BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 57184 | #define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 57185 | #define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 57186 | #define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 57187 | #define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 57188 | #define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 57189 | #define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 57190 | //BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 |
|---|
| 57191 | #define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 57192 | #define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
|---|
| 57193 | #define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
|---|
| 57194 | #define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 57195 | #define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 57196 | #define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
|---|
| 57197 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS |
|---|
| 57198 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 57199 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
|---|
| 57200 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 57201 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
|---|
| 57202 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 57203 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57204 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57205 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57206 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57207 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57208 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57209 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57210 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57211 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57212 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57213 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL |
|---|
| 57214 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57215 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57216 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57217 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57218 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57219 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57220 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57221 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57222 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57223 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57224 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL |
|---|
| 57225 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57226 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57227 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57228 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57229 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57230 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57231 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57232 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57233 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57234 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57235 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL |
|---|
| 57236 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57237 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57238 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57239 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57240 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57241 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57242 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57243 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57244 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57245 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57246 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL |
|---|
| 57247 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57248 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57249 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57250 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57251 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57252 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57253 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57254 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57255 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57256 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57257 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 57258 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57259 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57260 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57261 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57262 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57263 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57264 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57265 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57266 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57267 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57268 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 57269 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57270 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57271 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57272 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57273 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57274 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57275 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57276 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57277 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57278 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57279 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 57280 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57281 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57282 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57283 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57284 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57285 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57286 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57287 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57288 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57289 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57290 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 57291 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57292 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57293 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57294 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57295 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57296 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57297 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57298 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57299 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57300 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57301 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 57302 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57303 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57304 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57305 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57306 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57307 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57308 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57309 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57310 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57311 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57312 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 57313 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57314 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57315 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57316 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57317 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57318 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57319 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57320 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57321 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57322 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57323 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 57324 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57325 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57326 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57327 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57328 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57329 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57330 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57331 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57332 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57333 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57334 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 57335 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57336 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57337 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57338 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57339 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57340 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57341 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57342 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57343 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57344 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57345 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 57346 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57347 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57348 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57349 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57350 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57351 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57352 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57353 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57354 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57355 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57356 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 57357 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57358 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57359 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57360 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57361 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57362 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57363 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57364 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57365 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57366 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57367 | //BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 57368 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 57369 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 57370 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 57371 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 57372 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 57373 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 57374 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 57375 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 57376 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 57377 | #define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 57378 | //BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST |
|---|
| 57379 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 57380 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 57381 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 57382 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 57383 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 57384 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 57385 | //BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP |
|---|
| 57386 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 57387 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 57388 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 57389 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 57390 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 57391 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 57392 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 57393 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 57394 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 57395 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 57396 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 57397 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 57398 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 57399 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 57400 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 57401 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 57402 | //BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL |
|---|
| 57403 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 57404 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 57405 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 57406 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 57407 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 57408 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 57409 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 57410 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 57411 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 57412 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 57413 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 57414 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 57415 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 57416 | #define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 57417 | //BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST |
|---|
| 57418 | #define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 57419 | #define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 57420 | #define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 57421 | #define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 57422 | #define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 57423 | #define BIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 57424 | //BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP |
|---|
| 57425 | #define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 57426 | #define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
|---|
| 57427 | #define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 57428 | #define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
|---|
| 57429 | //BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS |
|---|
| 57430 | #define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 57431 | #define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
|---|
| 57432 | #define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 57433 | #define BIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
|---|
| 57434 | //BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST |
|---|
| 57435 | #define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 57436 | #define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 57437 | #define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 57438 | #define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 57439 | #define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 57440 | #define BIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 57441 | //BIF_CFG_DEV0_SWDS0_LINK_CAP_16GT |
|---|
| 57442 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
|---|
| 57443 | #define BIF_CFG_DEV0_SWDS0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 57444 | //BIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT |
|---|
| 57445 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
|---|
| 57446 | #define BIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 57447 | //BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT |
|---|
| 57448 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
|---|
| 57449 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
|---|
| 57450 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
|---|
| 57451 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
|---|
| 57452 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
|---|
| 57453 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
|---|
| 57454 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
|---|
| 57455 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
|---|
| 57456 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
|---|
| 57457 | #define BIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
|---|
| 57458 | //BIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT |
|---|
| 57459 | #define BIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 57460 | #define BIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 57461 | //BIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT |
|---|
| 57462 | #define BIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 57463 | #define BIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 57464 | //BIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT |
|---|
| 57465 | #define BIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 57466 | #define BIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 57467 | //BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT |
|---|
| 57468 | #define BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57469 | #define BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57470 | #define BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57471 | #define BIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57472 | //BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT |
|---|
| 57473 | #define BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57474 | #define BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57475 | #define BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57476 | #define BIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57477 | //BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT |
|---|
| 57478 | #define BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57479 | #define BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57480 | #define BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57481 | #define BIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57482 | //BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT |
|---|
| 57483 | #define BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57484 | #define BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57485 | #define BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57486 | #define BIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57487 | //BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT |
|---|
| 57488 | #define BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57489 | #define BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57490 | #define BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57491 | #define BIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57492 | //BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT |
|---|
| 57493 | #define BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57494 | #define BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57495 | #define BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57496 | #define BIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57497 | //BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT |
|---|
| 57498 | #define BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57499 | #define BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57500 | #define BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57501 | #define BIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57502 | //BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT |
|---|
| 57503 | #define BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57504 | #define BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57505 | #define BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57506 | #define BIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57507 | //BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT |
|---|
| 57508 | #define BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57509 | #define BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57510 | #define BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57511 | #define BIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57512 | //BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT |
|---|
| 57513 | #define BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57514 | #define BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57515 | #define BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57516 | #define BIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57517 | //BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT |
|---|
| 57518 | #define BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57519 | #define BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57520 | #define BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57521 | #define BIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57522 | //BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT |
|---|
| 57523 | #define BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57524 | #define BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57525 | #define BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57526 | #define BIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57527 | //BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT |
|---|
| 57528 | #define BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57529 | #define BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57530 | #define BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57531 | #define BIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57532 | //BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT |
|---|
| 57533 | #define BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57534 | #define BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57535 | #define BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57536 | #define BIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57537 | //BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 57538 | #define BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57539 | #define BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57540 | #define BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57541 | #define BIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57542 | //BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 57543 | #define BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 57544 | #define BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 57545 | #define BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 57546 | #define BIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 57547 | //BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 57548 | #define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 57549 | #define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 57550 | #define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 57551 | #define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 57552 | #define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 57553 | #define BIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 57554 | //BIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP |
|---|
| 57555 | #define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 57556 | #define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 57557 | //BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS |
|---|
| 57558 | #define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
|---|
| 57559 | #define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
|---|
| 57560 | #define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
|---|
| 57561 | #define BIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
|---|
| 57562 | //BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL |
|---|
| 57563 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57564 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57565 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57566 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57567 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57568 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57569 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 57570 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57571 | //BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS |
|---|
| 57572 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57573 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57574 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57575 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57576 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57577 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57578 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57579 | #define BIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57580 | //BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL |
|---|
| 57581 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57582 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57583 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57584 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57585 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57586 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57587 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 57588 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57589 | //BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS |
|---|
| 57590 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57591 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57592 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57593 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57594 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57595 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57596 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57597 | #define BIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57598 | //BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL |
|---|
| 57599 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57600 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57601 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57602 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57603 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57604 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57605 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 57606 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57607 | //BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS |
|---|
| 57608 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57609 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57610 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57611 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57612 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57613 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57614 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57615 | #define BIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57616 | //BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL |
|---|
| 57617 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57618 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57619 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57620 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57621 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57622 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57623 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 57624 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57625 | //BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS |
|---|
| 57626 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57627 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57628 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57629 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57630 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57631 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57632 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57633 | #define BIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57634 | //BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL |
|---|
| 57635 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57636 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57637 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57638 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57639 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57640 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57641 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 57642 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57643 | //BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS |
|---|
| 57644 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57645 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57646 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57647 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57648 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57649 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57650 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57651 | #define BIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57652 | //BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL |
|---|
| 57653 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57654 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57655 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57656 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57657 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57658 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57659 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 57660 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57661 | //BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS |
|---|
| 57662 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57663 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57664 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57665 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57666 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57667 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57668 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57669 | #define BIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57670 | //BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL |
|---|
| 57671 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57672 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57673 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57674 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57675 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57676 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57677 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 57678 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57679 | //BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS |
|---|
| 57680 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57681 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57682 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57683 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57684 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57685 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57686 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57687 | #define BIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57688 | //BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL |
|---|
| 57689 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57690 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57691 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57692 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57693 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57694 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57695 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 57696 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57697 | //BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS |
|---|
| 57698 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57699 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57700 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57701 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57702 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57703 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57704 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57705 | #define BIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57706 | //BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL |
|---|
| 57707 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57708 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57709 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57710 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57711 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57712 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57713 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 57714 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57715 | //BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS |
|---|
| 57716 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57717 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57718 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57719 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57720 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57721 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57722 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57723 | #define BIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57724 | //BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL |
|---|
| 57725 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57726 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57727 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57728 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57729 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57730 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57731 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 57732 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57733 | //BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS |
|---|
| 57734 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57735 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57736 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57737 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57738 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57739 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57740 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57741 | #define BIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57742 | //BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL |
|---|
| 57743 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57744 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57745 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57746 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57747 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57748 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57749 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 57750 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57751 | //BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS |
|---|
| 57752 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57753 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57754 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57755 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57756 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57757 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57758 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57759 | #define BIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57760 | //BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL |
|---|
| 57761 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57762 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57763 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57764 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57765 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57766 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57767 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 57768 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57769 | //BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS |
|---|
| 57770 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57771 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57772 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57773 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57774 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57775 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57776 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57777 | #define BIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57778 | //BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL |
|---|
| 57779 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57780 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57781 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57782 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57783 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57784 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57785 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 57786 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57787 | //BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS |
|---|
| 57788 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57789 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57790 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57791 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57792 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57793 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57794 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57795 | #define BIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57796 | //BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL |
|---|
| 57797 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57798 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57799 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57800 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57801 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57802 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57803 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 57804 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57805 | //BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS |
|---|
| 57806 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57807 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57808 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57809 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57810 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57811 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57812 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57813 | #define BIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57814 | //BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL |
|---|
| 57815 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57816 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57817 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57818 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57819 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57820 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57821 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 57822 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57823 | //BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS |
|---|
| 57824 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57825 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57826 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57827 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57828 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57829 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57830 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57831 | #define BIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57832 | //BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL |
|---|
| 57833 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 57834 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 57835 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 57836 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 57837 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 57838 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 57839 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 57840 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 57841 | //BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS |
|---|
| 57842 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 57843 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 57844 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 57845 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 57846 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 57847 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 57848 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 57849 | #define BIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 57850 | |
|---|
| 57851 | |
|---|
| 57852 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp |
|---|
| 57853 | //BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID |
|---|
| 57854 | #define BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 57855 | #define BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 57856 | //BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID |
|---|
| 57857 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 57858 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 57859 | //BIF_CFG_DEV0_EPF0_VF0_0_COMMAND |
|---|
| 57860 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 57861 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 57862 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 57863 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 57864 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 57865 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 57866 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 57867 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 57868 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 57869 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 57870 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 57871 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 57872 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 57873 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 57874 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 57875 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 57876 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 57877 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 57878 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 57879 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 57880 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 57881 | #define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 57882 | //BIF_CFG_DEV0_EPF0_VF0_0_STATUS |
|---|
| 57883 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 57884 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 57885 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 57886 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 57887 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 57888 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 57889 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 57890 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 57891 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 57892 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 57893 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 57894 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 57895 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 57896 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 57897 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 57898 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 57899 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 57900 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 57901 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 57902 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 57903 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 57904 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 57905 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 57906 | #define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 57907 | //BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID |
|---|
| 57908 | #define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 57909 | #define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 57910 | #define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 57911 | #define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 57912 | //BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE |
|---|
| 57913 | #define BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 57914 | #define BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 57915 | //BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS |
|---|
| 57916 | #define BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 57917 | #define BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 57918 | //BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS |
|---|
| 57919 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 57920 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 57921 | //BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE |
|---|
| 57922 | #define BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 57923 | #define BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 57924 | //BIF_CFG_DEV0_EPF0_VF0_0_LATENCY |
|---|
| 57925 | #define BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 57926 | #define BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 57927 | //BIF_CFG_DEV0_EPF0_VF0_0_HEADER |
|---|
| 57928 | #define 0x0 |
|---|
| 57929 | #define 0x7 |
|---|
| 57930 | #define 0x7FL |
|---|
| 57931 | #define 0x80L |
|---|
| 57932 | //BIF_CFG_DEV0_EPF0_VF0_0_BIST |
|---|
| 57933 | #define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 57934 | #define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 57935 | #define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 57936 | #define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 57937 | #define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 57938 | #define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 57939 | //BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 |
|---|
| 57940 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 57941 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 57942 | //BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 |
|---|
| 57943 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 57944 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 57945 | //BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 |
|---|
| 57946 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 57947 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 57948 | //BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 |
|---|
| 57949 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 57950 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 57951 | //BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 |
|---|
| 57952 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 57953 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 57954 | //BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 |
|---|
| 57955 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 57956 | #define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 57957 | //BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR |
|---|
| 57958 | #define BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 57959 | #define BIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 57960 | //BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID |
|---|
| 57961 | #define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 57962 | #define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 57963 | #define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 57964 | #define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 57965 | //BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR |
|---|
| 57966 | #define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 57967 | #define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 57968 | //BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR |
|---|
| 57969 | #define BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 57970 | #define BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 57971 | //BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE |
|---|
| 57972 | #define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 57973 | #define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 57974 | //BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN |
|---|
| 57975 | #define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 57976 | #define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 57977 | //BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT |
|---|
| 57978 | #define BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 57979 | #define BIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 57980 | //BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY |
|---|
| 57981 | #define BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 57982 | #define BIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 57983 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST |
|---|
| 57984 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 57985 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 57986 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 57987 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 57988 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP |
|---|
| 57989 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 57990 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 57991 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 57992 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 57993 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 57994 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 57995 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 57996 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 57997 | //BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP |
|---|
| 57998 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 57999 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 58000 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 58001 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 58002 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 58003 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 58004 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 58005 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 58006 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 58007 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 58008 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 58009 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 58010 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 58011 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 58012 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 58013 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 58014 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 58015 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 58016 | //BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL |
|---|
| 58017 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 58018 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 58019 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 58020 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 58021 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 58022 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 58023 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 58024 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 58025 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 58026 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 58027 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 58028 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 58029 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 58030 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 58031 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 58032 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 58033 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 58034 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 58035 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 58036 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 58037 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 58038 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 58039 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 58040 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 58041 | //BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS |
|---|
| 58042 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 58043 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 58044 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 58045 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 58046 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 58047 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 58048 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 58049 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 58050 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 58051 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 58052 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 58053 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 58054 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 58055 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 58056 | //BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP |
|---|
| 58057 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 58058 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 58059 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 58060 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 58061 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 58062 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 58063 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 58064 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 58065 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 58066 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 58067 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 58068 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 58069 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 58070 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 58071 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 58072 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 58073 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 58074 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 58075 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 58076 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 58077 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 58078 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 58079 | //BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL |
|---|
| 58080 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 58081 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 58082 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 58083 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 58084 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 58085 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 58086 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 58087 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 58088 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 58089 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 58090 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 58091 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 58092 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 58093 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 58094 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 58095 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 58096 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 58097 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 58098 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 58099 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 58100 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 58101 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 58102 | //BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS |
|---|
| 58103 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 58104 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 58105 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 58106 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 58107 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 58108 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 58109 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 58110 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 58111 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 58112 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 58113 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 58114 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 58115 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 58116 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 58117 | //BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 |
|---|
| 58118 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 58119 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 58120 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 58121 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 58122 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 58123 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 58124 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 58125 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 58126 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 58127 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 58128 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 58129 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 58130 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 58131 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 58132 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 58133 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 58134 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 58135 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 58136 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 58137 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 58138 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 58139 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 58140 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 58141 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 58142 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 58143 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 58144 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 58145 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 58146 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 58147 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 58148 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 58149 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 58150 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 58151 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 58152 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 58153 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 58154 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 58155 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 58156 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 58157 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 58158 | //BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 |
|---|
| 58159 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 58160 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 58161 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 58162 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 58163 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 58164 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 58165 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 58166 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 58167 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 58168 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 58169 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 58170 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 58171 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 58172 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 58173 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 58174 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 58175 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 58176 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 58177 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 58178 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 58179 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 58180 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 58181 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 58182 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 58183 | //BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 |
|---|
| 58184 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 58185 | #define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 58186 | //BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 |
|---|
| 58187 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 58188 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 58189 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 58190 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 58191 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 58192 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 58193 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 58194 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 58195 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 58196 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 58197 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 58198 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 58199 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 58200 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 58201 | //BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 |
|---|
| 58202 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 58203 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 58204 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 58205 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 58206 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 58207 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 58208 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 58209 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 58210 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 58211 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 58212 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 58213 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 58214 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 58215 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 58216 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 58217 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 58218 | //BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 |
|---|
| 58219 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 58220 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 58221 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 58222 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 58223 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 58224 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 58225 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 58226 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 58227 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 58228 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 58229 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 58230 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 58231 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 58232 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 58233 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 58234 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 58235 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 58236 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 58237 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 58238 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 58239 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 58240 | #define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 58241 | //BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST |
|---|
| 58242 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 58243 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 58244 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 58245 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 58246 | //BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL |
|---|
| 58247 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 58248 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 58249 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 58250 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 58251 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 58252 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 58253 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 58254 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 58255 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 58256 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 58257 | //BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO |
|---|
| 58258 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 58259 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 58260 | //BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI |
|---|
| 58261 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 58262 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 58263 | //BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA |
|---|
| 58264 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 58265 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 58266 | //BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK |
|---|
| 58267 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 58268 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 58269 | //BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 |
|---|
| 58270 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 58271 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 58272 | //BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 |
|---|
| 58273 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 58274 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 58275 | //BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING |
|---|
| 58276 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 58277 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 58278 | //BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 |
|---|
| 58279 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 58280 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 58281 | //BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST |
|---|
| 58282 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 58283 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 58284 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 58285 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 58286 | //BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL |
|---|
| 58287 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 58288 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 58289 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 58290 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 58291 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 58292 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 58293 | //BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE |
|---|
| 58294 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 58295 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 58296 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 58297 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 58298 | //BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA |
|---|
| 58299 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 58300 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 58301 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 58302 | #define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 58303 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 58304 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 58305 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 58306 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 58307 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 58308 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 58309 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 58310 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 58311 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 58312 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 58313 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 58314 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 58315 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 58316 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 58317 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 58318 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 58319 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 58320 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 58321 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 58322 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 58323 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 58324 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 58325 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 58326 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 58327 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 58328 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 58329 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 58330 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 58331 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 58332 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 58333 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 58334 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 58335 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 58336 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 58337 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 58338 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 58339 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 58340 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 58341 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 58342 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 58343 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 58344 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 58345 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 58346 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 58347 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 58348 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 58349 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 58350 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 58351 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 58352 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 58353 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 58354 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 58355 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 58356 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 58357 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 58358 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 58359 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 58360 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 58361 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 58362 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 58363 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK |
|---|
| 58364 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 58365 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 58366 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 58367 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 58368 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 58369 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 58370 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 58371 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 58372 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 58373 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 58374 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 58375 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 58376 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 58377 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 58378 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 58379 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 58380 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 58381 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 58382 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 58383 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 58384 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 58385 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 58386 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 58387 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 58388 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 58389 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 58390 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 58391 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 58392 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 58393 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 58394 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 58395 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 58396 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY |
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| 58397 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 58398 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 58399 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 58400 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 58401 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 58402 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 58403 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 58404 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 58405 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 58406 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 58407 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 58408 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 58409 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 58410 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 58411 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 58412 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 58413 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 58414 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 58415 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 58416 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 58417 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 58418 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 58419 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 58420 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 58421 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 58422 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 58423 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 58424 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 58425 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 58426 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 58427 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 58428 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 58429 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS |
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| 58430 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 58431 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 58432 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 58433 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 58434 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 58435 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 58436 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 58437 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 58438 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 58439 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 58440 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 58441 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 58442 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 58443 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 58444 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 58445 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 58446 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK |
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| 58447 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 58448 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 58449 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 58450 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 58451 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 58452 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 58453 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 58454 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 58455 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 58456 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 58457 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 58458 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
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| 58459 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
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| 58460 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
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| 58461 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
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| 58462 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 58463 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 58464 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 58465 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 58466 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 58467 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
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| 58468 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
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| 58469 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
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| 58470 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
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| 58471 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
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| 58472 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
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| 58473 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
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| 58474 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
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| 58475 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
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| 58476 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
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| 58477 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
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| 58478 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
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| 58479 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
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| 58480 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
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| 58481 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
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| 58482 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 |
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| 58483 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
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| 58484 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
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| 58485 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 |
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| 58486 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
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| 58487 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
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| 58488 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 |
|---|
| 58489 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
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| 58490 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
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| 58491 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 |
|---|
| 58492 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
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| 58493 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
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| 58494 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 58495 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
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| 58496 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 58497 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 58498 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
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| 58499 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 58500 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 58501 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
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| 58502 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 58503 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 58504 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
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| 58505 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 58506 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST |
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| 58507 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 58508 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 58509 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 58510 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 58511 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 58512 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 58513 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP |
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| 58514 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 58515 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 58516 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 58517 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 58518 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 58519 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 58520 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL |
|---|
| 58521 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 58522 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 58523 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 58524 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 58525 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 58526 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 58527 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 58528 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 58529 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 58530 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 58531 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 58532 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP |
|---|
| 58533 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 58534 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 58535 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 58536 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 58537 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 58538 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 58539 | //BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL |
|---|
| 58540 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 58541 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 58542 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 58543 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 58544 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 58545 | #define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 58546 | |
|---|
| 58547 | |
|---|
| 58548 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp |
|---|
| 58549 | //BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID |
|---|
| 58550 | #define BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 58551 | #define BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 58552 | //BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID |
|---|
| 58553 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 58554 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 58555 | //BIF_CFG_DEV0_EPF0_VF1_0_COMMAND |
|---|
| 58556 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 58557 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 58558 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 58559 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 58560 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 58561 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 58562 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 58563 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 58564 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 58565 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 58566 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 58567 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 58568 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 58569 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 58570 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 58571 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 58572 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 58573 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 58574 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 58575 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 58576 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 58577 | #define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 58578 | //BIF_CFG_DEV0_EPF0_VF1_0_STATUS |
|---|
| 58579 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 58580 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 58581 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 58582 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 58583 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 58584 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 58585 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 58586 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 58587 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 58588 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 58589 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 58590 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 58591 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 58592 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 58593 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 58594 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 58595 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 58596 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 58597 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 58598 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 58599 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 58600 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 58601 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 58602 | #define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 58603 | //BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID |
|---|
| 58604 | #define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 58605 | #define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 58606 | #define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 58607 | #define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 58608 | //BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE |
|---|
| 58609 | #define BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 58610 | #define BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 58611 | //BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS |
|---|
| 58612 | #define BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 58613 | #define BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 58614 | //BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS |
|---|
| 58615 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 58616 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 58617 | //BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE |
|---|
| 58618 | #define BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 58619 | #define BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 58620 | //BIF_CFG_DEV0_EPF0_VF1_0_LATENCY |
|---|
| 58621 | #define BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 58622 | #define BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 58623 | //BIF_CFG_DEV0_EPF0_VF1_0_HEADER |
|---|
| 58624 | #define 0x0 |
|---|
| 58625 | #define 0x7 |
|---|
| 58626 | #define 0x7FL |
|---|
| 58627 | #define 0x80L |
|---|
| 58628 | //BIF_CFG_DEV0_EPF0_VF1_0_BIST |
|---|
| 58629 | #define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 58630 | #define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 58631 | #define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 58632 | #define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 58633 | #define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 58634 | #define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 58635 | //BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 |
|---|
| 58636 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 58637 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 58638 | //BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 |
|---|
| 58639 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 58640 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 58641 | //BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 |
|---|
| 58642 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 58643 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 58644 | //BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 |
|---|
| 58645 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 58646 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 58647 | //BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 |
|---|
| 58648 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 58649 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 58650 | //BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 |
|---|
| 58651 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 58652 | #define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 58653 | //BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR |
|---|
| 58654 | #define BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 58655 | #define BIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 58656 | //BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID |
|---|
| 58657 | #define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 58658 | #define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 58659 | #define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 58660 | #define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 58661 | //BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR |
|---|
| 58662 | #define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 58663 | #define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 58664 | //BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR |
|---|
| 58665 | #define BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 58666 | #define BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 58667 | //BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE |
|---|
| 58668 | #define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 58669 | #define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 58670 | //BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN |
|---|
| 58671 | #define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 58672 | #define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 58673 | //BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT |
|---|
| 58674 | #define BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 58675 | #define BIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 58676 | //BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY |
|---|
| 58677 | #define BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 58678 | #define BIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 58679 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST |
|---|
| 58680 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 58681 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 58682 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 58683 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 58684 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP |
|---|
| 58685 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 58686 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 58687 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 58688 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 58689 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 58690 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 58691 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 58692 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 58693 | //BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP |
|---|
| 58694 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 58695 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 58696 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 58697 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 58698 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 58699 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 58700 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 58701 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 58702 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 58703 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 58704 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 58705 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 58706 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 58707 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 58708 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 58709 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 58710 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 58711 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 58712 | //BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL |
|---|
| 58713 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 58714 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 58715 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 58716 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 58717 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 58718 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 58719 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 58720 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 58721 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 58722 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 58723 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 58724 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 58725 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 58726 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 58727 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 58728 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 58729 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 58730 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 58731 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 58732 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 58733 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 58734 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 58735 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 58736 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 58737 | //BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS |
|---|
| 58738 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 58739 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 58740 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 58741 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 58742 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 58743 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 58744 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 58745 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 58746 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 58747 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 58748 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 58749 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 58750 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 58751 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 58752 | //BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP |
|---|
| 58753 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 58754 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 58755 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 58756 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 58757 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 58758 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 58759 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 58760 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 58761 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 58762 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 58763 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 58764 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 58765 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 58766 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 58767 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 58768 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 58769 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 58770 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 58771 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 58772 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 58773 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 58774 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 58775 | //BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL |
|---|
| 58776 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 58777 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 58778 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 58779 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 58780 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 58781 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 58782 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 58783 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 58784 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 58785 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 58786 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 58787 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 58788 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 58789 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 58790 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 58791 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 58792 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 58793 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 58794 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 58795 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 58796 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 58797 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 58798 | //BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS |
|---|
| 58799 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 58800 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 58801 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 58802 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 58803 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 58804 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 58805 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 58806 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 58807 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 58808 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 58809 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 58810 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 58811 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 58812 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 58813 | //BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 |
|---|
| 58814 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 58815 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 58816 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 58817 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 58818 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 58819 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 58820 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 58821 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 58822 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 58823 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 58824 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 58825 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 58826 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 58827 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 58828 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 58829 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 58830 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 58831 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 58832 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 58833 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 58834 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 58835 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 58836 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 58837 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 58838 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 58839 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 58840 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 58841 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 58842 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 58843 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 58844 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 58845 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 58846 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 58847 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 58848 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 58849 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 58850 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 58851 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 58852 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 58853 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 58854 | //BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 |
|---|
| 58855 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 58856 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 58857 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 58858 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 58859 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 58860 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 58861 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 58862 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 58863 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 58864 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 58865 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 58866 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 58867 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 58868 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 58869 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 58870 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 58871 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 58872 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 58873 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 58874 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 58875 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 58876 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 58877 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 58878 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 58879 | //BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 |
|---|
| 58880 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 58881 | #define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 58882 | //BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 |
|---|
| 58883 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 58884 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 58885 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 58886 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 58887 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 58888 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 58889 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 58890 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 58891 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 58892 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 58893 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 58894 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 58895 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 58896 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 58897 | //BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 |
|---|
| 58898 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 58899 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 58900 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 58901 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 58902 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 58903 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 58904 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 58905 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 58906 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 58907 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 58908 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 58909 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 58910 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 58911 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 58912 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 58913 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 58914 | //BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 |
|---|
| 58915 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 58916 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 58917 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 58918 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 58919 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 58920 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 58921 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 58922 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 58923 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 58924 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 58925 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 58926 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 58927 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 58928 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 58929 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 58930 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 58931 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 58932 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 58933 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 58934 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 58935 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 58936 | #define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 58937 | //BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST |
|---|
| 58938 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 58939 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 58940 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 58941 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 58942 | //BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL |
|---|
| 58943 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 58944 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 58945 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 58946 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 58947 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 58948 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 58949 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 58950 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 58951 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 58952 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 58953 | //BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO |
|---|
| 58954 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 58955 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 58956 | //BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI |
|---|
| 58957 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 58958 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 58959 | //BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA |
|---|
| 58960 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 58961 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 58962 | //BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK |
|---|
| 58963 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 58964 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 58965 | //BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 |
|---|
| 58966 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 58967 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 58968 | //BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 |
|---|
| 58969 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 58970 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 58971 | //BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING |
|---|
| 58972 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 58973 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 58974 | //BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 |
|---|
| 58975 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 58976 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 58977 | //BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST |
|---|
| 58978 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 58979 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 58980 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 58981 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 58982 | //BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL |
|---|
| 58983 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 58984 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 58985 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 58986 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 58987 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 58988 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 58989 | //BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE |
|---|
| 58990 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 58991 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 58992 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 58993 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 58994 | //BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA |
|---|
| 58995 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 58996 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 58997 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 58998 | #define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 58999 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 59000 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59001 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 59002 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 59003 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 59004 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 59005 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 59006 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 59007 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 59008 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 59009 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 59010 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 59011 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 59012 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 59013 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 59014 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 59015 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 59016 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 59017 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 59018 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 59019 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 59020 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59021 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 59022 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 59023 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 59024 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 59025 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 59026 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 59027 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 59028 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 59029 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 59030 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 59031 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 59032 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 59033 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 59034 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 59035 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 59036 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 59037 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 59038 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 59039 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 59040 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 59041 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 59042 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 59043 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 59044 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 59045 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 59046 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 59047 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 59048 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 59049 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 59050 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 59051 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 59052 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 59053 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 59054 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 59055 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 59056 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 59057 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 59058 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 59059 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK |
|---|
| 59060 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 59061 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 59062 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 59063 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 59064 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 59065 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 59066 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 59067 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 59068 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 59069 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 59070 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 59071 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 59072 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 59073 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 59074 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 59075 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 59076 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 59077 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 59078 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 59079 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 59080 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 59081 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 59082 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 59083 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 59084 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 59085 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 59086 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 59087 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 59088 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 59089 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 59090 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 59091 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 59092 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 59093 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 59094 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 59095 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 59096 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 59097 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 59098 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 59099 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 59100 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 59101 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 59102 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 59103 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 59104 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 59105 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 59106 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 59107 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 59108 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 59109 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 59110 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 59111 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 59112 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 59113 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 59114 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 59115 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 59116 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 59117 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 59118 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 59119 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 59120 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 59121 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 59122 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 59123 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 59124 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 59125 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS |
|---|
| 59126 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 59127 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 59128 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 59129 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 59130 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 59131 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 59132 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 59133 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 59134 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 59135 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 59136 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 59137 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 59138 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 59139 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 59140 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 59141 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 59142 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK |
|---|
| 59143 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 59144 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 59145 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 59146 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 59147 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 59148 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 59149 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 59150 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 59151 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 59152 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 59153 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 59154 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 59155 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 59156 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 59157 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 59158 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 59159 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 59160 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 59161 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 59162 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 59163 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 59164 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 59165 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 59166 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 59167 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 59168 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 59169 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 59170 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 59171 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 59172 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 59173 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 59174 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 59175 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 59176 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 59177 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 59178 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 |
|---|
| 59179 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 59180 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 59181 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 |
|---|
| 59182 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 59183 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 59184 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 |
|---|
| 59185 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 59186 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 59187 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 |
|---|
| 59188 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 59189 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 59190 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 59191 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 59192 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 59193 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 59194 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 59195 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 59196 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 59197 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 59198 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 59199 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 59200 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 59201 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 59202 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 59203 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59204 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 59205 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 59206 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 59207 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 59208 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 59209 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP |
|---|
| 59210 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 59211 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 59212 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 59213 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 59214 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 59215 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 59216 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL |
|---|
| 59217 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 59218 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 59219 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 59220 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 59221 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 59222 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59223 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 59224 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 59225 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 59226 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 59227 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 59228 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP |
|---|
| 59229 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 59230 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 59231 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 59232 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 59233 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 59234 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 59235 | //BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL |
|---|
| 59236 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 59237 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 59238 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 59239 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 59240 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 59241 | #define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 59242 | |
|---|
| 59243 | |
|---|
| 59244 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp |
|---|
| 59245 | //BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID |
|---|
| 59246 | #define BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 59247 | #define BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 59248 | //BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID |
|---|
| 59249 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 59250 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 59251 | //BIF_CFG_DEV0_EPF0_VF2_0_COMMAND |
|---|
| 59252 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 59253 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 59254 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 59255 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 59256 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 59257 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 59258 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 59259 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 59260 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 59261 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 59262 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 59263 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 59264 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 59265 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 59266 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 59267 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 59268 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 59269 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 59270 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 59271 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 59272 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 59273 | #define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 59274 | //BIF_CFG_DEV0_EPF0_VF2_0_STATUS |
|---|
| 59275 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 59276 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 59277 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 59278 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 59279 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 59280 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 59281 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 59282 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 59283 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 59284 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 59285 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 59286 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 59287 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 59288 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 59289 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 59290 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 59291 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 59292 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 59293 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 59294 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 59295 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 59296 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 59297 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 59298 | #define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 59299 | //BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID |
|---|
| 59300 | #define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 59301 | #define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 59302 | #define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 59303 | #define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 59304 | //BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE |
|---|
| 59305 | #define BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 59306 | #define BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 59307 | //BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS |
|---|
| 59308 | #define BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 59309 | #define BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 59310 | //BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS |
|---|
| 59311 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 59312 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 59313 | //BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE |
|---|
| 59314 | #define BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 59315 | #define BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 59316 | //BIF_CFG_DEV0_EPF0_VF2_0_LATENCY |
|---|
| 59317 | #define BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 59318 | #define BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 59319 | //BIF_CFG_DEV0_EPF0_VF2_0_HEADER |
|---|
| 59320 | #define 0x0 |
|---|
| 59321 | #define 0x7 |
|---|
| 59322 | #define 0x7FL |
|---|
| 59323 | #define 0x80L |
|---|
| 59324 | //BIF_CFG_DEV0_EPF0_VF2_0_BIST |
|---|
| 59325 | #define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 59326 | #define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 59327 | #define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 59328 | #define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 59329 | #define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 59330 | #define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 59331 | //BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 |
|---|
| 59332 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 59333 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 59334 | //BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 |
|---|
| 59335 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 59336 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 59337 | //BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 |
|---|
| 59338 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 59339 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 59340 | //BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 |
|---|
| 59341 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 59342 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 59343 | //BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 |
|---|
| 59344 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 59345 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 59346 | //BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 |
|---|
| 59347 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 59348 | #define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 59349 | //BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR |
|---|
| 59350 | #define BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 59351 | #define BIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 59352 | //BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID |
|---|
| 59353 | #define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 59354 | #define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 59355 | #define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 59356 | #define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 59357 | //BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR |
|---|
| 59358 | #define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 59359 | #define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 59360 | //BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR |
|---|
| 59361 | #define BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 59362 | #define BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 59363 | //BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE |
|---|
| 59364 | #define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 59365 | #define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 59366 | //BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN |
|---|
| 59367 | #define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 59368 | #define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 59369 | //BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT |
|---|
| 59370 | #define BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 59371 | #define BIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 59372 | //BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY |
|---|
| 59373 | #define BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 59374 | #define BIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 59375 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST |
|---|
| 59376 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59377 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 59378 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 59379 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 59380 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP |
|---|
| 59381 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 59382 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 59383 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 59384 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 59385 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 59386 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 59387 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 59388 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 59389 | //BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP |
|---|
| 59390 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 59391 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 59392 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 59393 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 59394 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 59395 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 59396 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 59397 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 59398 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 59399 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 59400 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 59401 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 59402 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 59403 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 59404 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 59405 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 59406 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 59407 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 59408 | //BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL |
|---|
| 59409 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 59410 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 59411 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 59412 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 59413 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 59414 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 59415 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 59416 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 59417 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 59418 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 59419 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 59420 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 59421 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 59422 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 59423 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 59424 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 59425 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 59426 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 59427 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 59428 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 59429 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 59430 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 59431 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 59432 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 59433 | //BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS |
|---|
| 59434 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 59435 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 59436 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 59437 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 59438 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 59439 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 59440 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 59441 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 59442 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 59443 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 59444 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 59445 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 59446 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 59447 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 59448 | //BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP |
|---|
| 59449 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 59450 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 59451 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 59452 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 59453 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 59454 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 59455 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 59456 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 59457 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 59458 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 59459 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 59460 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 59461 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 59462 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 59463 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 59464 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 59465 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 59466 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 59467 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 59468 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 59469 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 59470 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 59471 | //BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL |
|---|
| 59472 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 59473 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 59474 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 59475 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 59476 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 59477 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 59478 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 59479 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 59480 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 59481 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 59482 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 59483 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 59484 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 59485 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 59486 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 59487 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 59488 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 59489 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 59490 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 59491 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 59492 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 59493 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 59494 | //BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS |
|---|
| 59495 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 59496 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 59497 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 59498 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 59499 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 59500 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 59501 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 59502 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 59503 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 59504 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 59505 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 59506 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 59507 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 59508 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 59509 | //BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 |
|---|
| 59510 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 59511 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 59512 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 59513 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 59514 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 59515 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 59516 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 59517 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 59518 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 59519 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 59520 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 59521 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 59522 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 59523 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 59524 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 59525 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 59526 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 59527 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 59528 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 59529 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 59530 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 59531 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 59532 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 59533 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 59534 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 59535 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 59536 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 59537 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 59538 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 59539 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 59540 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 59541 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 59542 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 59543 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 59544 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 59545 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 59546 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 59547 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 59548 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 59549 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 59550 | //BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 |
|---|
| 59551 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 59552 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 59553 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 59554 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 59555 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 59556 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 59557 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 59558 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 59559 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 59560 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 59561 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 59562 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 59563 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 59564 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 59565 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 59566 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 59567 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 59568 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 59569 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 59570 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 59571 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 59572 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 59573 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 59574 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 59575 | //BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 |
|---|
| 59576 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 59577 | #define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 59578 | //BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 |
|---|
| 59579 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 59580 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 59581 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 59582 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 59583 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 59584 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 59585 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 59586 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 59587 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 59588 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 59589 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 59590 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 59591 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 59592 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 59593 | //BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 |
|---|
| 59594 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 59595 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 59596 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 59597 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 59598 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 59599 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 59600 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 59601 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 59602 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 59603 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 59604 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 59605 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 59606 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 59607 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 59608 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 59609 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 59610 | //BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 |
|---|
| 59611 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 59612 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 59613 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 59614 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 59615 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 59616 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 59617 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 59618 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 59619 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 59620 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 59621 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 59622 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 59623 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 59624 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 59625 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 59626 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 59627 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 59628 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 59629 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 59630 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 59631 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 59632 | #define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 59633 | //BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST |
|---|
| 59634 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59635 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 59636 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 59637 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 59638 | //BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL |
|---|
| 59639 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 59640 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 59641 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 59642 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 59643 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 59644 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 59645 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 59646 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 59647 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 59648 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 59649 | //BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO |
|---|
| 59650 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 59651 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 59652 | //BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI |
|---|
| 59653 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 59654 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 59655 | //BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA |
|---|
| 59656 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 59657 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 59658 | //BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK |
|---|
| 59659 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 59660 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 59661 | //BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 |
|---|
| 59662 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 59663 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 59664 | //BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 |
|---|
| 59665 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 59666 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 59667 | //BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING |
|---|
| 59668 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 59669 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 59670 | //BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 |
|---|
| 59671 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 59672 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 59673 | //BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST |
|---|
| 59674 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59675 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 59676 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 59677 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 59678 | //BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL |
|---|
| 59679 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 59680 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 59681 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 59682 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 59683 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 59684 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 59685 | //BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE |
|---|
| 59686 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 59687 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 59688 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 59689 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 59690 | //BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA |
|---|
| 59691 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 59692 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 59693 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 59694 | #define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 59695 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 59696 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59697 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 59698 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 59699 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 59700 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 59701 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 59702 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 59703 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 59704 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 59705 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 59706 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 59707 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 59708 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 59709 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 59710 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 59711 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 59712 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 59713 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 59714 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 59715 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 59716 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59717 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 59718 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 59719 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 59720 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 59721 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 59722 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 59723 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 59724 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 59725 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 59726 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 59727 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 59728 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 59729 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 59730 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 59731 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 59732 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 59733 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 59734 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 59735 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 59736 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 59737 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 59738 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 59739 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 59740 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 59741 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 59742 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 59743 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 59744 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 59745 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 59746 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 59747 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 59748 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 59749 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 59750 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 59751 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 59752 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 59753 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 59754 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 59755 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK |
|---|
| 59756 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 59757 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 59758 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 59759 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 59760 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 59761 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 59762 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 59763 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 59764 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 59765 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 59766 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 59767 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 59768 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 59769 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 59770 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 59771 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 59772 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 59773 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 59774 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 59775 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 59776 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 59777 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 59778 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 59779 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 59780 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 59781 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 59782 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 59783 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 59784 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 59785 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 59786 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 59787 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 59788 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 59789 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 59790 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 59791 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 59792 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 59793 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 59794 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 59795 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 59796 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 59797 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 59798 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 59799 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 59800 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 59801 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 59802 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 59803 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 59804 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 59805 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 59806 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 59807 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 59808 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 59809 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 59810 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 59811 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 59812 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 59813 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 59814 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 59815 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 59816 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 59817 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 59818 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 59819 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 59820 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 59821 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS |
|---|
| 59822 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 59823 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 59824 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 59825 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 59826 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 59827 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 59828 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 59829 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 59830 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 59831 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 59832 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 59833 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 59834 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 59835 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 59836 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 59837 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 59838 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK |
|---|
| 59839 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 59840 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 59841 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 59842 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 59843 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 59844 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 59845 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 59846 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 59847 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 59848 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 59849 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 59850 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 59851 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 59852 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 59853 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 59854 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 59855 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 59856 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 59857 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 59858 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 59859 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 59860 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 59861 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 59862 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 59863 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 59864 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 59865 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 59866 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 59867 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 59868 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 59869 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 59870 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 59871 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 59872 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 59873 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 59874 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 |
|---|
| 59875 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 59876 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 59877 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 |
|---|
| 59878 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 59879 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 59880 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 |
|---|
| 59881 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 59882 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 59883 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 |
|---|
| 59884 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 59885 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 59886 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 59887 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 59888 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 59889 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 59890 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 59891 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 59892 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 59893 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 59894 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 59895 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 59896 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 59897 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 59898 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 59899 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59900 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 59901 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 59902 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 59903 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 59904 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 59905 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP |
|---|
| 59906 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 59907 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 59908 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 59909 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 59910 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 59911 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 59912 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL |
|---|
| 59913 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 59914 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 59915 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 59916 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 59917 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 59918 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 59919 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 59920 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 59921 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 59922 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 59923 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 59924 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP |
|---|
| 59925 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 59926 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 59927 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 59928 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 59929 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 59930 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 59931 | //BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL |
|---|
| 59932 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 59933 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 59934 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 59935 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 59936 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 59937 | #define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 59938 | |
|---|
| 59939 | |
|---|
| 59940 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp |
|---|
| 59941 | //BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID |
|---|
| 59942 | #define BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 59943 | #define BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 59944 | //BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID |
|---|
| 59945 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 59946 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 59947 | //BIF_CFG_DEV0_EPF0_VF3_0_COMMAND |
|---|
| 59948 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 59949 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 59950 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 59951 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 59952 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 59953 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 59954 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 59955 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 59956 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 59957 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 59958 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 59959 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 59960 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 59961 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 59962 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 59963 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 59964 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 59965 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 59966 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 59967 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 59968 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 59969 | #define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 59970 | //BIF_CFG_DEV0_EPF0_VF3_0_STATUS |
|---|
| 59971 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 59972 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 59973 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 59974 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 59975 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 59976 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 59977 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 59978 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 59979 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 59980 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 59981 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 59982 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 59983 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 59984 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 59985 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 59986 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 59987 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 59988 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 59989 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 59990 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 59991 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 59992 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 59993 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 59994 | #define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 59995 | //BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID |
|---|
| 59996 | #define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 59997 | #define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 59998 | #define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 59999 | #define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 60000 | //BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE |
|---|
| 60001 | #define BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 60002 | #define BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 60003 | //BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS |
|---|
| 60004 | #define BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 60005 | #define BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 60006 | //BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS |
|---|
| 60007 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 60008 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 60009 | //BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE |
|---|
| 60010 | #define BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 60011 | #define BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 60012 | //BIF_CFG_DEV0_EPF0_VF3_0_LATENCY |
|---|
| 60013 | #define BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 60014 | #define BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 60015 | //BIF_CFG_DEV0_EPF0_VF3_0_HEADER |
|---|
| 60016 | #define 0x0 |
|---|
| 60017 | #define 0x7 |
|---|
| 60018 | #define 0x7FL |
|---|
| 60019 | #define 0x80L |
|---|
| 60020 | //BIF_CFG_DEV0_EPF0_VF3_0_BIST |
|---|
| 60021 | #define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 60022 | #define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 60023 | #define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 60024 | #define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 60025 | #define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 60026 | #define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 60027 | //BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 |
|---|
| 60028 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 60029 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60030 | //BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 |
|---|
| 60031 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 60032 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60033 | //BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 |
|---|
| 60034 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 60035 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60036 | //BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 |
|---|
| 60037 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 60038 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60039 | //BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 |
|---|
| 60040 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 60041 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 60042 | //BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 |
|---|
| 60043 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 60044 | #define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60045 | //BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR |
|---|
| 60046 | #define BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 60047 | #define BIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
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| 60048 | //BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID |
|---|
| 60049 | #define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 60050 | #define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 60051 | #define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 60052 | #define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 60053 | //BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR |
|---|
| 60054 | #define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 60055 | #define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60056 | //BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR |
|---|
| 60057 | #define BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 60058 | #define BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 60059 | //BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE |
|---|
| 60060 | #define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 60061 | #define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 60062 | //BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN |
|---|
| 60063 | #define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 60064 | #define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 60065 | //BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT |
|---|
| 60066 | #define BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 60067 | #define BIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 60068 | //BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY |
|---|
| 60069 | #define BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 60070 | #define BIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 60071 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST |
|---|
| 60072 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 60073 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 60074 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 60075 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 60076 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP |
|---|
| 60077 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 60078 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 60079 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 60080 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 60081 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 60082 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 60083 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 60084 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 60085 | //BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP |
|---|
| 60086 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 60087 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 60088 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 60089 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 60090 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 60091 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 60092 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 60093 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 60094 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 60095 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 60096 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 60097 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 60098 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 60099 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 60100 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 60101 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 60102 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 60103 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 60104 | //BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL |
|---|
| 60105 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 60106 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 60107 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 60108 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 60109 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 60110 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 60111 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 60112 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 60113 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 60114 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 60115 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 60116 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 60117 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 60118 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 60119 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 60120 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 60121 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 60122 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 60123 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 60124 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 60125 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 60126 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 60127 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 60128 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 60129 | //BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS |
|---|
| 60130 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 60131 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 60132 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 60133 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 60134 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 60135 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 60136 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 60137 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 60138 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 60139 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 60140 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 60141 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 60142 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 60143 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 60144 | //BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP |
|---|
| 60145 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 60146 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 60147 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 60148 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 60149 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 60150 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 60151 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 60152 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 60153 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 60154 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 60155 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 60156 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 60157 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 60158 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 60159 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 60160 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 60161 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 60162 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 60163 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 60164 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 60165 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 60166 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 60167 | //BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL |
|---|
| 60168 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 60169 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 60170 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 60171 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 60172 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 60173 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 60174 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 60175 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 60176 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 60177 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 60178 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 60179 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 60180 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 60181 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 60182 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 60183 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 60184 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 60185 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 60186 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 60187 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 60188 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 60189 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 60190 | //BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS |
|---|
| 60191 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 60192 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 60193 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 60194 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 60195 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 60196 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 60197 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 60198 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 60199 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 60200 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 60201 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 60202 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 60203 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 60204 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 60205 | //BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 |
|---|
| 60206 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 60207 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 60208 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 60209 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 60210 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 60211 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 60212 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 60213 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 60214 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 60215 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 60216 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 60217 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 60218 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 60219 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 60220 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 60221 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 60222 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 60223 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 60224 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 60225 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 60226 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 60227 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 60228 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 60229 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 60230 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 60231 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 60232 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 60233 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 60234 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 60235 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 60236 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 60237 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 60238 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 60239 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 60240 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 60241 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 60242 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 60243 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 60244 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 60245 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 60246 | //BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 |
|---|
| 60247 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 60248 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 60249 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 60250 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 60251 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 60252 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 60253 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 60254 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 60255 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 60256 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 60257 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 60258 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 60259 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 60260 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 60261 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 60262 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 60263 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 60264 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 60265 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 60266 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 60267 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 60268 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 60269 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 60270 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 60271 | //BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 |
|---|
| 60272 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 60273 | #define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 60274 | //BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 |
|---|
| 60275 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 60276 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 60277 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 60278 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 60279 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 60280 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 60281 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 60282 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 60283 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 60284 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 60285 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 60286 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 60287 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 60288 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 60289 | //BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 |
|---|
| 60290 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 60291 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 60292 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 60293 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 60294 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 60295 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 60296 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 60297 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 60298 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 60299 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 60300 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 60301 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 60302 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 60303 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 60304 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 60305 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 60306 | //BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 |
|---|
| 60307 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 60308 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 60309 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 60310 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 60311 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 60312 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 60313 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 60314 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 60315 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 60316 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 60317 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 60318 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 60319 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 60320 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 60321 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 60322 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 60323 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 60324 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 60325 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 60326 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 60327 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 60328 | #define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 60329 | //BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST |
|---|
| 60330 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 60331 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 60332 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 60333 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 60334 | //BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL |
|---|
| 60335 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 60336 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 60337 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 60338 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 60339 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 60340 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 60341 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 60342 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 60343 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 60344 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 60345 | //BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO |
|---|
| 60346 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 60347 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 60348 | //BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI |
|---|
| 60349 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 60350 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 60351 | //BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA |
|---|
| 60352 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 60353 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 60354 | //BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK |
|---|
| 60355 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 60356 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 60357 | //BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 |
|---|
| 60358 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 60359 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 60360 | //BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 |
|---|
| 60361 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 60362 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 60363 | //BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING |
|---|
| 60364 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 60365 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 60366 | //BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 |
|---|
| 60367 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 60368 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 60369 | //BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST |
|---|
| 60370 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 60371 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 60372 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 60373 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 60374 | //BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL |
|---|
| 60375 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 60376 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 60377 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 60378 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 60379 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 60380 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 60381 | //BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE |
|---|
| 60382 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 60383 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 60384 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 60385 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 60386 | //BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA |
|---|
| 60387 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 60388 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 60389 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 60390 | #define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 60391 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 60392 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 60393 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 60394 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 60395 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 60396 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 60397 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 60398 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 60399 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 60400 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 60401 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 60402 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 60403 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 60404 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 60405 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 60406 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 60407 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 60408 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 60409 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 60410 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 60411 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 60412 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 60413 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 60414 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 60415 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 60416 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 60417 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 60418 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 60419 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 60420 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 60421 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 60422 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 60423 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 60424 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 60425 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 60426 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 60427 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 60428 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 60429 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 60430 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 60431 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 60432 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 60433 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 60434 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 60435 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 60436 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 60437 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 60438 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 60439 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 60440 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 60441 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 60442 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 60443 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 60444 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 60445 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 60446 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 60447 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 60448 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 60449 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 60450 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 60451 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK |
|---|
| 60452 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 60453 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 60454 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 60455 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 60456 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 60457 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 60458 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 60459 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 60460 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 60461 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 60462 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 60463 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 60464 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 60465 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 60466 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 60467 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 60468 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 60469 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 60470 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 60471 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 60472 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 60473 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 60474 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 60475 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 60476 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 60477 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 60478 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 60479 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 60480 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 60481 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 60482 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 60483 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 60484 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 60485 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 60486 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 60487 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 60488 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 60489 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 60490 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 60491 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 60492 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 60493 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 60494 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 60495 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 60496 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 60497 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 60498 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 60499 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 60500 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 60501 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 60502 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 60503 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 60504 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 60505 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 60506 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 60507 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 60508 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 60509 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 60510 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 60511 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 60512 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 60513 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 60514 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 60515 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 60516 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 60517 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS |
|---|
| 60518 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 60519 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 60520 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 60521 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 60522 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 60523 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 60524 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 60525 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 60526 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 60527 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 60528 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 60529 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 60530 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 60531 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 60532 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 60533 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 60534 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK |
|---|
| 60535 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 60536 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 60537 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 60538 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 60539 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 60540 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 60541 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 60542 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 60543 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 60544 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 60545 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 60546 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 60547 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 60548 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 60549 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 60550 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 60551 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 60552 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 60553 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 60554 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 60555 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 60556 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 60557 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 60558 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 60559 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 60560 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 60561 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 60562 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 60563 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 60564 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 60565 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 60566 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 60567 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 60568 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 60569 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 60570 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 |
|---|
| 60571 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 60572 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 60573 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 |
|---|
| 60574 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 60575 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 60576 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 |
|---|
| 60577 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 60578 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 60579 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 |
|---|
| 60580 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 60581 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 60582 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 60583 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 60584 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 60585 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 60586 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 60587 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 60588 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 60589 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 60590 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 60591 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 60592 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 60593 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 60594 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 60595 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 60596 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 60597 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 60598 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 60599 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 60600 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 60601 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP |
|---|
| 60602 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 60603 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 60604 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 60605 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 60606 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 60607 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 60608 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL |
|---|
| 60609 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 60610 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 60611 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 60612 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 60613 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 60614 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 60615 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 60616 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 60617 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 60618 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 60619 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 60620 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP |
|---|
| 60621 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 60622 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 60623 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 60624 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 60625 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 60626 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 60627 | //BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL |
|---|
| 60628 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 60629 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 60630 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 60631 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 60632 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 60633 | #define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 60634 | |
|---|
| 60635 | |
|---|
| 60636 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp |
|---|
| 60637 | //BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID |
|---|
| 60638 | #define BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 60639 | #define BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 60640 | //BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID |
|---|
| 60641 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 60642 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 60643 | //BIF_CFG_DEV0_EPF0_VF4_0_COMMAND |
|---|
| 60644 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 60645 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 60646 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 60647 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 60648 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 60649 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 60650 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 60651 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 60652 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 60653 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 60654 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 60655 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 60656 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 60657 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 60658 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 60659 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 60660 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 60661 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 60662 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 60663 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 60664 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 60665 | #define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 60666 | //BIF_CFG_DEV0_EPF0_VF4_0_STATUS |
|---|
| 60667 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 60668 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 60669 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 60670 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 60671 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 60672 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 60673 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 60674 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 60675 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 60676 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 60677 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 60678 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 60679 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 60680 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 60681 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 60682 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 60683 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 60684 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 60685 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 60686 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 60687 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 60688 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 60689 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 60690 | #define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 60691 | //BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID |
|---|
| 60692 | #define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 60693 | #define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 60694 | #define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 60695 | #define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 60696 | //BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE |
|---|
| 60697 | #define BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 60698 | #define BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 60699 | //BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS |
|---|
| 60700 | #define BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 60701 | #define BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 60702 | //BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS |
|---|
| 60703 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 60704 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 60705 | //BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE |
|---|
| 60706 | #define BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 60707 | #define BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 60708 | //BIF_CFG_DEV0_EPF0_VF4_0_LATENCY |
|---|
| 60709 | #define BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 60710 | #define BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 60711 | //BIF_CFG_DEV0_EPF0_VF4_0_HEADER |
|---|
| 60712 | #define 0x0 |
|---|
| 60713 | #define 0x7 |
|---|
| 60714 | #define 0x7FL |
|---|
| 60715 | #define 0x80L |
|---|
| 60716 | //BIF_CFG_DEV0_EPF0_VF4_0_BIST |
|---|
| 60717 | #define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 60718 | #define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 60719 | #define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 60720 | #define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 60721 | #define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 60722 | #define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 60723 | //BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 |
|---|
| 60724 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 60725 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60726 | //BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 |
|---|
| 60727 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 60728 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60729 | //BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 |
|---|
| 60730 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 60731 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60732 | //BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 |
|---|
| 60733 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 60734 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60735 | //BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 |
|---|
| 60736 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 60737 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60738 | //BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 |
|---|
| 60739 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 60740 | #define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60741 | //BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR |
|---|
| 60742 | #define BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 60743 | #define BIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 60744 | //BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID |
|---|
| 60745 | #define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 60746 | #define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 60747 | #define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 60748 | #define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 60749 | //BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR |
|---|
| 60750 | #define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 60751 | #define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 60752 | //BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR |
|---|
| 60753 | #define BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 60754 | #define BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 60755 | //BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE |
|---|
| 60756 | #define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 60757 | #define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 60758 | //BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN |
|---|
| 60759 | #define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 60760 | #define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 60761 | //BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT |
|---|
| 60762 | #define BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 60763 | #define BIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 60764 | //BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY |
|---|
| 60765 | #define BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 60766 | #define BIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 60767 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST |
|---|
| 60768 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 60769 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 60770 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 60771 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 60772 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP |
|---|
| 60773 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 60774 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 60775 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 60776 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 60777 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 60778 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 60779 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 60780 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 60781 | //BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP |
|---|
| 60782 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 60783 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 60784 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 60785 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 60786 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 60787 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 60788 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 60789 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 60790 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 60791 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 60792 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 60793 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 60794 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 60795 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 60796 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 60797 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 60798 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 60799 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 60800 | //BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL |
|---|
| 60801 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 60802 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 60803 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 60804 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 60805 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 60806 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 60807 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 60808 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 60809 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 60810 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 60811 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 60812 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 60813 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 60814 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 60815 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 60816 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 60817 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 60818 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 60819 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 60820 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 60821 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 60822 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 60823 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 60824 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 60825 | //BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS |
|---|
| 60826 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 60827 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 60828 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 60829 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 60830 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 60831 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 60832 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 60833 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 60834 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 60835 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 60836 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 60837 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 60838 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 60839 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 60840 | //BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP |
|---|
| 60841 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 60842 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 60843 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 60844 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 60845 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 60846 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 60847 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 60848 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 60849 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 60850 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 60851 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 60852 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 60853 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 60854 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 60855 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 60856 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 60857 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 60858 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 60859 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 60860 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 60861 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 60862 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 60863 | //BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL |
|---|
| 60864 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 60865 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 60866 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 60867 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 60868 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 60869 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 60870 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 60871 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 60872 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 60873 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 60874 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 60875 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 60876 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 60877 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 60878 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 60879 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 60880 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 60881 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 60882 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 60883 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 60884 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 60885 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 60886 | //BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS |
|---|
| 60887 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 60888 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 60889 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 60890 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 60891 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 60892 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 60893 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 60894 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 60895 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 60896 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 60897 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 60898 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 60899 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 60900 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 60901 | //BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 |
|---|
| 60902 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 60903 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 60904 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 60905 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 60906 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 60907 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 60908 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 60909 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 60910 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 60911 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 60912 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 60913 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 60914 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 60915 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 60916 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 60917 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 60918 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 60919 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 60920 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 60921 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 60922 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 60923 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 60924 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 60925 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 60926 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 60927 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 60928 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 60929 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 60930 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 60931 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 60932 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 60933 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 60934 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 60935 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 60936 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 60937 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 60938 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 60939 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 60940 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 60941 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 60942 | //BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 |
|---|
| 60943 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 60944 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 60945 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 60946 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 60947 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 60948 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 60949 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 60950 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 60951 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 60952 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 60953 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 60954 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 60955 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 60956 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 60957 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 60958 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 60959 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 60960 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 60961 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 60962 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 60963 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 60964 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 60965 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 60966 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 60967 | //BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 |
|---|
| 60968 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 60969 | #define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 60970 | //BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 |
|---|
| 60971 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 60972 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 60973 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 60974 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 60975 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 60976 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 60977 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 60978 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 60979 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 60980 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 60981 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 60982 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 60983 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 60984 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 60985 | //BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 |
|---|
| 60986 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 60987 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 60988 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 60989 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 60990 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 60991 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 60992 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 60993 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 60994 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 60995 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 60996 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 60997 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 60998 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 60999 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 61000 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 61001 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 61002 | //BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 |
|---|
| 61003 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 61004 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 61005 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 61006 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 61007 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 61008 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 61009 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 61010 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 61011 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 61012 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 61013 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 61014 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 61015 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 61016 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 61017 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 61018 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 61019 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 61020 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 61021 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 61022 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 61023 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 61024 | #define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 61025 | //BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST |
|---|
| 61026 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61027 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 61028 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 61029 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 61030 | //BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL |
|---|
| 61031 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 61032 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 61033 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 61034 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 61035 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 61036 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 61037 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 61038 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 61039 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 61040 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 61041 | //BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO |
|---|
| 61042 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 61043 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 61044 | //BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI |
|---|
| 61045 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 61046 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 61047 | //BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA |
|---|
| 61048 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 61049 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 61050 | //BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK |
|---|
| 61051 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 61052 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 61053 | //BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 |
|---|
| 61054 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 61055 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 61056 | //BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 |
|---|
| 61057 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 61058 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 61059 | //BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING |
|---|
| 61060 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 61061 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 61062 | //BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 |
|---|
| 61063 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 61064 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 61065 | //BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST |
|---|
| 61066 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61067 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 61068 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 61069 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 61070 | //BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL |
|---|
| 61071 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 61072 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 61073 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 61074 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 61075 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 61076 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 61077 | //BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE |
|---|
| 61078 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 61079 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 61080 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 61081 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 61082 | //BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA |
|---|
| 61083 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 61084 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 61085 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 61086 | #define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 61087 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 61088 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61089 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 61090 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 61091 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 61092 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 61093 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 61094 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 61095 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 61096 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 61097 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 61098 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 61099 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 61100 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 61101 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 61102 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 61103 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 61104 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 61105 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 61106 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 61107 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 61108 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61109 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 61110 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 61111 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 61112 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 61113 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 61114 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 61115 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 61116 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 61117 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 61118 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 61119 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 61120 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 61121 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 61122 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 61123 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 61124 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 61125 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 61126 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 61127 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 61128 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 61129 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 61130 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 61131 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 61132 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 61133 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 61134 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 61135 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 61136 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 61137 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 61138 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 61139 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 61140 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 61141 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 61142 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 61143 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 61144 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 61145 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 61146 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 61147 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK |
|---|
| 61148 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 61149 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 61150 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 61151 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 61152 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 61153 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 61154 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 61155 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 61156 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 61157 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 61158 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 61159 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 61160 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 61161 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 61162 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 61163 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 61164 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 61165 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 61166 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 61167 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 61168 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 61169 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 61170 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 61171 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 61172 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 61173 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 61174 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 61175 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 61176 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 61177 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 61178 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 61179 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 61180 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 61181 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 61182 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 61183 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 61184 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 61185 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 61186 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 61187 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 61188 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 61189 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 61190 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 61191 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 61192 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 61193 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 61194 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 61195 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 61196 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 61197 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 61198 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 61199 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 61200 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 61201 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 61202 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 61203 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 61204 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 61205 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 61206 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 61207 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 61208 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 61209 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 61210 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 61211 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 61212 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 61213 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS |
|---|
| 61214 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 61215 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 61216 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 61217 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 61218 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 61219 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 61220 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 61221 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 61222 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 61223 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 61224 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 61225 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 61226 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 61227 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 61228 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 61229 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 61230 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK |
|---|
| 61231 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 61232 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 61233 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 61234 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 61235 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 61236 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 61237 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 61238 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 61239 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 61240 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 61241 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 61242 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 61243 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 61244 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 61245 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 61246 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 61247 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 61248 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 61249 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 61250 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 61251 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 61252 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 61253 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 61254 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 61255 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 61256 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 61257 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 61258 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 61259 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 61260 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 61261 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 61262 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 61263 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 61264 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 61265 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 61266 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 |
|---|
| 61267 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 61268 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 61269 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 |
|---|
| 61270 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 61271 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 61272 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 |
|---|
| 61273 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 61274 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 61275 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 |
|---|
| 61276 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 61277 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 61278 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 61279 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 61280 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 61281 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 61282 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 61283 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 61284 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 61285 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 61286 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 61287 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 61288 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 61289 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 61290 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 61291 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61292 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 61293 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 61294 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 61295 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 61296 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 61297 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP |
|---|
| 61298 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 61299 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 61300 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 61301 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 61302 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 61303 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 61304 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL |
|---|
| 61305 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 61306 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 61307 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 61308 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 61309 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 61310 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61311 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 61312 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 61313 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 61314 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 61315 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 61316 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP |
|---|
| 61317 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 61318 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 61319 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 61320 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 61321 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 61322 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 61323 | //BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL |
|---|
| 61324 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 61325 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 61326 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 61327 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 61328 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 61329 | #define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 61330 | |
|---|
| 61331 | |
|---|
| 61332 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp |
|---|
| 61333 | //BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID |
|---|
| 61334 | #define BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 61335 | #define BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 61336 | //BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID |
|---|
| 61337 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 61338 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 61339 | //BIF_CFG_DEV0_EPF0_VF5_0_COMMAND |
|---|
| 61340 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 61341 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 61342 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 61343 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 61344 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 61345 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 61346 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 61347 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 61348 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 61349 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 61350 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 61351 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 61352 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 61353 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 61354 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 61355 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 61356 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 61357 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 61358 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 61359 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 61360 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 61361 | #define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 61362 | //BIF_CFG_DEV0_EPF0_VF5_0_STATUS |
|---|
| 61363 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 61364 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 61365 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 61366 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 61367 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 61368 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 61369 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 61370 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 61371 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 61372 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 61373 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 61374 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 61375 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 61376 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 61377 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 61378 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 61379 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 61380 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 61381 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 61382 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 61383 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 61384 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 61385 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 61386 | #define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 61387 | //BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID |
|---|
| 61388 | #define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 61389 | #define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 61390 | #define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 61391 | #define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 61392 | //BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE |
|---|
| 61393 | #define BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 61394 | #define BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 61395 | //BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS |
|---|
| 61396 | #define BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 61397 | #define BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 61398 | //BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS |
|---|
| 61399 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 61400 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 61401 | //BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE |
|---|
| 61402 | #define BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 61403 | #define BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 61404 | //BIF_CFG_DEV0_EPF0_VF5_0_LATENCY |
|---|
| 61405 | #define BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 61406 | #define BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 61407 | //BIF_CFG_DEV0_EPF0_VF5_0_HEADER |
|---|
| 61408 | #define 0x0 |
|---|
| 61409 | #define 0x7 |
|---|
| 61410 | #define 0x7FL |
|---|
| 61411 | #define 0x80L |
|---|
| 61412 | //BIF_CFG_DEV0_EPF0_VF5_0_BIST |
|---|
| 61413 | #define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 61414 | #define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 61415 | #define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 61416 | #define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 61417 | #define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 61418 | #define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 61419 | //BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 |
|---|
| 61420 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 61421 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 61422 | //BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 |
|---|
| 61423 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 61424 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 61425 | //BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 |
|---|
| 61426 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 61427 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 61428 | //BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 |
|---|
| 61429 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 61430 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 61431 | //BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 |
|---|
| 61432 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 61433 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 61434 | //BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 |
|---|
| 61435 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 61436 | #define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 61437 | //BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR |
|---|
| 61438 | #define BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 61439 | #define BIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 61440 | //BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID |
|---|
| 61441 | #define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 61442 | #define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 61443 | #define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 61444 | #define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 61445 | //BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR |
|---|
| 61446 | #define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 61447 | #define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 61448 | //BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR |
|---|
| 61449 | #define BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 61450 | #define BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 61451 | //BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE |
|---|
| 61452 | #define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 61453 | #define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 61454 | //BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN |
|---|
| 61455 | #define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 61456 | #define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 61457 | //BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT |
|---|
| 61458 | #define BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 61459 | #define BIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 61460 | //BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY |
|---|
| 61461 | #define BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 61462 | #define BIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 61463 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST |
|---|
| 61464 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61465 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 61466 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 61467 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 61468 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP |
|---|
| 61469 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 61470 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 61471 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 61472 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 61473 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 61474 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 61475 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 61476 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 61477 | //BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP |
|---|
| 61478 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 61479 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 61480 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 61481 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 61482 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 61483 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 61484 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 61485 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 61486 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 61487 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 61488 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 61489 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 61490 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 61491 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 61492 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 61493 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 61494 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 61495 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 61496 | //BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL |
|---|
| 61497 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 61498 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 61499 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 61500 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 61501 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 61502 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 61503 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 61504 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 61505 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 61506 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 61507 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 61508 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 61509 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 61510 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 61511 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 61512 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 61513 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 61514 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 61515 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 61516 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 61517 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 61518 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 61519 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 61520 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 61521 | //BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS |
|---|
| 61522 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 61523 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 61524 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 61525 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 61526 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 61527 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 61528 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 61529 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 61530 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 61531 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 61532 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 61533 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 61534 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 61535 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 61536 | //BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP |
|---|
| 61537 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 61538 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 61539 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 61540 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 61541 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 61542 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 61543 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 61544 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 61545 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 61546 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 61547 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 61548 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 61549 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 61550 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 61551 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 61552 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 61553 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 61554 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 61555 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 61556 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 61557 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 61558 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 61559 | //BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL |
|---|
| 61560 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 61561 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 61562 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 61563 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 61564 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 61565 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 61566 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 61567 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 61568 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 61569 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 61570 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 61571 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 61572 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 61573 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 61574 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 61575 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 61576 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 61577 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 61578 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 61579 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 61580 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 61581 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 61582 | //BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS |
|---|
| 61583 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 61584 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 61585 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 61586 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 61587 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 61588 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 61589 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 61590 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 61591 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 61592 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 61593 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 61594 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 61595 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 61596 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 61597 | //BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 |
|---|
| 61598 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 61599 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 61600 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 61601 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 61602 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 61603 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 61604 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 61605 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 61606 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 61607 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 61608 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 61609 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 61610 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 61611 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 61612 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 61613 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 61614 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 61615 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 61616 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 61617 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 61618 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 61619 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 61620 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 61621 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 61622 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 61623 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 61624 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 61625 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 61626 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 61627 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 61628 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 61629 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 61630 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 61631 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 61632 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 61633 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 61634 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 61635 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 61636 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 61637 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 61638 | //BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 |
|---|
| 61639 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 61640 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 61641 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 61642 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 61643 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 61644 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 61645 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 61646 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 61647 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 61648 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 61649 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 61650 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 61651 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 61652 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 61653 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 61654 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 61655 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 61656 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 61657 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 61658 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 61659 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 61660 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 61661 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 61662 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 61663 | //BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 |
|---|
| 61664 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 61665 | #define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 61666 | //BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 |
|---|
| 61667 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 61668 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 61669 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 61670 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 61671 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 61672 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 61673 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 61674 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 61675 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 61676 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 61677 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 61678 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 61679 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 61680 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 61681 | //BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 |
|---|
| 61682 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 61683 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 61684 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 61685 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 61686 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 61687 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 61688 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 61689 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 61690 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 61691 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 61692 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 61693 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 61694 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 61695 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 61696 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 61697 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 61698 | //BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 |
|---|
| 61699 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 61700 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 61701 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 61702 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 61703 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 61704 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 61705 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 61706 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 61707 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 61708 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 61709 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 61710 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 61711 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 61712 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 61713 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 61714 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 61715 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 61716 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 61717 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 61718 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 61719 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 61720 | #define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 61721 | //BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST |
|---|
| 61722 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61723 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 61724 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 61725 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 61726 | //BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL |
|---|
| 61727 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 61728 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 61729 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 61730 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 61731 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 61732 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 61733 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 61734 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 61735 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 61736 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 61737 | //BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO |
|---|
| 61738 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 61739 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 61740 | //BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI |
|---|
| 61741 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 61742 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 61743 | //BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA |
|---|
| 61744 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 61745 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 61746 | //BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK |
|---|
| 61747 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 61748 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 61749 | //BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 |
|---|
| 61750 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 61751 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 61752 | //BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 |
|---|
| 61753 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 61754 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 61755 | //BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING |
|---|
| 61756 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 61757 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 61758 | //BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 |
|---|
| 61759 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 61760 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 61761 | //BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST |
|---|
| 61762 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61763 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 61764 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 61765 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 61766 | //BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL |
|---|
| 61767 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 61768 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 61769 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 61770 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 61771 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 61772 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 61773 | //BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE |
|---|
| 61774 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 61775 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 61776 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 61777 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 61778 | //BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA |
|---|
| 61779 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 61780 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 61781 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 61782 | #define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 61783 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 61784 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61785 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 61786 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 61787 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 61788 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 61789 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 61790 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 61791 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 61792 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 61793 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 61794 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 61795 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 61796 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 61797 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 61798 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 61799 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 61800 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 61801 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 61802 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 61803 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 61804 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61805 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 61806 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 61807 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 61808 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 61809 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 61810 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 61811 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 61812 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 61813 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 61814 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 61815 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 61816 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 61817 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 61818 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 61819 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 61820 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 61821 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 61822 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 61823 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 61824 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 61825 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 61826 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 61827 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 61828 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 61829 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 61830 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 61831 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 61832 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 61833 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 61834 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 61835 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 61836 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 61837 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 61838 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 61839 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 61840 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 61841 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 61842 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 61843 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK |
|---|
| 61844 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 61845 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 61846 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 61847 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 61848 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 61849 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 61850 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 61851 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 61852 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 61853 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 61854 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 61855 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 61856 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 61857 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 61858 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 61859 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 61860 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 61861 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 61862 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 61863 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 61864 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 61865 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 61866 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 61867 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 61868 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 61869 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 61870 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 61871 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 61872 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 61873 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 61874 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 61875 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 61876 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 61877 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 61878 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 61879 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 61880 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 61881 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 61882 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 61883 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 61884 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 61885 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 61886 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 61887 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 61888 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 61889 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 61890 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 61891 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 61892 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 61893 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 61894 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 61895 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 61896 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 61897 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 61898 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 61899 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 61900 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 61901 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 61902 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 61903 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 61904 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 61905 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 61906 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 61907 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 61908 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 61909 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS |
|---|
| 61910 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 61911 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 61912 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 61913 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 61914 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 61915 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 61916 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 61917 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 61918 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 61919 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 61920 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 61921 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 61922 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 61923 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 61924 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 61925 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 61926 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK |
|---|
| 61927 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 61928 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 61929 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 61930 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 61931 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 61932 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 61933 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 61934 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 61935 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 61936 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 61937 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 61938 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 61939 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 61940 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 61941 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 61942 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 61943 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 61944 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 61945 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 61946 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 61947 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 61948 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 61949 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 61950 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 61951 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 61952 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 61953 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 61954 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 61955 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 61956 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 61957 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 61958 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 61959 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 61960 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 61961 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 61962 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 |
|---|
| 61963 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 61964 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 61965 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 |
|---|
| 61966 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 61967 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 61968 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 |
|---|
| 61969 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 61970 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 61971 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 |
|---|
| 61972 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 61973 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 61974 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 61975 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 61976 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 61977 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 61978 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 61979 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 61980 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 61981 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 61982 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 61983 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 61984 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 61985 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 61986 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 61987 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 61988 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 61989 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 61990 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 61991 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 61992 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 61993 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP |
|---|
| 61994 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 61995 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 61996 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 61997 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 61998 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 61999 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 62000 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL |
|---|
| 62001 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 62002 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 62003 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 62004 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 62005 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 62006 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 62007 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 62008 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 62009 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 62010 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 62011 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 62012 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP |
|---|
| 62013 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 62014 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 62015 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 62016 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 62017 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 62018 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 62019 | //BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL |
|---|
| 62020 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 62021 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 62022 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 62023 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 62024 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 62025 | #define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 62026 | |
|---|
| 62027 | |
|---|
| 62028 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp |
|---|
| 62029 | //BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID |
|---|
| 62030 | #define BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 62031 | #define BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 62032 | //BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID |
|---|
| 62033 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 62034 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 62035 | //BIF_CFG_DEV0_EPF0_VF6_0_COMMAND |
|---|
| 62036 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 62037 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 62038 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 62039 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 62040 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 62041 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 62042 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 62043 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 62044 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 62045 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 62046 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 62047 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 62048 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 62049 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 62050 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 62051 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 62052 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 62053 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 62054 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 62055 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 62056 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 62057 | #define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 62058 | //BIF_CFG_DEV0_EPF0_VF6_0_STATUS |
|---|
| 62059 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 62060 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 62061 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 62062 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 62063 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 62064 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 62065 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 62066 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 62067 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 62068 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 62069 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 62070 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 62071 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 62072 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 62073 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 62074 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 62075 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 62076 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 62077 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 62078 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 62079 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 62080 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 62081 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 62082 | #define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 62083 | //BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID |
|---|
| 62084 | #define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 62085 | #define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 62086 | #define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 62087 | #define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 62088 | //BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE |
|---|
| 62089 | #define BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 62090 | #define BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 62091 | //BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS |
|---|
| 62092 | #define BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 62093 | #define BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 62094 | //BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS |
|---|
| 62095 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 62096 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 62097 | //BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE |
|---|
| 62098 | #define BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 62099 | #define BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 62100 | //BIF_CFG_DEV0_EPF0_VF6_0_LATENCY |
|---|
| 62101 | #define BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 62102 | #define BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 62103 | //BIF_CFG_DEV0_EPF0_VF6_0_HEADER |
|---|
| 62104 | #define 0x0 |
|---|
| 62105 | #define 0x7 |
|---|
| 62106 | #define 0x7FL |
|---|
| 62107 | #define 0x80L |
|---|
| 62108 | //BIF_CFG_DEV0_EPF0_VF6_0_BIST |
|---|
| 62109 | #define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 62110 | #define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 62111 | #define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 62112 | #define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 62113 | #define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 62114 | #define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 62115 | //BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 |
|---|
| 62116 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 62117 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62118 | //BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 |
|---|
| 62119 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 62120 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62121 | //BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 |
|---|
| 62122 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 62123 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62124 | //BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 |
|---|
| 62125 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 62126 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62127 | //BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 |
|---|
| 62128 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 62129 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62130 | //BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 |
|---|
| 62131 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 62132 | #define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62133 | //BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR |
|---|
| 62134 | #define BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 62135 | #define BIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 62136 | //BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID |
|---|
| 62137 | #define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 62138 | #define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 62139 | #define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 62140 | #define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 62141 | //BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR |
|---|
| 62142 | #define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 62143 | #define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62144 | //BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR |
|---|
| 62145 | #define BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 62146 | #define BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 62147 | //BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE |
|---|
| 62148 | #define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 62149 | #define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 62150 | //BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN |
|---|
| 62151 | #define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 62152 | #define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 62153 | //BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT |
|---|
| 62154 | #define BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 62155 | #define BIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 62156 | //BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY |
|---|
| 62157 | #define BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 62158 | #define BIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 62159 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST |
|---|
| 62160 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 62161 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 62162 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 62163 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 62164 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP |
|---|
| 62165 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 62166 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 62167 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 62168 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 62169 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 62170 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 62171 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 62172 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 62173 | //BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP |
|---|
| 62174 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 62175 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 62176 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 62177 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 62178 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 62179 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 62180 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 62181 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 62182 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 62183 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 62184 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 62185 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 62186 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 62187 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 62188 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 62189 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 62190 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 62191 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 62192 | //BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL |
|---|
| 62193 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 62194 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 62195 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 62196 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 62197 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 62198 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 62199 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 62200 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 62201 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 62202 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 62203 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 62204 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 62205 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 62206 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 62207 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 62208 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 62209 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 62210 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 62211 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 62212 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 62213 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 62214 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 62215 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 62216 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 62217 | //BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS |
|---|
| 62218 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 62219 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 62220 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 62221 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 62222 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 62223 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 62224 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 62225 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 62226 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 62227 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 62228 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 62229 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 62230 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 62231 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 62232 | //BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP |
|---|
| 62233 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 62234 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 62235 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 62236 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 62237 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 62238 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 62239 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 62240 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 62241 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 62242 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 62243 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 62244 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 62245 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 62246 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 62247 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 62248 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 62249 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 62250 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 62251 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 62252 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 62253 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 62254 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 62255 | //BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL |
|---|
| 62256 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 62257 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 62258 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 62259 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 62260 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 62261 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 62262 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 62263 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 62264 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 62265 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 62266 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 62267 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 62268 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 62269 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 62270 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 62271 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 62272 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 62273 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 62274 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 62275 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 62276 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 62277 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 62278 | //BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS |
|---|
| 62279 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 62280 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 62281 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 62282 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 62283 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 62284 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 62285 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 62286 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 62287 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 62288 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 62289 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 62290 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 62291 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 62292 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 62293 | //BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 |
|---|
| 62294 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 62295 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 62296 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 62297 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 62298 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 62299 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 62300 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 62301 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 62302 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 62303 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 62304 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 62305 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 62306 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 62307 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 62308 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 62309 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 62310 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 62311 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 62312 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 62313 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 62314 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 62315 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 62316 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 62317 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 62318 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 62319 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 62320 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 62321 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 62322 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 62323 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 62324 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 62325 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 62326 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 62327 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 62328 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 62329 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 62330 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 62331 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 62332 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 62333 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 62334 | //BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 |
|---|
| 62335 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 62336 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 62337 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 62338 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 62339 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 62340 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 62341 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 62342 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 62343 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 62344 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 62345 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 62346 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 62347 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 62348 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 62349 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 62350 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 62351 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 62352 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 62353 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 62354 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 62355 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 62356 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 62357 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 62358 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 62359 | //BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 |
|---|
| 62360 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 62361 | #define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 62362 | //BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 |
|---|
| 62363 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 62364 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 62365 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 62366 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 62367 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 62368 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 62369 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 62370 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 62371 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 62372 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 62373 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 62374 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 62375 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 62376 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 62377 | //BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 |
|---|
| 62378 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 62379 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 62380 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 62381 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 62382 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 62383 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 62384 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 62385 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 62386 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 62387 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 62388 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 62389 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 62390 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 62391 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 62392 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 62393 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 62394 | //BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 |
|---|
| 62395 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 62396 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 62397 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 62398 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 62399 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 62400 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 62401 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 62402 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 62403 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 62404 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 62405 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 62406 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 62407 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 62408 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 62409 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 62410 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 62411 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 62412 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 62413 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 62414 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 62415 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 62416 | #define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 62417 | //BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST |
|---|
| 62418 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 62419 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 62420 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 62421 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 62422 | //BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL |
|---|
| 62423 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 62424 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 62425 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 62426 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 62427 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 62428 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 62429 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 62430 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 62431 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 62432 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 62433 | //BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO |
|---|
| 62434 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 62435 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 62436 | //BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI |
|---|
| 62437 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 62438 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 62439 | //BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA |
|---|
| 62440 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 62441 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 62442 | //BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK |
|---|
| 62443 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 62444 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 62445 | //BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 |
|---|
| 62446 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 62447 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 62448 | //BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 |
|---|
| 62449 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 62450 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 62451 | //BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING |
|---|
| 62452 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 62453 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 62454 | //BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 |
|---|
| 62455 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 62456 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 62457 | //BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST |
|---|
| 62458 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 62459 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 62460 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 62461 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 62462 | //BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL |
|---|
| 62463 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 62464 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 62465 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 62466 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 62467 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 62468 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 62469 | //BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE |
|---|
| 62470 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 62471 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 62472 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 62473 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 62474 | //BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA |
|---|
| 62475 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 62476 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 62477 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 62478 | #define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 62479 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 62480 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 62481 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 62482 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 62483 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 62484 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 62485 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 62486 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 62487 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 62488 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 62489 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 62490 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 62491 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 62492 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 62493 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 62494 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 62495 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 62496 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 62497 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 62498 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 62499 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 62500 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 62501 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 62502 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 62503 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 62504 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 62505 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 62506 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 62507 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 62508 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 62509 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 62510 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 62511 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 62512 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 62513 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 62514 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 62515 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 62516 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 62517 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 62518 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 62519 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 62520 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 62521 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 62522 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 62523 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 62524 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 62525 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 62526 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 62527 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 62528 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 62529 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 62530 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 62531 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 62532 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 62533 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 62534 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 62535 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 62536 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 62537 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 62538 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 62539 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK |
|---|
| 62540 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 62541 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 62542 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 62543 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 62544 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 62545 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 62546 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 62547 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 62548 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 62549 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 62550 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 62551 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 62552 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 62553 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 62554 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 62555 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 62556 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 62557 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 62558 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 62559 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 62560 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 62561 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 62562 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 62563 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 62564 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 62565 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 62566 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 62567 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 62568 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 62569 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 62570 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 62571 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 62572 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 62573 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 62574 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 62575 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 62576 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 62577 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 62578 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 62579 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 62580 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 62581 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 62582 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 62583 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 62584 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 62585 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 62586 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 62587 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 62588 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 62589 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 62590 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 62591 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 62592 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 62593 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 62594 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 62595 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 62596 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 62597 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 62598 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 62599 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 62600 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 62601 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 62602 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 62603 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 62604 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 62605 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS |
|---|
| 62606 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 62607 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 62608 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 62609 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 62610 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 62611 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 62612 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 62613 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 62614 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 62615 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 62616 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 62617 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 62618 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 62619 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 62620 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 62621 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 62622 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK |
|---|
| 62623 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 62624 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 62625 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 62626 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 62627 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 62628 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 62629 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 62630 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 62631 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 62632 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 62633 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 62634 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 62635 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 62636 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 62637 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 62638 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 62639 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 62640 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 62641 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 62642 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 62643 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 62644 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 62645 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 62646 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 62647 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 62648 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 62649 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 62650 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 62651 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 62652 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 62653 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 62654 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 62655 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 62656 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 62657 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 62658 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 |
|---|
| 62659 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 62660 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 62661 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 |
|---|
| 62662 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 62663 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 62664 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 |
|---|
| 62665 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 62666 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 62667 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 |
|---|
| 62668 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 62669 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 62670 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 62671 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 62672 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 62673 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 62674 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 62675 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 62676 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 62677 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 62678 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 62679 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 62680 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 62681 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 62682 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 62683 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 62684 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 62685 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 62686 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 62687 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 62688 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 62689 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP |
|---|
| 62690 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 62691 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 62692 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 62693 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 62694 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 62695 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 62696 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL |
|---|
| 62697 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 62698 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 62699 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 62700 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 62701 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 62702 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 62703 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 62704 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 62705 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 62706 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 62707 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 62708 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP |
|---|
| 62709 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 62710 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 62711 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 62712 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 62713 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 62714 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 62715 | //BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL |
|---|
| 62716 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 62717 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 62718 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 62719 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 62720 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 62721 | #define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 62722 | |
|---|
| 62723 | |
|---|
| 62724 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp |
|---|
| 62725 | //BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID |
|---|
| 62726 | #define BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 62727 | #define BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 62728 | //BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID |
|---|
| 62729 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 62730 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 62731 | //BIF_CFG_DEV0_EPF0_VF7_0_COMMAND |
|---|
| 62732 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 62733 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 62734 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 62735 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 62736 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 62737 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 62738 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 62739 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 62740 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 62741 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 62742 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 62743 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 62744 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 62745 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 62746 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 62747 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 62748 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 62749 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 62750 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 62751 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 62752 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 62753 | #define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 62754 | //BIF_CFG_DEV0_EPF0_VF7_0_STATUS |
|---|
| 62755 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 62756 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 62757 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 62758 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 62759 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 62760 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 62761 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 62762 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 62763 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 62764 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 62765 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 62766 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 62767 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 62768 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 62769 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 62770 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 62771 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 62772 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 62773 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 62774 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 62775 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 62776 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 62777 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 62778 | #define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 62779 | //BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID |
|---|
| 62780 | #define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 62781 | #define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 62782 | #define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 62783 | #define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 62784 | //BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE |
|---|
| 62785 | #define BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 62786 | #define BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 62787 | //BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS |
|---|
| 62788 | #define BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 62789 | #define BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 62790 | //BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS |
|---|
| 62791 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 62792 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 62793 | //BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE |
|---|
| 62794 | #define BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 62795 | #define BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 62796 | //BIF_CFG_DEV0_EPF0_VF7_0_LATENCY |
|---|
| 62797 | #define BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 62798 | #define BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 62799 | //BIF_CFG_DEV0_EPF0_VF7_0_HEADER |
|---|
| 62800 | #define 0x0 |
|---|
| 62801 | #define 0x7 |
|---|
| 62802 | #define 0x7FL |
|---|
| 62803 | #define 0x80L |
|---|
| 62804 | //BIF_CFG_DEV0_EPF0_VF7_0_BIST |
|---|
| 62805 | #define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 62806 | #define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 62807 | #define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 62808 | #define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 62809 | #define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 62810 | #define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 62811 | //BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 |
|---|
| 62812 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 62813 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62814 | //BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 |
|---|
| 62815 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 62816 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62817 | //BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 |
|---|
| 62818 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 62819 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62820 | //BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 |
|---|
| 62821 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 62822 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62823 | //BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 |
|---|
| 62824 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 62825 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62826 | //BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 |
|---|
| 62827 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 62828 | #define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62829 | //BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR |
|---|
| 62830 | #define BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 62831 | #define BIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 62832 | //BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID |
|---|
| 62833 | #define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 62834 | #define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 62835 | #define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 62836 | #define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 62837 | //BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR |
|---|
| 62838 | #define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 62839 | #define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 62840 | //BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR |
|---|
| 62841 | #define BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 62842 | #define BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 62843 | //BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE |
|---|
| 62844 | #define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 62845 | #define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 62846 | //BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN |
|---|
| 62847 | #define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 62848 | #define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 62849 | //BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT |
|---|
| 62850 | #define BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 62851 | #define BIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 62852 | //BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY |
|---|
| 62853 | #define BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 62854 | #define BIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 62855 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST |
|---|
| 62856 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 62857 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 62858 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 62859 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 62860 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP |
|---|
| 62861 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 62862 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 62863 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 62864 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 62865 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 62866 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 62867 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 62868 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 62869 | //BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP |
|---|
| 62870 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 62871 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 62872 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 62873 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 62874 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 62875 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 62876 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 62877 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 62878 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 62879 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 62880 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 62881 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 62882 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 62883 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 62884 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 62885 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 62886 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 62887 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 62888 | //BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL |
|---|
| 62889 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 62890 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 62891 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 62892 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 62893 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 62894 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 62895 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 62896 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 62897 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 62898 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 62899 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 62900 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 62901 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 62902 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 62903 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 62904 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 62905 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 62906 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 62907 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 62908 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 62909 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 62910 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 62911 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 62912 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 62913 | //BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS |
|---|
| 62914 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 62915 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 62916 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 62917 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 62918 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 62919 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 62920 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 62921 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 62922 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 62923 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 62924 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 62925 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 62926 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 62927 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 62928 | //BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP |
|---|
| 62929 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 62930 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 62931 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 62932 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 62933 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 62934 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 62935 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 62936 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 62937 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 62938 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 62939 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 62940 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 62941 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 62942 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 62943 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 62944 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 62945 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 62946 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 62947 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 62948 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 62949 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 62950 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 62951 | //BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL |
|---|
| 62952 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 62953 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 62954 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 62955 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 62956 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 62957 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 62958 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 62959 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 62960 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 62961 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 62962 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 62963 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 62964 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 62965 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 62966 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 62967 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 62968 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 62969 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 62970 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 62971 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 62972 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 62973 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 62974 | //BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS |
|---|
| 62975 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 62976 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 62977 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 62978 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 62979 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 62980 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 62981 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 62982 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 62983 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 62984 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 62985 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 62986 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 62987 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 62988 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 62989 | //BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 |
|---|
| 62990 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 62991 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 62992 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 62993 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 62994 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 62995 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 62996 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 62997 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 62998 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 62999 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 63000 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 63001 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 63002 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 63003 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 63004 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 63005 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 63006 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 63007 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 63008 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 63009 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 63010 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 63011 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 63012 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 63013 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 63014 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 63015 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 63016 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 63017 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 63018 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 63019 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 63020 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 63021 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 63022 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 63023 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 63024 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 63025 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 63026 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 63027 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 63028 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 63029 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 63030 | //BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 |
|---|
| 63031 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 63032 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 63033 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 63034 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 63035 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 63036 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 63037 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 63038 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 63039 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 63040 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 63041 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 63042 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 63043 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 63044 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 63045 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 63046 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 63047 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 63048 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 63049 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 63050 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 63051 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 63052 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 63053 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 63054 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 63055 | //BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 |
|---|
| 63056 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 63057 | #define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 63058 | //BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 |
|---|
| 63059 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 63060 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 63061 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 63062 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 63063 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 63064 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 63065 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 63066 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 63067 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 63068 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 63069 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 63070 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 63071 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 63072 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 63073 | //BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 |
|---|
| 63074 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 63075 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 63076 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 63077 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 63078 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 63079 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 63080 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 63081 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 63082 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 63083 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 63084 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 63085 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 63086 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 63087 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 63088 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 63089 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 63090 | //BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 |
|---|
| 63091 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 63092 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 63093 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 63094 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 63095 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 63096 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 63097 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 63098 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 63099 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 63100 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 63101 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 63102 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 63103 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 63104 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 63105 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 63106 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 63107 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 63108 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 63109 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 63110 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 63111 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 63112 | #define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 63113 | //BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST |
|---|
| 63114 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63115 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 63116 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 63117 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 63118 | //BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL |
|---|
| 63119 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 63120 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 63121 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 63122 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 63123 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 63124 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 63125 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 63126 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 63127 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 63128 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 63129 | //BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO |
|---|
| 63130 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 63131 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 63132 | //BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI |
|---|
| 63133 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 63134 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 63135 | //BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA |
|---|
| 63136 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 63137 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 63138 | //BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK |
|---|
| 63139 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 63140 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 63141 | //BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 |
|---|
| 63142 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 63143 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 63144 | //BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 |
|---|
| 63145 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 63146 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 63147 | //BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING |
|---|
| 63148 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 63149 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 63150 | //BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 |
|---|
| 63151 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 63152 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 63153 | //BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST |
|---|
| 63154 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63155 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 63156 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 63157 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 63158 | //BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL |
|---|
| 63159 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 63160 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 63161 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 63162 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 63163 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 63164 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 63165 | //BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE |
|---|
| 63166 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 63167 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 63168 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 63169 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 63170 | //BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA |
|---|
| 63171 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 63172 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 63173 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 63174 | #define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 63175 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 63176 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63177 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 63178 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 63179 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 63180 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 63181 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 63182 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 63183 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 63184 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 63185 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 63186 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 63187 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 63188 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 63189 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 63190 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 63191 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 63192 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 63193 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 63194 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 63195 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 63196 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63197 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 63198 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 63199 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 63200 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 63201 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 63202 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 63203 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 63204 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 63205 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 63206 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 63207 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 63208 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 63209 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 63210 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 63211 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 63212 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 63213 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 63214 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 63215 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 63216 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 63217 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 63218 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 63219 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 63220 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 63221 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 63222 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 63223 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 63224 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 63225 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 63226 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 63227 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 63228 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 63229 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 63230 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 63231 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 63232 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 63233 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 63234 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 63235 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK |
|---|
| 63236 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 63237 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 63238 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 63239 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 63240 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 63241 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 63242 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 63243 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 63244 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 63245 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 63246 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 63247 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 63248 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 63249 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 63250 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 63251 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 63252 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 63253 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 63254 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 63255 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 63256 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 63257 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 63258 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 63259 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 63260 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 63261 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 63262 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 63263 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 63264 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 63265 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 63266 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 63267 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 63268 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 63269 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 63270 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 63271 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 63272 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 63273 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 63274 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 63275 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 63276 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 63277 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 63278 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 63279 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 63280 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 63281 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 63282 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 63283 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 63284 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 63285 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 63286 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 63287 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 63288 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 63289 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 63290 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 63291 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 63292 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 63293 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 63294 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 63295 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 63296 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 63297 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 63298 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 63299 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 63300 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 63301 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS |
|---|
| 63302 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 63303 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 63304 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 63305 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 63306 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 63307 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 63308 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 63309 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 63310 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 63311 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 63312 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 63313 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 63314 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 63315 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 63316 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 63317 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 63318 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK |
|---|
| 63319 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 63320 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 63321 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 63322 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 63323 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 63324 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 63325 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 63326 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 63327 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 63328 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 63329 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 63330 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 63331 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 63332 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 63333 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 63334 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 63335 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 63336 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 63337 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 63338 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 63339 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 63340 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 63341 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 63342 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 63343 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 63344 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 63345 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 63346 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 63347 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 63348 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 63349 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 63350 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 63351 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 63352 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 63353 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 63354 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 |
|---|
| 63355 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 63356 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 63357 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 |
|---|
| 63358 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 63359 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 63360 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 |
|---|
| 63361 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 63362 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 63363 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 |
|---|
| 63364 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 63365 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 63366 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 63367 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 63368 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 63369 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 63370 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 63371 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 63372 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 63373 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 63374 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 63375 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 63376 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 63377 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 63378 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 63379 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63380 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 63381 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 63382 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 63383 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 63384 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 63385 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP |
|---|
| 63386 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 63387 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 63388 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 63389 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 63390 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 63391 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 63392 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL |
|---|
| 63393 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 63394 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 63395 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 63396 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 63397 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 63398 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63399 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 63400 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 63401 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 63402 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 63403 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 63404 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP |
|---|
| 63405 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 63406 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 63407 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 63408 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 63409 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 63410 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 63411 | //BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL |
|---|
| 63412 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 63413 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 63414 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 63415 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 63416 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 63417 | #define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 63418 | |
|---|
| 63419 | |
|---|
| 63420 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp |
|---|
| 63421 | //BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID |
|---|
| 63422 | #define BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 63423 | #define BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 63424 | //BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID |
|---|
| 63425 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 63426 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 63427 | //BIF_CFG_DEV0_EPF0_VF8_0_COMMAND |
|---|
| 63428 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 63429 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 63430 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 63431 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 63432 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 63433 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 63434 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 63435 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 63436 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 63437 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 63438 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 63439 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 63440 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 63441 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 63442 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 63443 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 63444 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 63445 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 63446 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 63447 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 63448 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 63449 | #define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 63450 | //BIF_CFG_DEV0_EPF0_VF8_0_STATUS |
|---|
| 63451 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 63452 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 63453 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 63454 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 63455 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 63456 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 63457 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 63458 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 63459 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 63460 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 63461 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 63462 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 63463 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 63464 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 63465 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 63466 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 63467 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 63468 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 63469 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 63470 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 63471 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 63472 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 63473 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 63474 | #define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 63475 | //BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID |
|---|
| 63476 | #define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 63477 | #define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 63478 | #define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 63479 | #define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 63480 | //BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE |
|---|
| 63481 | #define BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 63482 | #define BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 63483 | //BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS |
|---|
| 63484 | #define BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 63485 | #define BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 63486 | //BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS |
|---|
| 63487 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 63488 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 63489 | //BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE |
|---|
| 63490 | #define BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 63491 | #define BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 63492 | //BIF_CFG_DEV0_EPF0_VF8_0_LATENCY |
|---|
| 63493 | #define BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 63494 | #define BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 63495 | //BIF_CFG_DEV0_EPF0_VF8_0_HEADER |
|---|
| 63496 | #define 0x0 |
|---|
| 63497 | #define 0x7 |
|---|
| 63498 | #define 0x7FL |
|---|
| 63499 | #define 0x80L |
|---|
| 63500 | //BIF_CFG_DEV0_EPF0_VF8_0_BIST |
|---|
| 63501 | #define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 63502 | #define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 63503 | #define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 63504 | #define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 63505 | #define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 63506 | #define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 63507 | //BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 |
|---|
| 63508 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 63509 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 63510 | //BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 |
|---|
| 63511 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 63512 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 63513 | //BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 |
|---|
| 63514 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 63515 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 63516 | //BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 |
|---|
| 63517 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 63518 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 63519 | //BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 |
|---|
| 63520 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 63521 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 63522 | //BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 |
|---|
| 63523 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 63524 | #define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 63525 | //BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR |
|---|
| 63526 | #define BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 63527 | #define BIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 63528 | //BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID |
|---|
| 63529 | #define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 63530 | #define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 63531 | #define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 63532 | #define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 63533 | //BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR |
|---|
| 63534 | #define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 63535 | #define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 63536 | //BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR |
|---|
| 63537 | #define BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 63538 | #define BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 63539 | //BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE |
|---|
| 63540 | #define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 63541 | #define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 63542 | //BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN |
|---|
| 63543 | #define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 63544 | #define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 63545 | //BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT |
|---|
| 63546 | #define BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 63547 | #define BIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 63548 | //BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY |
|---|
| 63549 | #define BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 63550 | #define BIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 63551 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST |
|---|
| 63552 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63553 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 63554 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 63555 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 63556 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP |
|---|
| 63557 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 63558 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 63559 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 63560 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 63561 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 63562 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 63563 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 63564 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 63565 | //BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP |
|---|
| 63566 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 63567 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 63568 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 63569 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 63570 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 63571 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 63572 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 63573 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 63574 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 63575 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 63576 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 63577 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 63578 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 63579 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 63580 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 63581 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 63582 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 63583 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 63584 | //BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL |
|---|
| 63585 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 63586 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 63587 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 63588 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 63589 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 63590 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 63591 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 63592 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 63593 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 63594 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 63595 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 63596 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 63597 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 63598 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 63599 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 63600 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 63601 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 63602 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 63603 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 63604 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 63605 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 63606 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 63607 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 63608 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 63609 | //BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS |
|---|
| 63610 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 63611 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 63612 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 63613 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 63614 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 63615 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 63616 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 63617 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 63618 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 63619 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 63620 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 63621 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 63622 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 63623 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 63624 | //BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP |
|---|
| 63625 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 63626 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 63627 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 63628 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 63629 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 63630 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 63631 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 63632 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 63633 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 63634 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 63635 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 63636 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 63637 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 63638 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 63639 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 63640 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 63641 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 63642 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 63643 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 63644 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 63645 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 63646 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 63647 | //BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL |
|---|
| 63648 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 63649 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 63650 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 63651 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 63652 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 63653 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 63654 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 63655 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 63656 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 63657 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 63658 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 63659 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 63660 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 63661 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 63662 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 63663 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 63664 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 63665 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 63666 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 63667 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 63668 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 63669 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 63670 | //BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS |
|---|
| 63671 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 63672 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 63673 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 63674 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 63675 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 63676 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 63677 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 63678 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 63679 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 63680 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 63681 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 63682 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 63683 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 63684 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 63685 | //BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 |
|---|
| 63686 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 63687 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 63688 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 63689 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 63690 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 63691 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 63692 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 63693 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 63694 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 63695 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 63696 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 63697 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 63698 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 63699 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 63700 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 63701 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 63702 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 63703 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 63704 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 63705 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 63706 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 63707 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 63708 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 63709 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 63710 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 63711 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 63712 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 63713 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 63714 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 63715 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 63716 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 63717 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 63718 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 63719 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 63720 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 63721 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 63722 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 63723 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 63724 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 63725 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 63726 | //BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 |
|---|
| 63727 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 63728 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 63729 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 63730 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 63731 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 63732 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 63733 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 63734 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 63735 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 63736 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 63737 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 63738 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 63739 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 63740 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 63741 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 63742 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 63743 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 63744 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 63745 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 63746 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 63747 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 63748 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 63749 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 63750 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 63751 | //BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 |
|---|
| 63752 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 63753 | #define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 63754 | //BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 |
|---|
| 63755 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 63756 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 63757 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 63758 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 63759 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 63760 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 63761 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 63762 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 63763 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 63764 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 63765 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 63766 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 63767 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 63768 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 63769 | //BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 |
|---|
| 63770 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 63771 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 63772 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 63773 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 63774 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 63775 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 63776 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 63777 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 63778 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 63779 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 63780 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 63781 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 63782 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 63783 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 63784 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 63785 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 63786 | //BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 |
|---|
| 63787 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 63788 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 63789 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 63790 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 63791 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 63792 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 63793 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 63794 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 63795 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 63796 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 63797 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 63798 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 63799 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 63800 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 63801 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 63802 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 63803 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 63804 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 63805 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 63806 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 63807 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 63808 | #define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 63809 | //BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST |
|---|
| 63810 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63811 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 63812 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 63813 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 63814 | //BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL |
|---|
| 63815 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 63816 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 63817 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 63818 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 63819 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 63820 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 63821 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 63822 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 63823 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 63824 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 63825 | //BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO |
|---|
| 63826 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 63827 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 63828 | //BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI |
|---|
| 63829 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 63830 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 63831 | //BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA |
|---|
| 63832 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 63833 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 63834 | //BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK |
|---|
| 63835 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 63836 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 63837 | //BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 |
|---|
| 63838 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 63839 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 63840 | //BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 |
|---|
| 63841 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 63842 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 63843 | //BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING |
|---|
| 63844 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 63845 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 63846 | //BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 |
|---|
| 63847 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 63848 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 63849 | //BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST |
|---|
| 63850 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63851 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 63852 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 63853 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 63854 | //BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL |
|---|
| 63855 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 63856 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 63857 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 63858 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 63859 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 63860 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 63861 | //BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE |
|---|
| 63862 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 63863 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 63864 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 63865 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 63866 | //BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA |
|---|
| 63867 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 63868 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 63869 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 63870 | #define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 63871 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 63872 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63873 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 63874 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 63875 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 63876 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 63877 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 63878 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 63879 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 63880 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 63881 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 63882 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 63883 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 63884 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 63885 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 63886 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 63887 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 63888 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 63889 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 63890 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 63891 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 63892 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 63893 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 63894 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 63895 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 63896 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 63897 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 63898 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 63899 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 63900 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 63901 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 63902 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 63903 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 63904 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 63905 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 63906 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 63907 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 63908 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 63909 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 63910 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 63911 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 63912 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 63913 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 63914 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 63915 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 63916 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 63917 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 63918 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 63919 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 63920 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 63921 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 63922 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 63923 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 63924 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 63925 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 63926 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 63927 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 63928 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 63929 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 63930 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 63931 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK |
|---|
| 63932 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 63933 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 63934 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 63935 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 63936 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 63937 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 63938 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 63939 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 63940 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 63941 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 63942 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 63943 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 63944 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 63945 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 63946 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 63947 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 63948 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 63949 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 63950 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 63951 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 63952 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 63953 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 63954 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 63955 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 63956 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 63957 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 63958 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 63959 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 63960 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 63961 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 63962 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 63963 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 63964 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 63965 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 63966 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 63967 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 63968 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 63969 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 63970 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 63971 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 63972 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 63973 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 63974 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 63975 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 63976 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 63977 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 63978 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 63979 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 63980 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 63981 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 63982 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 63983 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 63984 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 63985 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 63986 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 63987 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 63988 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 63989 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 63990 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 63991 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 63992 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 63993 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 63994 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 63995 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 63996 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 63997 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS |
|---|
| 63998 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 63999 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 64000 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 64001 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 64002 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 64003 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 64004 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 64005 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 64006 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 64007 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 64008 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 64009 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 64010 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 64011 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 64012 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 64013 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 64014 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK |
|---|
| 64015 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 64016 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 64017 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 64018 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 64019 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 64020 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 64021 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 64022 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 64023 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 64024 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 64025 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 64026 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 64027 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 64028 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 64029 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 64030 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 64031 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 64032 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 64033 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 64034 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 64035 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 64036 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 64037 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 64038 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 64039 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 64040 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 64041 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 64042 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 64043 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 64044 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 64045 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 64046 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 64047 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 64048 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 64049 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 64050 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 |
|---|
| 64051 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 64052 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 64053 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 |
|---|
| 64054 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 64055 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 64056 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 |
|---|
| 64057 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 64058 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 64059 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 |
|---|
| 64060 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 64061 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 64062 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 64063 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 64064 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 64065 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 64066 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 64067 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 64068 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 64069 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 64070 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 64071 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 64072 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 64073 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 64074 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 64075 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 64076 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 64077 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 64078 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 64079 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 64080 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 64081 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP |
|---|
| 64082 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 64083 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 64084 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 64085 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 64086 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 64087 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 64088 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL |
|---|
| 64089 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 64090 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 64091 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 64092 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 64093 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 64094 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 64095 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 64096 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 64097 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 64098 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 64099 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 64100 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP |
|---|
| 64101 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 64102 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 64103 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 64104 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 64105 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 64106 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 64107 | //BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL |
|---|
| 64108 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 64109 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 64110 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 64111 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 64112 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 64113 | #define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 64114 | |
|---|
| 64115 | |
|---|
| 64116 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp |
|---|
| 64117 | //BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID |
|---|
| 64118 | #define BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 64119 | #define BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 64120 | //BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID |
|---|
| 64121 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 64122 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 64123 | //BIF_CFG_DEV0_EPF0_VF9_0_COMMAND |
|---|
| 64124 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 64125 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 64126 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 64127 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 64128 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 64129 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 64130 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 64131 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 64132 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 64133 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 64134 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 64135 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 64136 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 64137 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 64138 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 64139 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 64140 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 64141 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 64142 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 64143 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 64144 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 64145 | #define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 64146 | //BIF_CFG_DEV0_EPF0_VF9_0_STATUS |
|---|
| 64147 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 64148 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 64149 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 64150 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 64151 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 64152 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 64153 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 64154 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 64155 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 64156 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 64157 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 64158 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 64159 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 64160 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 64161 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 64162 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 64163 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 64164 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 64165 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 64166 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 64167 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 64168 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 64169 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 64170 | #define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 64171 | //BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID |
|---|
| 64172 | #define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 64173 | #define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 64174 | #define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 64175 | #define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 64176 | //BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE |
|---|
| 64177 | #define BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 64178 | #define BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 64179 | //BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS |
|---|
| 64180 | #define BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 64181 | #define BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 64182 | //BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS |
|---|
| 64183 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 64184 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 64185 | //BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE |
|---|
| 64186 | #define BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 64187 | #define BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 64188 | //BIF_CFG_DEV0_EPF0_VF9_0_LATENCY |
|---|
| 64189 | #define BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 64190 | #define BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 64191 | //BIF_CFG_DEV0_EPF0_VF9_0_HEADER |
|---|
| 64192 | #define 0x0 |
|---|
| 64193 | #define 0x7 |
|---|
| 64194 | #define 0x7FL |
|---|
| 64195 | #define 0x80L |
|---|
| 64196 | //BIF_CFG_DEV0_EPF0_VF9_0_BIST |
|---|
| 64197 | #define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 64198 | #define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 64199 | #define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 64200 | #define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 64201 | #define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 64202 | #define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 64203 | //BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 |
|---|
| 64204 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 64205 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64206 | //BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 |
|---|
| 64207 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 64208 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64209 | //BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 |
|---|
| 64210 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 64211 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64212 | //BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 |
|---|
| 64213 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 64214 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64215 | //BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 |
|---|
| 64216 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 64217 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64218 | //BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 |
|---|
| 64219 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 64220 | #define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64221 | //BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR |
|---|
| 64222 | #define BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 64223 | #define BIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 64224 | //BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID |
|---|
| 64225 | #define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 64226 | #define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 64227 | #define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 64228 | #define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 64229 | //BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR |
|---|
| 64230 | #define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 64231 | #define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64232 | //BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR |
|---|
| 64233 | #define BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 64234 | #define BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 64235 | //BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE |
|---|
| 64236 | #define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 64237 | #define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 64238 | //BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN |
|---|
| 64239 | #define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 64240 | #define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 64241 | //BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT |
|---|
| 64242 | #define BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 64243 | #define BIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 64244 | //BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY |
|---|
| 64245 | #define BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 64246 | #define BIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 64247 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST |
|---|
| 64248 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 64249 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 64250 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 64251 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 64252 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP |
|---|
| 64253 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 64254 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 64255 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 64256 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 64257 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 64258 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 64259 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 64260 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 64261 | //BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP |
|---|
| 64262 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 64263 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 64264 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 64265 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 64266 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 64267 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 64268 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 64269 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 64270 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 64271 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 64272 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 64273 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 64274 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 64275 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 64276 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 64277 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 64278 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 64279 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 64280 | //BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL |
|---|
| 64281 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 64282 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 64283 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 64284 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 64285 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 64286 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 64287 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 64288 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 64289 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 64290 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 64291 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 64292 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 64293 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 64294 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 64295 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 64296 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 64297 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 64298 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 64299 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 64300 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 64301 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 64302 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 64303 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 64304 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 64305 | //BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS |
|---|
| 64306 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 64307 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 64308 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 64309 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 64310 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 64311 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 64312 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 64313 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 64314 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 64315 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 64316 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 64317 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 64318 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 64319 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 64320 | //BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP |
|---|
| 64321 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 64322 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 64323 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 64324 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 64325 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 64326 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 64327 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 64328 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 64329 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 64330 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 64331 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 64332 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 64333 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 64334 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 64335 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 64336 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 64337 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 64338 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 64339 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 64340 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 64341 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 64342 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 64343 | //BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL |
|---|
| 64344 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 64345 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 64346 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 64347 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 64348 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 64349 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 64350 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 64351 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 64352 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 64353 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 64354 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 64355 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 64356 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 64357 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 64358 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 64359 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 64360 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 64361 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 64362 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 64363 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 64364 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 64365 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 64366 | //BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS |
|---|
| 64367 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 64368 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 64369 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 64370 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 64371 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 64372 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 64373 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 64374 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 64375 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 64376 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 64377 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 64378 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 64379 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 64380 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 64381 | //BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 |
|---|
| 64382 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 64383 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 64384 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 64385 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 64386 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 64387 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 64388 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 64389 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 64390 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 64391 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 64392 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 64393 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 64394 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 64395 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 64396 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 64397 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 64398 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 64399 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 64400 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 64401 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 64402 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 64403 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 64404 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 64405 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 64406 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 64407 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 64408 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 64409 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 64410 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 64411 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 64412 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 64413 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 64414 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 64415 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 64416 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 64417 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 64418 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 64419 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 64420 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 64421 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 64422 | //BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 |
|---|
| 64423 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 64424 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 64425 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 64426 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 64427 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 64428 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 64429 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 64430 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 64431 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 64432 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 64433 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 64434 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 64435 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 64436 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 64437 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 64438 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 64439 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 64440 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 64441 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 64442 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 64443 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 64444 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 64445 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 64446 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 64447 | //BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 |
|---|
| 64448 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 64449 | #define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 64450 | //BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 |
|---|
| 64451 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 64452 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 64453 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 64454 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 64455 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 64456 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 64457 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 64458 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 64459 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 64460 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 64461 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 64462 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 64463 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 64464 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 64465 | //BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 |
|---|
| 64466 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 64467 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 64468 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 64469 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 64470 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 64471 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 64472 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 64473 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 64474 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 64475 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 64476 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 64477 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 64478 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 64479 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 64480 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 64481 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 64482 | //BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 |
|---|
| 64483 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 64484 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 64485 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 64486 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 64487 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 64488 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 64489 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 64490 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 64491 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 64492 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 64493 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 64494 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 64495 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 64496 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 64497 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 64498 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 64499 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 64500 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 64501 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 64502 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 64503 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 64504 | #define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 64505 | //BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST |
|---|
| 64506 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 64507 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 64508 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 64509 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 64510 | //BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL |
|---|
| 64511 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 64512 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 64513 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 64514 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 64515 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 64516 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 64517 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 64518 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 64519 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 64520 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 64521 | //BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO |
|---|
| 64522 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 64523 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 64524 | //BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI |
|---|
| 64525 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 64526 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 64527 | //BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA |
|---|
| 64528 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 64529 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 64530 | //BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK |
|---|
| 64531 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 64532 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 64533 | //BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 |
|---|
| 64534 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 64535 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 64536 | //BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 |
|---|
| 64537 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 64538 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 64539 | //BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING |
|---|
| 64540 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 64541 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 64542 | //BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 |
|---|
| 64543 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 64544 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 64545 | //BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST |
|---|
| 64546 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 64547 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 64548 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 64549 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 64550 | //BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL |
|---|
| 64551 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 64552 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 64553 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 64554 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 64555 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 64556 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 64557 | //BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE |
|---|
| 64558 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 64559 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 64560 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 64561 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 64562 | //BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA |
|---|
| 64563 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 64564 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 64565 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 64566 | #define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 64567 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 64568 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 64569 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 64570 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 64571 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 64572 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 64573 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 64574 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 64575 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 64576 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 64577 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 64578 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 64579 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 64580 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 64581 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 64582 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 64583 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 64584 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 64585 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 64586 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 64587 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 64588 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 64589 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 64590 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 64591 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 64592 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 64593 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 64594 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 64595 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 64596 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 64597 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 64598 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 64599 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 64600 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 64601 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 64602 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 64603 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 64604 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 64605 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 64606 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 64607 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 64608 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 64609 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 64610 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 64611 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 64612 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 64613 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 64614 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 64615 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 64616 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 64617 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 64618 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 64619 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 64620 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 64621 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 64622 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 64623 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 64624 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 64625 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 64626 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 64627 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK |
|---|
| 64628 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 64629 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 64630 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 64631 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 64632 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 64633 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 64634 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 64635 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 64636 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 64637 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 64638 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 64639 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 64640 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 64641 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 64642 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 64643 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 64644 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 64645 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 64646 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 64647 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 64648 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 64649 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 64650 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 64651 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 64652 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 64653 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 64654 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 64655 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 64656 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 64657 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 64658 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 64659 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 64660 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 64661 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 64662 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 64663 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 64664 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 64665 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 64666 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 64667 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 64668 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 64669 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 64670 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 64671 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 64672 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 64673 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 64674 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 64675 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 64676 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 64677 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 64678 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 64679 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 64680 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 64681 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 64682 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 64683 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 64684 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 64685 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 64686 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 64687 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 64688 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 64689 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 64690 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 64691 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 64692 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 64693 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS |
|---|
| 64694 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 64695 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 64696 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 64697 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 64698 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 64699 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 64700 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 64701 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 64702 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 64703 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 64704 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 64705 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 64706 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 64707 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 64708 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 64709 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 64710 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK |
|---|
| 64711 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 64712 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 64713 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 64714 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 64715 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 64716 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 64717 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 64718 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 64719 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 64720 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 64721 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 64722 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 64723 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 64724 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 64725 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 64726 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 64727 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 64728 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 64729 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 64730 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 64731 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 64732 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 64733 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 64734 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 64735 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 64736 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 64737 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 64738 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 64739 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 64740 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 64741 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 64742 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 64743 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 64744 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 64745 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 64746 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 |
|---|
| 64747 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 64748 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 64749 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 |
|---|
| 64750 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 64751 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 64752 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 |
|---|
| 64753 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 64754 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 64755 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 |
|---|
| 64756 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 64757 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 64758 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 64759 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 64760 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 64761 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 64762 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 64763 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 64764 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 64765 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 64766 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 64767 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 64768 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 64769 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 64770 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 64771 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 64772 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 64773 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 64774 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 64775 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 64776 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 64777 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP |
|---|
| 64778 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 64779 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 64780 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 64781 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 64782 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 64783 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 64784 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL |
|---|
| 64785 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 64786 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 64787 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 64788 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 64789 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 64790 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 64791 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 64792 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 64793 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 64794 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 64795 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 64796 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP |
|---|
| 64797 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 64798 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 64799 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 64800 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 64801 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 64802 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 64803 | //BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL |
|---|
| 64804 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 64805 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 64806 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 64807 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 64808 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 64809 | #define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 64810 | |
|---|
| 64811 | |
|---|
| 64812 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp |
|---|
| 64813 | //BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID |
|---|
| 64814 | #define BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 64815 | #define BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 64816 | //BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID |
|---|
| 64817 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 64818 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 64819 | //BIF_CFG_DEV0_EPF0_VF10_0_COMMAND |
|---|
| 64820 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 64821 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 64822 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 64823 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 64824 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 64825 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 64826 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 64827 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 64828 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 64829 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 64830 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 64831 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 64832 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 64833 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 64834 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 64835 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 64836 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 64837 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 64838 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 64839 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 64840 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 64841 | #define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 64842 | //BIF_CFG_DEV0_EPF0_VF10_0_STATUS |
|---|
| 64843 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 64844 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 64845 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 64846 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 64847 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 64848 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 64849 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 64850 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 64851 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 64852 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 64853 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 64854 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 64855 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 64856 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 64857 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 64858 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 64859 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 64860 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 64861 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 64862 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 64863 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 64864 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 64865 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 64866 | #define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 64867 | //BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID |
|---|
| 64868 | #define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 64869 | #define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 64870 | #define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 64871 | #define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 64872 | //BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE |
|---|
| 64873 | #define BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 64874 | #define BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 64875 | //BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS |
|---|
| 64876 | #define BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 64877 | #define BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 64878 | //BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS |
|---|
| 64879 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 64880 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 64881 | //BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE |
|---|
| 64882 | #define BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 64883 | #define BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 64884 | //BIF_CFG_DEV0_EPF0_VF10_0_LATENCY |
|---|
| 64885 | #define BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 64886 | #define BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 64887 | //BIF_CFG_DEV0_EPF0_VF10_0_HEADER |
|---|
| 64888 | #define 0x0 |
|---|
| 64889 | #define 0x7 |
|---|
| 64890 | #define 0x7FL |
|---|
| 64891 | #define 0x80L |
|---|
| 64892 | //BIF_CFG_DEV0_EPF0_VF10_0_BIST |
|---|
| 64893 | #define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 64894 | #define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 64895 | #define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 64896 | #define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 64897 | #define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 64898 | #define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 64899 | //BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 |
|---|
| 64900 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 64901 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64902 | //BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 |
|---|
| 64903 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 64904 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64905 | //BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 |
|---|
| 64906 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 64907 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64908 | //BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 |
|---|
| 64909 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 64910 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64911 | //BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 |
|---|
| 64912 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 64913 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64914 | //BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 |
|---|
| 64915 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 64916 | #define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64917 | //BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR |
|---|
| 64918 | #define BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 64919 | #define BIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 64920 | //BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID |
|---|
| 64921 | #define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 64922 | #define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 64923 | #define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 64924 | #define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 64925 | //BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR |
|---|
| 64926 | #define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 64927 | #define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 64928 | //BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR |
|---|
| 64929 | #define BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 64930 | #define BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 64931 | //BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE |
|---|
| 64932 | #define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 64933 | #define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 64934 | //BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN |
|---|
| 64935 | #define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 64936 | #define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 64937 | //BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT |
|---|
| 64938 | #define BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 64939 | #define BIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 64940 | //BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY |
|---|
| 64941 | #define BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 64942 | #define BIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 64943 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST |
|---|
| 64944 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 64945 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 64946 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 64947 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 64948 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP |
|---|
| 64949 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 64950 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 64951 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 64952 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 64953 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 64954 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 64955 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 64956 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 64957 | //BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP |
|---|
| 64958 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 64959 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 64960 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 64961 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 64962 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 64963 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 64964 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 64965 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 64966 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 64967 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 64968 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 64969 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 64970 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 64971 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 64972 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 64973 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 64974 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 64975 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 64976 | //BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL |
|---|
| 64977 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 64978 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 64979 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 64980 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 64981 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 64982 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 64983 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 64984 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 64985 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 64986 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 64987 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 64988 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 64989 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 64990 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 64991 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 64992 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 64993 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 64994 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 64995 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 64996 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 64997 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 64998 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 64999 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 65000 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 65001 | //BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS |
|---|
| 65002 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 65003 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 65004 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 65005 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 65006 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 65007 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 65008 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 65009 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 65010 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 65011 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 65012 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 65013 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 65014 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 65015 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 65016 | //BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP |
|---|
| 65017 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 65018 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 65019 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 65020 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 65021 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 65022 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 65023 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 65024 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 65025 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 65026 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 65027 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 65028 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 65029 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 65030 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 65031 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 65032 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 65033 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 65034 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 65035 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 65036 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 65037 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 65038 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 65039 | //BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL |
|---|
| 65040 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 65041 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 65042 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 65043 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 65044 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 65045 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 65046 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 65047 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 65048 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 65049 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 65050 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 65051 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 65052 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 65053 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 65054 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 65055 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 65056 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 65057 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 65058 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 65059 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 65060 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 65061 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 65062 | //BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS |
|---|
| 65063 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 65064 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 65065 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 65066 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 65067 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 65068 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 65069 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 65070 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 65071 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 65072 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 65073 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 65074 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 65075 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 65076 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 65077 | //BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 |
|---|
| 65078 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 65079 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 65080 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 65081 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 65082 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 65083 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 65084 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 65085 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 65086 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 65087 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 65088 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 65089 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 65090 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 65091 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 65092 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 65093 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 65094 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 65095 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 65096 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 65097 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 65098 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 65099 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 65100 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 65101 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 65102 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 65103 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 65104 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 65105 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 65106 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 65107 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 65108 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 65109 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 65110 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 65111 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 65112 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 65113 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 65114 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 65115 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 65116 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 65117 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 65118 | //BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 |
|---|
| 65119 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 65120 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 65121 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 65122 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 65123 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 65124 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 65125 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 65126 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 65127 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 65128 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 65129 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 65130 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 65131 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 65132 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 65133 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 65134 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 65135 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 65136 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 65137 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 65138 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 65139 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 65140 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 65141 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 65142 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 65143 | //BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 |
|---|
| 65144 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 65145 | #define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 65146 | //BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 |
|---|
| 65147 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 65148 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 65149 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 65150 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 65151 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 65152 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 65153 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 65154 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 65155 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 65156 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 65157 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 65158 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 65159 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 65160 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 65161 | //BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 |
|---|
| 65162 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 65163 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 65164 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 65165 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 65166 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 65167 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 65168 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 65169 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 65170 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 65171 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 65172 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 65173 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 65174 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 65175 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 65176 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 65177 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 65178 | //BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 |
|---|
| 65179 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 65180 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 65181 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 65182 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 65183 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 65184 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 65185 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 65186 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 65187 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 65188 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 65189 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 65190 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 65191 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 65192 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 65193 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 65194 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 65195 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 65196 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 65197 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 65198 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 65199 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 65200 | #define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 65201 | //BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST |
|---|
| 65202 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 65203 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 65204 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 65205 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 65206 | //BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL |
|---|
| 65207 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 65208 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 65209 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 65210 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 65211 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 65212 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 65213 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 65214 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 65215 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 65216 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 65217 | //BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO |
|---|
| 65218 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 65219 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 65220 | //BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI |
|---|
| 65221 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 65222 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 65223 | //BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA |
|---|
| 65224 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 65225 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 65226 | //BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK |
|---|
| 65227 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 65228 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 65229 | //BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 |
|---|
| 65230 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 65231 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 65232 | //BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 |
|---|
| 65233 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 65234 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 65235 | //BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING |
|---|
| 65236 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 65237 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 65238 | //BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 |
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| 65239 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
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| 65240 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
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| 65241 | //BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST |
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| 65242 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 65243 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 65244 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 65245 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 65246 | //BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL |
|---|
| 65247 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
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| 65248 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
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| 65249 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
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| 65250 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
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| 65251 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 65252 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
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| 65253 | //BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE |
|---|
| 65254 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
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| 65255 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
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| 65256 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
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| 65257 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
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| 65258 | //BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA |
|---|
| 65259 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
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| 65260 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 65261 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 65262 | #define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
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| 65263 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 65264 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 65265 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 65266 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 65267 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 65268 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 65269 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 65270 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 65271 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 65272 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 65273 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 65274 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 65275 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 65276 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 65277 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 65278 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 65279 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 65280 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 65281 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 65282 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 65283 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 65284 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 65285 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 65286 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 65287 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 65288 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 65289 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 65290 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 65291 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 65292 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 65293 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 65294 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 65295 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 65296 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 65297 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 65298 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 65299 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 65300 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 65301 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 65302 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 65303 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 65304 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 65305 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 65306 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 65307 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 65308 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 65309 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 65310 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 65311 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 65312 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 65313 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 65314 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 65315 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 65316 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 65317 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 65318 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 65319 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 65320 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 65321 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 65322 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 65323 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK |
|---|
| 65324 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 65325 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 65326 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 65327 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 65328 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 65329 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 65330 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 65331 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 65332 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 65333 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 65334 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 65335 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 65336 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 65337 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 65338 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 65339 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 65340 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 65341 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 65342 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 65343 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 65344 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 65345 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 65346 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 65347 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 65348 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 65349 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 65350 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 65351 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 65352 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 65353 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 65354 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 65355 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 65356 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 65357 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 65358 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 65359 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 65360 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 65361 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 65362 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 65363 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 65364 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 65365 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 65366 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 65367 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 65368 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 65369 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 65370 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 65371 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 65372 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 65373 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 65374 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 65375 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 65376 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 65377 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 65378 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 65379 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 65380 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 65381 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 65382 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 65383 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 65384 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 65385 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 65386 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 65387 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 65388 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 65389 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS |
|---|
| 65390 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 65391 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 65392 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 65393 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 65394 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 65395 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 65396 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 65397 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 65398 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 65399 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 65400 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 65401 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 65402 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 65403 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 65404 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 65405 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 65406 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK |
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| 65407 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 65408 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 65409 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 65410 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 65411 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 65412 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 65413 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 65414 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 65415 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 65416 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 65417 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 65418 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 65419 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 65420 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 65421 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 65422 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 65423 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL |
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| 65424 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 65425 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 65426 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 65427 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 65428 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 65429 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 65430 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 65431 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 65432 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 65433 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 65434 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 65435 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 65436 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 65437 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
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| 65438 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
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| 65439 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
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| 65440 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
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| 65441 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
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| 65442 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 |
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| 65443 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
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| 65444 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
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| 65445 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 |
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| 65446 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
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| 65447 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
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| 65448 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 |
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| 65449 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
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| 65450 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
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| 65451 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 |
|---|
| 65452 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
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| 65453 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
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| 65454 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 65455 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
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| 65456 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 65457 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 |
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| 65458 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
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| 65459 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 65460 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 |
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| 65461 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
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| 65462 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 65463 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 |
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| 65464 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
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| 65465 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 65466 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST |
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| 65467 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 65468 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 65469 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 65470 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 65471 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 65472 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 65473 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP |
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| 65474 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
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| 65475 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
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| 65476 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
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| 65477 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
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| 65478 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
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| 65479 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
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| 65480 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL |
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| 65481 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
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| 65482 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
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| 65483 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
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| 65484 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
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| 65485 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST |
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| 65486 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 65487 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 65488 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 65489 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 65490 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 65491 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 65492 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP |
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| 65493 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
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| 65494 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
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| 65495 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
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| 65496 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
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| 65497 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
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| 65498 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
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| 65499 | //BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL |
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| 65500 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
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| 65501 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
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| 65502 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
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| 65503 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
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| 65504 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
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| 65505 | #define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
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| 65506 | |
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| 65507 | |
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| 65508 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp |
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| 65509 | //BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID |
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| 65510 | #define BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
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| 65511 | #define BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
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| 65512 | //BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID |
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| 65513 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
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| 65514 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
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| 65515 | //BIF_CFG_DEV0_EPF0_VF11_0_COMMAND |
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| 65516 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
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| 65517 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
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| 65518 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
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| 65519 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
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| 65520 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
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| 65521 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
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| 65522 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
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| 65523 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
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| 65524 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN__SHIFT 0x8 |
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| 65525 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
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| 65526 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS__SHIFT 0xa |
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| 65527 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
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| 65528 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
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| 65529 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
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| 65530 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
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| 65531 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
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| 65532 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
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| 65533 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
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| 65534 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING_MASK 0x0080L |
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| 65535 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN_MASK 0x0100L |
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| 65536 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
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| 65537 | #define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS_MASK 0x0400L |
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| 65538 | //BIF_CFG_DEV0_EPF0_VF11_0_STATUS |
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| 65539 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
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| 65540 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS__SHIFT 0x3 |
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| 65541 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST__SHIFT 0x4 |
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| 65542 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
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| 65543 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
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| 65544 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
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| 65545 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
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| 65546 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
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| 65547 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
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| 65548 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
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| 65549 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
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| 65550 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
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| 65551 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
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| 65552 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS_MASK 0x0008L |
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| 65553 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST_MASK 0x0010L |
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| 65554 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_CAP_MASK 0x0020L |
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| 65555 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
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| 65556 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
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| 65557 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 65558 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 65559 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 65560 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 65561 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 65562 | #define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 65563 | //BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID |
|---|
| 65564 | #define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 65565 | #define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 65566 | #define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 65567 | #define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 65568 | //BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE |
|---|
| 65569 | #define BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 65570 | #define BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 65571 | //BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS |
|---|
| 65572 | #define BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 65573 | #define BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 65574 | //BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS |
|---|
| 65575 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 65576 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 65577 | //BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE |
|---|
| 65578 | #define BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 65579 | #define BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 65580 | //BIF_CFG_DEV0_EPF0_VF11_0_LATENCY |
|---|
| 65581 | #define BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 65582 | #define BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 65583 | //BIF_CFG_DEV0_EPF0_VF11_0_HEADER |
|---|
| 65584 | #define 0x0 |
|---|
| 65585 | #define 0x7 |
|---|
| 65586 | #define 0x7FL |
|---|
| 65587 | #define 0x80L |
|---|
| 65588 | //BIF_CFG_DEV0_EPF0_VF11_0_BIST |
|---|
| 65589 | #define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 65590 | #define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 65591 | #define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 65592 | #define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 65593 | #define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 65594 | #define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 65595 | //BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 |
|---|
| 65596 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 65597 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 65598 | //BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 |
|---|
| 65599 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 65600 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 65601 | //BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 |
|---|
| 65602 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 65603 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 65604 | //BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 |
|---|
| 65605 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 65606 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 65607 | //BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 |
|---|
| 65608 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 65609 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 65610 | //BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 |
|---|
| 65611 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 65612 | #define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 65613 | //BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR |
|---|
| 65614 | #define BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 65615 | #define BIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 65616 | //BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID |
|---|
| 65617 | #define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 65618 | #define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 65619 | #define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 65620 | #define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 65621 | //BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR |
|---|
| 65622 | #define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 65623 | #define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 65624 | //BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR |
|---|
| 65625 | #define BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 65626 | #define BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 65627 | //BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE |
|---|
| 65628 | #define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 65629 | #define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 65630 | //BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN |
|---|
| 65631 | #define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 65632 | #define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 65633 | //BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT |
|---|
| 65634 | #define BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 65635 | #define BIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 65636 | //BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY |
|---|
| 65637 | #define BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 65638 | #define BIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 65639 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST |
|---|
| 65640 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 65641 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 65642 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 65643 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 65644 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP |
|---|
| 65645 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 65646 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 65647 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 65648 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 65649 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 65650 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 65651 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 65652 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 65653 | //BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP |
|---|
| 65654 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 65655 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 65656 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 65657 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 65658 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 65659 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 65660 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 65661 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 65662 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 65663 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 65664 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 65665 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 65666 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 65667 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 65668 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 65669 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 65670 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 65671 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 65672 | //BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL |
|---|
| 65673 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 65674 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 65675 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 65676 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 65677 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 65678 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 65679 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 65680 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 65681 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 65682 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 65683 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 65684 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 65685 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 65686 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 65687 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 65688 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 65689 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 65690 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 65691 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 65692 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 65693 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 65694 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 65695 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 65696 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 65697 | //BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS |
|---|
| 65698 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 65699 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 65700 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 65701 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 65702 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 65703 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 65704 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 65705 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 65706 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 65707 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 65708 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 65709 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 65710 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 65711 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 65712 | //BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP |
|---|
| 65713 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 65714 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 65715 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 65716 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 65717 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 65718 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 65719 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 65720 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 65721 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 65722 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 65723 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 65724 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 65725 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 65726 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 65727 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 65728 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 65729 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 65730 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 65731 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 65732 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 65733 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 65734 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 65735 | //BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL |
|---|
| 65736 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 65737 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 65738 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 65739 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 65740 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 65741 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 65742 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 65743 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 65744 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 65745 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 65746 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 65747 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 65748 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 65749 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 65750 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 65751 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 65752 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 65753 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 65754 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 65755 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 65756 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 65757 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 65758 | //BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS |
|---|
| 65759 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 65760 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 65761 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 65762 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 65763 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 65764 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 65765 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 65766 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 65767 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 65768 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 65769 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 65770 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 65771 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 65772 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 65773 | //BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 |
|---|
| 65774 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 65775 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 65776 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 65777 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 65778 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 65779 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 65780 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 65781 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 65782 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 65783 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 65784 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 65785 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 65786 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 65787 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 65788 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 65789 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 65790 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 65791 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 65792 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 65793 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 65794 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 65795 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 65796 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 65797 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 65798 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 65799 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 65800 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 65801 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 65802 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 65803 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 65804 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 65805 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 65806 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 65807 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 65808 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 65809 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 65810 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 65811 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 65812 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 65813 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 65814 | //BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 |
|---|
| 65815 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 65816 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 65817 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 65818 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 65819 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 65820 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 65821 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 65822 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 65823 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 65824 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 65825 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 65826 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 65827 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 65828 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 65829 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 65830 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 65831 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 65832 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 65833 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 65834 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 65835 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 65836 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 65837 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 65838 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 65839 | //BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 |
|---|
| 65840 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 65841 | #define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 65842 | //BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 |
|---|
| 65843 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 65844 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 65845 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 65846 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 65847 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 65848 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 65849 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 65850 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 65851 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 65852 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 65853 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 65854 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 65855 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 65856 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 65857 | //BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 |
|---|
| 65858 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 65859 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 65860 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 65861 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 65862 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 65863 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 65864 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 65865 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 65866 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 65867 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 65868 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 65869 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 65870 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 65871 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 65872 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 65873 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 65874 | //BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 |
|---|
| 65875 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 65876 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 65877 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 65878 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 65879 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 65880 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 65881 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 65882 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 65883 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 65884 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 65885 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 65886 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 65887 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 65888 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 65889 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 65890 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 65891 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 65892 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 65893 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 65894 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 65895 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 65896 | #define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 65897 | //BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST |
|---|
| 65898 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 65899 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 65900 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 65901 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 65902 | //BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL |
|---|
| 65903 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 65904 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 65905 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 65906 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 65907 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 65908 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 65909 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 65910 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 65911 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 65912 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 65913 | //BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO |
|---|
| 65914 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 65915 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 65916 | //BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI |
|---|
| 65917 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 65918 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 65919 | //BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA |
|---|
| 65920 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 65921 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 65922 | //BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK |
|---|
| 65923 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 65924 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 65925 | //BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 |
|---|
| 65926 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 65927 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 65928 | //BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 |
|---|
| 65929 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 65930 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 65931 | //BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING |
|---|
| 65932 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 65933 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 65934 | //BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 |
|---|
| 65935 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 65936 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 65937 | //BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST |
|---|
| 65938 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 65939 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 65940 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 65941 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 65942 | //BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL |
|---|
| 65943 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 65944 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 65945 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 65946 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 65947 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 65948 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 65949 | //BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE |
|---|
| 65950 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 65951 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 65952 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 65953 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 65954 | //BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA |
|---|
| 65955 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 65956 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 65957 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 65958 | #define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 65959 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 65960 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 65961 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 65962 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 65963 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 65964 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 65965 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 65966 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 65967 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 65968 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 65969 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 65970 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 65971 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 65972 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 65973 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 65974 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 65975 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 65976 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 65977 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 65978 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 65979 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 65980 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 65981 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 65982 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 65983 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 65984 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 65985 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 65986 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 65987 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 65988 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 65989 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 65990 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 65991 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 65992 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 65993 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 65994 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 65995 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 65996 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 65997 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 65998 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 65999 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 66000 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 66001 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 66002 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 66003 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 66004 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 66005 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 66006 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 66007 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 66008 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 66009 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 66010 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 66011 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 66012 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 66013 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 66014 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 66015 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 66016 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 66017 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 66018 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 66019 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK |
|---|
| 66020 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 66021 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 66022 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 66023 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 66024 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 66025 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 66026 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 66027 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 66028 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 66029 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 66030 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 66031 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 66032 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 66033 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 66034 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 66035 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 66036 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 66037 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 66038 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 66039 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 66040 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 66041 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 66042 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 66043 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 66044 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 66045 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 66046 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 66047 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 66048 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 66049 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 66050 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 66051 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 66052 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 66053 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 66054 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 66055 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 66056 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 66057 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 66058 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 66059 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 66060 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 66061 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 66062 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 66063 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 66064 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 66065 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 66066 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 66067 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 66068 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 66069 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 66070 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 66071 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 66072 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 66073 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 66074 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 66075 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 66076 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 66077 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 66078 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 66079 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 66080 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 66081 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 66082 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 66083 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 66084 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 66085 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS |
|---|
| 66086 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 66087 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 66088 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 66089 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 66090 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 66091 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 66092 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 66093 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 66094 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 66095 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 66096 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 66097 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 66098 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 66099 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 66100 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 66101 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 66102 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK |
|---|
| 66103 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 66104 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 66105 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 66106 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 66107 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 66108 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 66109 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 66110 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 66111 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 66112 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 66113 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 66114 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 66115 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 66116 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 66117 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 66118 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 66119 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 66120 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 66121 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 66122 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 66123 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 66124 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 66125 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 66126 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 66127 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 66128 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 66129 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 66130 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 66131 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 66132 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 66133 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 66134 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 66135 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 66136 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 66137 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 66138 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 |
|---|
| 66139 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 66140 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 66141 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 |
|---|
| 66142 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 66143 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 66144 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 |
|---|
| 66145 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 66146 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 66147 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 |
|---|
| 66148 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 66149 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 66150 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 66151 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 66152 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 66153 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 66154 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 66155 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 66156 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 66157 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 66158 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 66159 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 66160 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 66161 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 66162 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 66163 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 66164 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 66165 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 66166 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 66167 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 66168 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 66169 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP |
|---|
| 66170 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 66171 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 66172 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 66173 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 66174 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 66175 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 66176 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL |
|---|
| 66177 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 66178 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 66179 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 66180 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 66181 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 66182 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 66183 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 66184 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 66185 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 66186 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 66187 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 66188 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP |
|---|
| 66189 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 66190 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 66191 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 66192 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 66193 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 66194 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 66195 | //BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL |
|---|
| 66196 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 66197 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 66198 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 66199 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 66200 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 66201 | #define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 66202 | |
|---|
| 66203 | |
|---|
| 66204 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp |
|---|
| 66205 | //BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID |
|---|
| 66206 | #define BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 66207 | #define BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 66208 | //BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID |
|---|
| 66209 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 66210 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 66211 | //BIF_CFG_DEV0_EPF0_VF12_0_COMMAND |
|---|
| 66212 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 66213 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 66214 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 66215 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 66216 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 66217 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 66218 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 66219 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 66220 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 66221 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 66222 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 66223 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 66224 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 66225 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 66226 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 66227 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 66228 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 66229 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 66230 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 66231 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 66232 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 66233 | #define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 66234 | //BIF_CFG_DEV0_EPF0_VF12_0_STATUS |
|---|
| 66235 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 66236 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 66237 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 66238 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 66239 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 66240 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 66241 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 66242 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 66243 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 66244 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 66245 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 66246 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 66247 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 66248 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 66249 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 66250 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 66251 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 66252 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 66253 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 66254 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 66255 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 66256 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 66257 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 66258 | #define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 66259 | //BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID |
|---|
| 66260 | #define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 66261 | #define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 66262 | #define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 66263 | #define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 66264 | //BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE |
|---|
| 66265 | #define BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 66266 | #define BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 66267 | //BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS |
|---|
| 66268 | #define BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 66269 | #define BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 66270 | //BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS |
|---|
| 66271 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 66272 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 66273 | //BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE |
|---|
| 66274 | #define BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 66275 | #define BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 66276 | //BIF_CFG_DEV0_EPF0_VF12_0_LATENCY |
|---|
| 66277 | #define BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 66278 | #define BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 66279 | //BIF_CFG_DEV0_EPF0_VF12_0_HEADER |
|---|
| 66280 | #define 0x0 |
|---|
| 66281 | #define 0x7 |
|---|
| 66282 | #define 0x7FL |
|---|
| 66283 | #define 0x80L |
|---|
| 66284 | //BIF_CFG_DEV0_EPF0_VF12_0_BIST |
|---|
| 66285 | #define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 66286 | #define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 66287 | #define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 66288 | #define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 66289 | #define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 66290 | #define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 66291 | //BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 |
|---|
| 66292 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 66293 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66294 | //BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 |
|---|
| 66295 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 66296 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66297 | //BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 |
|---|
| 66298 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 66299 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66300 | //BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 |
|---|
| 66301 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 66302 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66303 | //BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 |
|---|
| 66304 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 66305 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66306 | //BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 |
|---|
| 66307 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 66308 | #define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66309 | //BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR |
|---|
| 66310 | #define BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 66311 | #define BIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 66312 | //BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID |
|---|
| 66313 | #define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 66314 | #define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 66315 | #define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 66316 | #define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 66317 | //BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR |
|---|
| 66318 | #define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 66319 | #define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66320 | //BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR |
|---|
| 66321 | #define BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 66322 | #define BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 66323 | //BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE |
|---|
| 66324 | #define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 66325 | #define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 66326 | //BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN |
|---|
| 66327 | #define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 66328 | #define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 66329 | //BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT |
|---|
| 66330 | #define BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 66331 | #define BIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 66332 | //BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY |
|---|
| 66333 | #define BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 66334 | #define BIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 66335 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST |
|---|
| 66336 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 66337 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 66338 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 66339 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 66340 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP |
|---|
| 66341 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 66342 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 66343 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 66344 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 66345 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 66346 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 66347 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 66348 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 66349 | //BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP |
|---|
| 66350 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 66351 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 66352 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 66353 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 66354 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 66355 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 66356 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 66357 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 66358 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 66359 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 66360 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 66361 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 66362 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 66363 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 66364 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 66365 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 66366 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 66367 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 66368 | //BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL |
|---|
| 66369 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 66370 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 66371 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 66372 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 66373 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 66374 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 66375 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 66376 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 66377 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 66378 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 66379 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 66380 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 66381 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 66382 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 66383 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 66384 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 66385 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 66386 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 66387 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 66388 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 66389 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 66390 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 66391 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 66392 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 66393 | //BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS |
|---|
| 66394 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 66395 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 66396 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 66397 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 66398 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 66399 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 66400 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 66401 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 66402 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 66403 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 66404 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 66405 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 66406 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 66407 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 66408 | //BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP |
|---|
| 66409 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 66410 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 66411 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 66412 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 66413 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 66414 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 66415 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 66416 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 66417 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 66418 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 66419 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 66420 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 66421 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 66422 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 66423 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 66424 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 66425 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 66426 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 66427 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 66428 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 66429 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 66430 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 66431 | //BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL |
|---|
| 66432 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 66433 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 66434 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 66435 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 66436 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 66437 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 66438 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 66439 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 66440 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 66441 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 66442 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 66443 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 66444 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 66445 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 66446 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 66447 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 66448 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 66449 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 66450 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 66451 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 66452 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 66453 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 66454 | //BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS |
|---|
| 66455 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 66456 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 66457 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 66458 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 66459 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 66460 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 66461 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 66462 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 66463 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 66464 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 66465 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 66466 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 66467 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 66468 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 66469 | //BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 |
|---|
| 66470 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 66471 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 66472 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 66473 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 66474 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 66475 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 66476 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 66477 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 66478 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 66479 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 66480 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 66481 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 66482 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 66483 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 66484 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 66485 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 66486 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 66487 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 66488 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 66489 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 66490 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 66491 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 66492 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 66493 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 66494 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 66495 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 66496 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 66497 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 66498 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 66499 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 66500 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 66501 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 66502 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 66503 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 66504 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 66505 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 66506 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 66507 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 66508 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 66509 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 66510 | //BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 |
|---|
| 66511 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 66512 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 66513 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 66514 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 66515 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 66516 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 66517 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 66518 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 66519 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 66520 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 66521 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 66522 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 66523 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 66524 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 66525 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 66526 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 66527 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 66528 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 66529 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 66530 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 66531 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 66532 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 66533 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 66534 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 66535 | //BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 |
|---|
| 66536 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 66537 | #define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 66538 | //BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 |
|---|
| 66539 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 66540 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 66541 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 66542 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 66543 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 66544 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 66545 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 66546 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 66547 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 66548 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 66549 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 66550 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 66551 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 66552 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 66553 | //BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 |
|---|
| 66554 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 66555 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 66556 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 66557 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 66558 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 66559 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 66560 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 66561 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 66562 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 66563 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 66564 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 66565 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 66566 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 66567 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 66568 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 66569 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 66570 | //BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 |
|---|
| 66571 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 66572 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 66573 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 66574 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 66575 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 66576 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 66577 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 66578 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 66579 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 66580 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 66581 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 66582 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 66583 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 66584 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 66585 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 66586 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 66587 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 66588 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 66589 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 66590 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 66591 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 66592 | #define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 66593 | //BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST |
|---|
| 66594 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 66595 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 66596 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 66597 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 66598 | //BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL |
|---|
| 66599 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 66600 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 66601 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 66602 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 66603 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 66604 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 66605 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 66606 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 66607 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 66608 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 66609 | //BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO |
|---|
| 66610 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 66611 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 66612 | //BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI |
|---|
| 66613 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 66614 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 66615 | //BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA |
|---|
| 66616 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 66617 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 66618 | //BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK |
|---|
| 66619 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 66620 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 66621 | //BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 |
|---|
| 66622 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 66623 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 66624 | //BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 |
|---|
| 66625 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 66626 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 66627 | //BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING |
|---|
| 66628 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 66629 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 66630 | //BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 |
|---|
| 66631 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 66632 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 66633 | //BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST |
|---|
| 66634 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 66635 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 66636 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 66637 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 66638 | //BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL |
|---|
| 66639 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 66640 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 66641 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 66642 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 66643 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 66644 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 66645 | //BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE |
|---|
| 66646 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 66647 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 66648 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 66649 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 66650 | //BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA |
|---|
| 66651 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 66652 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 66653 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 66654 | #define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 66655 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 66656 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 66657 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 66658 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 66659 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 66660 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 66661 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 66662 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 66663 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 66664 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 66665 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 66666 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 66667 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 66668 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 66669 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 66670 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 66671 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 66672 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 66673 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 66674 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 66675 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 66676 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 66677 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 66678 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 66679 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 66680 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 66681 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 66682 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 66683 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 66684 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 66685 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 66686 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 66687 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 66688 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 66689 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 66690 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 66691 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 66692 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 66693 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 66694 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 66695 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 66696 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 66697 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 66698 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 66699 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 66700 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 66701 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 66702 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 66703 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 66704 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 66705 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 66706 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 66707 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 66708 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 66709 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 66710 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 66711 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 66712 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 66713 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 66714 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 66715 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK |
|---|
| 66716 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 66717 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 66718 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 66719 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 66720 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 66721 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 66722 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 66723 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 66724 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 66725 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 66726 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 66727 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 66728 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 66729 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 66730 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 66731 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 66732 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 66733 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 66734 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 66735 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 66736 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 66737 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 66738 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 66739 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 66740 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 66741 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 66742 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 66743 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 66744 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 66745 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 66746 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 66747 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 66748 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 66749 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 66750 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 66751 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 66752 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 66753 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 66754 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 66755 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 66756 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 66757 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 66758 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 66759 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 66760 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 66761 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 66762 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 66763 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 66764 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 66765 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 66766 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 66767 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 66768 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 66769 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 66770 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 66771 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 66772 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 66773 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 66774 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 66775 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 66776 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 66777 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 66778 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 66779 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 66780 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 66781 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS |
|---|
| 66782 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 66783 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 66784 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 66785 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 66786 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 66787 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 66788 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 66789 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 66790 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 66791 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 66792 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 66793 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 66794 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 66795 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 66796 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 66797 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 66798 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK |
|---|
| 66799 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 66800 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 66801 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 66802 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 66803 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 66804 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 66805 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 66806 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 66807 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 66808 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 66809 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 66810 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 66811 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 66812 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 66813 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 66814 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 66815 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 66816 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 66817 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 66818 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 66819 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 66820 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 66821 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 66822 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 66823 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 66824 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 66825 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 66826 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 66827 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 66828 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 66829 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 66830 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 66831 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 66832 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 66833 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 66834 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 |
|---|
| 66835 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 66836 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 66837 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 |
|---|
| 66838 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 66839 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 66840 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 |
|---|
| 66841 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 66842 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 66843 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 |
|---|
| 66844 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 66845 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 66846 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 66847 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 66848 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 66849 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 66850 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 66851 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 66852 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 66853 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 66854 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 66855 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 66856 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 66857 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 66858 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 66859 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 66860 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 66861 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 66862 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 66863 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 66864 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 66865 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP |
|---|
| 66866 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 66867 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 66868 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 66869 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 66870 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 66871 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 66872 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL |
|---|
| 66873 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 66874 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 66875 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 66876 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 66877 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 66878 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 66879 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 66880 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 66881 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 66882 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 66883 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 66884 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP |
|---|
| 66885 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 66886 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 66887 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 66888 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 66889 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 66890 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 66891 | //BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL |
|---|
| 66892 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 66893 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 66894 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 66895 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 66896 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 66897 | #define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 66898 | |
|---|
| 66899 | |
|---|
| 66900 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp |
|---|
| 66901 | //BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID |
|---|
| 66902 | #define BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 66903 | #define BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 66904 | //BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID |
|---|
| 66905 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 66906 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 66907 | //BIF_CFG_DEV0_EPF0_VF13_0_COMMAND |
|---|
| 66908 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 66909 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 66910 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 66911 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 66912 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 66913 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 66914 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 66915 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 66916 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 66917 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 66918 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 66919 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 66920 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 66921 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 66922 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 66923 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 66924 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 66925 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 66926 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 66927 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 66928 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 66929 | #define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 66930 | //BIF_CFG_DEV0_EPF0_VF13_0_STATUS |
|---|
| 66931 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 66932 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 66933 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 66934 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 66935 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 66936 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 66937 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 66938 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 66939 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 66940 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 66941 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 66942 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 66943 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 66944 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 66945 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 66946 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 66947 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 66948 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 66949 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 66950 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 66951 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 66952 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 66953 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 66954 | #define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 66955 | //BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID |
|---|
| 66956 | #define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 66957 | #define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 66958 | #define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 66959 | #define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 66960 | //BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE |
|---|
| 66961 | #define BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 66962 | #define BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 66963 | //BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS |
|---|
| 66964 | #define BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 66965 | #define BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 66966 | //BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS |
|---|
| 66967 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 66968 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 66969 | //BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE |
|---|
| 66970 | #define BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 66971 | #define BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 66972 | //BIF_CFG_DEV0_EPF0_VF13_0_LATENCY |
|---|
| 66973 | #define BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 66974 | #define BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 66975 | //BIF_CFG_DEV0_EPF0_VF13_0_HEADER |
|---|
| 66976 | #define 0x0 |
|---|
| 66977 | #define 0x7 |
|---|
| 66978 | #define 0x7FL |
|---|
| 66979 | #define 0x80L |
|---|
| 66980 | //BIF_CFG_DEV0_EPF0_VF13_0_BIST |
|---|
| 66981 | #define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 66982 | #define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 66983 | #define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 66984 | #define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 66985 | #define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 66986 | #define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 66987 | //BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 |
|---|
| 66988 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 66989 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66990 | //BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 |
|---|
| 66991 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 66992 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66993 | //BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 |
|---|
| 66994 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 66995 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66996 | //BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 |
|---|
| 66997 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 66998 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 66999 | //BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 |
|---|
| 67000 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 67001 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 67002 | //BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 |
|---|
| 67003 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 67004 | #define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 67005 | //BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR |
|---|
| 67006 | #define BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 67007 | #define BIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 67008 | //BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID |
|---|
| 67009 | #define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 67010 | #define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 67011 | #define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 67012 | #define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 67013 | //BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR |
|---|
| 67014 | #define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 67015 | #define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 67016 | //BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR |
|---|
| 67017 | #define BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 67018 | #define BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 67019 | //BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE |
|---|
| 67020 | #define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 67021 | #define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 67022 | //BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN |
|---|
| 67023 | #define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 67024 | #define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 67025 | //BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT |
|---|
| 67026 | #define BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 67027 | #define BIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 67028 | //BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY |
|---|
| 67029 | #define BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 67030 | #define BIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 67031 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST |
|---|
| 67032 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 67033 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 67034 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 67035 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 67036 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP |
|---|
| 67037 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 67038 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 67039 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 67040 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 67041 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 67042 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 67043 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 67044 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 67045 | //BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP |
|---|
| 67046 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 67047 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 67048 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 67049 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 67050 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 67051 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 67052 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 67053 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 67054 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 67055 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 67056 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 67057 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 67058 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 67059 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 67060 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 67061 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 67062 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 67063 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 67064 | //BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL |
|---|
| 67065 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 67066 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 67067 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 67068 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 67069 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 67070 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 67071 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 67072 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 67073 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 67074 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 67075 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 67076 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 67077 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 67078 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 67079 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 67080 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 67081 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 67082 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 67083 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 67084 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 67085 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 67086 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 67087 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 67088 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 67089 | //BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS |
|---|
| 67090 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 67091 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 67092 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 67093 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 67094 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 67095 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 67096 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 67097 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 67098 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 67099 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 67100 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 67101 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 67102 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 67103 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 67104 | //BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP |
|---|
| 67105 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 67106 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 67107 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 67108 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 67109 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 67110 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 67111 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 67112 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 67113 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 67114 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 67115 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 67116 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 67117 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 67118 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 67119 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 67120 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 67121 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 67122 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 67123 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 67124 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 67125 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 67126 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 67127 | //BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL |
|---|
| 67128 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 67129 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 67130 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 67131 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 67132 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 67133 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 67134 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 67135 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 67136 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 67137 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 67138 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 67139 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 67140 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 67141 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 67142 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 67143 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 67144 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 67145 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 67146 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 67147 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 67148 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 67149 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 67150 | //BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS |
|---|
| 67151 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 67152 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 67153 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 67154 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 67155 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 67156 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 67157 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 67158 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 67159 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 67160 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 67161 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 67162 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 67163 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 67164 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 67165 | //BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 |
|---|
| 67166 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 67167 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 67168 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 67169 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 67170 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 67171 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 67172 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 67173 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 67174 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 67175 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 67176 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 67177 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 67178 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 67179 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 67180 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 67181 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 67182 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 67183 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 67184 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 67185 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 67186 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 67187 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 67188 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 67189 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 67190 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 67191 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 67192 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 67193 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 67194 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 67195 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 67196 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 67197 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 67198 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 67199 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 67200 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 67201 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 67202 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 67203 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 67204 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 67205 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 67206 | //BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 |
|---|
| 67207 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 67208 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 67209 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 67210 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 67211 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 67212 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 67213 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 67214 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 67215 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 67216 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 67217 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 67218 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 67219 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 67220 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 67221 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 67222 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 67223 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 67224 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 67225 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 67226 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 67227 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 67228 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 67229 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 67230 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 67231 | //BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 |
|---|
| 67232 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 67233 | #define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 67234 | //BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 |
|---|
| 67235 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 67236 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 67237 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 67238 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 67239 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 67240 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 67241 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 67242 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 67243 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 67244 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 67245 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 67246 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 67247 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 67248 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 67249 | //BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 |
|---|
| 67250 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 67251 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 67252 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 67253 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 67254 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 67255 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 67256 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 67257 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 67258 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 67259 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 67260 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 67261 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 67262 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 67263 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 67264 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 67265 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 67266 | //BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 |
|---|
| 67267 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 67268 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 67269 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 67270 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 67271 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 67272 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 67273 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 67274 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 67275 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 67276 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 67277 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 67278 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 67279 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 67280 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 67281 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 67282 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 67283 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 67284 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 67285 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 67286 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 67287 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 67288 | #define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 67289 | //BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST |
|---|
| 67290 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 67291 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 67292 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 67293 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 67294 | //BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL |
|---|
| 67295 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 67296 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 67297 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 67298 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 67299 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 67300 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 67301 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 67302 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 67303 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 67304 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 67305 | //BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO |
|---|
| 67306 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 67307 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 67308 | //BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI |
|---|
| 67309 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 67310 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 67311 | //BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA |
|---|
| 67312 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 67313 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 67314 | //BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK |
|---|
| 67315 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 67316 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 67317 | //BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 |
|---|
| 67318 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 67319 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 67320 | //BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 |
|---|
| 67321 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 67322 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 67323 | //BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING |
|---|
| 67324 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 67325 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 67326 | //BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 |
|---|
| 67327 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 67328 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 67329 | //BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST |
|---|
| 67330 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 67331 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 67332 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 67333 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 67334 | //BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL |
|---|
| 67335 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 67336 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 67337 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 67338 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 67339 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 67340 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 67341 | //BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE |
|---|
| 67342 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 67343 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 67344 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 67345 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 67346 | //BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA |
|---|
| 67347 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 67348 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 67349 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 67350 | #define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 67351 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 67352 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 67353 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 67354 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 67355 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 67356 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 67357 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 67358 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 67359 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 67360 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 67361 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 67362 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 67363 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 67364 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 67365 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 67366 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 67367 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 67368 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 67369 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 67370 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 67371 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 67372 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 67373 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 67374 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 67375 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 67376 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 67377 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 67378 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 67379 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 67380 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 67381 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 67382 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 67383 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 67384 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 67385 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 67386 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 67387 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 67388 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 67389 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 67390 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 67391 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 67392 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 67393 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 67394 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 67395 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 67396 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 67397 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 67398 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 67399 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 67400 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 67401 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 67402 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 67403 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 67404 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 67405 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 67406 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 67407 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 67408 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 67409 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 67410 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 67411 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK |
|---|
| 67412 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 67413 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 67414 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 67415 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 67416 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 67417 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 67418 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 67419 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 67420 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 67421 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 67422 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 67423 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 67424 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 67425 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 67426 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 67427 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 67428 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 67429 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 67430 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 67431 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 67432 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 67433 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 67434 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 67435 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 67436 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 67437 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 67438 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 67439 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 67440 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 67441 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 67442 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 67443 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 67444 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 67445 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 67446 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 67447 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 67448 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 67449 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 67450 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 67451 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 67452 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 67453 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 67454 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 67455 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 67456 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 67457 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 67458 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 67459 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 67460 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 67461 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 67462 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 67463 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 67464 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 67465 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 67466 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 67467 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 67468 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 67469 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 67470 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 67471 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 67472 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 67473 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 67474 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 67475 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 67476 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 67477 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS |
|---|
| 67478 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 67479 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 67480 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 67481 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 67482 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 67483 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 67484 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 67485 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 67486 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 67487 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 67488 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 67489 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 67490 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 67491 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 67492 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 67493 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 67494 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK |
|---|
| 67495 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 67496 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 67497 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 67498 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 67499 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 67500 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 67501 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 67502 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 67503 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 67504 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 67505 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 67506 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 67507 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 67508 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 67509 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 67510 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 67511 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 67512 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 67513 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 67514 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 67515 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
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| 67516 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
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| 67517 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
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| 67518 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
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| 67519 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 67520 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 67521 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 67522 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 67523 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 67524 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 67525 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 67526 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 67527 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 67528 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 67529 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 67530 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 |
|---|
| 67531 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 67532 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 67533 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 |
|---|
| 67534 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 67535 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 67536 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 |
|---|
| 67537 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 67538 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 67539 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 |
|---|
| 67540 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 67541 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 67542 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 67543 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 67544 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 67545 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 67546 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 67547 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 67548 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 67549 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 67550 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 67551 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 67552 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 67553 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 67554 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 67555 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 67556 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 67557 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 67558 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 67559 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 67560 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 67561 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP |
|---|
| 67562 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 67563 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 67564 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 67565 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 67566 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 67567 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 67568 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL |
|---|
| 67569 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 67570 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 67571 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 67572 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 67573 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 67574 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 67575 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 67576 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 67577 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 67578 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 67579 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 67580 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP |
|---|
| 67581 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 67582 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 67583 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 67584 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 67585 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 67586 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 67587 | //BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL |
|---|
| 67588 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 67589 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 67590 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 67591 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 67592 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 67593 | #define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 67594 | |
|---|
| 67595 | |
|---|
| 67596 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp |
|---|
| 67597 | //BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID |
|---|
| 67598 | #define BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 67599 | #define BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 67600 | //BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID |
|---|
| 67601 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 67602 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 67603 | //BIF_CFG_DEV0_EPF0_VF14_0_COMMAND |
|---|
| 67604 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 67605 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 67606 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 67607 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 67608 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 67609 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 67610 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 67611 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 67612 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 67613 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 67614 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 67615 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 67616 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 67617 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 67618 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 67619 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 67620 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 67621 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 67622 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 67623 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 67624 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 67625 | #define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 67626 | //BIF_CFG_DEV0_EPF0_VF14_0_STATUS |
|---|
| 67627 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 67628 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 67629 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 67630 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 67631 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 67632 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 67633 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 67634 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 67635 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 67636 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 67637 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 67638 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 67639 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 67640 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 67641 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 67642 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 67643 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 67644 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 67645 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 67646 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 67647 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 67648 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 67649 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 67650 | #define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 67651 | //BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID |
|---|
| 67652 | #define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 67653 | #define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 67654 | #define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 67655 | #define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 67656 | //BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE |
|---|
| 67657 | #define BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 67658 | #define BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 67659 | //BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS |
|---|
| 67660 | #define BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 67661 | #define BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 67662 | //BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS |
|---|
| 67663 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 67664 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 67665 | //BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE |
|---|
| 67666 | #define BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 67667 | #define BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 67668 | //BIF_CFG_DEV0_EPF0_VF14_0_LATENCY |
|---|
| 67669 | #define BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 67670 | #define BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 67671 | //BIF_CFG_DEV0_EPF0_VF14_0_HEADER |
|---|
| 67672 | #define 0x0 |
|---|
| 67673 | #define 0x7 |
|---|
| 67674 | #define 0x7FL |
|---|
| 67675 | #define 0x80L |
|---|
| 67676 | //BIF_CFG_DEV0_EPF0_VF14_0_BIST |
|---|
| 67677 | #define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 67678 | #define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 67679 | #define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 67680 | #define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 67681 | #define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 67682 | #define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 67683 | //BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 |
|---|
| 67684 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 67685 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 67686 | //BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 |
|---|
| 67687 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 67688 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 67689 | //BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 |
|---|
| 67690 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 67691 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 67692 | //BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 |
|---|
| 67693 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 67694 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 67695 | //BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 |
|---|
| 67696 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 67697 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 67698 | //BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 |
|---|
| 67699 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 67700 | #define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 67701 | //BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR |
|---|
| 67702 | #define BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 67703 | #define BIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 67704 | //BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID |
|---|
| 67705 | #define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 67706 | #define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 67707 | #define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 67708 | #define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 67709 | //BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR |
|---|
| 67710 | #define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 67711 | #define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 67712 | //BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR |
|---|
| 67713 | #define BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 67714 | #define BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 67715 | //BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE |
|---|
| 67716 | #define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 67717 | #define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 67718 | //BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN |
|---|
| 67719 | #define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 67720 | #define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 67721 | //BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT |
|---|
| 67722 | #define BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 67723 | #define BIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 67724 | //BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY |
|---|
| 67725 | #define BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 67726 | #define BIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 67727 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST |
|---|
| 67728 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 67729 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 67730 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 67731 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 67732 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP |
|---|
| 67733 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 67734 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 67735 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 67736 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 67737 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 67738 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 67739 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 67740 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 67741 | //BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP |
|---|
| 67742 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 67743 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 67744 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 67745 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 67746 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 67747 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 67748 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 67749 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 67750 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 67751 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 67752 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 67753 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 67754 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 67755 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 67756 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 67757 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 67758 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 67759 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 67760 | //BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL |
|---|
| 67761 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 67762 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 67763 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 67764 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 67765 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 67766 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 67767 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 67768 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 67769 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 67770 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 67771 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 67772 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 67773 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 67774 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 67775 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 67776 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 67777 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 67778 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 67779 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 67780 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 67781 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 67782 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 67783 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 67784 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 67785 | //BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS |
|---|
| 67786 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 67787 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 67788 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 67789 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 67790 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 67791 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 67792 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 67793 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 67794 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 67795 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 67796 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 67797 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 67798 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 67799 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 67800 | //BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP |
|---|
| 67801 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 67802 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 67803 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 67804 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 67805 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 67806 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 67807 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 67808 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 67809 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 67810 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 67811 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 67812 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 67813 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 67814 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 67815 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 67816 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 67817 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 67818 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 67819 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 67820 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 67821 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 67822 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 67823 | //BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL |
|---|
| 67824 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 67825 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 67826 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 67827 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 67828 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 67829 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 67830 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 67831 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 67832 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 67833 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 67834 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 67835 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 67836 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 67837 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 67838 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 67839 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 67840 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 67841 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 67842 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 67843 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 67844 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 67845 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 67846 | //BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS |
|---|
| 67847 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 67848 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 67849 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 67850 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 67851 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 67852 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 67853 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 67854 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 67855 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 67856 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 67857 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 67858 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 67859 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 67860 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 67861 | //BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 |
|---|
| 67862 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 67863 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 67864 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 67865 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 67866 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 67867 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 67868 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 67869 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 67870 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 67871 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 67872 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 67873 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 67874 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 67875 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 67876 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 67877 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 67878 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 67879 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 67880 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 67881 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 67882 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 67883 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 67884 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 67885 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 67886 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 67887 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 67888 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 67889 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 67890 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 67891 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 67892 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 67893 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 67894 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 67895 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 67896 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 67897 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 67898 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 67899 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 67900 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 67901 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 67902 | //BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 |
|---|
| 67903 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 67904 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 67905 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 67906 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 67907 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 67908 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 67909 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 67910 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 67911 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 67912 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 67913 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 67914 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 67915 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 67916 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 67917 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 67918 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 67919 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 67920 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 67921 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 67922 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 67923 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 67924 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 67925 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 67926 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 67927 | //BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 |
|---|
| 67928 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 67929 | #define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 67930 | //BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 |
|---|
| 67931 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 67932 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 67933 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 67934 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 67935 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 67936 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 67937 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 67938 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 67939 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 67940 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 67941 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 67942 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 67943 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 67944 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 67945 | //BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 |
|---|
| 67946 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 67947 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 67948 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 67949 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 67950 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 67951 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 67952 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 67953 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 67954 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 67955 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 67956 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 67957 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 67958 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 67959 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 67960 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 67961 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 67962 | //BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 |
|---|
| 67963 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 67964 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 67965 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 67966 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 67967 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 67968 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 67969 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 67970 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 67971 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 67972 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 67973 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 67974 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 67975 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 67976 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 67977 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 67978 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 67979 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 67980 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 67981 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 67982 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 67983 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 67984 | #define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 67985 | //BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST |
|---|
| 67986 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 67987 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 67988 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 67989 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 67990 | //BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL |
|---|
| 67991 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 67992 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 67993 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 67994 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 67995 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 67996 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 67997 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 67998 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 67999 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 68000 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 68001 | //BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO |
|---|
| 68002 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 68003 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 68004 | //BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI |
|---|
| 68005 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 68006 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 68007 | //BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA |
|---|
| 68008 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 68009 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 68010 | //BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK |
|---|
| 68011 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 68012 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 68013 | //BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 |
|---|
| 68014 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 68015 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 68016 | //BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 |
|---|
| 68017 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 68018 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 68019 | //BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING |
|---|
| 68020 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 68021 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 68022 | //BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 |
|---|
| 68023 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 68024 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 68025 | //BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST |
|---|
| 68026 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68027 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 68028 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 68029 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 68030 | //BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL |
|---|
| 68031 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 68032 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 68033 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 68034 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 68035 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 68036 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 68037 | //BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE |
|---|
| 68038 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 68039 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 68040 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 68041 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 68042 | //BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA |
|---|
| 68043 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 68044 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 68045 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 68046 | #define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 68047 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 68048 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68049 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 68050 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 68051 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 68052 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 68053 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 68054 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 68055 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 68056 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 68057 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 68058 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 68059 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 68060 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 68061 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 68062 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 68063 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 68064 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 68065 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 68066 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 68067 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 68068 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68069 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 68070 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 68071 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 68072 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 68073 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 68074 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 68075 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 68076 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 68077 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 68078 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 68079 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 68080 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 68081 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 68082 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 68083 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 68084 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 68085 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 68086 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 68087 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 68088 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 68089 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 68090 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 68091 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 68092 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 68093 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 68094 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 68095 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 68096 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 68097 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 68098 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 68099 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 68100 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 68101 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 68102 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 68103 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 68104 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 68105 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 68106 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 68107 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK |
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| 68108 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 68109 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 68110 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 68111 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 68112 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 68113 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 68114 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 68115 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 68116 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 68117 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 68118 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 68119 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 68120 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 68121 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 68122 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 68123 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 68124 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 68125 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 68126 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 68127 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 68128 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 68129 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 68130 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 68131 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 68132 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 68133 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 68134 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 68135 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 68136 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 68137 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 68138 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 68139 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 68140 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 68141 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 68142 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 68143 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 68144 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 68145 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 68146 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 68147 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 68148 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 68149 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 68150 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 68151 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 68152 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 68153 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 68154 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 68155 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 68156 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 68157 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 68158 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 68159 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 68160 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 68161 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 68162 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 68163 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 68164 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 68165 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 68166 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 68167 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 68168 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 68169 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 68170 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 68171 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 68172 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 68173 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS |
|---|
| 68174 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 68175 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 68176 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 68177 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 68178 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 68179 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 68180 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 68181 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 68182 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 68183 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 68184 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 68185 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 68186 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 68187 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 68188 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 68189 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 68190 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK |
|---|
| 68191 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 68192 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 68193 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 68194 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 68195 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 68196 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 68197 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 68198 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 68199 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 68200 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 68201 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 68202 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 68203 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 68204 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 68205 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 68206 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 68207 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 68208 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 68209 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 68210 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 68211 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 68212 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 68213 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 68214 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 68215 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 68216 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 68217 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 68218 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 68219 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 68220 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 68221 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 68222 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 68223 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 68224 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 68225 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 68226 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 |
|---|
| 68227 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
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| 68228 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
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| 68229 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 |
|---|
| 68230 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
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| 68231 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 68232 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 |
|---|
| 68233 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
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| 68234 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 68235 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 |
|---|
| 68236 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 68237 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
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| 68238 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 68239 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 68240 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 68241 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 68242 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 68243 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 68244 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 68245 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 68246 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 68247 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 68248 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 68249 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 68250 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 68251 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68252 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 68253 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 68254 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 68255 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 68256 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 68257 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP |
|---|
| 68258 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 68259 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 68260 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 68261 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 68262 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 68263 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 68264 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL |
|---|
| 68265 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 68266 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 68267 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 68268 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 68269 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 68270 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68271 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 68272 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 68273 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 68274 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 68275 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 68276 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP |
|---|
| 68277 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 68278 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 68279 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 68280 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 68281 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 68282 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 68283 | //BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL |
|---|
| 68284 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 68285 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 68286 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 68287 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 68288 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 68289 | #define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 68290 | |
|---|
| 68291 | |
|---|
| 68292 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp |
|---|
| 68293 | //BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID |
|---|
| 68294 | #define BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 68295 | #define BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 68296 | //BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID |
|---|
| 68297 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 68298 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 68299 | //BIF_CFG_DEV0_EPF0_VF15_0_COMMAND |
|---|
| 68300 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 68301 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 68302 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 68303 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 68304 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 68305 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 68306 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 68307 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 68308 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 68309 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 68310 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 68311 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 68312 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 68313 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 68314 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 68315 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 68316 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 68317 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 68318 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 68319 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 68320 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 68321 | #define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 68322 | //BIF_CFG_DEV0_EPF0_VF15_0_STATUS |
|---|
| 68323 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 68324 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 68325 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 68326 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 68327 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 68328 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 68329 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 68330 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 68331 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 68332 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 68333 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 68334 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 68335 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 68336 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 68337 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 68338 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 68339 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 68340 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 68341 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 68342 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 68343 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 68344 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 68345 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 68346 | #define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 68347 | //BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID |
|---|
| 68348 | #define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 68349 | #define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 68350 | #define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 68351 | #define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 68352 | //BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE |
|---|
| 68353 | #define BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 68354 | #define BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 68355 | //BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS |
|---|
| 68356 | #define BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 68357 | #define BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 68358 | //BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS |
|---|
| 68359 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 68360 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 68361 | //BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE |
|---|
| 68362 | #define BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 68363 | #define BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 68364 | //BIF_CFG_DEV0_EPF0_VF15_0_LATENCY |
|---|
| 68365 | #define BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 68366 | #define BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 68367 | //BIF_CFG_DEV0_EPF0_VF15_0_HEADER |
|---|
| 68368 | #define 0x0 |
|---|
| 68369 | #define 0x7 |
|---|
| 68370 | #define 0x7FL |
|---|
| 68371 | #define 0x80L |
|---|
| 68372 | //BIF_CFG_DEV0_EPF0_VF15_0_BIST |
|---|
| 68373 | #define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 68374 | #define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 68375 | #define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 68376 | #define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 68377 | #define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 68378 | #define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 68379 | //BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 |
|---|
| 68380 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 68381 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 68382 | //BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 |
|---|
| 68383 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 68384 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 68385 | //BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 |
|---|
| 68386 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 68387 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 68388 | //BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 |
|---|
| 68389 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 68390 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 68391 | //BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 |
|---|
| 68392 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 68393 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 68394 | //BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 |
|---|
| 68395 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 68396 | #define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 68397 | //BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR |
|---|
| 68398 | #define BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 68399 | #define BIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 68400 | //BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID |
|---|
| 68401 | #define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 68402 | #define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 68403 | #define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 68404 | #define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 68405 | //BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR |
|---|
| 68406 | #define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 68407 | #define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 68408 | //BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR |
|---|
| 68409 | #define BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 68410 | #define BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 68411 | //BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE |
|---|
| 68412 | #define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 68413 | #define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 68414 | //BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN |
|---|
| 68415 | #define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 68416 | #define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 68417 | //BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT |
|---|
| 68418 | #define BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 68419 | #define BIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 68420 | //BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY |
|---|
| 68421 | #define BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 68422 | #define BIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 68423 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST |
|---|
| 68424 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68425 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 68426 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 68427 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 68428 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP |
|---|
| 68429 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 68430 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 68431 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 68432 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 68433 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 68434 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 68435 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 68436 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 68437 | //BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP |
|---|
| 68438 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 68439 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 68440 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 68441 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 68442 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 68443 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 68444 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 68445 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 68446 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 68447 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 68448 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 68449 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 68450 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 68451 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 68452 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 68453 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 68454 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 68455 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 68456 | //BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL |
|---|
| 68457 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 68458 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 68459 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 68460 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 68461 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 68462 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 68463 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 68464 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 68465 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 68466 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 68467 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 68468 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 68469 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 68470 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 68471 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 68472 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 68473 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 68474 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 68475 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 68476 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 68477 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 68478 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 68479 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 68480 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 68481 | //BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS |
|---|
| 68482 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 68483 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 68484 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 68485 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 68486 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 68487 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 68488 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 68489 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 68490 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 68491 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 68492 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 68493 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 68494 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 68495 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 68496 | //BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP |
|---|
| 68497 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 68498 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 68499 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 68500 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 68501 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 68502 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 68503 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 68504 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 68505 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 68506 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 68507 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 68508 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 68509 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 68510 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 68511 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 68512 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 68513 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 68514 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 68515 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 68516 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 68517 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 68518 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 68519 | //BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL |
|---|
| 68520 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 68521 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 68522 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 68523 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 68524 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 68525 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 68526 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 68527 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 68528 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 68529 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 68530 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 68531 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 68532 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 68533 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 68534 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 68535 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 68536 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 68537 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 68538 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 68539 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 68540 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 68541 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 68542 | //BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS |
|---|
| 68543 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 68544 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 68545 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 68546 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 68547 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 68548 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 68549 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 68550 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 68551 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 68552 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 68553 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 68554 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 68555 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 68556 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 68557 | //BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 |
|---|
| 68558 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 68559 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 68560 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 68561 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 68562 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 68563 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 68564 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 68565 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 68566 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 68567 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 68568 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 68569 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 68570 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 68571 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 68572 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 68573 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 68574 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 68575 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 68576 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 68577 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 68578 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 68579 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 68580 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 68581 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 68582 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 68583 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 68584 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 68585 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 68586 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 68587 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 68588 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 68589 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 68590 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 68591 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 68592 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 68593 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 68594 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 68595 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 68596 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 68597 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 68598 | //BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 |
|---|
| 68599 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 68600 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 68601 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 68602 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 68603 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 68604 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 68605 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 68606 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 68607 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 68608 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 68609 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 68610 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 68611 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 68612 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 68613 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 68614 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 68615 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 68616 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 68617 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 68618 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 68619 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 68620 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 68621 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 68622 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 68623 | //BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 |
|---|
| 68624 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 68625 | #define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 68626 | //BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 |
|---|
| 68627 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 68628 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 68629 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 68630 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 68631 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 68632 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 68633 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 68634 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 68635 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 68636 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 68637 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 68638 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 68639 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 68640 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 68641 | //BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 |
|---|
| 68642 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 68643 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 68644 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 68645 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 68646 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 68647 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 68648 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 68649 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 68650 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 68651 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 68652 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 68653 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 68654 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 68655 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 68656 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 68657 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 68658 | //BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 |
|---|
| 68659 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 68660 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 68661 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 68662 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 68663 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 68664 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 68665 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 68666 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 68667 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 68668 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 68669 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 68670 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 68671 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 68672 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 68673 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 68674 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 68675 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 68676 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 68677 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 68678 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 68679 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 68680 | #define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 68681 | //BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST |
|---|
| 68682 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68683 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 68684 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 68685 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 68686 | //BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL |
|---|
| 68687 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 68688 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 68689 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 68690 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 68691 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 68692 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 68693 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 68694 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 68695 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 68696 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 68697 | //BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO |
|---|
| 68698 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 68699 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 68700 | //BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI |
|---|
| 68701 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 68702 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 68703 | //BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA |
|---|
| 68704 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 68705 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 68706 | //BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK |
|---|
| 68707 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 68708 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 68709 | //BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 |
|---|
| 68710 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 68711 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 68712 | //BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 |
|---|
| 68713 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 68714 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 68715 | //BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING |
|---|
| 68716 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 68717 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 68718 | //BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 |
|---|
| 68719 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 68720 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 68721 | //BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST |
|---|
| 68722 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68723 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 68724 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 68725 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 68726 | //BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL |
|---|
| 68727 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 68728 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 68729 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 68730 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 68731 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 68732 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 68733 | //BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE |
|---|
| 68734 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 68735 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 68736 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 68737 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 68738 | //BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA |
|---|
| 68739 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 68740 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 68741 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 68742 | #define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 68743 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 68744 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68745 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 68746 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 68747 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 68748 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 68749 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 68750 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 68751 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 68752 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 68753 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 68754 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 68755 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 68756 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 68757 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 68758 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 68759 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 68760 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 68761 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 68762 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 68763 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 68764 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68765 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 68766 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 68767 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 68768 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 68769 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 68770 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 68771 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 68772 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 68773 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 68774 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 68775 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 68776 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 68777 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 68778 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 68779 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 68780 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 68781 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 68782 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 68783 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 68784 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 68785 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 68786 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 68787 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 68788 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 68789 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 68790 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 68791 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 68792 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 68793 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 68794 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 68795 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 68796 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 68797 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 68798 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 68799 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 68800 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 68801 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 68802 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 68803 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK |
|---|
| 68804 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 68805 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 68806 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 68807 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 68808 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 68809 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 68810 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 68811 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 68812 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 68813 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 68814 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 68815 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 68816 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 68817 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 68818 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 68819 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 68820 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 68821 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 68822 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 68823 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 68824 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 68825 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 68826 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 68827 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 68828 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 68829 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 68830 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 68831 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 68832 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 68833 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 68834 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 68835 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 68836 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 68837 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 68838 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 68839 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 68840 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 68841 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 68842 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 68843 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 68844 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 68845 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 68846 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 68847 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 68848 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 68849 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 68850 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 68851 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 68852 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 68853 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 68854 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 68855 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 68856 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 68857 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 68858 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 68859 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 68860 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 68861 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 68862 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 68863 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 68864 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 68865 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 68866 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 68867 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 68868 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 68869 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS |
|---|
| 68870 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 68871 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 68872 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 68873 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 68874 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 68875 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 68876 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 68877 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 68878 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 68879 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 68880 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 68881 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 68882 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 68883 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 68884 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 68885 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 68886 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK |
|---|
| 68887 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 68888 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 68889 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 68890 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 68891 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 68892 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 68893 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 68894 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 68895 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 68896 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 68897 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 68898 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 68899 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 68900 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 68901 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 68902 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 68903 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 68904 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 68905 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 68906 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 68907 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 68908 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 68909 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 68910 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 68911 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 68912 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 68913 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 68914 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 68915 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 68916 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 68917 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 68918 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 68919 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 68920 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 68921 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 68922 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 |
|---|
| 68923 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 68924 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 68925 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 |
|---|
| 68926 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 68927 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 68928 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 |
|---|
| 68929 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 68930 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 68931 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 |
|---|
| 68932 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 68933 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 68934 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 68935 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 68936 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 68937 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 68938 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 68939 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 68940 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 68941 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 68942 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 68943 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 68944 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 68945 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 68946 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 68947 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68948 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 68949 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 68950 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 68951 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 68952 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 68953 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP |
|---|
| 68954 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 68955 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 68956 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 68957 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 68958 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 68959 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 68960 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL |
|---|
| 68961 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 68962 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 68963 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 68964 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 68965 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 68966 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 68967 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 68968 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 68969 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 68970 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 68971 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 68972 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP |
|---|
| 68973 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 68974 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 68975 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 68976 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 68977 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 68978 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 68979 | //BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL |
|---|
| 68980 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 68981 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 68982 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 68983 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 68984 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 68985 | #define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 68986 | |
|---|
| 68987 | |
|---|
| 68988 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp |
|---|
| 68989 | //BIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID |
|---|
| 68990 | #define BIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 68991 | #define BIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 68992 | //BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID |
|---|
| 68993 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 68994 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 68995 | //BIF_CFG_DEV0_EPF0_VF16_0_COMMAND |
|---|
| 68996 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 68997 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 68998 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 68999 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 69000 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 69001 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 69002 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 69003 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 69004 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 69005 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 69006 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 69007 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 69008 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 69009 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 69010 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 69011 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 69012 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 69013 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 69014 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 69015 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 69016 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 69017 | #define BIF_CFG_DEV0_EPF0_VF16_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 69018 | //BIF_CFG_DEV0_EPF0_VF16_0_STATUS |
|---|
| 69019 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 69020 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 69021 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 69022 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 69023 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 69024 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 69025 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 69026 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 69027 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 69028 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 69029 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 69030 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 69031 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 69032 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 69033 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 69034 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 69035 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 69036 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 69037 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 69038 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 69039 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 69040 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 69041 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 69042 | #define BIF_CFG_DEV0_EPF0_VF16_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 69043 | //BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID |
|---|
| 69044 | #define BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 69045 | #define BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 69046 | #define BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 69047 | #define BIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 69048 | //BIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE |
|---|
| 69049 | #define BIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 69050 | #define BIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 69051 | //BIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS |
|---|
| 69052 | #define BIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 69053 | #define BIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 69054 | //BIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS |
|---|
| 69055 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 69056 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 69057 | //BIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE |
|---|
| 69058 | #define BIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 69059 | #define BIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 69060 | //BIF_CFG_DEV0_EPF0_VF16_0_LATENCY |
|---|
| 69061 | #define BIF_CFG_DEV0_EPF0_VF16_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 69062 | #define BIF_CFG_DEV0_EPF0_VF16_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 69063 | //BIF_CFG_DEV0_EPF0_VF16_0_HEADER |
|---|
| 69064 | #define 0x0 |
|---|
| 69065 | #define 0x7 |
|---|
| 69066 | #define 0x7FL |
|---|
| 69067 | #define 0x80L |
|---|
| 69068 | //BIF_CFG_DEV0_EPF0_VF16_0_BIST |
|---|
| 69069 | #define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 69070 | #define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 69071 | #define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 69072 | #define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 69073 | #define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 69074 | #define BIF_CFG_DEV0_EPF0_VF16_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 69075 | //BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1 |
|---|
| 69076 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 69077 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69078 | //BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2 |
|---|
| 69079 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 69080 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69081 | //BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3 |
|---|
| 69082 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 69083 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69084 | //BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4 |
|---|
| 69085 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 69086 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69087 | //BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5 |
|---|
| 69088 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 69089 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69090 | //BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6 |
|---|
| 69091 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 69092 | #define BIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69093 | //BIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR |
|---|
| 69094 | #define BIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 69095 | #define BIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 69096 | //BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID |
|---|
| 69097 | #define BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 69098 | #define BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 69099 | #define BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 69100 | #define BIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 69101 | //BIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR |
|---|
| 69102 | #define BIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 69103 | #define BIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69104 | //BIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR |
|---|
| 69105 | #define BIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 69106 | #define BIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 69107 | //BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE |
|---|
| 69108 | #define BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 69109 | #define BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 69110 | //BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN |
|---|
| 69111 | #define BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 69112 | #define BIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 69113 | //BIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT |
|---|
| 69114 | #define BIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 69115 | #define BIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 69116 | //BIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY |
|---|
| 69117 | #define BIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 69118 | #define BIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 69119 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST |
|---|
| 69120 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 69121 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 69122 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 69123 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 69124 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP |
|---|
| 69125 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 69126 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 69127 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 69128 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 69129 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 69130 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 69131 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 69132 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 69133 | //BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP |
|---|
| 69134 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 69135 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 69136 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 69137 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 69138 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 69139 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 69140 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 69141 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 69142 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 69143 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 69144 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 69145 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 69146 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 69147 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 69148 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 69149 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 69150 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 69151 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 69152 | //BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL |
|---|
| 69153 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 69154 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 69155 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 69156 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 69157 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 69158 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 69159 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 69160 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 69161 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 69162 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 69163 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 69164 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 69165 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 69166 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 69167 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 69168 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 69169 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 69170 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 69171 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 69172 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 69173 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 69174 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 69175 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 69176 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 69177 | //BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS |
|---|
| 69178 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 69179 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 69180 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 69181 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 69182 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 69183 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 69184 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 69185 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 69186 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 69187 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 69188 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 69189 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 69190 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 69191 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 69192 | //BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP |
|---|
| 69193 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 69194 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 69195 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 69196 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 69197 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 69198 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 69199 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 69200 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 69201 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 69202 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 69203 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 69204 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 69205 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 69206 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 69207 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 69208 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 69209 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 69210 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 69211 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 69212 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 69213 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 69214 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 69215 | //BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL |
|---|
| 69216 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 69217 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 69218 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 69219 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 69220 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 69221 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 69222 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 69223 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 69224 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 69225 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 69226 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 69227 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 69228 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 69229 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 69230 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 69231 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 69232 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 69233 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 69234 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 69235 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 69236 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 69237 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 69238 | //BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS |
|---|
| 69239 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 69240 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 69241 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 69242 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 69243 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 69244 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 69245 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 69246 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 69247 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 69248 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 69249 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 69250 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 69251 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 69252 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 69253 | //BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2 |
|---|
| 69254 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 69255 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 69256 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 69257 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 69258 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 69259 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 69260 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 69261 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 69262 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 69263 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 69264 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 69265 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 69266 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 69267 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 69268 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 69269 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 69270 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 69271 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 69272 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 69273 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 69274 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 69275 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 69276 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 69277 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 69278 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 69279 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 69280 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 69281 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 69282 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 69283 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 69284 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 69285 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 69286 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 69287 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 69288 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 69289 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 69290 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 69291 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 69292 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 69293 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 69294 | //BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2 |
|---|
| 69295 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 69296 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 69297 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 69298 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 69299 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 69300 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 69301 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 69302 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 69303 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 69304 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 69305 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 69306 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 69307 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 69308 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 69309 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 69310 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 69311 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 69312 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 69313 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 69314 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 69315 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 69316 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 69317 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 69318 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 69319 | //BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2 |
|---|
| 69320 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 69321 | #define BIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 69322 | //BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2 |
|---|
| 69323 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 69324 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 69325 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 69326 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 69327 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 69328 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 69329 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 69330 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 69331 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 69332 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 69333 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 69334 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 69335 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 69336 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 69337 | //BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2 |
|---|
| 69338 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 69339 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 69340 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 69341 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 69342 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 69343 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 69344 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 69345 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 69346 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 69347 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 69348 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 69349 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 69350 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 69351 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 69352 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 69353 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 69354 | //BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2 |
|---|
| 69355 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 69356 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 69357 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 69358 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 69359 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 69360 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 69361 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 69362 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 69363 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 69364 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 69365 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 69366 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 69367 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 69368 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 69369 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 69370 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 69371 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 69372 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 69373 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 69374 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 69375 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 69376 | #define BIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 69377 | //BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST |
|---|
| 69378 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 69379 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 69380 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 69381 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 69382 | //BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL |
|---|
| 69383 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 69384 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 69385 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 69386 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 69387 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 69388 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 69389 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 69390 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 69391 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 69392 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 69393 | //BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO |
|---|
| 69394 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 69395 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 69396 | //BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI |
|---|
| 69397 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 69398 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 69399 | //BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA |
|---|
| 69400 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 69401 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 69402 | //BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK |
|---|
| 69403 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 69404 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 69405 | //BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64 |
|---|
| 69406 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 69407 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 69408 | //BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64 |
|---|
| 69409 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 69410 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 69411 | //BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING |
|---|
| 69412 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 69413 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 69414 | //BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64 |
|---|
| 69415 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 69416 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 69417 | //BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST |
|---|
| 69418 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 69419 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 69420 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 69421 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 69422 | //BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL |
|---|
| 69423 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 69424 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 69425 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 69426 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 69427 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 69428 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 69429 | //BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE |
|---|
| 69430 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 69431 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 69432 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 69433 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 69434 | //BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA |
|---|
| 69435 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 69436 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 69437 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 69438 | #define BIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 69439 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 69440 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 69441 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 69442 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 69443 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 69444 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 69445 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 69446 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 69447 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 69448 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 69449 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 69450 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 69451 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 69452 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 69453 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 69454 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 69455 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 69456 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 69457 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 69458 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 69459 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 69460 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 69461 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 69462 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 69463 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 69464 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 69465 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 69466 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 69467 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 69468 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 69469 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 69470 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 69471 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 69472 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 69473 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 69474 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 69475 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 69476 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 69477 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 69478 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 69479 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 69480 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 69481 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 69482 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 69483 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 69484 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 69485 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 69486 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 69487 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 69488 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 69489 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 69490 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 69491 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 69492 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 69493 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 69494 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 69495 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 69496 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 69497 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 69498 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 69499 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK |
|---|
| 69500 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 69501 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 69502 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 69503 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 69504 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 69505 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 69506 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 69507 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 69508 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 69509 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 69510 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 69511 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 69512 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 69513 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 69514 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 69515 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 69516 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 69517 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 69518 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 69519 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 69520 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 69521 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 69522 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 69523 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 69524 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 69525 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 69526 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 69527 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 69528 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 69529 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 69530 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 69531 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 69532 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 69533 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 69534 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 69535 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 69536 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 69537 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 69538 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 69539 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 69540 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 69541 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 69542 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 69543 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 69544 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 69545 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 69546 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 69547 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 69548 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 69549 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 69550 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 69551 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 69552 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 69553 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 69554 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 69555 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 69556 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 69557 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 69558 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 69559 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 69560 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 69561 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 69562 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 69563 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 69564 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 69565 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS |
|---|
| 69566 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 69567 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 69568 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 69569 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 69570 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 69571 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 69572 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 69573 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 69574 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 69575 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 69576 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 69577 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 69578 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 69579 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 69580 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 69581 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 69582 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK |
|---|
| 69583 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 69584 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 69585 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 69586 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 69587 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 69588 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 69589 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 69590 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 69591 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 69592 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 69593 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 69594 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 69595 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 69596 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 69597 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 69598 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 69599 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 69600 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 69601 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 69602 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 69603 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 69604 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 69605 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 69606 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 69607 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 69608 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 69609 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 69610 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 69611 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 69612 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 69613 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 69614 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 69615 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 69616 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 69617 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 69618 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0 |
|---|
| 69619 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 69620 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 69621 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1 |
|---|
| 69622 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 69623 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 69624 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2 |
|---|
| 69625 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 69626 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 69627 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3 |
|---|
| 69628 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 69629 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 69630 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 69631 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 69632 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 69633 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 69634 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 69635 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 69636 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 69637 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 69638 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 69639 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 69640 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 69641 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 69642 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 69643 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 69644 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 69645 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 69646 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 69647 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 69648 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 69649 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP |
|---|
| 69650 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 69651 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 69652 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 69653 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 69654 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 69655 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 69656 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL |
|---|
| 69657 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 69658 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 69659 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 69660 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 69661 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 69662 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 69663 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 69664 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 69665 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 69666 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 69667 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 69668 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP |
|---|
| 69669 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 69670 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 69671 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 69672 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 69673 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 69674 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 69675 | //BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL |
|---|
| 69676 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 69677 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 69678 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 69679 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 69680 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 69681 | #define BIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 69682 | |
|---|
| 69683 | |
|---|
| 69684 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp |
|---|
| 69685 | //BIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID |
|---|
| 69686 | #define BIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 69687 | #define BIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 69688 | //BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID |
|---|
| 69689 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 69690 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 69691 | //BIF_CFG_DEV0_EPF0_VF17_0_COMMAND |
|---|
| 69692 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 69693 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 69694 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 69695 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 69696 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 69697 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 69698 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 69699 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 69700 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 69701 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 69702 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 69703 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 69704 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 69705 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 69706 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 69707 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 69708 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 69709 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 69710 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 69711 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 69712 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 69713 | #define BIF_CFG_DEV0_EPF0_VF17_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 69714 | //BIF_CFG_DEV0_EPF0_VF17_0_STATUS |
|---|
| 69715 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 69716 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 69717 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 69718 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 69719 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 69720 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 69721 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 69722 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 69723 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 69724 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 69725 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 69726 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 69727 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 69728 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 69729 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 69730 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 69731 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 69732 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 69733 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 69734 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 69735 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 69736 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 69737 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 69738 | #define BIF_CFG_DEV0_EPF0_VF17_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 69739 | //BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID |
|---|
| 69740 | #define BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 69741 | #define BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 69742 | #define BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 69743 | #define BIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 69744 | //BIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE |
|---|
| 69745 | #define BIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 69746 | #define BIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 69747 | //BIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS |
|---|
| 69748 | #define BIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 69749 | #define BIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 69750 | //BIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS |
|---|
| 69751 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 69752 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 69753 | //BIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE |
|---|
| 69754 | #define BIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 69755 | #define BIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 69756 | //BIF_CFG_DEV0_EPF0_VF17_0_LATENCY |
|---|
| 69757 | #define BIF_CFG_DEV0_EPF0_VF17_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 69758 | #define BIF_CFG_DEV0_EPF0_VF17_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 69759 | //BIF_CFG_DEV0_EPF0_VF17_0_HEADER |
|---|
| 69760 | #define 0x0 |
|---|
| 69761 | #define 0x7 |
|---|
| 69762 | #define 0x7FL |
|---|
| 69763 | #define 0x80L |
|---|
| 69764 | //BIF_CFG_DEV0_EPF0_VF17_0_BIST |
|---|
| 69765 | #define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 69766 | #define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 69767 | #define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 69768 | #define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 69769 | #define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 69770 | #define BIF_CFG_DEV0_EPF0_VF17_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 69771 | //BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1 |
|---|
| 69772 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 69773 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69774 | //BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2 |
|---|
| 69775 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 69776 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69777 | //BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3 |
|---|
| 69778 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 69779 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69780 | //BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4 |
|---|
| 69781 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 69782 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69783 | //BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5 |
|---|
| 69784 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 69785 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69786 | //BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6 |
|---|
| 69787 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 69788 | #define BIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69789 | //BIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR |
|---|
| 69790 | #define BIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 69791 | #define BIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 69792 | //BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID |
|---|
| 69793 | #define BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 69794 | #define BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 69795 | #define BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 69796 | #define BIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 69797 | //BIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR |
|---|
| 69798 | #define BIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 69799 | #define BIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 69800 | //BIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR |
|---|
| 69801 | #define BIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 69802 | #define BIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 69803 | //BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE |
|---|
| 69804 | #define BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 69805 | #define BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 69806 | //BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN |
|---|
| 69807 | #define BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 69808 | #define BIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 69809 | //BIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT |
|---|
| 69810 | #define BIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 69811 | #define BIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 69812 | //BIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY |
|---|
| 69813 | #define BIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 69814 | #define BIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 69815 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST |
|---|
| 69816 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 69817 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 69818 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 69819 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 69820 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP |
|---|
| 69821 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 69822 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 69823 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 69824 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 69825 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 69826 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 69827 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 69828 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 69829 | //BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP |
|---|
| 69830 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 69831 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 69832 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 69833 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 69834 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 69835 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 69836 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 69837 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 69838 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 69839 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 69840 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 69841 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 69842 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 69843 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 69844 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 69845 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 69846 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 69847 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 69848 | //BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL |
|---|
| 69849 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 69850 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 69851 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 69852 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 69853 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 69854 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 69855 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 69856 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 69857 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 69858 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 69859 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 69860 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 69861 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 69862 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 69863 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 69864 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 69865 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 69866 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 69867 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 69868 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 69869 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 69870 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 69871 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 69872 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 69873 | //BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS |
|---|
| 69874 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 69875 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 69876 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 69877 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 69878 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 69879 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 69880 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 69881 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 69882 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 69883 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 69884 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 69885 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 69886 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 69887 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 69888 | //BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP |
|---|
| 69889 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 69890 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 69891 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 69892 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 69893 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 69894 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 69895 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 69896 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 69897 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 69898 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 69899 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 69900 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 69901 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 69902 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 69903 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 69904 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 69905 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 69906 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 69907 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 69908 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 69909 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 69910 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 69911 | //BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL |
|---|
| 69912 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 69913 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 69914 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 69915 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 69916 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 69917 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 69918 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 69919 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 69920 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 69921 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 69922 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 69923 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 69924 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 69925 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 69926 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 69927 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 69928 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 69929 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 69930 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 69931 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 69932 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 69933 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 69934 | //BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS |
|---|
| 69935 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 69936 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 69937 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 69938 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 69939 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 69940 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 69941 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 69942 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 69943 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 69944 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 69945 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 69946 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 69947 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 69948 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 69949 | //BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2 |
|---|
| 69950 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 69951 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 69952 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 69953 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 69954 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 69955 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 69956 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 69957 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 69958 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 69959 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 69960 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 69961 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 69962 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 69963 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 69964 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 69965 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 69966 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 69967 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 69968 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 69969 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 69970 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 69971 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 69972 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 69973 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 69974 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 69975 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 69976 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 69977 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 69978 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 69979 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 69980 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 69981 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 69982 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 69983 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 69984 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 69985 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 69986 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 69987 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 69988 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 69989 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 69990 | //BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2 |
|---|
| 69991 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 69992 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 69993 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 69994 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 69995 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 69996 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 69997 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 69998 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 69999 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 70000 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 70001 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 70002 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 70003 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 70004 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 70005 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 70006 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 70007 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 70008 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 70009 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 70010 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 70011 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 70012 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 70013 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 70014 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 70015 | //BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2 |
|---|
| 70016 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 70017 | #define BIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 70018 | //BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2 |
|---|
| 70019 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 70020 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 70021 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 70022 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 70023 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 70024 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 70025 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 70026 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 70027 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 70028 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 70029 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 70030 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 70031 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 70032 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 70033 | //BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2 |
|---|
| 70034 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 70035 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 70036 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 70037 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 70038 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 70039 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 70040 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 70041 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 70042 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 70043 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 70044 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 70045 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 70046 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 70047 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 70048 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 70049 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 70050 | //BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2 |
|---|
| 70051 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 70052 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 70053 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 70054 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 70055 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 70056 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 70057 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 70058 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 70059 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 70060 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 70061 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 70062 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 70063 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 70064 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 70065 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 70066 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 70067 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 70068 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 70069 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 70070 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 70071 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 70072 | #define BIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 70073 | //BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST |
|---|
| 70074 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70075 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 70076 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 70077 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 70078 | //BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL |
|---|
| 70079 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 70080 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 70081 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 70082 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 70083 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 70084 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 70085 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 70086 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 70087 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 70088 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 70089 | //BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO |
|---|
| 70090 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 70091 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 70092 | //BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI |
|---|
| 70093 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 70094 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 70095 | //BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA |
|---|
| 70096 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 70097 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 70098 | //BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK |
|---|
| 70099 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 70100 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 70101 | //BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64 |
|---|
| 70102 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 70103 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 70104 | //BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64 |
|---|
| 70105 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 70106 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 70107 | //BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING |
|---|
| 70108 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 70109 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 70110 | //BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64 |
|---|
| 70111 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 70112 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 70113 | //BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST |
|---|
| 70114 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70115 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 70116 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 70117 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 70118 | //BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL |
|---|
| 70119 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 70120 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 70121 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 70122 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 70123 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 70124 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 70125 | //BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE |
|---|
| 70126 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 70127 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 70128 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 70129 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 70130 | //BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA |
|---|
| 70131 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 70132 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 70133 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 70134 | #define BIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 70135 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 70136 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70137 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 70138 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 70139 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 70140 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 70141 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 70142 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 70143 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 70144 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 70145 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 70146 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 70147 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 70148 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 70149 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 70150 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 70151 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 70152 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 70153 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 70154 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 70155 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 70156 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70157 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 70158 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 70159 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 70160 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 70161 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 70162 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 70163 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 70164 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 70165 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 70166 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 70167 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 70168 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 70169 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 70170 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 70171 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 70172 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 70173 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 70174 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 70175 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 70176 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 70177 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 70178 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 70179 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 70180 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 70181 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 70182 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 70183 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 70184 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 70185 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 70186 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 70187 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 70188 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 70189 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 70190 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 70191 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 70192 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 70193 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 70194 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 70195 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK |
|---|
| 70196 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 70197 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 70198 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 70199 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 70200 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 70201 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 70202 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 70203 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 70204 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 70205 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 70206 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 70207 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 70208 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 70209 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 70210 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 70211 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 70212 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 70213 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 70214 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 70215 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 70216 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 70217 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 70218 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 70219 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 70220 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 70221 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 70222 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 70223 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 70224 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 70225 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 70226 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 70227 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 70228 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 70229 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 70230 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 70231 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 70232 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 70233 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 70234 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 70235 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 70236 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 70237 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 70238 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 70239 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 70240 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 70241 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 70242 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 70243 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 70244 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 70245 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 70246 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 70247 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 70248 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 70249 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 70250 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 70251 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 70252 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 70253 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 70254 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 70255 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 70256 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 70257 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 70258 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 70259 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 70260 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 70261 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS |
|---|
| 70262 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 70263 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 70264 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 70265 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 70266 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 70267 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 70268 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 70269 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 70270 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 70271 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 70272 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 70273 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 70274 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 70275 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 70276 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 70277 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 70278 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK |
|---|
| 70279 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 70280 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 70281 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 70282 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 70283 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 70284 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 70285 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 70286 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 70287 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 70288 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 70289 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 70290 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 70291 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 70292 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 70293 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 70294 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 70295 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 70296 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 70297 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 70298 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 70299 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 70300 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 70301 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 70302 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 70303 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 70304 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 70305 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 70306 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 70307 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 70308 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 70309 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 70310 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 70311 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 70312 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 70313 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 70314 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0 |
|---|
| 70315 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 70316 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 70317 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1 |
|---|
| 70318 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 70319 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 70320 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2 |
|---|
| 70321 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 70322 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 70323 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3 |
|---|
| 70324 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 70325 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 70326 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 70327 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 70328 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 70329 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 70330 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 70331 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 70332 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 70333 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 70334 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 70335 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 70336 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 70337 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 70338 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 70339 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70340 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 70341 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 70342 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 70343 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 70344 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 70345 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP |
|---|
| 70346 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 70347 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 70348 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 70349 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 70350 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 70351 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 70352 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL |
|---|
| 70353 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 70354 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 70355 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 70356 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 70357 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 70358 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70359 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 70360 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 70361 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 70362 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 70363 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 70364 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP |
|---|
| 70365 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 70366 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 70367 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 70368 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 70369 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 70370 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 70371 | //BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL |
|---|
| 70372 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 70373 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 70374 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 70375 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 70376 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 70377 | #define BIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 70378 | |
|---|
| 70379 | |
|---|
| 70380 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp |
|---|
| 70381 | //BIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID |
|---|
| 70382 | #define BIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 70383 | #define BIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 70384 | //BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID |
|---|
| 70385 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 70386 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 70387 | //BIF_CFG_DEV0_EPF0_VF18_0_COMMAND |
|---|
| 70388 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 70389 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 70390 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 70391 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 70392 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 70393 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 70394 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 70395 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 70396 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 70397 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 70398 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 70399 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 70400 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 70401 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 70402 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 70403 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 70404 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 70405 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 70406 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 70407 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 70408 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 70409 | #define BIF_CFG_DEV0_EPF0_VF18_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 70410 | //BIF_CFG_DEV0_EPF0_VF18_0_STATUS |
|---|
| 70411 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 70412 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 70413 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 70414 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 70415 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 70416 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 70417 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 70418 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 70419 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 70420 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 70421 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 70422 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 70423 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 70424 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 70425 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 70426 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 70427 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 70428 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 70429 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 70430 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 70431 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 70432 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 70433 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 70434 | #define BIF_CFG_DEV0_EPF0_VF18_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 70435 | //BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID |
|---|
| 70436 | #define BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 70437 | #define BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 70438 | #define BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 70439 | #define BIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 70440 | //BIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE |
|---|
| 70441 | #define BIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 70442 | #define BIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 70443 | //BIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS |
|---|
| 70444 | #define BIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 70445 | #define BIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 70446 | //BIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS |
|---|
| 70447 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 70448 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 70449 | //BIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE |
|---|
| 70450 | #define BIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 70451 | #define BIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 70452 | //BIF_CFG_DEV0_EPF0_VF18_0_LATENCY |
|---|
| 70453 | #define BIF_CFG_DEV0_EPF0_VF18_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 70454 | #define BIF_CFG_DEV0_EPF0_VF18_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 70455 | //BIF_CFG_DEV0_EPF0_VF18_0_HEADER |
|---|
| 70456 | #define 0x0 |
|---|
| 70457 | #define 0x7 |
|---|
| 70458 | #define 0x7FL |
|---|
| 70459 | #define 0x80L |
|---|
| 70460 | //BIF_CFG_DEV0_EPF0_VF18_0_BIST |
|---|
| 70461 | #define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 70462 | #define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 70463 | #define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 70464 | #define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 70465 | #define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 70466 | #define BIF_CFG_DEV0_EPF0_VF18_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 70467 | //BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1 |
|---|
| 70468 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 70469 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 70470 | //BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2 |
|---|
| 70471 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 70472 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 70473 | //BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3 |
|---|
| 70474 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 70475 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 70476 | //BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4 |
|---|
| 70477 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 70478 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 70479 | //BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5 |
|---|
| 70480 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 70481 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 70482 | //BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6 |
|---|
| 70483 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 70484 | #define BIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 70485 | //BIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR |
|---|
| 70486 | #define BIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 70487 | #define BIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 70488 | //BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID |
|---|
| 70489 | #define BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 70490 | #define BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 70491 | #define BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 70492 | #define BIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 70493 | //BIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR |
|---|
| 70494 | #define BIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 70495 | #define BIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 70496 | //BIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR |
|---|
| 70497 | #define BIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 70498 | #define BIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 70499 | //BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE |
|---|
| 70500 | #define BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 70501 | #define BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 70502 | //BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN |
|---|
| 70503 | #define BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 70504 | #define BIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 70505 | //BIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT |
|---|
| 70506 | #define BIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 70507 | #define BIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 70508 | //BIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY |
|---|
| 70509 | #define BIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 70510 | #define BIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 70511 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST |
|---|
| 70512 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70513 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 70514 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 70515 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 70516 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP |
|---|
| 70517 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 70518 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 70519 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 70520 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 70521 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 70522 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 70523 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 70524 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 70525 | //BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP |
|---|
| 70526 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 70527 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 70528 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 70529 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 70530 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 70531 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 70532 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 70533 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 70534 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 70535 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 70536 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 70537 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 70538 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 70539 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 70540 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 70541 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 70542 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 70543 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 70544 | //BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL |
|---|
| 70545 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 70546 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 70547 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 70548 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 70549 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 70550 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 70551 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 70552 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 70553 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 70554 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 70555 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 70556 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 70557 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 70558 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 70559 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 70560 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 70561 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 70562 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 70563 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 70564 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 70565 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 70566 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 70567 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 70568 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 70569 | //BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS |
|---|
| 70570 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 70571 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 70572 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 70573 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 70574 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 70575 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 70576 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 70577 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 70578 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 70579 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 70580 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 70581 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 70582 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 70583 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 70584 | //BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP |
|---|
| 70585 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 70586 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 70587 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 70588 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 70589 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 70590 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 70591 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 70592 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 70593 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 70594 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 70595 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 70596 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 70597 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 70598 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 70599 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 70600 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 70601 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 70602 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 70603 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 70604 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 70605 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 70606 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 70607 | //BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL |
|---|
| 70608 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 70609 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 70610 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 70611 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 70612 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 70613 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 70614 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 70615 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 70616 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 70617 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 70618 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 70619 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 70620 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 70621 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 70622 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 70623 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 70624 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 70625 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 70626 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 70627 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 70628 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 70629 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 70630 | //BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS |
|---|
| 70631 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 70632 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 70633 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 70634 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 70635 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 70636 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 70637 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 70638 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 70639 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 70640 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 70641 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 70642 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 70643 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 70644 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 70645 | //BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2 |
|---|
| 70646 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 70647 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 70648 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 70649 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 70650 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 70651 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 70652 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 70653 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 70654 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 70655 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 70656 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 70657 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 70658 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 70659 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 70660 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 70661 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 70662 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 70663 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 70664 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 70665 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 70666 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 70667 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 70668 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 70669 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 70670 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 70671 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 70672 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 70673 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 70674 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 70675 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 70676 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 70677 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 70678 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 70679 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 70680 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 70681 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 70682 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 70683 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 70684 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 70685 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 70686 | //BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2 |
|---|
| 70687 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 70688 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 70689 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 70690 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 70691 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 70692 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 70693 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 70694 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 70695 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 70696 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 70697 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 70698 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 70699 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 70700 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 70701 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 70702 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 70703 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 70704 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 70705 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 70706 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 70707 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 70708 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 70709 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 70710 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 70711 | //BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2 |
|---|
| 70712 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 70713 | #define BIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 70714 | //BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2 |
|---|
| 70715 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 70716 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 70717 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 70718 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 70719 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 70720 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 70721 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 70722 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 70723 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 70724 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 70725 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 70726 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 70727 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 70728 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 70729 | //BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2 |
|---|
| 70730 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 70731 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 70732 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 70733 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 70734 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 70735 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 70736 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 70737 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 70738 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 70739 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 70740 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 70741 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 70742 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 70743 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 70744 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 70745 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 70746 | //BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2 |
|---|
| 70747 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 70748 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 70749 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 70750 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 70751 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 70752 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 70753 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 70754 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 70755 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 70756 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 70757 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 70758 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 70759 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 70760 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 70761 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 70762 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 70763 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 70764 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 70765 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 70766 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 70767 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 70768 | #define BIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 70769 | //BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST |
|---|
| 70770 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70771 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 70772 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 70773 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 70774 | //BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL |
|---|
| 70775 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 70776 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 70777 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 70778 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 70779 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 70780 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 70781 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 70782 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 70783 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 70784 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 70785 | //BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO |
|---|
| 70786 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 70787 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 70788 | //BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI |
|---|
| 70789 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 70790 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 70791 | //BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA |
|---|
| 70792 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 70793 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 70794 | //BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK |
|---|
| 70795 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 70796 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 70797 | //BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64 |
|---|
| 70798 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 70799 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 70800 | //BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64 |
|---|
| 70801 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 70802 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 70803 | //BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING |
|---|
| 70804 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 70805 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 70806 | //BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64 |
|---|
| 70807 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 70808 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 70809 | //BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST |
|---|
| 70810 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70811 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 70812 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 70813 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 70814 | //BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL |
|---|
| 70815 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 70816 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 70817 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 70818 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 70819 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 70820 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 70821 | //BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE |
|---|
| 70822 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 70823 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 70824 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 70825 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 70826 | //BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA |
|---|
| 70827 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 70828 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 70829 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 70830 | #define BIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 70831 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 70832 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70833 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 70834 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 70835 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 70836 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 70837 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 70838 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 70839 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 70840 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 70841 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 70842 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 70843 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 70844 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 70845 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 70846 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 70847 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 70848 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 70849 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 70850 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 70851 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 70852 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 70853 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 70854 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 70855 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 70856 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 70857 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 70858 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 70859 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 70860 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 70861 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 70862 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 70863 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 70864 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 70865 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 70866 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 70867 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 70868 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 70869 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 70870 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 70871 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 70872 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 70873 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 70874 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 70875 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 70876 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 70877 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 70878 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 70879 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 70880 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 70881 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 70882 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 70883 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 70884 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 70885 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 70886 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 70887 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 70888 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 70889 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 70890 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 70891 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK |
|---|
| 70892 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 70893 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 70894 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 70895 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 70896 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 70897 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 70898 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 70899 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 70900 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 70901 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 70902 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 70903 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 70904 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 70905 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 70906 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 70907 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 70908 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 70909 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 70910 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 70911 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 70912 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 70913 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 70914 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 70915 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 70916 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 70917 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 70918 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 70919 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 70920 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 70921 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 70922 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 70923 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 70924 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 70925 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 70926 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 70927 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 70928 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 70929 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 70930 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 70931 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 70932 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 70933 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 70934 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 70935 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 70936 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 70937 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 70938 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 70939 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 70940 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 70941 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 70942 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 70943 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 70944 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 70945 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 70946 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 70947 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 70948 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 70949 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 70950 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 70951 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 70952 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 70953 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 70954 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 70955 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 70956 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 70957 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS |
|---|
| 70958 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 70959 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 70960 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 70961 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 70962 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 70963 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 70964 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 70965 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 70966 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 70967 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 70968 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 70969 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 70970 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 70971 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 70972 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 70973 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 70974 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK |
|---|
| 70975 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 70976 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 70977 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 70978 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 70979 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 70980 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 70981 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 70982 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 70983 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 70984 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 70985 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 70986 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 70987 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 70988 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 70989 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 70990 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 70991 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 70992 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 70993 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 70994 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 70995 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 70996 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 70997 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 70998 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 70999 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 71000 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 71001 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 71002 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 71003 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 71004 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 71005 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 71006 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 71007 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 71008 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 71009 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 71010 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0 |
|---|
| 71011 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 71012 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 71013 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1 |
|---|
| 71014 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 71015 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 71016 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2 |
|---|
| 71017 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 71018 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 71019 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3 |
|---|
| 71020 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 71021 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 71022 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 71023 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 71024 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 71025 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 71026 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 71027 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 71028 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 71029 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 71030 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 71031 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 71032 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 71033 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 71034 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 71035 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 71036 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 71037 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 71038 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 71039 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 71040 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 71041 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP |
|---|
| 71042 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 71043 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 71044 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 71045 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 71046 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 71047 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 71048 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL |
|---|
| 71049 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 71050 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 71051 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 71052 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 71053 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 71054 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 71055 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 71056 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 71057 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 71058 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 71059 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 71060 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP |
|---|
| 71061 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 71062 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 71063 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 71064 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 71065 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 71066 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 71067 | //BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL |
|---|
| 71068 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 71069 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 71070 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 71071 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 71072 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 71073 | #define BIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 71074 | |
|---|
| 71075 | |
|---|
| 71076 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp |
|---|
| 71077 | //BIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID |
|---|
| 71078 | #define BIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 71079 | #define BIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 71080 | //BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID |
|---|
| 71081 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 71082 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 71083 | //BIF_CFG_DEV0_EPF0_VF19_0_COMMAND |
|---|
| 71084 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 71085 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 71086 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 71087 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 71088 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 71089 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 71090 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 71091 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 71092 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 71093 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 71094 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 71095 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 71096 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 71097 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 71098 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 71099 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 71100 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 71101 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 71102 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 71103 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 71104 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 71105 | #define BIF_CFG_DEV0_EPF0_VF19_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 71106 | //BIF_CFG_DEV0_EPF0_VF19_0_STATUS |
|---|
| 71107 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 71108 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 71109 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 71110 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 71111 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 71112 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 71113 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 71114 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 71115 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 71116 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 71117 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 71118 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 71119 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 71120 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 71121 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 71122 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 71123 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 71124 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 71125 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 71126 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 71127 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 71128 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 71129 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 71130 | #define BIF_CFG_DEV0_EPF0_VF19_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 71131 | //BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID |
|---|
| 71132 | #define BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 71133 | #define BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 71134 | #define BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 71135 | #define BIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 71136 | //BIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE |
|---|
| 71137 | #define BIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 71138 | #define BIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 71139 | //BIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS |
|---|
| 71140 | #define BIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 71141 | #define BIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 71142 | //BIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS |
|---|
| 71143 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 71144 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 71145 | //BIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE |
|---|
| 71146 | #define BIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 71147 | #define BIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 71148 | //BIF_CFG_DEV0_EPF0_VF19_0_LATENCY |
|---|
| 71149 | #define BIF_CFG_DEV0_EPF0_VF19_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 71150 | #define BIF_CFG_DEV0_EPF0_VF19_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 71151 | //BIF_CFG_DEV0_EPF0_VF19_0_HEADER |
|---|
| 71152 | #define 0x0 |
|---|
| 71153 | #define 0x7 |
|---|
| 71154 | #define 0x7FL |
|---|
| 71155 | #define 0x80L |
|---|
| 71156 | //BIF_CFG_DEV0_EPF0_VF19_0_BIST |
|---|
| 71157 | #define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 71158 | #define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 71159 | #define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 71160 | #define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 71161 | #define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 71162 | #define BIF_CFG_DEV0_EPF0_VF19_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 71163 | //BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1 |
|---|
| 71164 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 71165 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71166 | //BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2 |
|---|
| 71167 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 71168 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71169 | //BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3 |
|---|
| 71170 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 71171 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71172 | //BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4 |
|---|
| 71173 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 71174 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71175 | //BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5 |
|---|
| 71176 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 71177 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71178 | //BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6 |
|---|
| 71179 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 71180 | #define BIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71181 | //BIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR |
|---|
| 71182 | #define BIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 71183 | #define BIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 71184 | //BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID |
|---|
| 71185 | #define BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 71186 | #define BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 71187 | #define BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 71188 | #define BIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 71189 | //BIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR |
|---|
| 71190 | #define BIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 71191 | #define BIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71192 | //BIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR |
|---|
| 71193 | #define BIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 71194 | #define BIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 71195 | //BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE |
|---|
| 71196 | #define BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 71197 | #define BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 71198 | //BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN |
|---|
| 71199 | #define BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 71200 | #define BIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 71201 | //BIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT |
|---|
| 71202 | #define BIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 71203 | #define BIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 71204 | //BIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY |
|---|
| 71205 | #define BIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 71206 | #define BIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 71207 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST |
|---|
| 71208 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 71209 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 71210 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 71211 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 71212 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP |
|---|
| 71213 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 71214 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 71215 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 71216 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 71217 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 71218 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 71219 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 71220 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 71221 | //BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP |
|---|
| 71222 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 71223 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 71224 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 71225 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 71226 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 71227 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 71228 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 71229 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 71230 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 71231 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 71232 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 71233 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 71234 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 71235 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 71236 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 71237 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 71238 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 71239 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 71240 | //BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL |
|---|
| 71241 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 71242 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 71243 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 71244 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 71245 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 71246 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 71247 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 71248 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 71249 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 71250 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 71251 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 71252 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 71253 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 71254 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 71255 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 71256 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 71257 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 71258 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 71259 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 71260 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 71261 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 71262 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 71263 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 71264 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 71265 | //BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS |
|---|
| 71266 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 71267 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 71268 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 71269 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 71270 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 71271 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 71272 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 71273 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 71274 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 71275 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 71276 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 71277 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 71278 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 71279 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 71280 | //BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP |
|---|
| 71281 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 71282 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 71283 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 71284 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 71285 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 71286 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 71287 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 71288 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 71289 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 71290 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 71291 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 71292 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 71293 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 71294 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 71295 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 71296 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 71297 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 71298 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 71299 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 71300 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 71301 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 71302 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 71303 | //BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL |
|---|
| 71304 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 71305 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 71306 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 71307 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 71308 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 71309 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 71310 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 71311 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 71312 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 71313 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 71314 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 71315 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 71316 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 71317 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 71318 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 71319 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 71320 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 71321 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 71322 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 71323 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 71324 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 71325 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 71326 | //BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS |
|---|
| 71327 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 71328 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 71329 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 71330 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 71331 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 71332 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 71333 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 71334 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 71335 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 71336 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 71337 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 71338 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 71339 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 71340 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 71341 | //BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2 |
|---|
| 71342 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 71343 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 71344 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 71345 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 71346 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 71347 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 71348 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 71349 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 71350 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 71351 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 71352 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 71353 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 71354 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 71355 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 71356 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 71357 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 71358 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 71359 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 71360 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 71361 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 71362 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 71363 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 71364 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 71365 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 71366 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 71367 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 71368 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 71369 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 71370 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 71371 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 71372 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 71373 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 71374 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 71375 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 71376 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 71377 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 71378 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 71379 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 71380 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 71381 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 71382 | //BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2 |
|---|
| 71383 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 71384 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 71385 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 71386 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 71387 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 71388 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 71389 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 71390 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 71391 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 71392 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 71393 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 71394 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 71395 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 71396 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 71397 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 71398 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 71399 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 71400 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 71401 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 71402 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 71403 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 71404 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 71405 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 71406 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 71407 | //BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2 |
|---|
| 71408 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 71409 | #define BIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 71410 | //BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2 |
|---|
| 71411 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 71412 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 71413 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 71414 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 71415 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 71416 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 71417 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 71418 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 71419 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 71420 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 71421 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 71422 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 71423 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 71424 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 71425 | //BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2 |
|---|
| 71426 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 71427 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 71428 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 71429 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 71430 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 71431 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 71432 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 71433 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 71434 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 71435 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 71436 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 71437 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 71438 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 71439 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 71440 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 71441 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 71442 | //BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2 |
|---|
| 71443 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 71444 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 71445 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 71446 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 71447 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 71448 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 71449 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 71450 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 71451 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 71452 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 71453 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 71454 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 71455 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 71456 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 71457 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 71458 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 71459 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 71460 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 71461 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 71462 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 71463 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 71464 | #define BIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 71465 | //BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST |
|---|
| 71466 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 71467 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 71468 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 71469 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 71470 | //BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL |
|---|
| 71471 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 71472 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 71473 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 71474 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 71475 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 71476 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 71477 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 71478 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 71479 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 71480 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 71481 | //BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO |
|---|
| 71482 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 71483 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 71484 | //BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI |
|---|
| 71485 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 71486 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 71487 | //BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA |
|---|
| 71488 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 71489 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 71490 | //BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK |
|---|
| 71491 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 71492 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 71493 | //BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64 |
|---|
| 71494 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 71495 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 71496 | //BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64 |
|---|
| 71497 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 71498 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 71499 | //BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING |
|---|
| 71500 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 71501 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 71502 | //BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64 |
|---|
| 71503 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 71504 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 71505 | //BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST |
|---|
| 71506 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 71507 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 71508 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 71509 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 71510 | //BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL |
|---|
| 71511 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 71512 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 71513 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 71514 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 71515 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 71516 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 71517 | //BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE |
|---|
| 71518 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 71519 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 71520 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 71521 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 71522 | //BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA |
|---|
| 71523 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 71524 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 71525 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 71526 | #define BIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 71527 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 71528 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 71529 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 71530 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 71531 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 71532 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 71533 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 71534 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 71535 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 71536 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 71537 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 71538 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 71539 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 71540 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 71541 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 71542 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 71543 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 71544 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 71545 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 71546 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 71547 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 71548 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 71549 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 71550 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 71551 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 71552 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 71553 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 71554 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 71555 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 71556 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 71557 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 71558 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 71559 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 71560 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 71561 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 71562 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 71563 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 71564 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 71565 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 71566 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 71567 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 71568 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 71569 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 71570 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 71571 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 71572 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 71573 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 71574 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 71575 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 71576 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 71577 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 71578 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 71579 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 71580 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 71581 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 71582 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 71583 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 71584 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 71585 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 71586 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 71587 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK |
|---|
| 71588 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 71589 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 71590 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 71591 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 71592 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 71593 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 71594 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 71595 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 71596 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 71597 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 71598 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 71599 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 71600 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 71601 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 71602 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 71603 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 71604 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 71605 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 71606 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 71607 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 71608 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 71609 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 71610 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 71611 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 71612 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 71613 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 71614 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 71615 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 71616 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 71617 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 71618 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 71619 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 71620 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 71621 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 71622 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 71623 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 71624 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 71625 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 71626 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 71627 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 71628 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 71629 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 71630 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 71631 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 71632 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 71633 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 71634 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 71635 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 71636 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 71637 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 71638 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 71639 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 71640 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 71641 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 71642 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 71643 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 71644 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 71645 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 71646 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 71647 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 71648 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 71649 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 71650 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 71651 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 71652 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 71653 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS |
|---|
| 71654 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 71655 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 71656 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 71657 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 71658 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 71659 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 71660 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 71661 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 71662 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 71663 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 71664 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 71665 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 71666 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 71667 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 71668 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 71669 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 71670 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK |
|---|
| 71671 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 71672 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 71673 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 71674 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 71675 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 71676 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 71677 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 71678 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 71679 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 71680 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 71681 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 71682 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 71683 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 71684 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 71685 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 71686 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 71687 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 71688 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 71689 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 71690 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 71691 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 71692 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 71693 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 71694 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 71695 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 71696 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 71697 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 71698 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 71699 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 71700 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 71701 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 71702 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 71703 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 71704 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 71705 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 71706 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0 |
|---|
| 71707 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 71708 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 71709 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1 |
|---|
| 71710 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 71711 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 71712 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2 |
|---|
| 71713 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 71714 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 71715 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3 |
|---|
| 71716 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 71717 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 71718 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 71719 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 71720 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 71721 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 71722 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 71723 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 71724 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 71725 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 71726 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 71727 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 71728 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 71729 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 71730 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 71731 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 71732 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 71733 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 71734 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 71735 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 71736 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 71737 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP |
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| 71738 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
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| 71739 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
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| 71740 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
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| 71741 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 71742 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 71743 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
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| 71744 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL |
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| 71745 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
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| 71746 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
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| 71747 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
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| 71748 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
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| 71749 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 71750 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 71751 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 71752 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 71753 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 71754 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 71755 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 71756 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP |
|---|
| 71757 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 71758 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 71759 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 71760 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 71761 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 71762 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 71763 | //BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL |
|---|
| 71764 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 71765 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 71766 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 71767 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 71768 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 71769 | #define BIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
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| 71770 | |
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| 71771 | |
|---|
| 71772 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp |
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| 71773 | //BIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID |
|---|
| 71774 | #define BIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 71775 | #define BIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 71776 | //BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID |
|---|
| 71777 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 71778 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 71779 | //BIF_CFG_DEV0_EPF0_VF20_0_COMMAND |
|---|
| 71780 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 71781 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 71782 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 71783 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 71784 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 71785 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 71786 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
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| 71787 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 71788 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SERR_EN__SHIFT 0x8 |
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| 71789 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
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| 71790 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 71791 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 71792 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 71793 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 71794 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 71795 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 71796 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 71797 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
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| 71798 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 71799 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 71800 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 71801 | #define BIF_CFG_DEV0_EPF0_VF20_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 71802 | //BIF_CFG_DEV0_EPF0_VF20_0_STATUS |
|---|
| 71803 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
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| 71804 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__INT_STATUS__SHIFT 0x3 |
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| 71805 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__CAP_LIST__SHIFT 0x4 |
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| 71806 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
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| 71807 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
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| 71808 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 71809 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 71810 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 71811 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
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| 71812 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
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| 71813 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
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| 71814 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
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| 71815 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
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| 71816 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__INT_STATUS_MASK 0x0008L |
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| 71817 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__CAP_LIST_MASK 0x0010L |
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| 71818 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PCI_66_CAP_MASK 0x0020L |
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| 71819 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
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| 71820 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
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| 71821 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
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| 71822 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 71823 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
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| 71824 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
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| 71825 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
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| 71826 | #define BIF_CFG_DEV0_EPF0_VF20_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
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| 71827 | //BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID |
|---|
| 71828 | #define BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
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| 71829 | #define BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 71830 | #define BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 71831 | #define BIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
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| 71832 | //BIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE |
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| 71833 | #define BIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 71834 | #define BIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
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| 71835 | //BIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS |
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| 71836 | #define BIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
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| 71837 | #define BIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 71838 | //BIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS |
|---|
| 71839 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 71840 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 71841 | //BIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE |
|---|
| 71842 | #define BIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 71843 | #define BIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
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| 71844 | //BIF_CFG_DEV0_EPF0_VF20_0_LATENCY |
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| 71845 | #define BIF_CFG_DEV0_EPF0_VF20_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 71846 | #define BIF_CFG_DEV0_EPF0_VF20_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 71847 | //BIF_CFG_DEV0_EPF0_VF20_0_HEADER |
|---|
| 71848 | #define 0x0 |
|---|
| 71849 | #define 0x7 |
|---|
| 71850 | #define 0x7FL |
|---|
| 71851 | #define 0x80L |
|---|
| 71852 | //BIF_CFG_DEV0_EPF0_VF20_0_BIST |
|---|
| 71853 | #define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 71854 | #define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 71855 | #define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 71856 | #define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 71857 | #define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 71858 | #define BIF_CFG_DEV0_EPF0_VF20_0_BIST__BIST_CAP_MASK 0x80L |
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| 71859 | //BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1 |
|---|
| 71860 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 71861 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71862 | //BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2 |
|---|
| 71863 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 71864 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71865 | //BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3 |
|---|
| 71866 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 71867 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71868 | //BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4 |
|---|
| 71869 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 71870 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71871 | //BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5 |
|---|
| 71872 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 71873 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71874 | //BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6 |
|---|
| 71875 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 71876 | #define BIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71877 | //BIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR |
|---|
| 71878 | #define BIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 71879 | #define BIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 71880 | //BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID |
|---|
| 71881 | #define BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 71882 | #define BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 71883 | #define BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 71884 | #define BIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 71885 | //BIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR |
|---|
| 71886 | #define BIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 71887 | #define BIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 71888 | //BIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR |
|---|
| 71889 | #define BIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 71890 | #define BIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 71891 | //BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE |
|---|
| 71892 | #define BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 71893 | #define BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 71894 | //BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN |
|---|
| 71895 | #define BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 71896 | #define BIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 71897 | //BIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT |
|---|
| 71898 | #define BIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 71899 | #define BIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 71900 | //BIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY |
|---|
| 71901 | #define BIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 71902 | #define BIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 71903 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST |
|---|
| 71904 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 71905 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 71906 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 71907 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 71908 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP |
|---|
| 71909 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 71910 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 71911 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 71912 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 71913 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 71914 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 71915 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 71916 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 71917 | //BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP |
|---|
| 71918 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 71919 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 71920 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 71921 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 71922 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 71923 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 71924 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 71925 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 71926 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 71927 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 71928 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 71929 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 71930 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 71931 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 71932 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 71933 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 71934 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 71935 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 71936 | //BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL |
|---|
| 71937 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 71938 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 71939 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 71940 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 71941 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 71942 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 71943 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 71944 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 71945 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 71946 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 71947 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 71948 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 71949 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 71950 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 71951 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 71952 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 71953 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 71954 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 71955 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 71956 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 71957 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 71958 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 71959 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 71960 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 71961 | //BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS |
|---|
| 71962 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 71963 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 71964 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 71965 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 71966 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 71967 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 71968 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 71969 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 71970 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 71971 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 71972 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 71973 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 71974 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 71975 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 71976 | //BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP |
|---|
| 71977 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 71978 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 71979 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 71980 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 71981 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 71982 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 71983 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 71984 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 71985 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 71986 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 71987 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 71988 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 71989 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 71990 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 71991 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 71992 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 71993 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 71994 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 71995 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 71996 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 71997 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 71998 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 71999 | //BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL |
|---|
| 72000 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 72001 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 72002 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 72003 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 72004 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 72005 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 72006 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 72007 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 72008 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 72009 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 72010 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 72011 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 72012 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 72013 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 72014 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 72015 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 72016 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 72017 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 72018 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 72019 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 72020 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 72021 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 72022 | //BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS |
|---|
| 72023 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 72024 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 72025 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 72026 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 72027 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 72028 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 72029 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 72030 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 72031 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 72032 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 72033 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 72034 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 72035 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 72036 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 72037 | //BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2 |
|---|
| 72038 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 72039 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 72040 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 72041 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 72042 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 72043 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 72044 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 72045 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 72046 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 72047 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 72048 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 72049 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 72050 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 72051 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 72052 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 72053 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 72054 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 72055 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 72056 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 72057 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 72058 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 72059 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 72060 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 72061 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 72062 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 72063 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 72064 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 72065 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 72066 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 72067 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 72068 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 72069 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 72070 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 72071 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 72072 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 72073 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 72074 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 72075 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 72076 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 72077 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 72078 | //BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2 |
|---|
| 72079 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 72080 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 72081 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 72082 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 72083 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 72084 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 72085 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 72086 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 72087 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 72088 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 72089 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 72090 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 72091 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 72092 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 72093 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 72094 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 72095 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 72096 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 72097 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 72098 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 72099 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 72100 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 72101 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 72102 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 72103 | //BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2 |
|---|
| 72104 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 72105 | #define BIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 72106 | //BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2 |
|---|
| 72107 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 72108 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 72109 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 72110 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 72111 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 72112 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 72113 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 72114 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 72115 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 72116 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 72117 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 72118 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 72119 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 72120 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 72121 | //BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2 |
|---|
| 72122 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 72123 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 72124 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 72125 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 72126 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 72127 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 72128 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 72129 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 72130 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 72131 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 72132 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 72133 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 72134 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 72135 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 72136 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 72137 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 72138 | //BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2 |
|---|
| 72139 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 72140 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 72141 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 72142 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 72143 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 72144 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 72145 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 72146 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 72147 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 72148 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 72149 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 72150 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 72151 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 72152 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 72153 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 72154 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 72155 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 72156 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 72157 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 72158 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 72159 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 72160 | #define BIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 72161 | //BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST |
|---|
| 72162 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72163 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 72164 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 72165 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 72166 | //BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL |
|---|
| 72167 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 72168 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 72169 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 72170 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 72171 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 72172 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 72173 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 72174 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 72175 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 72176 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 72177 | //BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO |
|---|
| 72178 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 72179 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 72180 | //BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI |
|---|
| 72181 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 72182 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 72183 | //BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA |
|---|
| 72184 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 72185 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 72186 | //BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK |
|---|
| 72187 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 72188 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 72189 | //BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64 |
|---|
| 72190 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 72191 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 72192 | //BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64 |
|---|
| 72193 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 72194 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 72195 | //BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING |
|---|
| 72196 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 72197 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 72198 | //BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64 |
|---|
| 72199 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 72200 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 72201 | //BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST |
|---|
| 72202 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72203 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 72204 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 72205 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 72206 | //BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL |
|---|
| 72207 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 72208 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 72209 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 72210 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 72211 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 72212 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 72213 | //BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE |
|---|
| 72214 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 72215 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 72216 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 72217 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 72218 | //BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA |
|---|
| 72219 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 72220 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 72221 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 72222 | #define BIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 72223 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 72224 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72225 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 72226 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 72227 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 72228 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 72229 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 72230 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 72231 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 72232 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 72233 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 72234 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 72235 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 72236 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 72237 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 72238 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 72239 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 72240 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 72241 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 72242 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 72243 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 72244 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72245 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 72246 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 72247 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 72248 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 72249 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 72250 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 72251 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 72252 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 72253 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 72254 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 72255 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 72256 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 72257 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 72258 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 72259 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 72260 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 72261 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 72262 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 72263 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 72264 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 72265 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 72266 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 72267 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 72268 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 72269 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 72270 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 72271 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 72272 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 72273 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 72274 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 72275 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 72276 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 72277 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 72278 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 72279 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 72280 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 72281 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 72282 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 72283 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK |
|---|
| 72284 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 72285 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 72286 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 72287 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 72288 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 72289 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 72290 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 72291 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 72292 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 72293 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 72294 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 72295 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 72296 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 72297 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 72298 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 72299 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 72300 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 72301 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 72302 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 72303 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 72304 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 72305 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 72306 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 72307 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 72308 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 72309 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 72310 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 72311 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 72312 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 72313 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 72314 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 72315 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 72316 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 72317 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 72318 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 72319 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 72320 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 72321 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 72322 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 72323 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 72324 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 72325 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 72326 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 72327 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 72328 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 72329 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 72330 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 72331 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 72332 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 72333 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 72334 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 72335 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 72336 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 72337 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 72338 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 72339 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 72340 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 72341 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 72342 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 72343 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 72344 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 72345 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 72346 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 72347 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 72348 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 72349 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS |
|---|
| 72350 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 72351 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 72352 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 72353 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 72354 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 72355 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 72356 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 72357 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 72358 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 72359 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 72360 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 72361 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 72362 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 72363 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 72364 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 72365 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 72366 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK |
|---|
| 72367 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 72368 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 72369 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 72370 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 72371 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 72372 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 72373 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 72374 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 72375 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 72376 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 72377 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 72378 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 72379 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 72380 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 72381 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 72382 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 72383 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 72384 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 72385 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 72386 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 72387 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 72388 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 72389 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 72390 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 72391 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 72392 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 72393 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 72394 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 72395 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 72396 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 72397 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 72398 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 72399 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 72400 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 72401 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 72402 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0 |
|---|
| 72403 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 72404 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 72405 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1 |
|---|
| 72406 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 72407 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 72408 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2 |
|---|
| 72409 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 72410 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 72411 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3 |
|---|
| 72412 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 72413 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 72414 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 72415 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 72416 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 72417 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 72418 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 72419 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 72420 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 72421 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 72422 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 72423 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 72424 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 72425 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 72426 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 72427 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72428 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 72429 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 72430 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 72431 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 72432 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 72433 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP |
|---|
| 72434 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 72435 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 72436 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 72437 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 72438 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 72439 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 72440 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL |
|---|
| 72441 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 72442 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 72443 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 72444 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 72445 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 72446 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72447 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 72448 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 72449 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 72450 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 72451 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 72452 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP |
|---|
| 72453 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 72454 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 72455 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 72456 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 72457 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 72458 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 72459 | //BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL |
|---|
| 72460 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 72461 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 72462 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 72463 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 72464 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 72465 | #define BIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 72466 | |
|---|
| 72467 | |
|---|
| 72468 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp |
|---|
| 72469 | //BIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID |
|---|
| 72470 | #define BIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 72471 | #define BIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 72472 | //BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID |
|---|
| 72473 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 72474 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 72475 | //BIF_CFG_DEV0_EPF0_VF21_0_COMMAND |
|---|
| 72476 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 72477 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 72478 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 72479 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 72480 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 72481 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 72482 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 72483 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 72484 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 72485 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 72486 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 72487 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 72488 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 72489 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 72490 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 72491 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 72492 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 72493 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 72494 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 72495 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 72496 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 72497 | #define BIF_CFG_DEV0_EPF0_VF21_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 72498 | //BIF_CFG_DEV0_EPF0_VF21_0_STATUS |
|---|
| 72499 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 72500 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 72501 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 72502 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 72503 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 72504 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 72505 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 72506 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 72507 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 72508 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 72509 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 72510 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 72511 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 72512 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 72513 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 72514 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 72515 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 72516 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 72517 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 72518 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 72519 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 72520 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 72521 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 72522 | #define BIF_CFG_DEV0_EPF0_VF21_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 72523 | //BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID |
|---|
| 72524 | #define BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 72525 | #define BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 72526 | #define BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 72527 | #define BIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 72528 | //BIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE |
|---|
| 72529 | #define BIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 72530 | #define BIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 72531 | //BIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS |
|---|
| 72532 | #define BIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 72533 | #define BIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 72534 | //BIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS |
|---|
| 72535 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 72536 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 72537 | //BIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE |
|---|
| 72538 | #define BIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 72539 | #define BIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 72540 | //BIF_CFG_DEV0_EPF0_VF21_0_LATENCY |
|---|
| 72541 | #define BIF_CFG_DEV0_EPF0_VF21_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 72542 | #define BIF_CFG_DEV0_EPF0_VF21_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 72543 | //BIF_CFG_DEV0_EPF0_VF21_0_HEADER |
|---|
| 72544 | #define 0x0 |
|---|
| 72545 | #define 0x7 |
|---|
| 72546 | #define 0x7FL |
|---|
| 72547 | #define 0x80L |
|---|
| 72548 | //BIF_CFG_DEV0_EPF0_VF21_0_BIST |
|---|
| 72549 | #define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 72550 | #define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 72551 | #define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 72552 | #define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 72553 | #define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 72554 | #define BIF_CFG_DEV0_EPF0_VF21_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 72555 | //BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1 |
|---|
| 72556 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 72557 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 72558 | //BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2 |
|---|
| 72559 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 72560 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 72561 | //BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3 |
|---|
| 72562 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 72563 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 72564 | //BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4 |
|---|
| 72565 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 72566 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 72567 | //BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5 |
|---|
| 72568 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 72569 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 72570 | //BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6 |
|---|
| 72571 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 72572 | #define BIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 72573 | //BIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR |
|---|
| 72574 | #define BIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 72575 | #define BIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 72576 | //BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID |
|---|
| 72577 | #define BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 72578 | #define BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 72579 | #define BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 72580 | #define BIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 72581 | //BIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR |
|---|
| 72582 | #define BIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 72583 | #define BIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 72584 | //BIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR |
|---|
| 72585 | #define BIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 72586 | #define BIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 72587 | //BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE |
|---|
| 72588 | #define BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 72589 | #define BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 72590 | //BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN |
|---|
| 72591 | #define BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 72592 | #define BIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 72593 | //BIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT |
|---|
| 72594 | #define BIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 72595 | #define BIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 72596 | //BIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY |
|---|
| 72597 | #define BIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 72598 | #define BIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 72599 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST |
|---|
| 72600 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72601 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 72602 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 72603 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 72604 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP |
|---|
| 72605 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 72606 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 72607 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 72608 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 72609 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 72610 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 72611 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 72612 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 72613 | //BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP |
|---|
| 72614 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 72615 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 72616 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 72617 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 72618 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 72619 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 72620 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 72621 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 72622 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 72623 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 72624 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 72625 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 72626 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 72627 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 72628 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 72629 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 72630 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 72631 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 72632 | //BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL |
|---|
| 72633 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 72634 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 72635 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 72636 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 72637 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 72638 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 72639 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 72640 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 72641 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 72642 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 72643 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 72644 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 72645 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 72646 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 72647 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 72648 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 72649 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 72650 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 72651 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 72652 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 72653 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 72654 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 72655 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 72656 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 72657 | //BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS |
|---|
| 72658 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 72659 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 72660 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 72661 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 72662 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 72663 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 72664 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 72665 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 72666 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 72667 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 72668 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 72669 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 72670 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 72671 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 72672 | //BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP |
|---|
| 72673 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 72674 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 72675 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 72676 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 72677 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 72678 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 72679 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 72680 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 72681 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 72682 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 72683 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 72684 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 72685 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 72686 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 72687 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 72688 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 72689 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 72690 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 72691 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 72692 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 72693 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 72694 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 72695 | //BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL |
|---|
| 72696 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 72697 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 72698 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 72699 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 72700 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 72701 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 72702 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 72703 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 72704 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 72705 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 72706 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 72707 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 72708 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 72709 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 72710 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 72711 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 72712 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 72713 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 72714 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 72715 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 72716 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 72717 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 72718 | //BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS |
|---|
| 72719 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 72720 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 72721 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 72722 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 72723 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 72724 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 72725 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 72726 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 72727 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 72728 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 72729 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 72730 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 72731 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 72732 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 72733 | //BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2 |
|---|
| 72734 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 72735 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 72736 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 72737 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 72738 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 72739 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 72740 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 72741 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 72742 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 72743 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 72744 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 72745 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 72746 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 72747 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 72748 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 72749 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 72750 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 72751 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 72752 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 72753 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 72754 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 72755 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 72756 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 72757 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 72758 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 72759 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 72760 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 72761 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 72762 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 72763 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 72764 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 72765 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 72766 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 72767 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 72768 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 72769 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 72770 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 72771 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 72772 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 72773 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 72774 | //BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2 |
|---|
| 72775 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 72776 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 72777 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 72778 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 72779 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 72780 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 72781 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 72782 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 72783 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 72784 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 72785 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 72786 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 72787 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 72788 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 72789 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 72790 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 72791 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 72792 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 72793 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 72794 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 72795 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 72796 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 72797 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 72798 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 72799 | //BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2 |
|---|
| 72800 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 72801 | #define BIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 72802 | //BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2 |
|---|
| 72803 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 72804 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 72805 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 72806 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 72807 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 72808 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 72809 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 72810 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 72811 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 72812 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 72813 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 72814 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 72815 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 72816 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 72817 | //BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2 |
|---|
| 72818 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 72819 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 72820 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 72821 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 72822 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 72823 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 72824 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 72825 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 72826 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 72827 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 72828 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 72829 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 72830 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 72831 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 72832 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 72833 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 72834 | //BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2 |
|---|
| 72835 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 72836 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 72837 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 72838 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 72839 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 72840 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 72841 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 72842 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 72843 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 72844 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 72845 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 72846 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 72847 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 72848 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 72849 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 72850 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 72851 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 72852 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 72853 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 72854 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 72855 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 72856 | #define BIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 72857 | //BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST |
|---|
| 72858 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72859 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 72860 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 72861 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 72862 | //BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL |
|---|
| 72863 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 72864 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 72865 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 72866 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 72867 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 72868 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 72869 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 72870 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 72871 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 72872 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 72873 | //BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO |
|---|
| 72874 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 72875 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 72876 | //BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI |
|---|
| 72877 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 72878 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 72879 | //BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA |
|---|
| 72880 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 72881 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 72882 | //BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK |
|---|
| 72883 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 72884 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 72885 | //BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64 |
|---|
| 72886 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 72887 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 72888 | //BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64 |
|---|
| 72889 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 72890 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 72891 | //BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING |
|---|
| 72892 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 72893 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 72894 | //BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64 |
|---|
| 72895 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 72896 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 72897 | //BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST |
|---|
| 72898 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72899 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 72900 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 72901 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 72902 | //BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL |
|---|
| 72903 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 72904 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 72905 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 72906 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 72907 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 72908 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 72909 | //BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE |
|---|
| 72910 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 72911 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 72912 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 72913 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 72914 | //BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA |
|---|
| 72915 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 72916 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 72917 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 72918 | #define BIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 72919 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 72920 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72921 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 72922 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 72923 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 72924 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 72925 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 72926 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 72927 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 72928 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 72929 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 72930 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 72931 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 72932 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 72933 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 72934 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 72935 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 72936 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 72937 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 72938 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 72939 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 72940 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 72941 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 72942 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 72943 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 72944 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 72945 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 72946 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 72947 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 72948 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 72949 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 72950 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 72951 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 72952 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 72953 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 72954 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 72955 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 72956 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 72957 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 72958 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 72959 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 72960 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 72961 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 72962 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 72963 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 72964 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 72965 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 72966 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 72967 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 72968 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 72969 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 72970 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 72971 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 72972 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 72973 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 72974 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 72975 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 72976 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 72977 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 72978 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 72979 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK |
|---|
| 72980 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 72981 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 72982 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 72983 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 72984 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 72985 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 72986 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 72987 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 72988 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 72989 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 72990 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 72991 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 72992 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 72993 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 72994 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 72995 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 72996 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 72997 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 72998 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 72999 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 73000 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 73001 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 73002 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 73003 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 73004 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 73005 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 73006 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 73007 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 73008 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 73009 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 73010 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 73011 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 73012 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 73013 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 73014 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 73015 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 73016 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 73017 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 73018 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 73019 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 73020 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 73021 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 73022 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 73023 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 73024 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 73025 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 73026 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 73027 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 73028 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 73029 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 73030 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 73031 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 73032 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 73033 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 73034 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 73035 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 73036 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 73037 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 73038 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 73039 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 73040 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 73041 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 73042 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 73043 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 73044 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 73045 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS |
|---|
| 73046 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 73047 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 73048 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 73049 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 73050 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 73051 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 73052 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 73053 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 73054 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 73055 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 73056 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 73057 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 73058 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 73059 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 73060 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 73061 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 73062 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK |
|---|
| 73063 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 73064 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 73065 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 73066 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 73067 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 73068 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 73069 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 73070 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 73071 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 73072 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 73073 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 73074 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 73075 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 73076 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 73077 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 73078 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 73079 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 73080 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 73081 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 73082 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 73083 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 73084 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 73085 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 73086 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 73087 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 73088 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 73089 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 73090 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 73091 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 73092 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 73093 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 73094 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 73095 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 73096 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 73097 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 73098 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0 |
|---|
| 73099 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 73100 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 73101 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1 |
|---|
| 73102 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 73103 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 73104 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2 |
|---|
| 73105 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 73106 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 73107 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3 |
|---|
| 73108 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 73109 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 73110 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 73111 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 73112 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 73113 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 73114 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 73115 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 73116 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 73117 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 73118 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 73119 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 73120 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 73121 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 73122 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 73123 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 73124 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 73125 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 73126 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 73127 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 73128 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 73129 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP |
|---|
| 73130 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 73131 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 73132 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 73133 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 73134 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 73135 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 73136 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL |
|---|
| 73137 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 73138 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 73139 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 73140 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 73141 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 73142 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 73143 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 73144 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 73145 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 73146 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 73147 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 73148 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP |
|---|
| 73149 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 73150 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 73151 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 73152 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 73153 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 73154 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 73155 | //BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL |
|---|
| 73156 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 73157 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 73158 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 73159 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 73160 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 73161 | #define BIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 73162 | |
|---|
| 73163 | |
|---|
| 73164 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp |
|---|
| 73165 | //BIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID |
|---|
| 73166 | #define BIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 73167 | #define BIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 73168 | //BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID |
|---|
| 73169 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 73170 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 73171 | //BIF_CFG_DEV0_EPF0_VF22_0_COMMAND |
|---|
| 73172 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 73173 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 73174 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 73175 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 73176 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 73177 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 73178 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 73179 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 73180 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 73181 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 73182 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 73183 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 73184 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 73185 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 73186 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 73187 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 73188 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 73189 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 73190 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 73191 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 73192 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 73193 | #define BIF_CFG_DEV0_EPF0_VF22_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 73194 | //BIF_CFG_DEV0_EPF0_VF22_0_STATUS |
|---|
| 73195 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 73196 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 73197 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 73198 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 73199 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 73200 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 73201 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 73202 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 73203 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 73204 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 73205 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 73206 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 73207 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 73208 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 73209 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 73210 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 73211 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 73212 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 73213 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 73214 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 73215 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 73216 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 73217 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 73218 | #define BIF_CFG_DEV0_EPF0_VF22_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 73219 | //BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID |
|---|
| 73220 | #define BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 73221 | #define BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 73222 | #define BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 73223 | #define BIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 73224 | //BIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE |
|---|
| 73225 | #define BIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 73226 | #define BIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 73227 | //BIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS |
|---|
| 73228 | #define BIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 73229 | #define BIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 73230 | //BIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS |
|---|
| 73231 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 73232 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 73233 | //BIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE |
|---|
| 73234 | #define BIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 73235 | #define BIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 73236 | //BIF_CFG_DEV0_EPF0_VF22_0_LATENCY |
|---|
| 73237 | #define BIF_CFG_DEV0_EPF0_VF22_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 73238 | #define BIF_CFG_DEV0_EPF0_VF22_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 73239 | //BIF_CFG_DEV0_EPF0_VF22_0_HEADER |
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| 73240 | #define 0x0 |
|---|
| 73241 | #define 0x7 |
|---|
| 73242 | #define 0x7FL |
|---|
| 73243 | #define 0x80L |
|---|
| 73244 | //BIF_CFG_DEV0_EPF0_VF22_0_BIST |
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| 73245 | #define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 73246 | #define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 73247 | #define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 73248 | #define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 73249 | #define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 73250 | #define BIF_CFG_DEV0_EPF0_VF22_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 73251 | //BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1 |
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| 73252 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 73253 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73254 | //BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2 |
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| 73255 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 73256 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73257 | //BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3 |
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| 73258 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 73259 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 73260 | //BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4 |
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| 73261 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 73262 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73263 | //BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5 |
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| 73264 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 73265 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 73266 | //BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6 |
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| 73267 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 73268 | #define BIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73269 | //BIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR |
|---|
| 73270 | #define BIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 73271 | #define BIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 73272 | //BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID |
|---|
| 73273 | #define BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 73274 | #define BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 73275 | #define BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 73276 | #define BIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 73277 | //BIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR |
|---|
| 73278 | #define BIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 73279 | #define BIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73280 | //BIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR |
|---|
| 73281 | #define BIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 73282 | #define BIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 73283 | //BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE |
|---|
| 73284 | #define BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 73285 | #define BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 73286 | //BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN |
|---|
| 73287 | #define BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 73288 | #define BIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 73289 | //BIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT |
|---|
| 73290 | #define BIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 73291 | #define BIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 73292 | //BIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY |
|---|
| 73293 | #define BIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 73294 | #define BIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 73295 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST |
|---|
| 73296 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 73297 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 73298 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 73299 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 73300 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP |
|---|
| 73301 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 73302 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 73303 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 73304 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 73305 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 73306 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 73307 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 73308 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 73309 | //BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP |
|---|
| 73310 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 73311 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 73312 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 73313 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 73314 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 73315 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 73316 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 73317 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 73318 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 73319 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 73320 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 73321 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 73322 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 73323 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 73324 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 73325 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 73326 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 73327 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 73328 | //BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL |
|---|
| 73329 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 73330 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 73331 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 73332 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 73333 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 73334 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 73335 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 73336 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 73337 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 73338 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 73339 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 73340 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 73341 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 73342 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 73343 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 73344 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 73345 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 73346 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 73347 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 73348 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 73349 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 73350 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 73351 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 73352 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 73353 | //BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS |
|---|
| 73354 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 73355 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 73356 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 73357 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 73358 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 73359 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 73360 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 73361 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 73362 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 73363 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 73364 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 73365 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 73366 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 73367 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 73368 | //BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP |
|---|
| 73369 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 73370 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 73371 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 73372 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 73373 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 73374 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 73375 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 73376 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 73377 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 73378 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 73379 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 73380 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 73381 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 73382 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 73383 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 73384 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 73385 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 73386 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 73387 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 73388 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 73389 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 73390 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 73391 | //BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL |
|---|
| 73392 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 73393 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 73394 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 73395 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 73396 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 73397 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 73398 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 73399 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 73400 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 73401 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 73402 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 73403 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 73404 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 73405 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 73406 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 73407 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 73408 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 73409 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 73410 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 73411 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 73412 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 73413 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 73414 | //BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS |
|---|
| 73415 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 73416 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 73417 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 73418 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 73419 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 73420 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 73421 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 73422 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 73423 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 73424 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 73425 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 73426 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 73427 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 73428 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 73429 | //BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2 |
|---|
| 73430 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 73431 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 73432 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 73433 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 73434 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 73435 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 73436 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 73437 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 73438 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 73439 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 73440 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 73441 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 73442 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 73443 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 73444 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 73445 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 73446 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 73447 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 73448 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 73449 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 73450 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 73451 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 73452 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 73453 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 73454 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 73455 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 73456 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 73457 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 73458 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 73459 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 73460 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 73461 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 73462 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 73463 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 73464 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 73465 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 73466 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 73467 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 73468 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 73469 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 73470 | //BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2 |
|---|
| 73471 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 73472 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 73473 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 73474 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 73475 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 73476 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 73477 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 73478 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 73479 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 73480 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 73481 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 73482 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 73483 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 73484 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 73485 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 73486 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 73487 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 73488 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 73489 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 73490 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 73491 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 73492 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 73493 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 73494 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 73495 | //BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2 |
|---|
| 73496 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 73497 | #define BIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 73498 | //BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2 |
|---|
| 73499 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 73500 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 73501 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 73502 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 73503 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 73504 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 73505 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 73506 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 73507 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 73508 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 73509 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 73510 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 73511 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 73512 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 73513 | //BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2 |
|---|
| 73514 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 73515 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 73516 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 73517 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 73518 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 73519 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 73520 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 73521 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 73522 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 73523 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 73524 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 73525 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 73526 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 73527 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 73528 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 73529 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 73530 | //BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2 |
|---|
| 73531 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 73532 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 73533 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 73534 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 73535 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 73536 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 73537 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 73538 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 73539 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 73540 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 73541 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 73542 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 73543 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 73544 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 73545 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 73546 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 73547 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 73548 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 73549 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 73550 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 73551 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 73552 | #define BIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 73553 | //BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST |
|---|
| 73554 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 73555 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 73556 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 73557 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 73558 | //BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL |
|---|
| 73559 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 73560 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 73561 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 73562 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 73563 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 73564 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 73565 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 73566 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 73567 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 73568 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 73569 | //BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO |
|---|
| 73570 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 73571 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 73572 | //BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI |
|---|
| 73573 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 73574 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 73575 | //BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA |
|---|
| 73576 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 73577 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 73578 | //BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK |
|---|
| 73579 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 73580 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 73581 | //BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64 |
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| 73582 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
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| 73583 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
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| 73584 | //BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64 |
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| 73585 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
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| 73586 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
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| 73587 | //BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING |
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| 73588 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
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| 73589 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
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| 73590 | //BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64 |
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| 73591 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
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| 73592 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
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| 73593 | //BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST |
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| 73594 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 73595 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 73596 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 73597 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 73598 | //BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL |
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| 73599 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
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| 73600 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
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| 73601 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
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| 73602 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
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| 73603 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
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| 73604 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
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| 73605 | //BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE |
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| 73606 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
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| 73607 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
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| 73608 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
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| 73609 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
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| 73610 | //BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA |
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| 73611 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
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| 73612 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
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| 73613 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
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| 73614 | #define BIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
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| 73615 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
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| 73616 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 73617 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 73618 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 73619 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 73620 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 73621 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 73622 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR |
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| 73623 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
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| 73624 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
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| 73625 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
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| 73626 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 73627 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 73628 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 73629 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 73630 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 73631 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 73632 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2 |
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| 73633 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 73634 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
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| 73635 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 73636 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 73637 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 73638 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 73639 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 73640 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 73641 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 73642 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS |
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| 73643 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 73644 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 73645 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 73646 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 73647 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 73648 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 73649 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 73650 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 73651 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 73652 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 73653 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 73654 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 73655 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 73656 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 73657 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 73658 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 73659 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 73660 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 73661 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 73662 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 73663 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 73664 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 73665 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 73666 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 73667 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 73668 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 73669 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 73670 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 73671 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 73672 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 73673 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 73674 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 73675 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK |
|---|
| 73676 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 73677 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 73678 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 73679 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 73680 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 73681 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 73682 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 73683 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 73684 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 73685 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 73686 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 73687 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 73688 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 73689 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 73690 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 73691 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 73692 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 73693 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 73694 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 73695 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 73696 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 73697 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 73698 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 73699 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 73700 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 73701 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 73702 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 73703 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 73704 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 73705 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 73706 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 73707 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 73708 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 73709 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 73710 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 73711 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 73712 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 73713 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 73714 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 73715 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 73716 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 73717 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 73718 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 73719 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 73720 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 73721 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 73722 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 73723 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 73724 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 73725 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 73726 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 73727 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 73728 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 73729 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 73730 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 73731 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 73732 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 73733 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 73734 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 73735 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 73736 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 73737 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 73738 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 73739 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 73740 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 73741 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS |
|---|
| 73742 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 73743 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 73744 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 73745 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 73746 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 73747 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 73748 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 73749 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 73750 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 73751 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 73752 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 73753 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 73754 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 73755 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 73756 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 73757 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 73758 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK |
|---|
| 73759 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 73760 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 73761 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 73762 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 73763 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 73764 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 73765 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 73766 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 73767 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 73768 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 73769 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 73770 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 73771 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 73772 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 73773 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 73774 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 73775 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 73776 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 73777 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 73778 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 73779 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 73780 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 73781 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 73782 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 73783 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 73784 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 73785 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 73786 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 73787 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 73788 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 73789 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 73790 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 73791 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 73792 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 73793 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 73794 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0 |
|---|
| 73795 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 73796 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 73797 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1 |
|---|
| 73798 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 73799 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 73800 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2 |
|---|
| 73801 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 73802 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 73803 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3 |
|---|
| 73804 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 73805 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 73806 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 73807 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 73808 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 73809 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 73810 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 73811 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 73812 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 73813 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 73814 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 73815 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 73816 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 73817 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 73818 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 73819 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 73820 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 73821 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 73822 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 73823 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 73824 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 73825 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP |
|---|
| 73826 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 73827 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 73828 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 73829 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 73830 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 73831 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 73832 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL |
|---|
| 73833 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 73834 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 73835 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 73836 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 73837 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 73838 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 73839 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 73840 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 73841 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 73842 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 73843 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 73844 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP |
|---|
| 73845 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 73846 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 73847 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 73848 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 73849 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 73850 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 73851 | //BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL |
|---|
| 73852 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 73853 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 73854 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 73855 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 73856 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 73857 | #define BIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 73858 | |
|---|
| 73859 | |
|---|
| 73860 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp |
|---|
| 73861 | //BIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID |
|---|
| 73862 | #define BIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 73863 | #define BIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 73864 | //BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID |
|---|
| 73865 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 73866 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 73867 | //BIF_CFG_DEV0_EPF0_VF23_0_COMMAND |
|---|
| 73868 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 73869 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 73870 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 73871 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 73872 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 73873 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 73874 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 73875 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 73876 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 73877 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 73878 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 73879 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 73880 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 73881 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 73882 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 73883 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 73884 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 73885 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 73886 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 73887 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 73888 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 73889 | #define BIF_CFG_DEV0_EPF0_VF23_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 73890 | //BIF_CFG_DEV0_EPF0_VF23_0_STATUS |
|---|
| 73891 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 73892 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 73893 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 73894 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 73895 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 73896 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 73897 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 73898 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 73899 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 73900 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 73901 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 73902 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 73903 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 73904 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 73905 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 73906 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 73907 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 73908 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 73909 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 73910 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 73911 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 73912 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 73913 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 73914 | #define BIF_CFG_DEV0_EPF0_VF23_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 73915 | //BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID |
|---|
| 73916 | #define BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 73917 | #define BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 73918 | #define BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 73919 | #define BIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 73920 | //BIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE |
|---|
| 73921 | #define BIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 73922 | #define BIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 73923 | //BIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS |
|---|
| 73924 | #define BIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 73925 | #define BIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 73926 | //BIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS |
|---|
| 73927 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 73928 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 73929 | //BIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE |
|---|
| 73930 | #define BIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 73931 | #define BIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 73932 | //BIF_CFG_DEV0_EPF0_VF23_0_LATENCY |
|---|
| 73933 | #define BIF_CFG_DEV0_EPF0_VF23_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 73934 | #define BIF_CFG_DEV0_EPF0_VF23_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 73935 | //BIF_CFG_DEV0_EPF0_VF23_0_HEADER |
|---|
| 73936 | #define 0x0 |
|---|
| 73937 | #define 0x7 |
|---|
| 73938 | #define 0x7FL |
|---|
| 73939 | #define 0x80L |
|---|
| 73940 | //BIF_CFG_DEV0_EPF0_VF23_0_BIST |
|---|
| 73941 | #define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 73942 | #define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 73943 | #define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 73944 | #define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 73945 | #define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 73946 | #define BIF_CFG_DEV0_EPF0_VF23_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 73947 | //BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1 |
|---|
| 73948 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 73949 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73950 | //BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2 |
|---|
| 73951 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 73952 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73953 | //BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3 |
|---|
| 73954 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 73955 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73956 | //BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4 |
|---|
| 73957 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 73958 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73959 | //BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5 |
|---|
| 73960 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 73961 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73962 | //BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6 |
|---|
| 73963 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 73964 | #define BIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73965 | //BIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR |
|---|
| 73966 | #define BIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 73967 | #define BIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 73968 | //BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID |
|---|
| 73969 | #define BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 73970 | #define BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 73971 | #define BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 73972 | #define BIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 73973 | //BIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR |
|---|
| 73974 | #define BIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 73975 | #define BIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 73976 | //BIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR |
|---|
| 73977 | #define BIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 73978 | #define BIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 73979 | //BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE |
|---|
| 73980 | #define BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 73981 | #define BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 73982 | //BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN |
|---|
| 73983 | #define BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 73984 | #define BIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 73985 | //BIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT |
|---|
| 73986 | #define BIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 73987 | #define BIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 73988 | //BIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY |
|---|
| 73989 | #define BIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 73990 | #define BIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 73991 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST |
|---|
| 73992 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 73993 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 73994 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 73995 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 73996 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP |
|---|
| 73997 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 73998 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 73999 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 74000 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 74001 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 74002 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 74003 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 74004 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 74005 | //BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP |
|---|
| 74006 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 74007 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 74008 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 74009 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 74010 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 74011 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 74012 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 74013 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 74014 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 74015 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 74016 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 74017 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 74018 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 74019 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 74020 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 74021 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 74022 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 74023 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 74024 | //BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL |
|---|
| 74025 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 74026 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 74027 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 74028 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 74029 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 74030 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 74031 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 74032 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 74033 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 74034 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 74035 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 74036 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 74037 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 74038 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 74039 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 74040 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 74041 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 74042 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 74043 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 74044 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 74045 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 74046 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 74047 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 74048 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 74049 | //BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS |
|---|
| 74050 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 74051 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 74052 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 74053 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 74054 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 74055 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 74056 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 74057 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 74058 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 74059 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 74060 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 74061 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 74062 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 74063 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 74064 | //BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP |
|---|
| 74065 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 74066 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 74067 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 74068 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 74069 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 74070 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 74071 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 74072 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 74073 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 74074 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 74075 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 74076 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 74077 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 74078 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 74079 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 74080 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 74081 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 74082 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 74083 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 74084 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 74085 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 74086 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 74087 | //BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL |
|---|
| 74088 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 74089 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 74090 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 74091 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 74092 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 74093 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 74094 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 74095 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 74096 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 74097 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 74098 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 74099 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 74100 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 74101 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 74102 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 74103 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 74104 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 74105 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 74106 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 74107 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 74108 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 74109 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 74110 | //BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS |
|---|
| 74111 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 74112 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 74113 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 74114 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 74115 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 74116 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 74117 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 74118 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 74119 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 74120 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 74121 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 74122 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 74123 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 74124 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 74125 | //BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2 |
|---|
| 74126 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 74127 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 74128 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 74129 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 74130 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 74131 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 74132 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 74133 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 74134 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 74135 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 74136 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 74137 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 74138 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 74139 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 74140 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 74141 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 74142 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 74143 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 74144 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 74145 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 74146 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 74147 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 74148 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 74149 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 74150 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 74151 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 74152 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 74153 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 74154 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 74155 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 74156 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 74157 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 74158 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 74159 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 74160 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 74161 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 74162 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 74163 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 74164 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 74165 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 74166 | //BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2 |
|---|
| 74167 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 74168 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 74169 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 74170 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 74171 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 74172 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 74173 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 74174 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 74175 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 74176 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 74177 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 74178 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 74179 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 74180 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 74181 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 74182 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 74183 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 74184 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 74185 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 74186 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 74187 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 74188 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 74189 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 74190 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 74191 | //BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2 |
|---|
| 74192 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 74193 | #define BIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 74194 | //BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2 |
|---|
| 74195 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 74196 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 74197 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 74198 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 74199 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 74200 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 74201 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 74202 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 74203 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 74204 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 74205 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 74206 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 74207 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 74208 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 74209 | //BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2 |
|---|
| 74210 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 74211 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 74212 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 74213 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 74214 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 74215 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 74216 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 74217 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 74218 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 74219 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 74220 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 74221 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 74222 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 74223 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 74224 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 74225 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 74226 | //BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2 |
|---|
| 74227 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 74228 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 74229 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 74230 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 74231 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 74232 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 74233 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 74234 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 74235 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 74236 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 74237 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 74238 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 74239 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 74240 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 74241 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 74242 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 74243 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 74244 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 74245 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 74246 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 74247 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 74248 | #define BIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 74249 | //BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST |
|---|
| 74250 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 74251 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 74252 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 74253 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 74254 | //BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL |
|---|
| 74255 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 74256 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 74257 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 74258 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 74259 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 74260 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 74261 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 74262 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 74263 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 74264 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 74265 | //BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO |
|---|
| 74266 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 74267 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 74268 | //BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI |
|---|
| 74269 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 74270 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 74271 | //BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA |
|---|
| 74272 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 74273 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 74274 | //BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK |
|---|
| 74275 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 74276 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 74277 | //BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64 |
|---|
| 74278 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 74279 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 74280 | //BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64 |
|---|
| 74281 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 74282 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 74283 | //BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING |
|---|
| 74284 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 74285 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 74286 | //BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64 |
|---|
| 74287 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 74288 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 74289 | //BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST |
|---|
| 74290 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 74291 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 74292 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 74293 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 74294 | //BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL |
|---|
| 74295 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 74296 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 74297 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 74298 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 74299 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 74300 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 74301 | //BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE |
|---|
| 74302 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 74303 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 74304 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 74305 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 74306 | //BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA |
|---|
| 74307 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 74308 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 74309 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 74310 | #define BIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 74311 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 74312 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 74313 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 74314 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 74315 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 74316 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 74317 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 74318 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 74319 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 74320 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 74321 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 74322 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 74323 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 74324 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 74325 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 74326 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 74327 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 74328 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 74329 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 74330 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 74331 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 74332 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 74333 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 74334 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 74335 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 74336 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 74337 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 74338 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 74339 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 74340 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 74341 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 74342 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 74343 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 74344 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 74345 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 74346 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 74347 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 74348 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 74349 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 74350 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 74351 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 74352 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 74353 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 74354 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 74355 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 74356 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 74357 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 74358 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 74359 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 74360 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 74361 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 74362 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 74363 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 74364 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 74365 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 74366 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 74367 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 74368 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 74369 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 74370 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 74371 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK |
|---|
| 74372 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 74373 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 74374 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 74375 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 74376 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 74377 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 74378 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 74379 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 74380 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 74381 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 74382 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 74383 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 74384 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 74385 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 74386 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 74387 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 74388 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 74389 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 74390 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 74391 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 74392 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 74393 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 74394 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 74395 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 74396 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 74397 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 74398 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 74399 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 74400 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 74401 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 74402 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 74403 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 74404 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 74405 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 74406 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 74407 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 74408 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 74409 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 74410 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 74411 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 74412 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 74413 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 74414 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 74415 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 74416 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 74417 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 74418 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 74419 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 74420 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 74421 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 74422 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 74423 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 74424 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 74425 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 74426 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 74427 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 74428 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 74429 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 74430 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 74431 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 74432 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 74433 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 74434 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 74435 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 74436 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 74437 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS |
|---|
| 74438 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 74439 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 74440 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 74441 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 74442 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 74443 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 74444 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 74445 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 74446 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 74447 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 74448 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 74449 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 74450 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 74451 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 74452 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 74453 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 74454 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK |
|---|
| 74455 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 74456 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 74457 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 74458 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 74459 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 74460 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 74461 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 74462 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 74463 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 74464 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 74465 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 74466 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 74467 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 74468 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 74469 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 74470 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 74471 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 74472 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 74473 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 74474 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 74475 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 74476 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 74477 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 74478 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 74479 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 74480 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 74481 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 74482 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 74483 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 74484 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 74485 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 74486 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 74487 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 74488 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 74489 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 74490 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0 |
|---|
| 74491 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 74492 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 74493 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1 |
|---|
| 74494 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 74495 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 74496 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2 |
|---|
| 74497 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 74498 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 74499 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3 |
|---|
| 74500 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 74501 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 74502 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 74503 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 74504 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 74505 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 74506 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 74507 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 74508 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 74509 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 74510 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 74511 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 74512 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 74513 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 74514 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 74515 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 74516 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 74517 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 74518 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 74519 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 74520 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 74521 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP |
|---|
| 74522 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 74523 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 74524 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 74525 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 74526 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 74527 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 74528 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL |
|---|
| 74529 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 74530 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 74531 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 74532 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 74533 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 74534 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 74535 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 74536 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 74537 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 74538 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 74539 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 74540 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP |
|---|
| 74541 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 74542 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 74543 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 74544 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 74545 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 74546 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 74547 | //BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL |
|---|
| 74548 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 74549 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 74550 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 74551 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 74552 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 74553 | #define BIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 74554 | |
|---|
| 74555 | |
|---|
| 74556 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp |
|---|
| 74557 | //BIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID |
|---|
| 74558 | #define BIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 74559 | #define BIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 74560 | //BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID |
|---|
| 74561 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 74562 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 74563 | //BIF_CFG_DEV0_EPF0_VF24_0_COMMAND |
|---|
| 74564 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 74565 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 74566 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 74567 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 74568 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 74569 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 74570 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 74571 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 74572 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 74573 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 74574 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 74575 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 74576 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 74577 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 74578 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 74579 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 74580 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 74581 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 74582 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 74583 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 74584 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 74585 | #define BIF_CFG_DEV0_EPF0_VF24_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 74586 | //BIF_CFG_DEV0_EPF0_VF24_0_STATUS |
|---|
| 74587 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 74588 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 74589 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 74590 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 74591 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 74592 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 74593 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 74594 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 74595 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 74596 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 74597 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 74598 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 74599 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 74600 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 74601 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 74602 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 74603 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 74604 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 74605 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 74606 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 74607 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 74608 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 74609 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 74610 | #define BIF_CFG_DEV0_EPF0_VF24_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 74611 | //BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID |
|---|
| 74612 | #define BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 74613 | #define BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 74614 | #define BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 74615 | #define BIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 74616 | //BIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE |
|---|
| 74617 | #define BIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 74618 | #define BIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 74619 | //BIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS |
|---|
| 74620 | #define BIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 74621 | #define BIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 74622 | //BIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS |
|---|
| 74623 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 74624 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 74625 | //BIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE |
|---|
| 74626 | #define BIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 74627 | #define BIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 74628 | //BIF_CFG_DEV0_EPF0_VF24_0_LATENCY |
|---|
| 74629 | #define BIF_CFG_DEV0_EPF0_VF24_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 74630 | #define BIF_CFG_DEV0_EPF0_VF24_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 74631 | //BIF_CFG_DEV0_EPF0_VF24_0_HEADER |
|---|
| 74632 | #define 0x0 |
|---|
| 74633 | #define 0x7 |
|---|
| 74634 | #define 0x7FL |
|---|
| 74635 | #define 0x80L |
|---|
| 74636 | //BIF_CFG_DEV0_EPF0_VF24_0_BIST |
|---|
| 74637 | #define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 74638 | #define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 74639 | #define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 74640 | #define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 74641 | #define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 74642 | #define BIF_CFG_DEV0_EPF0_VF24_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 74643 | //BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1 |
|---|
| 74644 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 74645 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 74646 | //BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2 |
|---|
| 74647 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 74648 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 74649 | //BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3 |
|---|
| 74650 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 74651 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 74652 | //BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4 |
|---|
| 74653 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 74654 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 74655 | //BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5 |
|---|
| 74656 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 74657 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 74658 | //BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6 |
|---|
| 74659 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 74660 | #define BIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 74661 | //BIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR |
|---|
| 74662 | #define BIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 74663 | #define BIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 74664 | //BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID |
|---|
| 74665 | #define BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 74666 | #define BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 74667 | #define BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 74668 | #define BIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 74669 | //BIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR |
|---|
| 74670 | #define BIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 74671 | #define BIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 74672 | //BIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR |
|---|
| 74673 | #define BIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 74674 | #define BIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 74675 | //BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE |
|---|
| 74676 | #define BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 74677 | #define BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 74678 | //BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN |
|---|
| 74679 | #define BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 74680 | #define BIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 74681 | //BIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT |
|---|
| 74682 | #define BIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 74683 | #define BIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 74684 | //BIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY |
|---|
| 74685 | #define BIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 74686 | #define BIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 74687 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST |
|---|
| 74688 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 74689 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 74690 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 74691 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 74692 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP |
|---|
| 74693 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 74694 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 74695 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 74696 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 74697 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 74698 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 74699 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 74700 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 74701 | //BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP |
|---|
| 74702 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 74703 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 74704 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 74705 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 74706 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 74707 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 74708 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 74709 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 74710 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 74711 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 74712 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 74713 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 74714 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 74715 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 74716 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 74717 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 74718 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 74719 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 74720 | //BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL |
|---|
| 74721 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 74722 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 74723 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 74724 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 74725 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 74726 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 74727 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 74728 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 74729 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 74730 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 74731 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 74732 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 74733 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 74734 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 74735 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 74736 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 74737 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 74738 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 74739 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 74740 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 74741 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 74742 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 74743 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 74744 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 74745 | //BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS |
|---|
| 74746 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 74747 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 74748 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 74749 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 74750 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 74751 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 74752 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 74753 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 74754 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 74755 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 74756 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 74757 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 74758 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 74759 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 74760 | //BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP |
|---|
| 74761 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 74762 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 74763 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 74764 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 74765 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 74766 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 74767 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 74768 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 74769 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 74770 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 74771 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 74772 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 74773 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 74774 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 74775 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 74776 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 74777 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 74778 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 74779 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 74780 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 74781 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 74782 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 74783 | //BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL |
|---|
| 74784 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 74785 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 74786 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 74787 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 74788 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 74789 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 74790 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 74791 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 74792 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 74793 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 74794 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 74795 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 74796 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 74797 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 74798 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 74799 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 74800 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 74801 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 74802 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 74803 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 74804 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 74805 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 74806 | //BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS |
|---|
| 74807 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 74808 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 74809 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 74810 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 74811 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 74812 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 74813 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 74814 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 74815 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 74816 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 74817 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 74818 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 74819 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 74820 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 74821 | //BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2 |
|---|
| 74822 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 74823 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 74824 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 74825 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 74826 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 74827 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 74828 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 74829 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 74830 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 74831 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 74832 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 74833 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 74834 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 74835 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 74836 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 74837 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 74838 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 74839 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 74840 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 74841 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 74842 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 74843 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 74844 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 74845 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 74846 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 74847 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 74848 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 74849 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 74850 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 74851 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 74852 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 74853 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 74854 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 74855 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 74856 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 74857 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 74858 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 74859 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 74860 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 74861 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 74862 | //BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2 |
|---|
| 74863 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 74864 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 74865 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 74866 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 74867 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 74868 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 74869 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 74870 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 74871 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 74872 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 74873 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 74874 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 74875 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 74876 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 74877 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 74878 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 74879 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 74880 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 74881 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 74882 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 74883 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 74884 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 74885 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 74886 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 74887 | //BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2 |
|---|
| 74888 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 74889 | #define BIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 74890 | //BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2 |
|---|
| 74891 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 74892 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 74893 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 74894 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 74895 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 74896 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 74897 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 74898 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 74899 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 74900 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 74901 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 74902 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 74903 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 74904 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 74905 | //BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2 |
|---|
| 74906 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 74907 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 74908 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 74909 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 74910 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 74911 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 74912 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 74913 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 74914 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 74915 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 74916 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 74917 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 74918 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 74919 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 74920 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 74921 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 74922 | //BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2 |
|---|
| 74923 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 74924 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 74925 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 74926 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 74927 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 74928 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 74929 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 74930 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 74931 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 74932 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 74933 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 74934 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 74935 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 74936 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 74937 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 74938 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 74939 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 74940 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 74941 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 74942 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 74943 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 74944 | #define BIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 74945 | //BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST |
|---|
| 74946 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 74947 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 74948 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 74949 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 74950 | //BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL |
|---|
| 74951 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 74952 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 74953 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 74954 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 74955 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 74956 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 74957 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 74958 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 74959 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 74960 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 74961 | //BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO |
|---|
| 74962 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 74963 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 74964 | //BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI |
|---|
| 74965 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 74966 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 74967 | //BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA |
|---|
| 74968 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 74969 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 74970 | //BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK |
|---|
| 74971 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 74972 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 74973 | //BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64 |
|---|
| 74974 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 74975 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 74976 | //BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64 |
|---|
| 74977 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 74978 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 74979 | //BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING |
|---|
| 74980 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 74981 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 74982 | //BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64 |
|---|
| 74983 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 74984 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 74985 | //BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST |
|---|
| 74986 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 74987 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 74988 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 74989 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 74990 | //BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL |
|---|
| 74991 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 74992 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 74993 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 74994 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 74995 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 74996 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 74997 | //BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE |
|---|
| 74998 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 74999 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 75000 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 75001 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 75002 | //BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA |
|---|
| 75003 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 75004 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 75005 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 75006 | #define BIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 75007 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 75008 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75009 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 75010 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 75011 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 75012 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 75013 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 75014 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 75015 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 75016 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 75017 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 75018 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 75019 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 75020 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 75021 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 75022 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 75023 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 75024 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 75025 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 75026 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 75027 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 75028 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75029 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 75030 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 75031 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 75032 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 75033 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 75034 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 75035 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 75036 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 75037 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 75038 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 75039 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 75040 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 75041 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 75042 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 75043 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 75044 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 75045 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 75046 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 75047 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 75048 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 75049 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 75050 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 75051 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 75052 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 75053 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 75054 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 75055 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 75056 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 75057 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 75058 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 75059 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 75060 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 75061 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 75062 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 75063 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 75064 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 75065 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 75066 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 75067 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK |
|---|
| 75068 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 75069 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 75070 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 75071 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 75072 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 75073 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 75074 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 75075 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 75076 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 75077 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 75078 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 75079 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 75080 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 75081 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 75082 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 75083 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 75084 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 75085 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 75086 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 75087 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 75088 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 75089 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 75090 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 75091 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 75092 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 75093 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 75094 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 75095 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 75096 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 75097 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 75098 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 75099 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 75100 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 75101 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 75102 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 75103 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 75104 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 75105 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 75106 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 75107 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 75108 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 75109 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 75110 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 75111 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 75112 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 75113 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 75114 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 75115 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 75116 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 75117 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 75118 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 75119 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 75120 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 75121 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 75122 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 75123 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 75124 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 75125 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 75126 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 75127 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 75128 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 75129 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 75130 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 75131 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 75132 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 75133 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS |
|---|
| 75134 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 75135 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 75136 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 75137 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 75138 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 75139 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 75140 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 75141 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 75142 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 75143 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 75144 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 75145 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 75146 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 75147 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 75148 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 75149 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 75150 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK |
|---|
| 75151 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 75152 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 75153 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 75154 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 75155 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 75156 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 75157 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 75158 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 75159 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 75160 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 75161 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 75162 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 75163 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 75164 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 75165 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 75166 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 75167 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 75168 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 75169 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 75170 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 75171 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 75172 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 75173 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 75174 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 75175 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 75176 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 75177 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 75178 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 75179 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 75180 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 75181 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 75182 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 75183 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 75184 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 75185 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 75186 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0 |
|---|
| 75187 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 75188 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 75189 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1 |
|---|
| 75190 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 75191 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 75192 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2 |
|---|
| 75193 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 75194 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 75195 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3 |
|---|
| 75196 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 75197 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 75198 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 75199 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 75200 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 75201 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 75202 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 75203 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 75204 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 75205 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 75206 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 75207 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 75208 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 75209 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 75210 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 75211 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75212 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 75213 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 75214 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 75215 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 75216 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 75217 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP |
|---|
| 75218 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 75219 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 75220 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 75221 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 75222 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 75223 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 75224 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL |
|---|
| 75225 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 75226 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 75227 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 75228 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 75229 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 75230 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75231 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 75232 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 75233 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 75234 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 75235 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 75236 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP |
|---|
| 75237 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 75238 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 75239 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 75240 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 75241 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 75242 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 75243 | //BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL |
|---|
| 75244 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 75245 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 75246 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 75247 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 75248 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 75249 | #define BIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 75250 | |
|---|
| 75251 | |
|---|
| 75252 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp |
|---|
| 75253 | //BIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID |
|---|
| 75254 | #define BIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 75255 | #define BIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 75256 | //BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID |
|---|
| 75257 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 75258 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 75259 | //BIF_CFG_DEV0_EPF0_VF25_0_COMMAND |
|---|
| 75260 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 75261 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 75262 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 75263 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 75264 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 75265 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 75266 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 75267 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 75268 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 75269 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 75270 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 75271 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 75272 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 75273 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 75274 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 75275 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 75276 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 75277 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 75278 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 75279 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 75280 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 75281 | #define BIF_CFG_DEV0_EPF0_VF25_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 75282 | //BIF_CFG_DEV0_EPF0_VF25_0_STATUS |
|---|
| 75283 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 75284 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 75285 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 75286 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 75287 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 75288 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 75289 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 75290 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 75291 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 75292 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 75293 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 75294 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 75295 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 75296 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 75297 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 75298 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 75299 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 75300 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 75301 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 75302 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 75303 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 75304 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 75305 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 75306 | #define BIF_CFG_DEV0_EPF0_VF25_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 75307 | //BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID |
|---|
| 75308 | #define BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 75309 | #define BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 75310 | #define BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 75311 | #define BIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 75312 | //BIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE |
|---|
| 75313 | #define BIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 75314 | #define BIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 75315 | //BIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS |
|---|
| 75316 | #define BIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 75317 | #define BIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 75318 | //BIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS |
|---|
| 75319 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 75320 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 75321 | //BIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE |
|---|
| 75322 | #define BIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 75323 | #define BIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 75324 | //BIF_CFG_DEV0_EPF0_VF25_0_LATENCY |
|---|
| 75325 | #define BIF_CFG_DEV0_EPF0_VF25_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 75326 | #define BIF_CFG_DEV0_EPF0_VF25_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 75327 | //BIF_CFG_DEV0_EPF0_VF25_0_HEADER |
|---|
| 75328 | #define 0x0 |
|---|
| 75329 | #define 0x7 |
|---|
| 75330 | #define 0x7FL |
|---|
| 75331 | #define 0x80L |
|---|
| 75332 | //BIF_CFG_DEV0_EPF0_VF25_0_BIST |
|---|
| 75333 | #define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 75334 | #define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 75335 | #define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 75336 | #define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 75337 | #define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 75338 | #define BIF_CFG_DEV0_EPF0_VF25_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 75339 | //BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1 |
|---|
| 75340 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 75341 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 75342 | //BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2 |
|---|
| 75343 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 75344 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 75345 | //BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3 |
|---|
| 75346 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 75347 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 75348 | //BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4 |
|---|
| 75349 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 75350 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 75351 | //BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5 |
|---|
| 75352 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 75353 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 75354 | //BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6 |
|---|
| 75355 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 75356 | #define BIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 75357 | //BIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR |
|---|
| 75358 | #define BIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 75359 | #define BIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 75360 | //BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID |
|---|
| 75361 | #define BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 75362 | #define BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 75363 | #define BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 75364 | #define BIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 75365 | //BIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR |
|---|
| 75366 | #define BIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 75367 | #define BIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 75368 | //BIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR |
|---|
| 75369 | #define BIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 75370 | #define BIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 75371 | //BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE |
|---|
| 75372 | #define BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 75373 | #define BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 75374 | //BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN |
|---|
| 75375 | #define BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 75376 | #define BIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 75377 | //BIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT |
|---|
| 75378 | #define BIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 75379 | #define BIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 75380 | //BIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY |
|---|
| 75381 | #define BIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 75382 | #define BIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 75383 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST |
|---|
| 75384 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75385 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 75386 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 75387 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 75388 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP |
|---|
| 75389 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 75390 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 75391 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 75392 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 75393 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 75394 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 75395 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 75396 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 75397 | //BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP |
|---|
| 75398 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 75399 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 75400 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 75401 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 75402 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 75403 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 75404 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 75405 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 75406 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 75407 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 75408 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 75409 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 75410 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 75411 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 75412 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 75413 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 75414 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 75415 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 75416 | //BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL |
|---|
| 75417 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 75418 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 75419 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 75420 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 75421 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 75422 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 75423 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 75424 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 75425 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 75426 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 75427 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 75428 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 75429 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 75430 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 75431 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 75432 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 75433 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 75434 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 75435 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 75436 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 75437 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 75438 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 75439 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 75440 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 75441 | //BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS |
|---|
| 75442 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 75443 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 75444 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 75445 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 75446 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 75447 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 75448 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 75449 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 75450 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 75451 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 75452 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 75453 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 75454 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 75455 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 75456 | //BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP |
|---|
| 75457 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 75458 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 75459 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 75460 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 75461 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 75462 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 75463 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 75464 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 75465 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 75466 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 75467 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 75468 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 75469 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 75470 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 75471 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 75472 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 75473 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 75474 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 75475 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 75476 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 75477 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 75478 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 75479 | //BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL |
|---|
| 75480 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 75481 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 75482 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 75483 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 75484 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 75485 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 75486 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 75487 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 75488 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 75489 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 75490 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 75491 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 75492 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 75493 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 75494 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 75495 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 75496 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 75497 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 75498 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 75499 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 75500 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 75501 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 75502 | //BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS |
|---|
| 75503 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 75504 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 75505 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 75506 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 75507 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 75508 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 75509 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 75510 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 75511 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 75512 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 75513 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 75514 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 75515 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 75516 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 75517 | //BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2 |
|---|
| 75518 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 75519 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 75520 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 75521 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 75522 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 75523 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 75524 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 75525 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 75526 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 75527 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 75528 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 75529 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 75530 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 75531 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 75532 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 75533 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 75534 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 75535 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 75536 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 75537 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 75538 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 75539 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 75540 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 75541 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 75542 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 75543 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 75544 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 75545 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 75546 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 75547 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 75548 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 75549 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 75550 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 75551 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 75552 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 75553 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 75554 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 75555 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 75556 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 75557 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 75558 | //BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2 |
|---|
| 75559 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 75560 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 75561 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 75562 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 75563 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 75564 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 75565 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 75566 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 75567 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 75568 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 75569 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 75570 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 75571 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 75572 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 75573 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 75574 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 75575 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 75576 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 75577 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 75578 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 75579 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 75580 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 75581 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 75582 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 75583 | //BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2 |
|---|
| 75584 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 75585 | #define BIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 75586 | //BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2 |
|---|
| 75587 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 75588 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 75589 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 75590 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 75591 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 75592 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 75593 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 75594 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 75595 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 75596 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 75597 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 75598 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 75599 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 75600 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 75601 | //BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2 |
|---|
| 75602 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 75603 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 75604 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 75605 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 75606 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 75607 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 75608 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 75609 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 75610 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 75611 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 75612 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 75613 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 75614 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 75615 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 75616 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 75617 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 75618 | //BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2 |
|---|
| 75619 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 75620 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 75621 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 75622 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 75623 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 75624 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 75625 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 75626 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 75627 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 75628 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 75629 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 75630 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 75631 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 75632 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 75633 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 75634 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 75635 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 75636 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 75637 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 75638 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 75639 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 75640 | #define BIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 75641 | //BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST |
|---|
| 75642 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75643 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 75644 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 75645 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 75646 | //BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL |
|---|
| 75647 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 75648 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 75649 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 75650 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 75651 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 75652 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 75653 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 75654 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 75655 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 75656 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 75657 | //BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO |
|---|
| 75658 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 75659 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 75660 | //BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI |
|---|
| 75661 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 75662 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 75663 | //BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA |
|---|
| 75664 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 75665 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 75666 | //BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK |
|---|
| 75667 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 75668 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 75669 | //BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64 |
|---|
| 75670 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 75671 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 75672 | //BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64 |
|---|
| 75673 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 75674 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 75675 | //BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING |
|---|
| 75676 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 75677 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 75678 | //BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64 |
|---|
| 75679 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 75680 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 75681 | //BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST |
|---|
| 75682 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75683 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 75684 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 75685 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 75686 | //BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL |
|---|
| 75687 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 75688 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 75689 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 75690 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 75691 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 75692 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 75693 | //BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE |
|---|
| 75694 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 75695 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 75696 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 75697 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 75698 | //BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA |
|---|
| 75699 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 75700 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 75701 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 75702 | #define BIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 75703 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 75704 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75705 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 75706 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 75707 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 75708 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 75709 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 75710 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 75711 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 75712 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 75713 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 75714 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 75715 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 75716 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 75717 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 75718 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 75719 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 75720 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 75721 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 75722 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 75723 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 75724 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75725 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 75726 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 75727 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 75728 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 75729 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 75730 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 75731 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 75732 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 75733 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 75734 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 75735 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 75736 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 75737 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 75738 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 75739 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 75740 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 75741 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 75742 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 75743 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 75744 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 75745 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 75746 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 75747 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 75748 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 75749 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 75750 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 75751 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 75752 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 75753 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 75754 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 75755 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 75756 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 75757 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 75758 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 75759 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 75760 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 75761 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 75762 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 75763 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK |
|---|
| 75764 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 75765 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 75766 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 75767 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 75768 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 75769 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 75770 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 75771 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 75772 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 75773 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 75774 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 75775 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 75776 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 75777 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 75778 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 75779 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 75780 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 75781 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 75782 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 75783 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 75784 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 75785 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 75786 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 75787 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 75788 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 75789 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 75790 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 75791 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 75792 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 75793 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 75794 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 75795 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 75796 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 75797 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 75798 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 75799 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 75800 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 75801 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 75802 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 75803 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 75804 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 75805 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 75806 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 75807 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 75808 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 75809 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 75810 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 75811 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 75812 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 75813 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 75814 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 75815 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 75816 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 75817 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 75818 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 75819 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 75820 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 75821 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 75822 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 75823 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 75824 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 75825 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 75826 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 75827 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 75828 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 75829 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS |
|---|
| 75830 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 75831 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 75832 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 75833 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 75834 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 75835 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 75836 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 75837 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 75838 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 75839 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 75840 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 75841 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 75842 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 75843 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 75844 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 75845 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 75846 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK |
|---|
| 75847 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 75848 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 75849 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 75850 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 75851 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 75852 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 75853 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 75854 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 75855 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 75856 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 75857 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 75858 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 75859 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 75860 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 75861 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 75862 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 75863 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 75864 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 75865 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 75866 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 75867 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 75868 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 75869 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 75870 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 75871 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 75872 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 75873 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 75874 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 75875 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 75876 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 75877 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 75878 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 75879 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 75880 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 75881 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 75882 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0 |
|---|
| 75883 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 75884 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 75885 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1 |
|---|
| 75886 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 75887 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 75888 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2 |
|---|
| 75889 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 75890 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 75891 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3 |
|---|
| 75892 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 75893 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 75894 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 75895 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 75896 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 75897 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 75898 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 75899 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 75900 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 75901 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 75902 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 75903 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 75904 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 75905 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 75906 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 75907 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75908 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 75909 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 75910 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 75911 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 75912 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 75913 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP |
|---|
| 75914 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 75915 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 75916 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 75917 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 75918 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 75919 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 75920 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL |
|---|
| 75921 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 75922 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 75923 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 75924 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 75925 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 75926 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 75927 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 75928 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 75929 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 75930 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 75931 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 75932 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP |
|---|
| 75933 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 75934 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 75935 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 75936 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 75937 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 75938 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 75939 | //BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL |
|---|
| 75940 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 75941 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 75942 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 75943 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 75944 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 75945 | #define BIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 75946 | |
|---|
| 75947 | |
|---|
| 75948 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp |
|---|
| 75949 | //BIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID |
|---|
| 75950 | #define BIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 75951 | #define BIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 75952 | //BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID |
|---|
| 75953 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 75954 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 75955 | //BIF_CFG_DEV0_EPF0_VF26_0_COMMAND |
|---|
| 75956 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 75957 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 75958 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 75959 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 75960 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 75961 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 75962 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 75963 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 75964 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 75965 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 75966 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 75967 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 75968 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 75969 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 75970 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 75971 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 75972 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 75973 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 75974 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 75975 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 75976 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 75977 | #define BIF_CFG_DEV0_EPF0_VF26_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 75978 | //BIF_CFG_DEV0_EPF0_VF26_0_STATUS |
|---|
| 75979 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 75980 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 75981 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 75982 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 75983 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 75984 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 75985 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 75986 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 75987 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 75988 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 75989 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 75990 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 75991 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 75992 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 75993 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 75994 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 75995 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 75996 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 75997 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 75998 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 75999 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 76000 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 76001 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 76002 | #define BIF_CFG_DEV0_EPF0_VF26_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 76003 | //BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID |
|---|
| 76004 | #define BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 76005 | #define BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 76006 | #define BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 76007 | #define BIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 76008 | //BIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE |
|---|
| 76009 | #define BIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 76010 | #define BIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 76011 | //BIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS |
|---|
| 76012 | #define BIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 76013 | #define BIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 76014 | //BIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS |
|---|
| 76015 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 76016 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 76017 | //BIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE |
|---|
| 76018 | #define BIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 76019 | #define BIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 76020 | //BIF_CFG_DEV0_EPF0_VF26_0_LATENCY |
|---|
| 76021 | #define BIF_CFG_DEV0_EPF0_VF26_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 76022 | #define BIF_CFG_DEV0_EPF0_VF26_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 76023 | //BIF_CFG_DEV0_EPF0_VF26_0_HEADER |
|---|
| 76024 | #define 0x0 |
|---|
| 76025 | #define 0x7 |
|---|
| 76026 | #define 0x7FL |
|---|
| 76027 | #define 0x80L |
|---|
| 76028 | //BIF_CFG_DEV0_EPF0_VF26_0_BIST |
|---|
| 76029 | #define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 76030 | #define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 76031 | #define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 76032 | #define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 76033 | #define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 76034 | #define BIF_CFG_DEV0_EPF0_VF26_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 76035 | //BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1 |
|---|
| 76036 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 76037 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76038 | //BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2 |
|---|
| 76039 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 76040 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76041 | //BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3 |
|---|
| 76042 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 76043 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76044 | //BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4 |
|---|
| 76045 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 76046 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76047 | //BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5 |
|---|
| 76048 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 76049 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76050 | //BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6 |
|---|
| 76051 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 76052 | #define BIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76053 | //BIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR |
|---|
| 76054 | #define BIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 76055 | #define BIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 76056 | //BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID |
|---|
| 76057 | #define BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 76058 | #define BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 76059 | #define BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 76060 | #define BIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 76061 | //BIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR |
|---|
| 76062 | #define BIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 76063 | #define BIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76064 | //BIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR |
|---|
| 76065 | #define BIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 76066 | #define BIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 76067 | //BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE |
|---|
| 76068 | #define BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 76069 | #define BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 76070 | //BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN |
|---|
| 76071 | #define BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 76072 | #define BIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 76073 | //BIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT |
|---|
| 76074 | #define BIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 76075 | #define BIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 76076 | //BIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY |
|---|
| 76077 | #define BIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
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| 76078 | #define BIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
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| 76079 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST |
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| 76080 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 76081 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 76082 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 76083 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 76084 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP |
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| 76085 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__VERSION__SHIFT 0x0 |
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| 76086 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 76087 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 76088 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
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| 76089 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__VERSION_MASK 0x000FL |
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| 76090 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
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| 76091 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
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| 76092 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
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| 76093 | //BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP |
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| 76094 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
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| 76095 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
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| 76096 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
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| 76097 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
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| 76098 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
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| 76099 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
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| 76100 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
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| 76101 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
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| 76102 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
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| 76103 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 76104 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 76105 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
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| 76106 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
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| 76107 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
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| 76108 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
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| 76109 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
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| 76110 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
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| 76111 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
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| 76112 | //BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL |
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| 76113 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
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| 76114 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
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| 76115 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
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| 76116 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
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| 76117 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 76118 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 76119 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
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| 76120 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
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| 76121 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
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| 76122 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 76123 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 76124 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
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| 76125 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
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| 76126 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
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| 76127 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
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| 76128 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
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| 76129 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
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| 76130 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
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| 76131 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
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| 76132 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
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| 76133 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
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| 76134 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
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| 76135 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
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| 76136 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
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| 76137 | //BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS |
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| 76138 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
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| 76139 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
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| 76140 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
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| 76141 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 76142 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 76143 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 76144 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
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| 76145 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
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| 76146 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 76147 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
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| 76148 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
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| 76149 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
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| 76150 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
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| 76151 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
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| 76152 | //BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP |
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| 76153 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
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| 76154 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 76155 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 76156 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
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| 76157 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 76158 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
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| 76159 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
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| 76160 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 76161 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
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| 76162 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 76163 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 76164 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
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| 76165 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
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| 76166 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
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| 76167 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
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| 76168 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
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| 76169 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
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| 76170 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
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| 76171 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
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| 76172 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
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| 76173 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
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| 76174 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
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| 76175 | //BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL |
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| 76176 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
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| 76177 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
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| 76178 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
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| 76179 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
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| 76180 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
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| 76181 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
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| 76182 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
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| 76183 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
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| 76184 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
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| 76185 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
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| 76186 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
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| 76187 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
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| 76188 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
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| 76189 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
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| 76190 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
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| 76191 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
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| 76192 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
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| 76193 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
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| 76194 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
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| 76195 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
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| 76196 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
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| 76197 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
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| 76198 | //BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS |
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| 76199 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
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| 76200 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
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| 76201 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
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| 76202 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
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| 76203 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
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| 76204 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
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| 76205 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
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| 76206 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
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| 76207 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
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| 76208 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
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| 76209 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
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| 76210 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
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| 76211 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
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| 76212 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
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| 76213 | //BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2 |
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| 76214 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
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| 76215 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
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| 76216 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
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| 76217 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
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| 76218 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
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| 76219 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
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| 76220 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
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| 76221 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
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| 76222 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
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| 76223 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
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| 76224 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
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| 76225 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
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| 76226 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
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| 76227 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
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| 76228 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
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| 76229 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
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| 76230 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
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| 76231 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
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| 76232 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
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| 76233 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
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| 76234 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
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| 76235 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
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| 76236 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
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| 76237 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
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| 76238 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 76239 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
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| 76240 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
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| 76241 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
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| 76242 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
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| 76243 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
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| 76244 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
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| 76245 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 76246 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
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| 76247 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 76248 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 76249 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 76250 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 76251 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 76252 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 76253 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 76254 | //BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2 |
|---|
| 76255 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 76256 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 76257 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 76258 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 76259 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 76260 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 76261 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 76262 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 76263 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 76264 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 76265 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 76266 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 76267 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 76268 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 76269 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 76270 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 76271 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 76272 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 76273 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 76274 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 76275 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 76276 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 76277 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 76278 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 76279 | //BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2 |
|---|
| 76280 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 76281 | #define BIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 76282 | //BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2 |
|---|
| 76283 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 76284 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 76285 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 76286 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 76287 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 76288 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 76289 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 76290 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 76291 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 76292 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 76293 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 76294 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 76295 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 76296 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 76297 | //BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2 |
|---|
| 76298 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 76299 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 76300 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 76301 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 76302 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 76303 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 76304 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 76305 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 76306 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 76307 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 76308 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 76309 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 76310 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 76311 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 76312 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 76313 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 76314 | //BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2 |
|---|
| 76315 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 76316 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 76317 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 76318 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 76319 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 76320 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 76321 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 76322 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 76323 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 76324 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 76325 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 76326 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 76327 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 76328 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 76329 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 76330 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 76331 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 76332 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 76333 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 76334 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 76335 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 76336 | #define BIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 76337 | //BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST |
|---|
| 76338 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 76339 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 76340 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 76341 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 76342 | //BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL |
|---|
| 76343 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 76344 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 76345 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 76346 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 76347 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 76348 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 76349 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 76350 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 76351 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 76352 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 76353 | //BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO |
|---|
| 76354 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 76355 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 76356 | //BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI |
|---|
| 76357 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 76358 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 76359 | //BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA |
|---|
| 76360 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 76361 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 76362 | //BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK |
|---|
| 76363 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 76364 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 76365 | //BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64 |
|---|
| 76366 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 76367 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 76368 | //BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64 |
|---|
| 76369 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 76370 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 76371 | //BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING |
|---|
| 76372 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 76373 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 76374 | //BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64 |
|---|
| 76375 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 76376 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 76377 | //BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST |
|---|
| 76378 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 76379 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 76380 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 76381 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 76382 | //BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL |
|---|
| 76383 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 76384 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 76385 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 76386 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 76387 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 76388 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 76389 | //BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE |
|---|
| 76390 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 76391 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 76392 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 76393 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 76394 | //BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA |
|---|
| 76395 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 76396 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 76397 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 76398 | #define BIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 76399 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 76400 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 76401 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 76402 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 76403 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 76404 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 76405 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 76406 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 76407 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 76408 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 76409 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 76410 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 76411 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 76412 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 76413 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 76414 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 76415 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 76416 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 76417 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 76418 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 76419 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 76420 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 76421 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 76422 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 76423 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 76424 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 76425 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 76426 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 76427 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 76428 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 76429 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 76430 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 76431 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 76432 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 76433 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 76434 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 76435 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 76436 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 76437 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 76438 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 76439 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 76440 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 76441 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 76442 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 76443 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 76444 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 76445 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 76446 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 76447 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 76448 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 76449 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 76450 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 76451 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 76452 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 76453 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 76454 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 76455 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 76456 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 76457 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 76458 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 76459 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK |
|---|
| 76460 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 76461 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 76462 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 76463 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 76464 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 76465 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 76466 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 76467 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 76468 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 76469 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 76470 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 76471 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 76472 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 76473 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 76474 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 76475 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 76476 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 76477 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 76478 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 76479 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 76480 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 76481 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 76482 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 76483 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 76484 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 76485 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 76486 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 76487 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 76488 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 76489 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 76490 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 76491 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 76492 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 76493 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 76494 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 76495 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 76496 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 76497 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 76498 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 76499 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 76500 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 76501 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 76502 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 76503 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 76504 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 76505 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 76506 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 76507 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 76508 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 76509 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 76510 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 76511 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 76512 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 76513 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 76514 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 76515 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 76516 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 76517 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 76518 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 76519 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 76520 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 76521 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 76522 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 76523 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 76524 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 76525 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS |
|---|
| 76526 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 76527 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 76528 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 76529 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 76530 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 76531 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 76532 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 76533 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 76534 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 76535 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 76536 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 76537 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 76538 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 76539 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 76540 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 76541 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 76542 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK |
|---|
| 76543 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 76544 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 76545 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 76546 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 76547 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 76548 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 76549 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 76550 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 76551 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 76552 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 76553 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 76554 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 76555 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 76556 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 76557 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 76558 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 76559 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 76560 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 76561 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 76562 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 76563 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 76564 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 76565 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 76566 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 76567 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 76568 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 76569 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 76570 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 76571 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 76572 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 76573 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 76574 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 76575 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 76576 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 76577 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 76578 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0 |
|---|
| 76579 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 76580 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 76581 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1 |
|---|
| 76582 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 76583 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 76584 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2 |
|---|
| 76585 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 76586 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 76587 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3 |
|---|
| 76588 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 76589 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 76590 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 76591 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 76592 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 76593 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 76594 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 76595 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 76596 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 76597 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 76598 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 76599 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 76600 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 76601 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 76602 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 76603 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 76604 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 76605 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 76606 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 76607 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 76608 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 76609 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP |
|---|
| 76610 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 76611 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 76612 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 76613 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 76614 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 76615 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 76616 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL |
|---|
| 76617 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 76618 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 76619 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 76620 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 76621 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 76622 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 76623 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 76624 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 76625 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 76626 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 76627 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 76628 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP |
|---|
| 76629 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 76630 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 76631 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 76632 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 76633 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 76634 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 76635 | //BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL |
|---|
| 76636 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 76637 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 76638 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 76639 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 76640 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 76641 | #define BIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 76642 | |
|---|
| 76643 | |
|---|
| 76644 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp |
|---|
| 76645 | //BIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID |
|---|
| 76646 | #define BIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 76647 | #define BIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 76648 | //BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID |
|---|
| 76649 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 76650 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 76651 | //BIF_CFG_DEV0_EPF0_VF27_0_COMMAND |
|---|
| 76652 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 76653 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 76654 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 76655 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 76656 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 76657 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 76658 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 76659 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 76660 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 76661 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 76662 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 76663 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 76664 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 76665 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 76666 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 76667 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 76668 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 76669 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 76670 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 76671 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 76672 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 76673 | #define BIF_CFG_DEV0_EPF0_VF27_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 76674 | //BIF_CFG_DEV0_EPF0_VF27_0_STATUS |
|---|
| 76675 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 76676 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 76677 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 76678 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 76679 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 76680 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 76681 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 76682 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 76683 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 76684 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 76685 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 76686 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 76687 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 76688 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 76689 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 76690 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 76691 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 76692 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 76693 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 76694 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 76695 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 76696 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 76697 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 76698 | #define BIF_CFG_DEV0_EPF0_VF27_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 76699 | //BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID |
|---|
| 76700 | #define BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 76701 | #define BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 76702 | #define BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 76703 | #define BIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 76704 | //BIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE |
|---|
| 76705 | #define BIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 76706 | #define BIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 76707 | //BIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS |
|---|
| 76708 | #define BIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 76709 | #define BIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 76710 | //BIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS |
|---|
| 76711 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 76712 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 76713 | //BIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE |
|---|
| 76714 | #define BIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 76715 | #define BIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 76716 | //BIF_CFG_DEV0_EPF0_VF27_0_LATENCY |
|---|
| 76717 | #define BIF_CFG_DEV0_EPF0_VF27_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 76718 | #define BIF_CFG_DEV0_EPF0_VF27_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 76719 | //BIF_CFG_DEV0_EPF0_VF27_0_HEADER |
|---|
| 76720 | #define 0x0 |
|---|
| 76721 | #define 0x7 |
|---|
| 76722 | #define 0x7FL |
|---|
| 76723 | #define 0x80L |
|---|
| 76724 | //BIF_CFG_DEV0_EPF0_VF27_0_BIST |
|---|
| 76725 | #define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 76726 | #define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 76727 | #define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 76728 | #define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 76729 | #define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 76730 | #define BIF_CFG_DEV0_EPF0_VF27_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 76731 | //BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1 |
|---|
| 76732 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 76733 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76734 | //BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2 |
|---|
| 76735 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 76736 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76737 | //BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3 |
|---|
| 76738 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 76739 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76740 | //BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4 |
|---|
| 76741 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 76742 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76743 | //BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5 |
|---|
| 76744 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 76745 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76746 | //BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6 |
|---|
| 76747 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 76748 | #define BIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76749 | //BIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR |
|---|
| 76750 | #define BIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 76751 | #define BIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 76752 | //BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID |
|---|
| 76753 | #define BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 76754 | #define BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 76755 | #define BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 76756 | #define BIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 76757 | //BIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR |
|---|
| 76758 | #define BIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 76759 | #define BIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 76760 | //BIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR |
|---|
| 76761 | #define BIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 76762 | #define BIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 76763 | //BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE |
|---|
| 76764 | #define BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 76765 | #define BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 76766 | //BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN |
|---|
| 76767 | #define BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 76768 | #define BIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 76769 | //BIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT |
|---|
| 76770 | #define BIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 76771 | #define BIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 76772 | //BIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY |
|---|
| 76773 | #define BIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 76774 | #define BIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 76775 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST |
|---|
| 76776 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 76777 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 76778 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 76779 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 76780 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP |
|---|
| 76781 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 76782 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 76783 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 76784 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 76785 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 76786 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 76787 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 76788 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 76789 | //BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP |
|---|
| 76790 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 76791 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 76792 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 76793 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 76794 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 76795 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 76796 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 76797 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 76798 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 76799 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 76800 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 76801 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 76802 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 76803 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 76804 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 76805 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 76806 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 76807 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 76808 | //BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL |
|---|
| 76809 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 76810 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 76811 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 76812 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 76813 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 76814 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 76815 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 76816 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 76817 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 76818 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 76819 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 76820 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 76821 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 76822 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 76823 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 76824 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 76825 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 76826 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 76827 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 76828 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 76829 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 76830 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 76831 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 76832 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 76833 | //BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS |
|---|
| 76834 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 76835 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 76836 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 76837 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 76838 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 76839 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 76840 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 76841 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 76842 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 76843 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 76844 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 76845 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 76846 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 76847 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 76848 | //BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP |
|---|
| 76849 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 76850 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 76851 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 76852 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 76853 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 76854 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 76855 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 76856 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 76857 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 76858 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 76859 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 76860 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 76861 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 76862 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 76863 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 76864 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 76865 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 76866 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 76867 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 76868 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 76869 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 76870 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 76871 | //BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL |
|---|
| 76872 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 76873 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 76874 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 76875 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 76876 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 76877 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 76878 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 76879 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 76880 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 76881 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 76882 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 76883 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 76884 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 76885 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 76886 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 76887 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 76888 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 76889 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 76890 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 76891 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 76892 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 76893 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 76894 | //BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS |
|---|
| 76895 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 76896 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 76897 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 76898 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 76899 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 76900 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 76901 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 76902 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 76903 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 76904 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 76905 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 76906 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 76907 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 76908 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 76909 | //BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2 |
|---|
| 76910 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 76911 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 76912 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 76913 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 76914 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 76915 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 76916 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 76917 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 76918 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 76919 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 76920 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 76921 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 76922 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 76923 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 76924 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 76925 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 76926 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 76927 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 76928 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 76929 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 76930 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 76931 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 76932 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 76933 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 76934 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 76935 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 76936 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 76937 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 76938 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 76939 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 76940 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 76941 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 76942 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 76943 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 76944 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 76945 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 76946 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 76947 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 76948 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 76949 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 76950 | //BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2 |
|---|
| 76951 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 76952 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 76953 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 76954 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 76955 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 76956 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 76957 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 76958 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 76959 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 76960 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 76961 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 76962 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 76963 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 76964 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 76965 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 76966 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 76967 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 76968 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 76969 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 76970 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 76971 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 76972 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 76973 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 76974 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 76975 | //BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2 |
|---|
| 76976 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 76977 | #define BIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 76978 | //BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2 |
|---|
| 76979 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 76980 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 76981 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 76982 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 76983 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 76984 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 76985 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 76986 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 76987 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 76988 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 76989 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 76990 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 76991 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 76992 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 76993 | //BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2 |
|---|
| 76994 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 76995 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 76996 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 76997 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 76998 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 76999 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 77000 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 77001 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 77002 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 77003 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 77004 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 77005 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 77006 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 77007 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 77008 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 77009 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 77010 | //BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2 |
|---|
| 77011 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 77012 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 77013 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 77014 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 77015 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 77016 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 77017 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 77018 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 77019 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 77020 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 77021 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 77022 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 77023 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 77024 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 77025 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 77026 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 77027 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 77028 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 77029 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 77030 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 77031 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 77032 | #define BIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 77033 | //BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST |
|---|
| 77034 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 77035 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 77036 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 77037 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 77038 | //BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL |
|---|
| 77039 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 77040 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 77041 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 77042 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 77043 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 77044 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 77045 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 77046 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 77047 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 77048 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 77049 | //BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO |
|---|
| 77050 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 77051 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 77052 | //BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI |
|---|
| 77053 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 77054 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 77055 | //BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA |
|---|
| 77056 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 77057 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 77058 | //BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK |
|---|
| 77059 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 77060 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 77061 | //BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64 |
|---|
| 77062 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 77063 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 77064 | //BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64 |
|---|
| 77065 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 77066 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 77067 | //BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING |
|---|
| 77068 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 77069 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 77070 | //BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64 |
|---|
| 77071 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 77072 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 77073 | //BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST |
|---|
| 77074 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 77075 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 77076 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 77077 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 77078 | //BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL |
|---|
| 77079 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 77080 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 77081 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 77082 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 77083 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 77084 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 77085 | //BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE |
|---|
| 77086 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 77087 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 77088 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 77089 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 77090 | //BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA |
|---|
| 77091 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 77092 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 77093 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 77094 | #define BIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 77095 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 77096 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 77097 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 77098 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 77099 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 77100 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 77101 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 77102 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 77103 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 77104 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 77105 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 77106 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 77107 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 77108 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 77109 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 77110 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 77111 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 77112 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 77113 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 77114 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 77115 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 77116 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 77117 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 77118 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 77119 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 77120 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 77121 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 77122 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 77123 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 77124 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 77125 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 77126 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 77127 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 77128 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 77129 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 77130 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 77131 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 77132 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 77133 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 77134 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 77135 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 77136 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 77137 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 77138 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 77139 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 77140 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 77141 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 77142 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 77143 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 77144 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 77145 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 77146 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 77147 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 77148 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 77149 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 77150 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 77151 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 77152 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 77153 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 77154 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 77155 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK |
|---|
| 77156 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 77157 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 77158 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 77159 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 77160 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 77161 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 77162 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 77163 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 77164 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 77165 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 77166 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 77167 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 77168 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 77169 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 77170 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 77171 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 77172 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 77173 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 77174 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 77175 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 77176 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 77177 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 77178 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 77179 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 77180 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 77181 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 77182 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 77183 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 77184 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 77185 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 77186 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 77187 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 77188 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 77189 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 77190 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 77191 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 77192 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 77193 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 77194 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 77195 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 77196 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 77197 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 77198 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 77199 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 77200 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 77201 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 77202 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 77203 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 77204 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 77205 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 77206 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 77207 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 77208 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 77209 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 77210 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 77211 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 77212 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 77213 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 77214 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 77215 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 77216 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 77217 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 77218 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 77219 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 77220 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 77221 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS |
|---|
| 77222 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 77223 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 77224 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 77225 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 77226 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 77227 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 77228 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 77229 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 77230 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 77231 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 77232 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 77233 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 77234 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 77235 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 77236 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 77237 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 77238 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK |
|---|
| 77239 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 77240 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 77241 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 77242 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 77243 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 77244 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 77245 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 77246 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 77247 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 77248 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 77249 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 77250 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 77251 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 77252 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 77253 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 77254 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 77255 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 77256 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 77257 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 77258 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 77259 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 77260 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 77261 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 77262 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 77263 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 77264 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 77265 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 77266 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 77267 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 77268 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 77269 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 77270 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 77271 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 77272 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 77273 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 77274 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0 |
|---|
| 77275 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 77276 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 77277 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1 |
|---|
| 77278 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 77279 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 77280 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2 |
|---|
| 77281 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 77282 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 77283 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3 |
|---|
| 77284 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 77285 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 77286 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 77287 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 77288 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 77289 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 77290 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 77291 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 77292 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 77293 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 77294 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 77295 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 77296 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 77297 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 77298 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 77299 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 77300 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 77301 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 77302 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 77303 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 77304 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 77305 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP |
|---|
| 77306 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 77307 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 77308 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 77309 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 77310 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 77311 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 77312 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL |
|---|
| 77313 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 77314 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 77315 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 77316 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 77317 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 77318 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 77319 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 77320 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 77321 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 77322 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 77323 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 77324 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP |
|---|
| 77325 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 77326 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 77327 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 77328 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 77329 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 77330 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 77331 | //BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL |
|---|
| 77332 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 77333 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 77334 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 77335 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 77336 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 77337 | #define BIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 77338 | |
|---|
| 77339 | |
|---|
| 77340 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp |
|---|
| 77341 | //BIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID |
|---|
| 77342 | #define BIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 77343 | #define BIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 77344 | //BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID |
|---|
| 77345 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 77346 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 77347 | //BIF_CFG_DEV0_EPF0_VF28_0_COMMAND |
|---|
| 77348 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 77349 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 77350 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 77351 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 77352 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 77353 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 77354 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 77355 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 77356 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 77357 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 77358 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 77359 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 77360 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 77361 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 77362 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 77363 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 77364 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 77365 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 77366 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 77367 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 77368 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 77369 | #define BIF_CFG_DEV0_EPF0_VF28_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 77370 | //BIF_CFG_DEV0_EPF0_VF28_0_STATUS |
|---|
| 77371 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 77372 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 77373 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 77374 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 77375 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 77376 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 77377 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 77378 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 77379 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 77380 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 77381 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 77382 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 77383 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 77384 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 77385 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 77386 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 77387 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 77388 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 77389 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 77390 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 77391 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 77392 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 77393 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 77394 | #define BIF_CFG_DEV0_EPF0_VF28_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 77395 | //BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID |
|---|
| 77396 | #define BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 77397 | #define BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 77398 | #define BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 77399 | #define BIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 77400 | //BIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE |
|---|
| 77401 | #define BIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 77402 | #define BIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 77403 | //BIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS |
|---|
| 77404 | #define BIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 77405 | #define BIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 77406 | //BIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS |
|---|
| 77407 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 77408 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 77409 | //BIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE |
|---|
| 77410 | #define BIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 77411 | #define BIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 77412 | //BIF_CFG_DEV0_EPF0_VF28_0_LATENCY |
|---|
| 77413 | #define BIF_CFG_DEV0_EPF0_VF28_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 77414 | #define BIF_CFG_DEV0_EPF0_VF28_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 77415 | //BIF_CFG_DEV0_EPF0_VF28_0_HEADER |
|---|
| 77416 | #define 0x0 |
|---|
| 77417 | #define 0x7 |
|---|
| 77418 | #define 0x7FL |
|---|
| 77419 | #define 0x80L |
|---|
| 77420 | //BIF_CFG_DEV0_EPF0_VF28_0_BIST |
|---|
| 77421 | #define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 77422 | #define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 77423 | #define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 77424 | #define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 77425 | #define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 77426 | #define BIF_CFG_DEV0_EPF0_VF28_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 77427 | //BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1 |
|---|
| 77428 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 77429 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 77430 | //BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2 |
|---|
| 77431 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 77432 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 77433 | //BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3 |
|---|
| 77434 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 77435 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 77436 | //BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4 |
|---|
| 77437 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 77438 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 77439 | //BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5 |
|---|
| 77440 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 77441 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 77442 | //BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6 |
|---|
| 77443 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 77444 | #define BIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 77445 | //BIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR |
|---|
| 77446 | #define BIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 77447 | #define BIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 77448 | //BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID |
|---|
| 77449 | #define BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 77450 | #define BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 77451 | #define BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 77452 | #define BIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 77453 | //BIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR |
|---|
| 77454 | #define BIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 77455 | #define BIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 77456 | //BIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR |
|---|
| 77457 | #define BIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 77458 | #define BIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 77459 | //BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE |
|---|
| 77460 | #define BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 77461 | #define BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 77462 | //BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN |
|---|
| 77463 | #define BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 77464 | #define BIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 77465 | //BIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT |
|---|
| 77466 | #define BIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 77467 | #define BIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 77468 | //BIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY |
|---|
| 77469 | #define BIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 77470 | #define BIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 77471 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST |
|---|
| 77472 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 77473 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 77474 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 77475 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 77476 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP |
|---|
| 77477 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 77478 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 77479 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 77480 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 77481 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 77482 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 77483 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 77484 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 77485 | //BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP |
|---|
| 77486 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 77487 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 77488 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 77489 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 77490 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 77491 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 77492 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 77493 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 77494 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 77495 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 77496 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 77497 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 77498 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 77499 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 77500 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 77501 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 77502 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 77503 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 77504 | //BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL |
|---|
| 77505 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 77506 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 77507 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 77508 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 77509 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 77510 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 77511 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 77512 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 77513 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 77514 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 77515 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 77516 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 77517 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 77518 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 77519 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 77520 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 77521 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 77522 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 77523 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 77524 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 77525 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 77526 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 77527 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 77528 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 77529 | //BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS |
|---|
| 77530 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 77531 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 77532 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 77533 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 77534 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 77535 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 77536 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 77537 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 77538 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 77539 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 77540 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 77541 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 77542 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 77543 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 77544 | //BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP |
|---|
| 77545 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 77546 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 77547 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 77548 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 77549 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 77550 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 77551 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 77552 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 77553 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 77554 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 77555 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 77556 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 77557 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 77558 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 77559 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 77560 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 77561 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 77562 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 77563 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 77564 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 77565 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 77566 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 77567 | //BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL |
|---|
| 77568 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 77569 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 77570 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 77571 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 77572 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 77573 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 77574 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 77575 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 77576 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 77577 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 77578 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 77579 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 77580 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 77581 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 77582 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 77583 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 77584 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 77585 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 77586 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 77587 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 77588 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 77589 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 77590 | //BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS |
|---|
| 77591 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 77592 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 77593 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 77594 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 77595 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 77596 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 77597 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 77598 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 77599 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 77600 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 77601 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 77602 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 77603 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 77604 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 77605 | //BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2 |
|---|
| 77606 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 77607 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 77608 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 77609 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 77610 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 77611 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 77612 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 77613 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 77614 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 77615 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 77616 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 77617 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 77618 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 77619 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 77620 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 77621 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 77622 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 77623 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 77624 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 77625 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 77626 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 77627 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 77628 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 77629 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 77630 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 77631 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 77632 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 77633 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 77634 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 77635 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 77636 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 77637 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 77638 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 77639 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 77640 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 77641 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 77642 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 77643 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 77644 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 77645 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 77646 | //BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2 |
|---|
| 77647 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 77648 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 77649 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 77650 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 77651 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 77652 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 77653 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 77654 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 77655 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 77656 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 77657 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 77658 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 77659 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 77660 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 77661 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 77662 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 77663 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 77664 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 77665 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 77666 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 77667 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 77668 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 77669 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 77670 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 77671 | //BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2 |
|---|
| 77672 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 77673 | #define BIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 77674 | //BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2 |
|---|
| 77675 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 77676 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 77677 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 77678 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 77679 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 77680 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 77681 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 77682 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 77683 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 77684 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 77685 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 77686 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 77687 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 77688 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 77689 | //BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2 |
|---|
| 77690 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 77691 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 77692 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 77693 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 77694 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 77695 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 77696 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 77697 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 77698 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 77699 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 77700 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 77701 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 77702 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 77703 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 77704 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 77705 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 77706 | //BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2 |
|---|
| 77707 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 77708 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 77709 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 77710 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 77711 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 77712 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 77713 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 77714 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 77715 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 77716 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 77717 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 77718 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 77719 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 77720 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 77721 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 77722 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 77723 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 77724 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 77725 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 77726 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 77727 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 77728 | #define BIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 77729 | //BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST |
|---|
| 77730 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 77731 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 77732 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 77733 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 77734 | //BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL |
|---|
| 77735 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 77736 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 77737 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 77738 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 77739 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 77740 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 77741 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 77742 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 77743 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 77744 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 77745 | //BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO |
|---|
| 77746 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 77747 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 77748 | //BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI |
|---|
| 77749 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
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| 77750 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 77751 | //BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA |
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| 77752 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
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| 77753 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
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| 77754 | //BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK |
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| 77755 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
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| 77756 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
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| 77757 | //BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64 |
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| 77758 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
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| 77759 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
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| 77760 | //BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64 |
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| 77761 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
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| 77762 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
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| 77763 | //BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING |
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| 77764 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
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| 77765 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
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| 77766 | //BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64 |
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| 77767 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
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| 77768 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
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| 77769 | //BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST |
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| 77770 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 77771 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 77772 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 77773 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 77774 | //BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL |
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| 77775 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
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| 77776 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
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| 77777 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
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| 77778 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
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| 77779 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
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| 77780 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
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| 77781 | //BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE |
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| 77782 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
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| 77783 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
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| 77784 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
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| 77785 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
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| 77786 | //BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA |
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| 77787 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
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| 77788 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
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| 77789 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
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| 77790 | #define BIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
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| 77791 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
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| 77792 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 77793 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 77794 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 77795 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 77796 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 77797 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 77798 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR |
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| 77799 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
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| 77800 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
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| 77801 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
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| 77802 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
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| 77803 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 77804 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
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| 77805 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1 |
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| 77806 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 77807 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 77808 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 77809 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 77810 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 77811 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 77812 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 77813 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 77814 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 77815 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 77816 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 77817 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 77818 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 77819 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 77820 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 77821 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 77822 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 77823 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 77824 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 77825 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 77826 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 77827 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 77828 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 77829 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 77830 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 77831 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 77832 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 77833 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 77834 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 77835 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 77836 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 77837 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 77838 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 77839 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 77840 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 77841 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 77842 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 77843 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 77844 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 77845 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 77846 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 77847 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 77848 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 77849 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 77850 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 77851 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK |
|---|
| 77852 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 77853 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 77854 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 77855 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 77856 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 77857 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 77858 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 77859 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 77860 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 77861 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 77862 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 77863 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 77864 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 77865 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 77866 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 77867 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 77868 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 77869 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 77870 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 77871 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 77872 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 77873 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 77874 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 77875 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 77876 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 77877 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 77878 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 77879 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 77880 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 77881 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 77882 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 77883 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 77884 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 77885 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 77886 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 77887 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 77888 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 77889 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 77890 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 77891 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 77892 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 77893 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 77894 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 77895 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 77896 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 77897 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 77898 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 77899 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 77900 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 77901 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 77902 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 77903 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 77904 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 77905 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 77906 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 77907 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 77908 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 77909 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 77910 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 77911 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 77912 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 77913 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 77914 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 77915 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 77916 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 77917 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS |
|---|
| 77918 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 77919 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 77920 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 77921 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 77922 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 77923 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 77924 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 77925 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 77926 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 77927 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 77928 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 77929 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 77930 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 77931 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 77932 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 77933 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 77934 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK |
|---|
| 77935 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 77936 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 77937 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 77938 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 77939 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 77940 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 77941 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 77942 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 77943 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 77944 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 77945 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 77946 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 77947 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 77948 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 77949 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 77950 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 77951 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 77952 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 77953 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 77954 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 77955 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 77956 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 77957 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 77958 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 77959 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 77960 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 77961 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 77962 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 77963 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 77964 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 77965 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 77966 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 77967 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 77968 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 77969 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 77970 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0 |
|---|
| 77971 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 77972 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 77973 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1 |
|---|
| 77974 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 77975 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 77976 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2 |
|---|
| 77977 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 77978 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 77979 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3 |
|---|
| 77980 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 77981 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 77982 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 77983 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 77984 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 77985 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 77986 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 77987 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 77988 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 77989 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 77990 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 77991 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 77992 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 77993 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 77994 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 77995 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 77996 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 77997 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 77998 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 77999 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 78000 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 78001 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP |
|---|
| 78002 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 78003 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 78004 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 78005 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 78006 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 78007 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 78008 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL |
|---|
| 78009 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 78010 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 78011 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 78012 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 78013 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 78014 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 78015 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 78016 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 78017 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 78018 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 78019 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 78020 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP |
|---|
| 78021 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 78022 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 78023 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 78024 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 78025 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 78026 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 78027 | //BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL |
|---|
| 78028 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 78029 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 78030 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 78031 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 78032 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 78033 | #define BIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 78034 | |
|---|
| 78035 | |
|---|
| 78036 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp |
|---|
| 78037 | //BIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID |
|---|
| 78038 | #define BIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 78039 | #define BIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 78040 | //BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID |
|---|
| 78041 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 78042 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 78043 | //BIF_CFG_DEV0_EPF0_VF29_0_COMMAND |
|---|
| 78044 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 78045 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 78046 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 78047 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 78048 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 78049 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 78050 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 78051 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 78052 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 78053 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 78054 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 78055 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 78056 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 78057 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 78058 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 78059 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 78060 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 78061 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 78062 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 78063 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 78064 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 78065 | #define BIF_CFG_DEV0_EPF0_VF29_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 78066 | //BIF_CFG_DEV0_EPF0_VF29_0_STATUS |
|---|
| 78067 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
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| 78068 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__INT_STATUS__SHIFT 0x3 |
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| 78069 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__CAP_LIST__SHIFT 0x4 |
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| 78070 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
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| 78071 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
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| 78072 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
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| 78073 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
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| 78074 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
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| 78075 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
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| 78076 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
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| 78077 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
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| 78078 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
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| 78079 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
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| 78080 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__INT_STATUS_MASK 0x0008L |
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| 78081 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__CAP_LIST_MASK 0x0010L |
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| 78082 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PCI_66_CAP_MASK 0x0020L |
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| 78083 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
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| 78084 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
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| 78085 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
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| 78086 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
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| 78087 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
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| 78088 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
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| 78089 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
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| 78090 | #define BIF_CFG_DEV0_EPF0_VF29_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
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| 78091 | //BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID |
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| 78092 | #define BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
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| 78093 | #define BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
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| 78094 | #define BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
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| 78095 | #define BIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
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| 78096 | //BIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE |
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| 78097 | #define BIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
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| 78098 | #define BIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
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| 78099 | //BIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS |
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| 78100 | #define BIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
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| 78101 | #define BIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
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| 78102 | //BIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS |
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| 78103 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
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| 78104 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
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| 78105 | //BIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE |
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| 78106 | #define BIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
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| 78107 | #define BIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
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| 78108 | //BIF_CFG_DEV0_EPF0_VF29_0_LATENCY |
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| 78109 | #define BIF_CFG_DEV0_EPF0_VF29_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
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| 78110 | #define BIF_CFG_DEV0_EPF0_VF29_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
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| 78111 | //BIF_CFG_DEV0_EPF0_VF29_0_HEADER |
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| 78112 | #define 0x0 |
|---|
| 78113 | #define 0x7 |
|---|
| 78114 | #define 0x7FL |
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| 78115 | #define 0x80L |
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| 78116 | //BIF_CFG_DEV0_EPF0_VF29_0_BIST |
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| 78117 | #define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_COMP__SHIFT 0x0 |
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| 78118 | #define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_STRT__SHIFT 0x6 |
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| 78119 | #define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_CAP__SHIFT 0x7 |
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| 78120 | #define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_COMP_MASK 0x0FL |
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| 78121 | #define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_STRT_MASK 0x40L |
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| 78122 | #define BIF_CFG_DEV0_EPF0_VF29_0_BIST__BIST_CAP_MASK 0x80L |
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| 78123 | //BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1 |
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| 78124 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
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| 78125 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 78126 | //BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2 |
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| 78127 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
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| 78128 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 78129 | //BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3 |
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| 78130 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
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| 78131 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 78132 | //BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4 |
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| 78133 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
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| 78134 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 78135 | //BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5 |
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| 78136 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
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| 78137 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 78138 | //BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6 |
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| 78139 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
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| 78140 | #define BIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 78141 | //BIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR |
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| 78142 | #define BIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
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| 78143 | #define BIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
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| 78144 | //BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID |
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| 78145 | #define BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
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| 78146 | #define BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
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| 78147 | #define BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 78148 | #define BIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
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| 78149 | //BIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR |
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| 78150 | #define BIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
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| 78151 | #define BIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 78152 | //BIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR |
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| 78153 | #define BIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
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| 78154 | #define BIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
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| 78155 | //BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE |
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| 78156 | #define BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
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| 78157 | #define BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 78158 | //BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN |
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| 78159 | #define BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
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| 78160 | #define BIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
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| 78161 | //BIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT |
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| 78162 | #define BIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
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| 78163 | #define BIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
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| 78164 | //BIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY |
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| 78165 | #define BIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
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| 78166 | #define BIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 78167 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST |
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| 78168 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 78169 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 78170 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 78171 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 78172 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP |
|---|
| 78173 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__VERSION__SHIFT 0x0 |
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| 78174 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 78175 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 78176 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
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| 78177 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__VERSION_MASK 0x000FL |
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| 78178 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
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| 78179 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 78180 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
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| 78181 | //BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP |
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| 78182 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
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| 78183 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
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| 78184 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
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| 78185 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 78186 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 78187 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 78188 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 78189 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 78190 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
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| 78191 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 78192 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 78193 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
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| 78194 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
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| 78195 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
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| 78196 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 78197 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 78198 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
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| 78199 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
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| 78200 | //BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL |
|---|
| 78201 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 78202 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 78203 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 78204 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 78205 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 78206 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 78207 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 78208 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 78209 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 78210 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 78211 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 78212 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 78213 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 78214 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 78215 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 78216 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 78217 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 78218 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 78219 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 78220 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 78221 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 78222 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 78223 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 78224 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 78225 | //BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS |
|---|
| 78226 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 78227 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 78228 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 78229 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 78230 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 78231 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 78232 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 78233 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 78234 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 78235 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 78236 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 78237 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 78238 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 78239 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 78240 | //BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP |
|---|
| 78241 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 78242 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 78243 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 78244 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 78245 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 78246 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 78247 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 78248 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 78249 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 78250 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 78251 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 78252 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 78253 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 78254 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 78255 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 78256 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 78257 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 78258 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 78259 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 78260 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 78261 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 78262 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 78263 | //BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL |
|---|
| 78264 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 78265 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 78266 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 78267 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 78268 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 78269 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 78270 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 78271 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 78272 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 78273 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 78274 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 78275 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 78276 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 78277 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 78278 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 78279 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 78280 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 78281 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 78282 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 78283 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 78284 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 78285 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 78286 | //BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS |
|---|
| 78287 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 78288 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 78289 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 78290 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 78291 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 78292 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 78293 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 78294 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 78295 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 78296 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 78297 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 78298 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 78299 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 78300 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 78301 | //BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2 |
|---|
| 78302 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 78303 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 78304 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 78305 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 78306 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 78307 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 78308 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 78309 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 78310 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 78311 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 78312 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 78313 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 78314 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 78315 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 78316 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 78317 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 78318 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 78319 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 78320 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 78321 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 78322 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 78323 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 78324 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 78325 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 78326 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 78327 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 78328 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 78329 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 78330 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 78331 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 78332 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 78333 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 78334 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 78335 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 78336 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 78337 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 78338 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 78339 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 78340 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 78341 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 78342 | //BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2 |
|---|
| 78343 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 78344 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 78345 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 78346 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 78347 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 78348 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 78349 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 78350 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 78351 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 78352 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 78353 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 78354 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 78355 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 78356 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 78357 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 78358 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 78359 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 78360 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 78361 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 78362 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 78363 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 78364 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 78365 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 78366 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 78367 | //BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2 |
|---|
| 78368 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 78369 | #define BIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 78370 | //BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2 |
|---|
| 78371 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 78372 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 78373 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 78374 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 78375 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 78376 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 78377 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 78378 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 78379 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 78380 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 78381 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 78382 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 78383 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 78384 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 78385 | //BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2 |
|---|
| 78386 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 78387 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 78388 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 78389 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 78390 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 78391 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 78392 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 78393 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 78394 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 78395 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 78396 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 78397 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 78398 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 78399 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 78400 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 78401 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 78402 | //BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2 |
|---|
| 78403 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 78404 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 78405 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 78406 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 78407 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 78408 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 78409 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 78410 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 78411 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 78412 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 78413 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 78414 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 78415 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 78416 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 78417 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 78418 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 78419 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 78420 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 78421 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 78422 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 78423 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 78424 | #define BIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 78425 | //BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST |
|---|
| 78426 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 78427 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 78428 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 78429 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 78430 | //BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL |
|---|
| 78431 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 78432 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 78433 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 78434 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 78435 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 78436 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 78437 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 78438 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 78439 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 78440 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 78441 | //BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO |
|---|
| 78442 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 78443 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 78444 | //BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI |
|---|
| 78445 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 78446 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 78447 | //BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA |
|---|
| 78448 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 78449 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 78450 | //BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK |
|---|
| 78451 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 78452 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 78453 | //BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64 |
|---|
| 78454 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 78455 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 78456 | //BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64 |
|---|
| 78457 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 78458 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 78459 | //BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING |
|---|
| 78460 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 78461 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 78462 | //BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64 |
|---|
| 78463 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 78464 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 78465 | //BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST |
|---|
| 78466 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 78467 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 78468 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 78469 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 78470 | //BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL |
|---|
| 78471 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 78472 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 78473 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 78474 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 78475 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 78476 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 78477 | //BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE |
|---|
| 78478 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 78479 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 78480 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 78481 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 78482 | //BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA |
|---|
| 78483 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 78484 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 78485 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 78486 | #define BIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 78487 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 78488 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 78489 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 78490 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 78491 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 78492 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 78493 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 78494 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 78495 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 78496 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 78497 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 78498 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 78499 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 78500 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 78501 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 78502 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 78503 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 78504 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 78505 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 78506 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 78507 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 78508 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 78509 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 78510 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 78511 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 78512 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 78513 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 78514 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 78515 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 78516 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 78517 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 78518 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 78519 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 78520 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 78521 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 78522 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 78523 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 78524 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 78525 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 78526 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 78527 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 78528 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 78529 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 78530 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 78531 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 78532 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 78533 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 78534 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 78535 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 78536 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 78537 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 78538 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 78539 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 78540 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 78541 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 78542 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 78543 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 78544 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 78545 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 78546 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 78547 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK |
|---|
| 78548 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 78549 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 78550 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 78551 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 78552 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 78553 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 78554 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 78555 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 78556 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 78557 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 78558 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 78559 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 78560 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 78561 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 78562 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 78563 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 78564 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 78565 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 78566 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 78567 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 78568 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 78569 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 78570 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 78571 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 78572 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 78573 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 78574 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 78575 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 78576 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 78577 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 78578 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 78579 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 78580 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 78581 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 78582 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 78583 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 78584 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 78585 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 78586 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 78587 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 78588 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 78589 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 78590 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 78591 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 78592 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 78593 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 78594 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 78595 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 78596 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 78597 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 78598 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 78599 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 78600 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 78601 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 78602 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 78603 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 78604 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 78605 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 78606 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 78607 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 78608 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 78609 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 78610 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 78611 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 78612 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 78613 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS |
|---|
| 78614 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 78615 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 78616 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 78617 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 78618 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 78619 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 78620 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 78621 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 78622 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 78623 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 78624 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 78625 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 78626 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 78627 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 78628 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 78629 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 78630 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK |
|---|
| 78631 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 78632 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 78633 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 78634 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 78635 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 78636 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 78637 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 78638 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 78639 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 78640 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 78641 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 78642 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 78643 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 78644 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 78645 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 78646 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 78647 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 78648 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 78649 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 78650 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 78651 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 78652 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 78653 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 78654 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 78655 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 78656 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 78657 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 78658 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 78659 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 78660 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 78661 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 78662 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 78663 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 78664 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 78665 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 78666 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0 |
|---|
| 78667 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 78668 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 78669 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1 |
|---|
| 78670 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 78671 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 78672 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2 |
|---|
| 78673 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 78674 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 78675 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3 |
|---|
| 78676 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 78677 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 78678 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 78679 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 78680 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 78681 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 78682 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 78683 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 78684 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 78685 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 78686 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 78687 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 78688 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 78689 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 78690 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 78691 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 78692 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 78693 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 78694 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 78695 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 78696 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 78697 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP |
|---|
| 78698 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 78699 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 78700 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 78701 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 78702 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 78703 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 78704 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL |
|---|
| 78705 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 78706 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 78707 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 78708 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 78709 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 78710 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 78711 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 78712 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 78713 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 78714 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 78715 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 78716 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP |
|---|
| 78717 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 78718 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 78719 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 78720 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 78721 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 78722 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 78723 | //BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL |
|---|
| 78724 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 78725 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 78726 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 78727 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 78728 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 78729 | #define BIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 78730 | |
|---|
| 78731 | |
|---|
| 78732 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp |
|---|
| 78733 | //BIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID |
|---|
| 78734 | #define BIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 78735 | #define BIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 78736 | //BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID |
|---|
| 78737 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 78738 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 78739 | //BIF_CFG_DEV0_EPF0_VF30_0_COMMAND |
|---|
| 78740 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 78741 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 78742 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 78743 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 78744 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 78745 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 78746 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 78747 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 78748 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 78749 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 78750 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 78751 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 78752 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 78753 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 78754 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 78755 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 78756 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 78757 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 78758 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 78759 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 78760 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 78761 | #define BIF_CFG_DEV0_EPF0_VF30_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 78762 | //BIF_CFG_DEV0_EPF0_VF30_0_STATUS |
|---|
| 78763 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 78764 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 78765 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 78766 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 78767 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 78768 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 78769 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 78770 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 78771 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 78772 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 78773 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 78774 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 78775 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 78776 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 78777 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 78778 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 78779 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 78780 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 78781 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 78782 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 78783 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 78784 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 78785 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 78786 | #define BIF_CFG_DEV0_EPF0_VF30_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 78787 | //BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID |
|---|
| 78788 | #define BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 78789 | #define BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 78790 | #define BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 78791 | #define BIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 78792 | //BIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE |
|---|
| 78793 | #define BIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 78794 | #define BIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 78795 | //BIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS |
|---|
| 78796 | #define BIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 78797 | #define BIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 78798 | //BIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS |
|---|
| 78799 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 78800 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 78801 | //BIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE |
|---|
| 78802 | #define BIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 78803 | #define BIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 78804 | //BIF_CFG_DEV0_EPF0_VF30_0_LATENCY |
|---|
| 78805 | #define BIF_CFG_DEV0_EPF0_VF30_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 78806 | #define BIF_CFG_DEV0_EPF0_VF30_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 78807 | //BIF_CFG_DEV0_EPF0_VF30_0_HEADER |
|---|
| 78808 | #define 0x0 |
|---|
| 78809 | #define 0x7 |
|---|
| 78810 | #define 0x7FL |
|---|
| 78811 | #define 0x80L |
|---|
| 78812 | //BIF_CFG_DEV0_EPF0_VF30_0_BIST |
|---|
| 78813 | #define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 78814 | #define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 78815 | #define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 78816 | #define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 78817 | #define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 78818 | #define BIF_CFG_DEV0_EPF0_VF30_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 78819 | //BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1 |
|---|
| 78820 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 78821 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 78822 | //BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2 |
|---|
| 78823 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 78824 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 78825 | //BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3 |
|---|
| 78826 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 78827 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 78828 | //BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4 |
|---|
| 78829 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 78830 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 78831 | //BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5 |
|---|
| 78832 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 78833 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 78834 | //BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6 |
|---|
| 78835 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 78836 | #define BIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 78837 | //BIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR |
|---|
| 78838 | #define BIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 78839 | #define BIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 78840 | //BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID |
|---|
| 78841 | #define BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 78842 | #define BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 78843 | #define BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 78844 | #define BIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 78845 | //BIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR |
|---|
| 78846 | #define BIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 78847 | #define BIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 78848 | //BIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR |
|---|
| 78849 | #define BIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 78850 | #define BIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 78851 | //BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE |
|---|
| 78852 | #define BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 78853 | #define BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 78854 | //BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN |
|---|
| 78855 | #define BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 78856 | #define BIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 78857 | //BIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT |
|---|
| 78858 | #define BIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 78859 | #define BIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 78860 | //BIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY |
|---|
| 78861 | #define BIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 78862 | #define BIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 78863 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST |
|---|
| 78864 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 78865 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 78866 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 78867 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 78868 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP |
|---|
| 78869 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 78870 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 78871 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 78872 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 78873 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 78874 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 78875 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 78876 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 78877 | //BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP |
|---|
| 78878 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 78879 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 78880 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 78881 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 78882 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 78883 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 78884 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 78885 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 78886 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 78887 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 78888 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 78889 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 78890 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 78891 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 78892 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 78893 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 78894 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 78895 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 78896 | //BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL |
|---|
| 78897 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 78898 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 78899 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 78900 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 78901 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 78902 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 78903 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 78904 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 78905 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 78906 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 78907 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 78908 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 78909 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 78910 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 78911 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 78912 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 78913 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 78914 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 78915 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 78916 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 78917 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 78918 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 78919 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 78920 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 78921 | //BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS |
|---|
| 78922 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 78923 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 78924 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 78925 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 78926 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 78927 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 78928 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 78929 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 78930 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 78931 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 78932 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 78933 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 78934 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 78935 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 78936 | //BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP |
|---|
| 78937 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 78938 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 78939 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 78940 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 78941 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 78942 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 78943 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 78944 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 78945 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 78946 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 78947 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 78948 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 78949 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 78950 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 78951 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 78952 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 78953 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 78954 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 78955 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 78956 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 78957 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 78958 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 78959 | //BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL |
|---|
| 78960 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 78961 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 78962 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 78963 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 78964 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 78965 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 78966 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 78967 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 78968 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 78969 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 78970 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 78971 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 78972 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 78973 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 78974 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 78975 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 78976 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 78977 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 78978 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 78979 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 78980 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 78981 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 78982 | //BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS |
|---|
| 78983 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 78984 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 78985 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 78986 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 78987 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 78988 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 78989 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 78990 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 78991 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 78992 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 78993 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 78994 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 78995 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 78996 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 78997 | //BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2 |
|---|
| 78998 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 78999 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 79000 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 79001 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 79002 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 79003 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 79004 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 79005 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 79006 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 79007 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 79008 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 79009 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 79010 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 79011 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 79012 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 79013 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 79014 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 79015 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 79016 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 79017 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 79018 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 79019 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 79020 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 79021 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 79022 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 79023 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 79024 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 79025 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 79026 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 79027 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 79028 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 79029 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 79030 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 79031 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 79032 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 79033 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 79034 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 79035 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 79036 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 79037 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 79038 | //BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2 |
|---|
| 79039 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 79040 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 79041 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 79042 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 79043 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 79044 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 79045 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 79046 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 79047 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 79048 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 79049 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 79050 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 79051 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 79052 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 79053 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 79054 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 79055 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 79056 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 79057 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 79058 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 79059 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 79060 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 79061 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 79062 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 79063 | //BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2 |
|---|
| 79064 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 79065 | #define BIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 79066 | //BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2 |
|---|
| 79067 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 79068 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 79069 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 79070 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 79071 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 79072 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 79073 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 79074 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 79075 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 79076 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 79077 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 79078 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 79079 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 79080 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 79081 | //BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2 |
|---|
| 79082 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 79083 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 79084 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 79085 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 79086 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 79087 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 79088 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 79089 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 79090 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 79091 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 79092 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 79093 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 79094 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 79095 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 79096 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 79097 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 79098 | //BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2 |
|---|
| 79099 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 79100 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 79101 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 79102 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 79103 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 79104 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 79105 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 79106 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 79107 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 79108 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 79109 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 79110 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 79111 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 79112 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 79113 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 79114 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 79115 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 79116 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 79117 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 79118 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 79119 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 79120 | #define BIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 79121 | //BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST |
|---|
| 79122 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 79123 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 79124 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 79125 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 79126 | //BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL |
|---|
| 79127 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 79128 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 79129 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 79130 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 79131 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 79132 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 79133 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 79134 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 79135 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 79136 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 79137 | //BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO |
|---|
| 79138 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 79139 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 79140 | //BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI |
|---|
| 79141 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 79142 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 79143 | //BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA |
|---|
| 79144 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 79145 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 79146 | //BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK |
|---|
| 79147 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 79148 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 79149 | //BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64 |
|---|
| 79150 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 79151 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 79152 | //BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64 |
|---|
| 79153 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 79154 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 79155 | //BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING |
|---|
| 79156 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 79157 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 79158 | //BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64 |
|---|
| 79159 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 79160 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 79161 | //BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST |
|---|
| 79162 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 79163 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 79164 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 79165 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 79166 | //BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL |
|---|
| 79167 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 79168 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 79169 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 79170 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 79171 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 79172 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 79173 | //BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE |
|---|
| 79174 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 79175 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 79176 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 79177 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 79178 | //BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA |
|---|
| 79179 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 79180 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 79181 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 79182 | #define BIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 79183 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 79184 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 79185 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 79186 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 79187 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 79188 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 79189 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 79190 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 79191 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 79192 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 79193 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 79194 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 79195 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 79196 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 79197 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 79198 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 79199 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 79200 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 79201 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 79202 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 79203 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 79204 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 79205 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 79206 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 79207 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 79208 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 79209 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 79210 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 79211 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 79212 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 79213 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 79214 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 79215 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 79216 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 79217 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 79218 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 79219 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 79220 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 79221 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 79222 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 79223 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 79224 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 79225 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 79226 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 79227 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 79228 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 79229 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 79230 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 79231 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 79232 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 79233 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 79234 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 79235 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 79236 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 79237 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 79238 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 79239 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 79240 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 79241 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 79242 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 79243 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK |
|---|
| 79244 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 79245 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 79246 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 79247 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 79248 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 79249 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 79250 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 79251 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 79252 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 79253 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 79254 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 79255 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 79256 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 79257 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 79258 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 79259 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 79260 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 79261 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 79262 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 79263 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 79264 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 79265 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 79266 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 79267 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 79268 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 79269 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 79270 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 79271 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 79272 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 79273 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 79274 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 79275 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 79276 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 79277 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 79278 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 79279 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 79280 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 79281 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 79282 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 79283 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 79284 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 79285 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 79286 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 79287 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 79288 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 79289 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 79290 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 79291 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 79292 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 79293 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 79294 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 79295 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 79296 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 79297 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 79298 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 79299 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 79300 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 79301 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 79302 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 79303 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 79304 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 79305 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 79306 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 79307 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 79308 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 79309 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS |
|---|
| 79310 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 79311 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 79312 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 79313 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 79314 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 79315 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 79316 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 79317 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 79318 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 79319 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 79320 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 79321 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 79322 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 79323 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 79324 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 79325 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 79326 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK |
|---|
| 79327 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 79328 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 79329 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 79330 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 79331 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 79332 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 79333 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 79334 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 79335 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 79336 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 79337 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 79338 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 79339 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 79340 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 79341 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 79342 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 79343 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 79344 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 79345 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 79346 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 79347 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 79348 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 79349 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 79350 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 79351 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 79352 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 79353 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 79354 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 79355 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 79356 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 79357 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 79358 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 79359 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 79360 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 79361 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 79362 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0 |
|---|
| 79363 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 79364 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 79365 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1 |
|---|
| 79366 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 79367 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 79368 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2 |
|---|
| 79369 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 79370 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 79371 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3 |
|---|
| 79372 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 79373 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 79374 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 79375 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 79376 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 79377 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 79378 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 79379 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 79380 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 79381 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 79382 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 79383 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 79384 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 79385 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 79386 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 79387 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 79388 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 79389 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 79390 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 79391 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 79392 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 79393 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP |
|---|
| 79394 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 79395 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 79396 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 79397 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 79398 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 79399 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 79400 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL |
|---|
| 79401 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 79402 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 79403 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 79404 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 79405 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 79406 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 79407 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 79408 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 79409 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 79410 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 79411 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 79412 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP |
|---|
| 79413 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 79414 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 79415 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 79416 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 79417 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 79418 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 79419 | //BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL |
|---|
| 79420 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 79421 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 79422 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 79423 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 79424 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 79425 | #define BIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 79426 | |
|---|
| 79427 | |
|---|
| 79428 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC |
|---|
| 79429 | //BIF_BX_DEV0_EPF0_VF0_MM_INDEX |
|---|
| 79430 | #define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 79431 | #define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 79432 | #define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 79433 | #define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 79434 | //BIF_BX_DEV0_EPF0_VF0_MM_DATA |
|---|
| 79435 | #define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 79436 | #define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 79437 | //BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI |
|---|
| 79438 | #define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 79439 | #define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 79440 | |
|---|
| 79441 | |
|---|
| 79442 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 |
|---|
| 79443 | //RCC_DEV0_EPF0_VF0_RCC_ERR_LOG |
|---|
| 79444 | #define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 79445 | #define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 79446 | #define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 79447 | #define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 79448 | //RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN |
|---|
| 79449 | #define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 79450 | #define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 79451 | //RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE |
|---|
| 79452 | #define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 79453 | #define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 79454 | //RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED |
|---|
| 79455 | #define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 79456 | #define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 79457 | //RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 79458 | #define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 79459 | #define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 79460 | #define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 79461 | #define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 79462 | |
|---|
| 79463 | |
|---|
| 79464 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 |
|---|
| 79465 | //BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS |
|---|
| 79466 | #define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 79467 | #define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 79468 | #define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 79469 | #define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 79470 | //BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG |
|---|
| 79471 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 79472 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 79473 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 79474 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 79475 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 79476 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 79477 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 79478 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 79479 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 79480 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 79481 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 79482 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 79483 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 79484 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 79485 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 79486 | #define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 79487 | //BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 79488 | #define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 79489 | #define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 79490 | //BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 79491 | #define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 79492 | #define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 79493 | //BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 79494 | #define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 79495 | #define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 79496 | #define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 79497 | #define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 79498 | #define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 79499 | #define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 79500 | //BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 79501 | #define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 79502 | #define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 79503 | //BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 79504 | #define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 79505 | #define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 79506 | //BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ |
|---|
| 79507 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 79508 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 79509 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 79510 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 79511 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 79512 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 79513 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 79514 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 79515 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 79516 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 79517 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 79518 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 79519 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 79520 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 79521 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 79522 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 79523 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 79524 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 79525 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 79526 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 79527 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 79528 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 79529 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 79530 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 79531 | //BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE |
|---|
| 79532 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 79533 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 79534 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 79535 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 79536 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 79537 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 79538 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 79539 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 79540 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 79541 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 79542 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 79543 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 79544 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 79545 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 79546 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 79547 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 79548 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 79549 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 79550 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 79551 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 79552 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 79553 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 79554 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 79555 | #define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 79556 | //BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING |
|---|
| 79557 | #define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 79558 | #define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 79559 | #define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 79560 | #define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 79561 | //BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 79562 | #define BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 79563 | #define BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 79564 | //BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 79565 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79566 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79567 | //BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 79568 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79569 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79570 | //BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 79571 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79572 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79573 | //BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 79574 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79575 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79576 | //BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 79577 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79578 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79579 | //BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 79580 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79581 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79582 | //BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 79583 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79584 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79585 | //BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 79586 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79587 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79588 | //BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL |
|---|
| 79589 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 79590 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 79591 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 79592 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 79593 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 79594 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 79595 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 79596 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 79597 | //BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL |
|---|
| 79598 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 79599 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 79600 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 79601 | #define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 79602 | //BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX |
|---|
| 79603 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 79604 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 79605 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 79606 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 79607 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 79608 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 79609 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 79610 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 79611 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 79612 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 79613 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 79614 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 79615 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 79616 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 79617 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 79618 | #define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 79619 | |
|---|
| 79620 | |
|---|
| 79621 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 |
|---|
| 79622 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO |
|---|
| 79623 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 79624 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 79625 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI |
|---|
| 79626 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 79627 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 79628 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA |
|---|
| 79629 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 79630 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 79631 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL |
|---|
| 79632 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 79633 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 79634 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO |
|---|
| 79635 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 79636 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 79637 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI |
|---|
| 79638 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 79639 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 79640 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA |
|---|
| 79641 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 79642 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 79643 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL |
|---|
| 79644 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 79645 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 79646 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO |
|---|
| 79647 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 79648 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 79649 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI |
|---|
| 79650 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 79651 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 79652 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA |
|---|
| 79653 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 79654 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 79655 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL |
|---|
| 79656 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 79657 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 79658 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO |
|---|
| 79659 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 79660 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 79661 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI |
|---|
| 79662 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 79663 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 79664 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA |
|---|
| 79665 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 79666 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 79667 | //RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL |
|---|
| 79668 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 79669 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 79670 | //RCC_DEV0_EPF0_VF0_GFXMSIX_PBA |
|---|
| 79671 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 79672 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 79673 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 79674 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 79675 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 79676 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 79677 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 79678 | #define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 79679 | |
|---|
| 79680 | |
|---|
| 79681 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC |
|---|
| 79682 | //BIF_BX_DEV0_EPF0_VF1_MM_INDEX |
|---|
| 79683 | #define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 79684 | #define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 79685 | #define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 79686 | #define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 79687 | //BIF_BX_DEV0_EPF0_VF1_MM_DATA |
|---|
| 79688 | #define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 79689 | #define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 79690 | //BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI |
|---|
| 79691 | #define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 79692 | #define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 79693 | |
|---|
| 79694 | |
|---|
| 79695 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 |
|---|
| 79696 | //RCC_DEV0_EPF0_VF1_RCC_ERR_LOG |
|---|
| 79697 | #define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 79698 | #define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 79699 | #define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 79700 | #define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 79701 | //RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN |
|---|
| 79702 | #define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 79703 | #define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 79704 | //RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE |
|---|
| 79705 | #define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 79706 | #define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 79707 | //RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED |
|---|
| 79708 | #define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 79709 | #define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 79710 | //RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 79711 | #define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 79712 | #define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 79713 | #define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 79714 | #define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 79715 | |
|---|
| 79716 | |
|---|
| 79717 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 |
|---|
| 79718 | //BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS |
|---|
| 79719 | #define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 79720 | #define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 79721 | #define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 79722 | #define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 79723 | //BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG |
|---|
| 79724 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 79725 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 79726 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 79727 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 79728 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 79729 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 79730 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 79731 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 79732 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 79733 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 79734 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 79735 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 79736 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 79737 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 79738 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 79739 | #define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 79740 | //BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 79741 | #define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 79742 | #define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 79743 | //BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 79744 | #define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 79745 | #define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 79746 | //BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 79747 | #define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 79748 | #define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 79749 | #define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 79750 | #define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 79751 | #define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 79752 | #define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 79753 | //BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 79754 | #define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 79755 | #define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 79756 | //BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 79757 | #define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 79758 | #define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 79759 | //BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ |
|---|
| 79760 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 79761 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 79762 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 79763 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 79764 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 79765 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 79766 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 79767 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 79768 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 79769 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 79770 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 79771 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 79772 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 79773 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 79774 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 79775 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 79776 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 79777 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 79778 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 79779 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 79780 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 79781 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 79782 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 79783 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 79784 | //BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE |
|---|
| 79785 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 79786 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 79787 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 79788 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 79789 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 79790 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 79791 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 79792 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 79793 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 79794 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 79795 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 79796 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 79797 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 79798 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 79799 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 79800 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 79801 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 79802 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 79803 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 79804 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 79805 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 79806 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 79807 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 79808 | #define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 79809 | //BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING |
|---|
| 79810 | #define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 79811 | #define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 79812 | #define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 79813 | #define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 79814 | //BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 79815 | #define BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 79816 | #define BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 79817 | //BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 79818 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79819 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79820 | //BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 79821 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79822 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79823 | //BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 79824 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79825 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79826 | //BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 79827 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79828 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79829 | //BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 79830 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79831 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79832 | //BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 79833 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79834 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79835 | //BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 79836 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79837 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79838 | //BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 79839 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 79840 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 79841 | //BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL |
|---|
| 79842 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 79843 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 79844 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 79845 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 79846 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 79847 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 79848 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 79849 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 79850 | //BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL |
|---|
| 79851 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 79852 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 79853 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 79854 | #define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 79855 | //BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX |
|---|
| 79856 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 79857 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 79858 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 79859 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 79860 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 79861 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 79862 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 79863 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 79864 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 79865 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 79866 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 79867 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 79868 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 79869 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 79870 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 79871 | #define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 79872 | |
|---|
| 79873 | |
|---|
| 79874 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 |
|---|
| 79875 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO |
|---|
| 79876 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 79877 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 79878 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI |
|---|
| 79879 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 79880 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 79881 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA |
|---|
| 79882 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 79883 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 79884 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL |
|---|
| 79885 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 79886 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 79887 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO |
|---|
| 79888 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 79889 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 79890 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI |
|---|
| 79891 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 79892 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 79893 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA |
|---|
| 79894 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 79895 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 79896 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL |
|---|
| 79897 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 79898 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 79899 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO |
|---|
| 79900 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 79901 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 79902 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI |
|---|
| 79903 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 79904 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 79905 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA |
|---|
| 79906 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 79907 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 79908 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL |
|---|
| 79909 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 79910 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 79911 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO |
|---|
| 79912 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 79913 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 79914 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI |
|---|
| 79915 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 79916 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 79917 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA |
|---|
| 79918 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 79919 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 79920 | //RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL |
|---|
| 79921 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 79922 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 79923 | //RCC_DEV0_EPF0_VF1_GFXMSIX_PBA |
|---|
| 79924 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 79925 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 79926 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 79927 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 79928 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 79929 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 79930 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 79931 | #define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 79932 | |
|---|
| 79933 | |
|---|
| 79934 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC |
|---|
| 79935 | //BIF_BX_DEV0_EPF0_VF2_MM_INDEX |
|---|
| 79936 | #define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 79937 | #define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 79938 | #define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 79939 | #define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 79940 | //BIF_BX_DEV0_EPF0_VF2_MM_DATA |
|---|
| 79941 | #define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 79942 | #define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 79943 | //BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI |
|---|
| 79944 | #define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 79945 | #define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 79946 | |
|---|
| 79947 | |
|---|
| 79948 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 |
|---|
| 79949 | //RCC_DEV0_EPF0_VF2_RCC_ERR_LOG |
|---|
| 79950 | #define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 79951 | #define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 79952 | #define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 79953 | #define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 79954 | //RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN |
|---|
| 79955 | #define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 79956 | #define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 79957 | //RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE |
|---|
| 79958 | #define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 79959 | #define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 79960 | //RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED |
|---|
| 79961 | #define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 79962 | #define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 79963 | //RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 79964 | #define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 79965 | #define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 79966 | #define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 79967 | #define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 79968 | |
|---|
| 79969 | |
|---|
| 79970 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 |
|---|
| 79971 | //BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS |
|---|
| 79972 | #define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 79973 | #define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 79974 | #define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 79975 | #define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 79976 | //BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG |
|---|
| 79977 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 79978 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 79979 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 79980 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 79981 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 79982 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 79983 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 79984 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 79985 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 79986 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 79987 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 79988 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 79989 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 79990 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 79991 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 79992 | #define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 79993 | //BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 79994 | #define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 79995 | #define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 79996 | //BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 79997 | #define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 79998 | #define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 79999 | //BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 80000 | #define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 80001 | #define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 80002 | #define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 80003 | #define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 80004 | #define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 80005 | #define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 80006 | //BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 80007 | #define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 80008 | #define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 80009 | //BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 80010 | #define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 80011 | #define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 80012 | //BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ |
|---|
| 80013 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 80014 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 80015 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 80016 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 80017 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 80018 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 80019 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 80020 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 80021 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 80022 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 80023 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 80024 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 80025 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 80026 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 80027 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 80028 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 80029 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 80030 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 80031 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 80032 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 80033 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 80034 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 80035 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 80036 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 80037 | //BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE |
|---|
| 80038 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 80039 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 80040 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 80041 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 80042 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 80043 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 80044 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 80045 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 80046 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 80047 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 80048 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 80049 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 80050 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 80051 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 80052 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 80053 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 80054 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 80055 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 80056 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 80057 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 80058 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 80059 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 80060 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 80061 | #define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 80062 | //BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING |
|---|
| 80063 | #define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 80064 | #define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 80065 | #define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 80066 | #define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 80067 | //BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 80068 | #define BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 80069 | #define BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 80070 | //BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 80071 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80072 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80073 | //BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 80074 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80075 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80076 | //BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 80077 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
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| 80078 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 80079 | //BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 |
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| 80080 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
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| 80081 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 80082 | //BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 |
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| 80083 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
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| 80084 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 80085 | //BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 |
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| 80086 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
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| 80087 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 80088 | //BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 |
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| 80089 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
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| 80090 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 80091 | //BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 |
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| 80092 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
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| 80093 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 80094 | //BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL |
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| 80095 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
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| 80096 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
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| 80097 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
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| 80098 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
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| 80099 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
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| 80100 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
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| 80101 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
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| 80102 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
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| 80103 | //BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL |
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| 80104 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
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| 80105 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
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| 80106 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
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| 80107 | #define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
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| 80108 | //BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX |
|---|
| 80109 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
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| 80110 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
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| 80111 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 80112 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 80113 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 80114 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
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| 80115 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
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| 80116 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 80117 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 80118 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 80119 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
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| 80120 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 80121 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
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| 80122 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
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| 80123 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 80124 | #define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
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| 80125 | |
|---|
| 80126 | |
|---|
| 80127 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 |
|---|
| 80128 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO |
|---|
| 80129 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
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| 80130 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
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| 80131 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI |
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| 80132 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
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| 80133 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 80134 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA |
|---|
| 80135 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80136 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80137 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL |
|---|
| 80138 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80139 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
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| 80140 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO |
|---|
| 80141 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
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| 80142 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
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| 80143 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI |
|---|
| 80144 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80145 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 80146 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA |
|---|
| 80147 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80148 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
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| 80149 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL |
|---|
| 80150 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
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| 80151 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
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| 80152 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO |
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| 80153 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
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| 80154 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
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| 80155 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI |
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| 80156 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
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| 80157 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 80158 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA |
|---|
| 80159 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
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| 80160 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
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| 80161 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL |
|---|
| 80162 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80163 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
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| 80164 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO |
|---|
| 80165 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
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| 80166 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
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| 80167 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI |
|---|
| 80168 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
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| 80169 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 80170 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA |
|---|
| 80171 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
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| 80172 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
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| 80173 | //RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL |
|---|
| 80174 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
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| 80175 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
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| 80176 | //RCC_DEV0_EPF0_VF2_GFXMSIX_PBA |
|---|
| 80177 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
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| 80178 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
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| 80179 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
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| 80180 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 80181 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
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| 80182 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
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| 80183 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
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| 80184 | #define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
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| 80185 | |
|---|
| 80186 | |
|---|
| 80187 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC |
|---|
| 80188 | //BIF_BX_DEV0_EPF0_VF3_MM_INDEX |
|---|
| 80189 | #define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
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| 80190 | #define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT 0x1f |
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| 80191 | #define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
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| 80192 | #define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 80193 | //BIF_BX_DEV0_EPF0_VF3_MM_DATA |
|---|
| 80194 | #define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 80195 | #define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 80196 | //BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI |
|---|
| 80197 | #define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 80198 | #define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 80199 | |
|---|
| 80200 | |
|---|
| 80201 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 |
|---|
| 80202 | //RCC_DEV0_EPF0_VF3_RCC_ERR_LOG |
|---|
| 80203 | #define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 80204 | #define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 80205 | #define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 80206 | #define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 80207 | //RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN |
|---|
| 80208 | #define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 80209 | #define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 80210 | //RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE |
|---|
| 80211 | #define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 80212 | #define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 80213 | //RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED |
|---|
| 80214 | #define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 80215 | #define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 80216 | //RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 80217 | #define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 80218 | #define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 80219 | #define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 80220 | #define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 80221 | |
|---|
| 80222 | |
|---|
| 80223 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 |
|---|
| 80224 | //BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS |
|---|
| 80225 | #define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 80226 | #define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 80227 | #define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 80228 | #define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 80229 | //BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG |
|---|
| 80230 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 80231 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 80232 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 80233 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 80234 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 80235 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 80236 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 80237 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 80238 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 80239 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 80240 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 80241 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 80242 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 80243 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 80244 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 80245 | #define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 80246 | //BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 80247 | #define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 80248 | #define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 80249 | //BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 80250 | #define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 80251 | #define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 80252 | //BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 80253 | #define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 80254 | #define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 80255 | #define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 80256 | #define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 80257 | #define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 80258 | #define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 80259 | //BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 80260 | #define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 80261 | #define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 80262 | //BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 80263 | #define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 80264 | #define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 80265 | //BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ |
|---|
| 80266 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 80267 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 80268 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 80269 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 80270 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 80271 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 80272 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 80273 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 80274 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 80275 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 80276 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 80277 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 80278 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 80279 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 80280 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 80281 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 80282 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 80283 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 80284 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 80285 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 80286 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 80287 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 80288 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 80289 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 80290 | //BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE |
|---|
| 80291 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 80292 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 80293 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 80294 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 80295 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 80296 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 80297 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 80298 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 80299 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 80300 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 80301 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 80302 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 80303 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 80304 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 80305 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 80306 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 80307 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 80308 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 80309 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 80310 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 80311 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 80312 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 80313 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 80314 | #define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 80315 | //BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING |
|---|
| 80316 | #define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 80317 | #define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 80318 | #define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 80319 | #define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 80320 | //BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 80321 | #define BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 80322 | #define BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 80323 | //BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 80324 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80325 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80326 | //BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 80327 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80328 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80329 | //BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 80330 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80331 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80332 | //BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 80333 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80334 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80335 | //BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 80336 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80337 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80338 | //BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 80339 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80340 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80341 | //BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 80342 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80343 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80344 | //BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 80345 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80346 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80347 | //BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL |
|---|
| 80348 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 80349 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 80350 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 80351 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 80352 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 80353 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 80354 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 80355 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 80356 | //BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL |
|---|
| 80357 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 80358 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 80359 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 80360 | #define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 80361 | //BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX |
|---|
| 80362 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 80363 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 80364 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 80365 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 80366 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 80367 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 80368 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 80369 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 80370 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 80371 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 80372 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 80373 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 80374 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 80375 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 80376 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 80377 | #define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 80378 | |
|---|
| 80379 | |
|---|
| 80380 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 |
|---|
| 80381 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO |
|---|
| 80382 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80383 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80384 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI |
|---|
| 80385 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80386 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80387 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA |
|---|
| 80388 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80389 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80390 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL |
|---|
| 80391 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80392 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80393 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO |
|---|
| 80394 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80395 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80396 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI |
|---|
| 80397 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80398 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80399 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA |
|---|
| 80400 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80401 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80402 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL |
|---|
| 80403 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80404 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80405 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO |
|---|
| 80406 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80407 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80408 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI |
|---|
| 80409 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80410 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80411 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA |
|---|
| 80412 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80413 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80414 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL |
|---|
| 80415 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80416 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80417 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO |
|---|
| 80418 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80419 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80420 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI |
|---|
| 80421 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80422 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80423 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA |
|---|
| 80424 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80425 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80426 | //RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL |
|---|
| 80427 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80428 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80429 | //RCC_DEV0_EPF0_VF3_GFXMSIX_PBA |
|---|
| 80430 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 80431 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 80432 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 80433 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 80434 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 80435 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 80436 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 80437 | #define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 80438 | |
|---|
| 80439 | |
|---|
| 80440 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC |
|---|
| 80441 | //BIF_BX_DEV0_EPF0_VF4_MM_INDEX |
|---|
| 80442 | #define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 80443 | #define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 80444 | #define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 80445 | #define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 80446 | //BIF_BX_DEV0_EPF0_VF4_MM_DATA |
|---|
| 80447 | #define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 80448 | #define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 80449 | //BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI |
|---|
| 80450 | #define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 80451 | #define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 80452 | |
|---|
| 80453 | |
|---|
| 80454 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 |
|---|
| 80455 | //RCC_DEV0_EPF0_VF4_RCC_ERR_LOG |
|---|
| 80456 | #define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 80457 | #define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 80458 | #define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 80459 | #define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 80460 | //RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN |
|---|
| 80461 | #define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 80462 | #define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 80463 | //RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE |
|---|
| 80464 | #define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 80465 | #define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 80466 | //RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED |
|---|
| 80467 | #define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 80468 | #define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 80469 | //RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 80470 | #define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 80471 | #define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 80472 | #define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 80473 | #define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 80474 | |
|---|
| 80475 | |
|---|
| 80476 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 |
|---|
| 80477 | //BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS |
|---|
| 80478 | #define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 80479 | #define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 80480 | #define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 80481 | #define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 80482 | //BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG |
|---|
| 80483 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 80484 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 80485 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 80486 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 80487 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 80488 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 80489 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 80490 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 80491 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 80492 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 80493 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 80494 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 80495 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 80496 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 80497 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 80498 | #define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 80499 | //BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 80500 | #define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 80501 | #define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 80502 | //BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 80503 | #define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 80504 | #define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 80505 | //BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 80506 | #define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 80507 | #define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 80508 | #define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 80509 | #define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 80510 | #define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 80511 | #define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 80512 | //BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 80513 | #define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 80514 | #define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 80515 | //BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 80516 | #define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 80517 | #define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 80518 | //BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ |
|---|
| 80519 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 80520 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 80521 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 80522 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 80523 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 80524 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 80525 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 80526 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 80527 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 80528 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 80529 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 80530 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 80531 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 80532 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 80533 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 80534 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 80535 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 80536 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 80537 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 80538 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 80539 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 80540 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 80541 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 80542 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 80543 | //BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE |
|---|
| 80544 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 80545 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 80546 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 80547 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 80548 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 80549 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 80550 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 80551 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 80552 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 80553 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 80554 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 80555 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 80556 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 80557 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 80558 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 80559 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 80560 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 80561 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 80562 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 80563 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 80564 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 80565 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 80566 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 80567 | #define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 80568 | //BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING |
|---|
| 80569 | #define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 80570 | #define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 80571 | #define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 80572 | #define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 80573 | //BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 80574 | #define BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 80575 | #define BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 80576 | //BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 80577 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80578 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80579 | //BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 80580 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80581 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80582 | //BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 80583 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80584 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80585 | //BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 80586 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80587 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80588 | //BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 80589 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80590 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80591 | //BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 80592 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80593 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80594 | //BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 80595 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80596 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80597 | //BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 80598 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80599 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80600 | //BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL |
|---|
| 80601 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 80602 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 80603 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
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| 80604 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 80605 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 80606 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
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| 80607 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
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| 80608 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
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| 80609 | //BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL |
|---|
| 80610 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 80611 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 80612 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 80613 | #define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 80614 | //BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX |
|---|
| 80615 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 80616 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 80617 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 80618 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 80619 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 80620 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 80621 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 80622 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 80623 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 80624 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 80625 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 80626 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 80627 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 80628 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 80629 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 80630 | #define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 80631 | |
|---|
| 80632 | |
|---|
| 80633 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 |
|---|
| 80634 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO |
|---|
| 80635 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80636 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80637 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI |
|---|
| 80638 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80639 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80640 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA |
|---|
| 80641 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80642 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80643 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL |
|---|
| 80644 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80645 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80646 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO |
|---|
| 80647 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80648 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80649 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI |
|---|
| 80650 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80651 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80652 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA |
|---|
| 80653 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80654 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80655 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL |
|---|
| 80656 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80657 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80658 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO |
|---|
| 80659 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80660 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80661 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI |
|---|
| 80662 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80663 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80664 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA |
|---|
| 80665 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80666 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80667 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL |
|---|
| 80668 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80669 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80670 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO |
|---|
| 80671 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80672 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80673 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI |
|---|
| 80674 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80675 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80676 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA |
|---|
| 80677 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80678 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80679 | //RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL |
|---|
| 80680 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80681 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80682 | //RCC_DEV0_EPF0_VF4_GFXMSIX_PBA |
|---|
| 80683 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 80684 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 80685 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 80686 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 80687 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 80688 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 80689 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 80690 | #define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 80691 | |
|---|
| 80692 | |
|---|
| 80693 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC |
|---|
| 80694 | //BIF_BX_DEV0_EPF0_VF5_MM_INDEX |
|---|
| 80695 | #define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 80696 | #define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 80697 | #define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 80698 | #define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 80699 | //BIF_BX_DEV0_EPF0_VF5_MM_DATA |
|---|
| 80700 | #define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 80701 | #define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 80702 | //BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI |
|---|
| 80703 | #define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 80704 | #define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 80705 | |
|---|
| 80706 | |
|---|
| 80707 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 |
|---|
| 80708 | //RCC_DEV0_EPF0_VF5_RCC_ERR_LOG |
|---|
| 80709 | #define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 80710 | #define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 80711 | #define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 80712 | #define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 80713 | //RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN |
|---|
| 80714 | #define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 80715 | #define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 80716 | //RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE |
|---|
| 80717 | #define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 80718 | #define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 80719 | //RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED |
|---|
| 80720 | #define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 80721 | #define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 80722 | //RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 80723 | #define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 80724 | #define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 80725 | #define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 80726 | #define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 80727 | |
|---|
| 80728 | |
|---|
| 80729 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 |
|---|
| 80730 | //BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS |
|---|
| 80731 | #define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 80732 | #define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 80733 | #define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 80734 | #define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 80735 | //BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG |
|---|
| 80736 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 80737 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 80738 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 80739 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 80740 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 80741 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 80742 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 80743 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 80744 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 80745 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 80746 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 80747 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 80748 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 80749 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 80750 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 80751 | #define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 80752 | //BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 80753 | #define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 80754 | #define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 80755 | //BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 80756 | #define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 80757 | #define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 80758 | //BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 80759 | #define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 80760 | #define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 80761 | #define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 80762 | #define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 80763 | #define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 80764 | #define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 80765 | //BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 80766 | #define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 80767 | #define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 80768 | //BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 80769 | #define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 80770 | #define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 80771 | //BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ |
|---|
| 80772 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 80773 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 80774 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 80775 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 80776 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 80777 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 80778 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 80779 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 80780 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 80781 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 80782 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 80783 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 80784 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 80785 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 80786 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 80787 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 80788 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 80789 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 80790 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 80791 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 80792 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 80793 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 80794 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 80795 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 80796 | //BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE |
|---|
| 80797 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 80798 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 80799 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 80800 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 80801 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 80802 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 80803 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 80804 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 80805 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 80806 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 80807 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 80808 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 80809 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 80810 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 80811 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 80812 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 80813 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 80814 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 80815 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 80816 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 80817 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 80818 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 80819 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 80820 | #define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 80821 | //BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING |
|---|
| 80822 | #define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 80823 | #define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 80824 | #define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 80825 | #define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 80826 | //BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 80827 | #define BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 80828 | #define BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 80829 | //BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 80830 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80831 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80832 | //BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 80833 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80834 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80835 | //BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 80836 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80837 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80838 | //BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 80839 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80840 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80841 | //BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 80842 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80843 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80844 | //BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 80845 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80846 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80847 | //BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 80848 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80849 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80850 | //BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 80851 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 80852 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 80853 | //BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL |
|---|
| 80854 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 80855 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 80856 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 80857 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 80858 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 80859 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 80860 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 80861 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 80862 | //BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL |
|---|
| 80863 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 80864 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 80865 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 80866 | #define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 80867 | //BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX |
|---|
| 80868 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 80869 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 80870 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 80871 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 80872 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 80873 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 80874 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 80875 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 80876 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 80877 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 80878 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 80879 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 80880 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 80881 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 80882 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 80883 | #define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 80884 | |
|---|
| 80885 | |
|---|
| 80886 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 |
|---|
| 80887 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO |
|---|
| 80888 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80889 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80890 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI |
|---|
| 80891 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80892 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80893 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA |
|---|
| 80894 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80895 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80896 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL |
|---|
| 80897 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80898 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80899 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO |
|---|
| 80900 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80901 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80902 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI |
|---|
| 80903 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80904 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80905 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA |
|---|
| 80906 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80907 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80908 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL |
|---|
| 80909 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80910 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80911 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO |
|---|
| 80912 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80913 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80914 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI |
|---|
| 80915 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80916 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80917 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA |
|---|
| 80918 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80919 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80920 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL |
|---|
| 80921 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80922 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80923 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO |
|---|
| 80924 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 80925 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 80926 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI |
|---|
| 80927 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 80928 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 80929 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA |
|---|
| 80930 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 80931 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 80932 | //RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL |
|---|
| 80933 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 80934 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 80935 | //RCC_DEV0_EPF0_VF5_GFXMSIX_PBA |
|---|
| 80936 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 80937 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 80938 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 80939 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 80940 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 80941 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 80942 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 80943 | #define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 80944 | |
|---|
| 80945 | |
|---|
| 80946 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC |
|---|
| 80947 | //BIF_BX_DEV0_EPF0_VF6_MM_INDEX |
|---|
| 80948 | #define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 80949 | #define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 80950 | #define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 80951 | #define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 80952 | //BIF_BX_DEV0_EPF0_VF6_MM_DATA |
|---|
| 80953 | #define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 80954 | #define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 80955 | //BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI |
|---|
| 80956 | #define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 80957 | #define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 80958 | |
|---|
| 80959 | |
|---|
| 80960 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 |
|---|
| 80961 | //RCC_DEV0_EPF0_VF6_RCC_ERR_LOG |
|---|
| 80962 | #define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 80963 | #define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 80964 | #define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 80965 | #define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 80966 | //RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN |
|---|
| 80967 | #define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 80968 | #define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 80969 | //RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE |
|---|
| 80970 | #define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 80971 | #define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 80972 | //RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED |
|---|
| 80973 | #define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 80974 | #define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 80975 | //RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 80976 | #define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 80977 | #define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 80978 | #define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 80979 | #define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 80980 | |
|---|
| 80981 | |
|---|
| 80982 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 |
|---|
| 80983 | //BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS |
|---|
| 80984 | #define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 80985 | #define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 80986 | #define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 80987 | #define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 80988 | //BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG |
|---|
| 80989 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 80990 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 80991 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 80992 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 80993 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 80994 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 80995 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 80996 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 80997 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 80998 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 80999 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 81000 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 81001 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 81002 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 81003 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 81004 | #define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 81005 | //BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 81006 | #define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 81007 | #define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 81008 | //BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 81009 | #define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 81010 | #define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 81011 | //BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 81012 | #define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 81013 | #define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 81014 | #define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 81015 | #define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 81016 | #define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 81017 | #define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 81018 | //BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 81019 | #define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 81020 | #define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 81021 | //BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 81022 | #define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 81023 | #define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 81024 | //BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ |
|---|
| 81025 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 81026 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 81027 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 81028 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 81029 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 81030 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 81031 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 81032 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 81033 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 81034 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 81035 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 81036 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 81037 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 81038 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 81039 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 81040 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 81041 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 81042 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 81043 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 81044 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 81045 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 81046 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 81047 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 81048 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 81049 | //BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE |
|---|
| 81050 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 81051 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 81052 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 81053 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 81054 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 81055 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 81056 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 81057 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 81058 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 81059 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 81060 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 81061 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 81062 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 81063 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 81064 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 81065 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 81066 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 81067 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 81068 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 81069 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 81070 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 81071 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 81072 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 81073 | #define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 81074 | //BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING |
|---|
| 81075 | #define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 81076 | #define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 81077 | #define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 81078 | #define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 81079 | //BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 81080 | #define BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 81081 | #define BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 81082 | //BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 81083 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81084 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81085 | //BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 81086 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81087 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81088 | //BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 81089 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81090 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81091 | //BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 81092 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81093 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81094 | //BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 81095 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81096 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 81097 | //BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 81098 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
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| 81099 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81100 | //BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 81101 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
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| 81102 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81103 | //BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 81104 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81105 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81106 | //BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL |
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| 81107 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 81108 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 81109 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 81110 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
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| 81111 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
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| 81112 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
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| 81113 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
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| 81114 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
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| 81115 | //BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL |
|---|
| 81116 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
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| 81117 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
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| 81118 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
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| 81119 | #define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
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| 81120 | //BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX |
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| 81121 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 81122 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 81123 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 81124 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 81125 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 81126 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 81127 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 81128 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 81129 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 81130 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 81131 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 81132 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 81133 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 81134 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 81135 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 81136 | #define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
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| 81137 | |
|---|
| 81138 | |
|---|
| 81139 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 |
|---|
| 81140 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO |
|---|
| 81141 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81142 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81143 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI |
|---|
| 81144 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81145 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81146 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA |
|---|
| 81147 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81148 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81149 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL |
|---|
| 81150 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81151 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81152 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO |
|---|
| 81153 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81154 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81155 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI |
|---|
| 81156 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81157 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81158 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA |
|---|
| 81159 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81160 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81161 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL |
|---|
| 81162 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81163 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81164 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO |
|---|
| 81165 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81166 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81167 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI |
|---|
| 81168 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81169 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81170 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA |
|---|
| 81171 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81172 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81173 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL |
|---|
| 81174 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81175 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81176 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO |
|---|
| 81177 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81178 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81179 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI |
|---|
| 81180 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81181 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81182 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA |
|---|
| 81183 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81184 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81185 | //RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL |
|---|
| 81186 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81187 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81188 | //RCC_DEV0_EPF0_VF6_GFXMSIX_PBA |
|---|
| 81189 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 81190 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 81191 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 81192 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 81193 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 81194 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 81195 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 81196 | #define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 81197 | |
|---|
| 81198 | |
|---|
| 81199 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC |
|---|
| 81200 | //BIF_BX_DEV0_EPF0_VF7_MM_INDEX |
|---|
| 81201 | #define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 81202 | #define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 81203 | #define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 81204 | #define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 81205 | //BIF_BX_DEV0_EPF0_VF7_MM_DATA |
|---|
| 81206 | #define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 81207 | #define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 81208 | //BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI |
|---|
| 81209 | #define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 81210 | #define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 81211 | |
|---|
| 81212 | |
|---|
| 81213 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 |
|---|
| 81214 | //RCC_DEV0_EPF0_VF7_RCC_ERR_LOG |
|---|
| 81215 | #define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 81216 | #define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 81217 | #define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 81218 | #define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 81219 | //RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN |
|---|
| 81220 | #define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 81221 | #define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 81222 | //RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE |
|---|
| 81223 | #define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 81224 | #define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 81225 | //RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED |
|---|
| 81226 | #define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 81227 | #define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 81228 | //RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 81229 | #define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 81230 | #define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 81231 | #define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 81232 | #define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 81233 | |
|---|
| 81234 | |
|---|
| 81235 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 |
|---|
| 81236 | //BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS |
|---|
| 81237 | #define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 81238 | #define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 81239 | #define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 81240 | #define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 81241 | //BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG |
|---|
| 81242 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 81243 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 81244 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 81245 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 81246 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 81247 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 81248 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 81249 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 81250 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 81251 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 81252 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 81253 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 81254 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 81255 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 81256 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 81257 | #define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 81258 | //BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 81259 | #define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 81260 | #define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 81261 | //BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 81262 | #define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 81263 | #define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 81264 | //BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 81265 | #define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 81266 | #define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 81267 | #define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 81268 | #define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 81269 | #define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 81270 | #define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 81271 | //BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 81272 | #define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 81273 | #define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 81274 | //BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 81275 | #define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 81276 | #define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 81277 | //BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ |
|---|
| 81278 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 81279 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 81280 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 81281 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 81282 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 81283 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 81284 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 81285 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 81286 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 81287 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 81288 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 81289 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 81290 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 81291 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 81292 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 81293 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 81294 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 81295 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 81296 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 81297 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 81298 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 81299 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 81300 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 81301 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 81302 | //BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE |
|---|
| 81303 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 81304 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 81305 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 81306 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 81307 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 81308 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 81309 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 81310 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 81311 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 81312 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 81313 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 81314 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 81315 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 81316 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 81317 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 81318 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 81319 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 81320 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 81321 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 81322 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 81323 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 81324 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 81325 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 81326 | #define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 81327 | //BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING |
|---|
| 81328 | #define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 81329 | #define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 81330 | #define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 81331 | #define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 81332 | //BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 81333 | #define BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 81334 | #define BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 81335 | //BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 81336 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81337 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81338 | //BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 81339 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81340 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81341 | //BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 81342 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81343 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81344 | //BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 81345 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81346 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81347 | //BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 81348 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81349 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81350 | //BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 81351 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81352 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81353 | //BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 81354 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81355 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81356 | //BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 81357 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81358 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81359 | //BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL |
|---|
| 81360 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 81361 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 81362 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 81363 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 81364 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 81365 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 81366 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 81367 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 81368 | //BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL |
|---|
| 81369 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 81370 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 81371 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 81372 | #define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 81373 | //BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX |
|---|
| 81374 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 81375 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 81376 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 81377 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 81378 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 81379 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 81380 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 81381 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 81382 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 81383 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 81384 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 81385 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 81386 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 81387 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 81388 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 81389 | #define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 81390 | |
|---|
| 81391 | |
|---|
| 81392 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 |
|---|
| 81393 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO |
|---|
| 81394 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81395 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81396 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI |
|---|
| 81397 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81398 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81399 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA |
|---|
| 81400 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81401 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81402 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL |
|---|
| 81403 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81404 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81405 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO |
|---|
| 81406 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81407 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81408 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI |
|---|
| 81409 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81410 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81411 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA |
|---|
| 81412 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81413 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81414 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL |
|---|
| 81415 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81416 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81417 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO |
|---|
| 81418 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81419 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81420 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI |
|---|
| 81421 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81422 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81423 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA |
|---|
| 81424 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81425 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81426 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL |
|---|
| 81427 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81428 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81429 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO |
|---|
| 81430 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81431 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81432 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI |
|---|
| 81433 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81434 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81435 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA |
|---|
| 81436 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81437 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81438 | //RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL |
|---|
| 81439 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81440 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81441 | //RCC_DEV0_EPF0_VF7_GFXMSIX_PBA |
|---|
| 81442 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 81443 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 81444 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 81445 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 81446 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 81447 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 81448 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 81449 | #define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 81450 | |
|---|
| 81451 | |
|---|
| 81452 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC |
|---|
| 81453 | //BIF_BX_DEV0_EPF0_VF8_MM_INDEX |
|---|
| 81454 | #define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 81455 | #define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 81456 | #define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 81457 | #define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 81458 | //BIF_BX_DEV0_EPF0_VF8_MM_DATA |
|---|
| 81459 | #define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 81460 | #define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 81461 | //BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI |
|---|
| 81462 | #define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 81463 | #define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 81464 | |
|---|
| 81465 | |
|---|
| 81466 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 |
|---|
| 81467 | //RCC_DEV0_EPF0_VF8_RCC_ERR_LOG |
|---|
| 81468 | #define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 81469 | #define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 81470 | #define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 81471 | #define RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 81472 | //RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN |
|---|
| 81473 | #define RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 81474 | #define RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 81475 | //RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE |
|---|
| 81476 | #define RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 81477 | #define RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 81478 | //RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED |
|---|
| 81479 | #define RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 81480 | #define RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 81481 | //RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 81482 | #define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 81483 | #define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 81484 | #define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 81485 | #define RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 81486 | |
|---|
| 81487 | |
|---|
| 81488 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 |
|---|
| 81489 | //BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS |
|---|
| 81490 | #define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 81491 | #define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 81492 | #define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 81493 | #define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 81494 | //BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG |
|---|
| 81495 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 81496 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 81497 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 81498 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 81499 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 81500 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 81501 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 81502 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 81503 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 81504 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 81505 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 81506 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 81507 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 81508 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 81509 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 81510 | #define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 81511 | //BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 81512 | #define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 81513 | #define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 81514 | //BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 81515 | #define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 81516 | #define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 81517 | //BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 81518 | #define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 81519 | #define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 81520 | #define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 81521 | #define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 81522 | #define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 81523 | #define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 81524 | //BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 81525 | #define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 81526 | #define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 81527 | //BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 81528 | #define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 81529 | #define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 81530 | //BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ |
|---|
| 81531 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 81532 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 81533 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 81534 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 81535 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 81536 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 81537 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 81538 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 81539 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 81540 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 81541 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 81542 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 81543 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 81544 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 81545 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 81546 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 81547 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 81548 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 81549 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 81550 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 81551 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 81552 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 81553 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 81554 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 81555 | //BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE |
|---|
| 81556 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 81557 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 81558 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 81559 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 81560 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 81561 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 81562 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 81563 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 81564 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 81565 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 81566 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 81567 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 81568 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 81569 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 81570 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 81571 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 81572 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 81573 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 81574 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 81575 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 81576 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 81577 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 81578 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 81579 | #define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 81580 | //BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING |
|---|
| 81581 | #define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 81582 | #define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 81583 | #define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 81584 | #define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 81585 | //BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 81586 | #define BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 81587 | #define BIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 81588 | //BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 81589 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81590 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81591 | //BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 81592 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81593 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81594 | //BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 81595 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81596 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81597 | //BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 81598 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81599 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81600 | //BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 81601 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
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| 81602 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 81603 | //BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 |
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| 81604 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
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| 81605 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 81606 | //BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 |
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| 81607 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
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| 81608 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 81609 | //BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 |
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| 81610 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
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| 81611 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 81612 | //BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL |
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| 81613 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
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| 81614 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
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| 81615 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
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| 81616 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
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| 81617 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
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| 81618 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
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| 81619 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
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| 81620 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
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| 81621 | //BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL |
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| 81622 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
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| 81623 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
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| 81624 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
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| 81625 | #define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
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| 81626 | //BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX |
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| 81627 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
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| 81628 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
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| 81629 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
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| 81630 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 81631 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 81632 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
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| 81633 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 81634 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 81635 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
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| 81636 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
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| 81637 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
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| 81638 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
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| 81639 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
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| 81640 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 81641 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
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| 81642 | #define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
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| 81643 | |
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| 81644 | |
|---|
| 81645 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 |
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| 81646 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO |
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| 81647 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81648 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81649 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI |
|---|
| 81650 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
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| 81651 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 81652 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA |
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| 81653 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
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| 81654 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
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| 81655 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL |
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| 81656 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81657 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81658 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO |
|---|
| 81659 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81660 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81661 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI |
|---|
| 81662 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
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| 81663 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81664 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA |
|---|
| 81665 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
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| 81666 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81667 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL |
|---|
| 81668 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81669 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81670 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO |
|---|
| 81671 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
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| 81672 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81673 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI |
|---|
| 81674 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
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| 81675 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 81676 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA |
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| 81677 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
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| 81678 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
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| 81679 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL |
|---|
| 81680 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
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| 81681 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81682 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO |
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| 81683 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
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| 81684 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
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| 81685 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI |
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| 81686 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
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| 81687 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81688 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA |
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| 81689 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
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| 81690 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
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| 81691 | //RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL |
|---|
| 81692 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81693 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81694 | //RCC_DEV0_EPF0_VF8_GFXMSIX_PBA |
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| 81695 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 81696 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
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| 81697 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 81698 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 81699 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 81700 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 81701 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 81702 | #define RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
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| 81703 | |
|---|
| 81704 | |
|---|
| 81705 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC |
|---|
| 81706 | //BIF_BX_DEV0_EPF0_VF9_MM_INDEX |
|---|
| 81707 | #define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 81708 | #define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 81709 | #define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 81710 | #define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 81711 | //BIF_BX_DEV0_EPF0_VF9_MM_DATA |
|---|
| 81712 | #define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 81713 | #define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 81714 | //BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI |
|---|
| 81715 | #define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 81716 | #define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 81717 | |
|---|
| 81718 | |
|---|
| 81719 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 |
|---|
| 81720 | //RCC_DEV0_EPF0_VF9_RCC_ERR_LOG |
|---|
| 81721 | #define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 81722 | #define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 81723 | #define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 81724 | #define RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 81725 | //RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN |
|---|
| 81726 | #define RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 81727 | #define RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 81728 | //RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE |
|---|
| 81729 | #define RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 81730 | #define RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 81731 | //RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED |
|---|
| 81732 | #define RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 81733 | #define RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 81734 | //RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 81735 | #define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 81736 | #define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 81737 | #define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 81738 | #define RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 81739 | |
|---|
| 81740 | |
|---|
| 81741 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 |
|---|
| 81742 | //BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS |
|---|
| 81743 | #define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 81744 | #define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 81745 | #define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 81746 | #define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 81747 | //BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG |
|---|
| 81748 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 81749 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 81750 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 81751 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 81752 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 81753 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 81754 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 81755 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 81756 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 81757 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 81758 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 81759 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 81760 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 81761 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 81762 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 81763 | #define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 81764 | //BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 81765 | #define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 81766 | #define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 81767 | //BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 81768 | #define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 81769 | #define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 81770 | //BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 81771 | #define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 81772 | #define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 81773 | #define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 81774 | #define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 81775 | #define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 81776 | #define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 81777 | //BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 81778 | #define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 81779 | #define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 81780 | //BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 81781 | #define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 81782 | #define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 81783 | //BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ |
|---|
| 81784 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 81785 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 81786 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 81787 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 81788 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 81789 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 81790 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 81791 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 81792 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 81793 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 81794 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 81795 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 81796 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 81797 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 81798 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 81799 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 81800 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 81801 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 81802 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 81803 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 81804 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 81805 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 81806 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 81807 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 81808 | //BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE |
|---|
| 81809 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 81810 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 81811 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 81812 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 81813 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 81814 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 81815 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 81816 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 81817 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 81818 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 81819 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 81820 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 81821 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 81822 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 81823 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 81824 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 81825 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 81826 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 81827 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 81828 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 81829 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 81830 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 81831 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 81832 | #define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 81833 | //BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING |
|---|
| 81834 | #define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 81835 | #define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 81836 | #define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 81837 | #define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 81838 | //BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 81839 | #define BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 81840 | #define BIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 81841 | //BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 81842 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81843 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81844 | //BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 81845 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81846 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81847 | //BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 81848 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81849 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81850 | //BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 81851 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81852 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81853 | //BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 81854 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81855 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81856 | //BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 81857 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81858 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81859 | //BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 81860 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81861 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81862 | //BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 81863 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 81864 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 81865 | //BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL |
|---|
| 81866 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 81867 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 81868 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 81869 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 81870 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 81871 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 81872 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 81873 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 81874 | //BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL |
|---|
| 81875 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 81876 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 81877 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 81878 | #define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 81879 | //BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX |
|---|
| 81880 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 81881 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 81882 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 81883 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 81884 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 81885 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 81886 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 81887 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 81888 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 81889 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 81890 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 81891 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 81892 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 81893 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 81894 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 81895 | #define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 81896 | |
|---|
| 81897 | |
|---|
| 81898 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 |
|---|
| 81899 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO |
|---|
| 81900 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81901 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81902 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI |
|---|
| 81903 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81904 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81905 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA |
|---|
| 81906 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81907 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81908 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL |
|---|
| 81909 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81910 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81911 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO |
|---|
| 81912 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81913 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81914 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI |
|---|
| 81915 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81916 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81917 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA |
|---|
| 81918 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81919 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81920 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL |
|---|
| 81921 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81922 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81923 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO |
|---|
| 81924 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81925 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81926 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI |
|---|
| 81927 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81928 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81929 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA |
|---|
| 81930 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81931 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81932 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL |
|---|
| 81933 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81934 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81935 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO |
|---|
| 81936 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 81937 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 81938 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI |
|---|
| 81939 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 81940 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 81941 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA |
|---|
| 81942 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 81943 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 81944 | //RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL |
|---|
| 81945 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 81946 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 81947 | //RCC_DEV0_EPF0_VF9_GFXMSIX_PBA |
|---|
| 81948 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 81949 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 81950 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 81951 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 81952 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 81953 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 81954 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 81955 | #define RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 81956 | |
|---|
| 81957 | |
|---|
| 81958 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC |
|---|
| 81959 | //BIF_BX_DEV0_EPF0_VF10_MM_INDEX |
|---|
| 81960 | #define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 81961 | #define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 81962 | #define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 81963 | #define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 81964 | //BIF_BX_DEV0_EPF0_VF10_MM_DATA |
|---|
| 81965 | #define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 81966 | #define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 81967 | //BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI |
|---|
| 81968 | #define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 81969 | #define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 81970 | |
|---|
| 81971 | |
|---|
| 81972 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 |
|---|
| 81973 | //RCC_DEV0_EPF0_VF10_RCC_ERR_LOG |
|---|
| 81974 | #define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 81975 | #define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 81976 | #define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 81977 | #define RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 81978 | //RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN |
|---|
| 81979 | #define RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 81980 | #define RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 81981 | //RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE |
|---|
| 81982 | #define RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 81983 | #define RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 81984 | //RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED |
|---|
| 81985 | #define RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 81986 | #define RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 81987 | //RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 81988 | #define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 81989 | #define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 81990 | #define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 81991 | #define RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 81992 | |
|---|
| 81993 | |
|---|
| 81994 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 |
|---|
| 81995 | //BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS |
|---|
| 81996 | #define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 81997 | #define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 81998 | #define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 81999 | #define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 82000 | //BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG |
|---|
| 82001 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 82002 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 82003 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 82004 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 82005 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 82006 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 82007 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 82008 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 82009 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 82010 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 82011 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 82012 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 82013 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 82014 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 82015 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 82016 | #define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 82017 | //BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 82018 | #define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 82019 | #define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 82020 | //BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 82021 | #define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 82022 | #define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 82023 | //BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 82024 | #define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 82025 | #define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 82026 | #define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 82027 | #define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 82028 | #define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 82029 | #define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 82030 | //BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 82031 | #define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 82032 | #define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 82033 | //BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 82034 | #define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 82035 | #define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 82036 | //BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ |
|---|
| 82037 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 82038 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 82039 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 82040 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 82041 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 82042 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 82043 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 82044 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 82045 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 82046 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 82047 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 82048 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 82049 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 82050 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 82051 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 82052 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 82053 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 82054 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 82055 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 82056 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 82057 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 82058 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 82059 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 82060 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 82061 | //BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE |
|---|
| 82062 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 82063 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 82064 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 82065 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 82066 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 82067 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 82068 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 82069 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 82070 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 82071 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 82072 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 82073 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 82074 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 82075 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 82076 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 82077 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 82078 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 82079 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 82080 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 82081 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 82082 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 82083 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 82084 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 82085 | #define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 82086 | //BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING |
|---|
| 82087 | #define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 82088 | #define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 82089 | #define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 82090 | #define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 82091 | //BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 82092 | #define BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 82093 | #define BIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 82094 | //BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 82095 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82096 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82097 | //BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 82098 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82099 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82100 | //BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 82101 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82102 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82103 | //BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 82104 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82105 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82106 | //BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 82107 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82108 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82109 | //BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 82110 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82111 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82112 | //BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 82113 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82114 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82115 | //BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 82116 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82117 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82118 | //BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL |
|---|
| 82119 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 82120 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 82121 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 82122 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 82123 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 82124 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 82125 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 82126 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 82127 | //BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL |
|---|
| 82128 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 82129 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 82130 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 82131 | #define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 82132 | //BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX |
|---|
| 82133 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 82134 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 82135 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 82136 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 82137 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 82138 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 82139 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 82140 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 82141 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 82142 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 82143 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 82144 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 82145 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 82146 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 82147 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 82148 | #define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 82149 | |
|---|
| 82150 | |
|---|
| 82151 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 |
|---|
| 82152 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO |
|---|
| 82153 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82154 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82155 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI |
|---|
| 82156 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82157 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82158 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA |
|---|
| 82159 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82160 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82161 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL |
|---|
| 82162 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82163 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82164 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO |
|---|
| 82165 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82166 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82167 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI |
|---|
| 82168 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82169 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82170 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA |
|---|
| 82171 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82172 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82173 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL |
|---|
| 82174 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82175 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82176 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO |
|---|
| 82177 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82178 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82179 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI |
|---|
| 82180 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82181 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82182 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA |
|---|
| 82183 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82184 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82185 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL |
|---|
| 82186 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82187 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82188 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO |
|---|
| 82189 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82190 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82191 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI |
|---|
| 82192 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82193 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82194 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA |
|---|
| 82195 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82196 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82197 | //RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL |
|---|
| 82198 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82199 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82200 | //RCC_DEV0_EPF0_VF10_GFXMSIX_PBA |
|---|
| 82201 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 82202 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 82203 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 82204 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 82205 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 82206 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 82207 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 82208 | #define RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 82209 | |
|---|
| 82210 | |
|---|
| 82211 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC |
|---|
| 82212 | //BIF_BX_DEV0_EPF0_VF11_MM_INDEX |
|---|
| 82213 | #define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 82214 | #define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 82215 | #define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 82216 | #define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 82217 | //BIF_BX_DEV0_EPF0_VF11_MM_DATA |
|---|
| 82218 | #define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 82219 | #define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 82220 | //BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI |
|---|
| 82221 | #define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 82222 | #define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 82223 | |
|---|
| 82224 | |
|---|
| 82225 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 |
|---|
| 82226 | //RCC_DEV0_EPF0_VF11_RCC_ERR_LOG |
|---|
| 82227 | #define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 82228 | #define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 82229 | #define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 82230 | #define RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 82231 | //RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN |
|---|
| 82232 | #define RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 82233 | #define RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 82234 | //RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE |
|---|
| 82235 | #define RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 82236 | #define RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 82237 | //RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED |
|---|
| 82238 | #define RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 82239 | #define RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 82240 | //RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 82241 | #define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 82242 | #define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 82243 | #define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 82244 | #define RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 82245 | |
|---|
| 82246 | |
|---|
| 82247 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 |
|---|
| 82248 | //BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS |
|---|
| 82249 | #define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 82250 | #define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 82251 | #define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 82252 | #define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 82253 | //BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG |
|---|
| 82254 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 82255 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 82256 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 82257 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 82258 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 82259 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 82260 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 82261 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 82262 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 82263 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 82264 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 82265 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 82266 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 82267 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 82268 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 82269 | #define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 82270 | //BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 82271 | #define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 82272 | #define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 82273 | //BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 82274 | #define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 82275 | #define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 82276 | //BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 82277 | #define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 82278 | #define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 82279 | #define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 82280 | #define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 82281 | #define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 82282 | #define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 82283 | //BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 82284 | #define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 82285 | #define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 82286 | //BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 82287 | #define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 82288 | #define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 82289 | //BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ |
|---|
| 82290 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 82291 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 82292 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 82293 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 82294 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 82295 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 82296 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 82297 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 82298 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 82299 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 82300 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 82301 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 82302 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 82303 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 82304 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 82305 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 82306 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 82307 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 82308 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 82309 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 82310 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 82311 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 82312 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 82313 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 82314 | //BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE |
|---|
| 82315 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 82316 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 82317 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 82318 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 82319 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 82320 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 82321 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 82322 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 82323 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 82324 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 82325 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 82326 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 82327 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 82328 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 82329 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 82330 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 82331 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 82332 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 82333 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 82334 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 82335 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 82336 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 82337 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 82338 | #define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 82339 | //BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING |
|---|
| 82340 | #define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 82341 | #define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 82342 | #define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 82343 | #define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 82344 | //BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 82345 | #define BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 82346 | #define BIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 82347 | //BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 82348 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82349 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82350 | //BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 82351 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82352 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82353 | //BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 82354 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82355 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82356 | //BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 82357 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82358 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82359 | //BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 82360 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82361 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82362 | //BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 82363 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82364 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82365 | //BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 82366 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82367 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82368 | //BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 82369 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82370 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82371 | //BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL |
|---|
| 82372 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 82373 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 82374 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 82375 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 82376 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 82377 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 82378 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 82379 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 82380 | //BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL |
|---|
| 82381 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 82382 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 82383 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 82384 | #define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 82385 | //BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX |
|---|
| 82386 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 82387 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 82388 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 82389 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 82390 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 82391 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 82392 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 82393 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 82394 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 82395 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 82396 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 82397 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 82398 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 82399 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 82400 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 82401 | #define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 82402 | |
|---|
| 82403 | |
|---|
| 82404 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 |
|---|
| 82405 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO |
|---|
| 82406 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82407 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82408 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI |
|---|
| 82409 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82410 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82411 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA |
|---|
| 82412 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82413 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82414 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL |
|---|
| 82415 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82416 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82417 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO |
|---|
| 82418 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82419 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82420 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI |
|---|
| 82421 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82422 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82423 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA |
|---|
| 82424 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82425 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82426 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL |
|---|
| 82427 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82428 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82429 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO |
|---|
| 82430 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82431 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82432 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI |
|---|
| 82433 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82434 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82435 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA |
|---|
| 82436 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82437 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82438 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL |
|---|
| 82439 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82440 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82441 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO |
|---|
| 82442 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82443 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82444 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI |
|---|
| 82445 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82446 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82447 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA |
|---|
| 82448 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82449 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82450 | //RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL |
|---|
| 82451 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82452 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82453 | //RCC_DEV0_EPF0_VF11_GFXMSIX_PBA |
|---|
| 82454 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 82455 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 82456 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 82457 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 82458 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 82459 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 82460 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 82461 | #define RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 82462 | |
|---|
| 82463 | |
|---|
| 82464 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC |
|---|
| 82465 | //BIF_BX_DEV0_EPF0_VF12_MM_INDEX |
|---|
| 82466 | #define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 82467 | #define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 82468 | #define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 82469 | #define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 82470 | //BIF_BX_DEV0_EPF0_VF12_MM_DATA |
|---|
| 82471 | #define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 82472 | #define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 82473 | //BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI |
|---|
| 82474 | #define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 82475 | #define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 82476 | |
|---|
| 82477 | |
|---|
| 82478 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 |
|---|
| 82479 | //RCC_DEV0_EPF0_VF12_RCC_ERR_LOG |
|---|
| 82480 | #define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 82481 | #define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 82482 | #define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 82483 | #define RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 82484 | //RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN |
|---|
| 82485 | #define RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 82486 | #define RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 82487 | //RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE |
|---|
| 82488 | #define RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 82489 | #define RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 82490 | //RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED |
|---|
| 82491 | #define RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 82492 | #define RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 82493 | //RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 82494 | #define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 82495 | #define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 82496 | #define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 82497 | #define RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 82498 | |
|---|
| 82499 | |
|---|
| 82500 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 |
|---|
| 82501 | //BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS |
|---|
| 82502 | #define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 82503 | #define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 82504 | #define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 82505 | #define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 82506 | //BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG |
|---|
| 82507 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 82508 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 82509 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 82510 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 82511 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 82512 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 82513 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 82514 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 82515 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 82516 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 82517 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 82518 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 82519 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 82520 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 82521 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 82522 | #define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 82523 | //BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 82524 | #define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 82525 | #define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 82526 | //BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 82527 | #define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 82528 | #define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 82529 | //BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 82530 | #define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 82531 | #define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 82532 | #define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 82533 | #define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 82534 | #define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 82535 | #define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 82536 | //BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 82537 | #define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 82538 | #define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 82539 | //BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 82540 | #define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 82541 | #define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 82542 | //BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ |
|---|
| 82543 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 82544 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 82545 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 82546 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 82547 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 82548 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 82549 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 82550 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 82551 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 82552 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 82553 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 82554 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 82555 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 82556 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 82557 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 82558 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 82559 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 82560 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 82561 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 82562 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 82563 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 82564 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 82565 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 82566 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 82567 | //BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE |
|---|
| 82568 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 82569 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 82570 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 82571 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 82572 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 82573 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 82574 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 82575 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 82576 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 82577 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 82578 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 82579 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 82580 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 82581 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 82582 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 82583 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 82584 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 82585 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 82586 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 82587 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 82588 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 82589 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 82590 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 82591 | #define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 82592 | //BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING |
|---|
| 82593 | #define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 82594 | #define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 82595 | #define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 82596 | #define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 82597 | //BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 82598 | #define BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 82599 | #define BIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 82600 | //BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 82601 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82602 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82603 | //BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 82604 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82605 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82606 | //BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 82607 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82608 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82609 | //BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 82610 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82611 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82612 | //BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 82613 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82614 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82615 | //BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 82616 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
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| 82617 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 82618 | //BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 |
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| 82619 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
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| 82620 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 82621 | //BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 |
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| 82622 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
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| 82623 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
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| 82624 | //BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL |
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| 82625 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
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| 82626 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
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| 82627 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
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| 82628 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
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| 82629 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
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| 82630 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
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| 82631 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
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| 82632 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
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| 82633 | //BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL |
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| 82634 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
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| 82635 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
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| 82636 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
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| 82637 | #define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
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| 82638 | //BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX |
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| 82639 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
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| 82640 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
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| 82641 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
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| 82642 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 82643 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
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| 82644 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
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| 82645 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 82646 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
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| 82647 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 82648 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 82649 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
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| 82650 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
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| 82651 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
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| 82652 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 82653 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
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| 82654 | #define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
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| 82655 | |
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| 82656 | |
|---|
| 82657 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 |
|---|
| 82658 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO |
|---|
| 82659 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82660 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82661 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI |
|---|
| 82662 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82663 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82664 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA |
|---|
| 82665 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82666 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82667 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL |
|---|
| 82668 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82669 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82670 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO |
|---|
| 82671 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82672 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82673 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI |
|---|
| 82674 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82675 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82676 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA |
|---|
| 82677 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82678 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82679 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL |
|---|
| 82680 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82681 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82682 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO |
|---|
| 82683 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82684 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82685 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI |
|---|
| 82686 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82687 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82688 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA |
|---|
| 82689 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
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| 82690 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
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| 82691 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL |
|---|
| 82692 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82693 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82694 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO |
|---|
| 82695 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
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| 82696 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82697 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI |
|---|
| 82698 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
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| 82699 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 82700 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA |
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| 82701 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
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| 82702 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
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| 82703 | //RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL |
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| 82704 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82705 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82706 | //RCC_DEV0_EPF0_VF12_GFXMSIX_PBA |
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| 82707 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
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| 82708 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
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| 82709 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
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| 82710 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 82711 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 82712 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 82713 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 82714 | #define RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
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| 82715 | |
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| 82716 | |
|---|
| 82717 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC |
|---|
| 82718 | //BIF_BX_DEV0_EPF0_VF13_MM_INDEX |
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| 82719 | #define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 82720 | #define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 82721 | #define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 82722 | #define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 82723 | //BIF_BX_DEV0_EPF0_VF13_MM_DATA |
|---|
| 82724 | #define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 82725 | #define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 82726 | //BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI |
|---|
| 82727 | #define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 82728 | #define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
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| 82729 | |
|---|
| 82730 | |
|---|
| 82731 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 |
|---|
| 82732 | //RCC_DEV0_EPF0_VF13_RCC_ERR_LOG |
|---|
| 82733 | #define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 82734 | #define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 82735 | #define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 82736 | #define RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
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| 82737 | //RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN |
|---|
| 82738 | #define RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 82739 | #define RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 82740 | //RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE |
|---|
| 82741 | #define RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 82742 | #define RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 82743 | //RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED |
|---|
| 82744 | #define RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 82745 | #define RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 82746 | //RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 82747 | #define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 82748 | #define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 82749 | #define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 82750 | #define RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 82751 | |
|---|
| 82752 | |
|---|
| 82753 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 |
|---|
| 82754 | //BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS |
|---|
| 82755 | #define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 82756 | #define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 82757 | #define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 82758 | #define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 82759 | //BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG |
|---|
| 82760 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 82761 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 82762 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 82763 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 82764 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 82765 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 82766 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 82767 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 82768 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 82769 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 82770 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 82771 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 82772 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 82773 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 82774 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 82775 | #define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 82776 | //BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 82777 | #define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 82778 | #define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 82779 | //BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 82780 | #define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 82781 | #define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 82782 | //BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 82783 | #define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 82784 | #define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 82785 | #define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 82786 | #define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 82787 | #define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 82788 | #define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 82789 | //BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 82790 | #define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 82791 | #define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 82792 | //BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 82793 | #define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 82794 | #define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 82795 | //BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ |
|---|
| 82796 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 82797 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 82798 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 82799 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 82800 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 82801 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 82802 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 82803 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 82804 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 82805 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 82806 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 82807 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 82808 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 82809 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 82810 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 82811 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 82812 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 82813 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 82814 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 82815 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 82816 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 82817 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 82818 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 82819 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 82820 | //BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE |
|---|
| 82821 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 82822 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 82823 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 82824 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 82825 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 82826 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 82827 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 82828 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 82829 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 82830 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 82831 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 82832 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 82833 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 82834 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 82835 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 82836 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 82837 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 82838 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 82839 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 82840 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 82841 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 82842 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 82843 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 82844 | #define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 82845 | //BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING |
|---|
| 82846 | #define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 82847 | #define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 82848 | #define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 82849 | #define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 82850 | //BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 82851 | #define BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 82852 | #define BIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 82853 | //BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 82854 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82855 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82856 | //BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 82857 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82858 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82859 | //BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 82860 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82861 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82862 | //BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 82863 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82864 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82865 | //BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 82866 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82867 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82868 | //BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 82869 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82870 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82871 | //BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 82872 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82873 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82874 | //BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 82875 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 82876 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 82877 | //BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL |
|---|
| 82878 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 82879 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 82880 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 82881 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 82882 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 82883 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 82884 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 82885 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 82886 | //BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL |
|---|
| 82887 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 82888 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 82889 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 82890 | #define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 82891 | //BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX |
|---|
| 82892 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 82893 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 82894 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 82895 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 82896 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 82897 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 82898 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 82899 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 82900 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 82901 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 82902 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 82903 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 82904 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 82905 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 82906 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 82907 | #define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 82908 | |
|---|
| 82909 | |
|---|
| 82910 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 |
|---|
| 82911 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO |
|---|
| 82912 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82913 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82914 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI |
|---|
| 82915 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82916 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82917 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA |
|---|
| 82918 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82919 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82920 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL |
|---|
| 82921 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82922 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82923 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO |
|---|
| 82924 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82925 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82926 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI |
|---|
| 82927 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82928 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82929 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA |
|---|
| 82930 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82931 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82932 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL |
|---|
| 82933 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82934 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82935 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO |
|---|
| 82936 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82937 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82938 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI |
|---|
| 82939 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82940 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82941 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA |
|---|
| 82942 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82943 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82944 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL |
|---|
| 82945 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82946 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82947 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO |
|---|
| 82948 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 82949 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 82950 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI |
|---|
| 82951 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 82952 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 82953 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA |
|---|
| 82954 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 82955 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 82956 | //RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL |
|---|
| 82957 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 82958 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 82959 | //RCC_DEV0_EPF0_VF13_GFXMSIX_PBA |
|---|
| 82960 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 82961 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 82962 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 82963 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 82964 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 82965 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 82966 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 82967 | #define RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 82968 | |
|---|
| 82969 | |
|---|
| 82970 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC |
|---|
| 82971 | //BIF_BX_DEV0_EPF0_VF14_MM_INDEX |
|---|
| 82972 | #define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 82973 | #define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 82974 | #define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 82975 | #define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 82976 | //BIF_BX_DEV0_EPF0_VF14_MM_DATA |
|---|
| 82977 | #define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 82978 | #define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 82979 | //BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI |
|---|
| 82980 | #define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 82981 | #define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 82982 | |
|---|
| 82983 | |
|---|
| 82984 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 |
|---|
| 82985 | //RCC_DEV0_EPF0_VF14_RCC_ERR_LOG |
|---|
| 82986 | #define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 82987 | #define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 82988 | #define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 82989 | #define RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 82990 | //RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN |
|---|
| 82991 | #define RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 82992 | #define RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 82993 | //RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE |
|---|
| 82994 | #define RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 82995 | #define RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 82996 | //RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED |
|---|
| 82997 | #define RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 82998 | #define RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 82999 | //RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 83000 | #define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 83001 | #define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 83002 | #define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 83003 | #define RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 83004 | |
|---|
| 83005 | |
|---|
| 83006 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 |
|---|
| 83007 | //BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS |
|---|
| 83008 | #define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 83009 | #define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 83010 | #define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 83011 | #define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 83012 | //BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG |
|---|
| 83013 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 83014 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 83015 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 83016 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 83017 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 83018 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 83019 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 83020 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 83021 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 83022 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 83023 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 83024 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 83025 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 83026 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 83027 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 83028 | #define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 83029 | //BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 83030 | #define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 83031 | #define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 83032 | //BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 83033 | #define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 83034 | #define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 83035 | //BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 83036 | #define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 83037 | #define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 83038 | #define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 83039 | #define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 83040 | #define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 83041 | #define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 83042 | //BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 83043 | #define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 83044 | #define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 83045 | //BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 83046 | #define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 83047 | #define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 83048 | //BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ |
|---|
| 83049 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 83050 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 83051 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 83052 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 83053 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 83054 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 83055 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 83056 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 83057 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 83058 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 83059 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 83060 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 83061 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 83062 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 83063 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 83064 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 83065 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 83066 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 83067 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 83068 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 83069 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 83070 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 83071 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 83072 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 83073 | //BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE |
|---|
| 83074 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 83075 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 83076 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 83077 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 83078 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 83079 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 83080 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 83081 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 83082 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 83083 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 83084 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 83085 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 83086 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 83087 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 83088 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 83089 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 83090 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 83091 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 83092 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 83093 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 83094 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 83095 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 83096 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 83097 | #define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 83098 | //BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING |
|---|
| 83099 | #define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 83100 | #define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 83101 | #define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 83102 | #define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 83103 | //BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 83104 | #define BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 83105 | #define BIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 83106 | //BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 83107 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83108 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83109 | //BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 83110 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83111 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83112 | //BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 83113 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83114 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83115 | //BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 83116 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83117 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83118 | //BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 83119 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83120 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83121 | //BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 83122 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83123 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83124 | //BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 83125 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83126 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83127 | //BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 83128 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83129 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83130 | //BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL |
|---|
| 83131 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 83132 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 83133 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 83134 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 83135 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 83136 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 83137 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 83138 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 83139 | //BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL |
|---|
| 83140 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 83141 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 83142 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 83143 | #define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 83144 | //BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX |
|---|
| 83145 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 83146 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 83147 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 83148 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 83149 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 83150 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 83151 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 83152 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 83153 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 83154 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 83155 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 83156 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 83157 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 83158 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 83159 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 83160 | #define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 83161 | |
|---|
| 83162 | |
|---|
| 83163 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 |
|---|
| 83164 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO |
|---|
| 83165 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83166 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83167 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI |
|---|
| 83168 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83169 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83170 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA |
|---|
| 83171 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83172 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83173 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL |
|---|
| 83174 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83175 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83176 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO |
|---|
| 83177 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83178 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83179 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI |
|---|
| 83180 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83181 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83182 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA |
|---|
| 83183 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83184 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83185 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL |
|---|
| 83186 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83187 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83188 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO |
|---|
| 83189 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83190 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83191 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI |
|---|
| 83192 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83193 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83194 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA |
|---|
| 83195 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83196 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83197 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL |
|---|
| 83198 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83199 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83200 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO |
|---|
| 83201 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83202 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83203 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI |
|---|
| 83204 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83205 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83206 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA |
|---|
| 83207 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83208 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83209 | //RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL |
|---|
| 83210 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83211 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83212 | //RCC_DEV0_EPF0_VF14_GFXMSIX_PBA |
|---|
| 83213 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 83214 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 83215 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 83216 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 83217 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 83218 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 83219 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 83220 | #define RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 83221 | |
|---|
| 83222 | |
|---|
| 83223 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC |
|---|
| 83224 | //BIF_BX_DEV0_EPF0_VF15_MM_INDEX |
|---|
| 83225 | #define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 83226 | #define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 83227 | #define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 83228 | #define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 83229 | //BIF_BX_DEV0_EPF0_VF15_MM_DATA |
|---|
| 83230 | #define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 83231 | #define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 83232 | //BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI |
|---|
| 83233 | #define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 83234 | #define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 83235 | |
|---|
| 83236 | |
|---|
| 83237 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 |
|---|
| 83238 | //RCC_DEV0_EPF0_VF15_RCC_ERR_LOG |
|---|
| 83239 | #define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 83240 | #define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 83241 | #define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 83242 | #define RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 83243 | //RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN |
|---|
| 83244 | #define RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 83245 | #define RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 83246 | //RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE |
|---|
| 83247 | #define RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 83248 | #define RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 83249 | //RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED |
|---|
| 83250 | #define RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 83251 | #define RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 83252 | //RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 83253 | #define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 83254 | #define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 83255 | #define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 83256 | #define RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 83257 | |
|---|
| 83258 | |
|---|
| 83259 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 |
|---|
| 83260 | //BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS |
|---|
| 83261 | #define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 83262 | #define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 83263 | #define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 83264 | #define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 83265 | //BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG |
|---|
| 83266 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 83267 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 83268 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 83269 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 83270 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 83271 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 83272 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 83273 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 83274 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 83275 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 83276 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 83277 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 83278 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 83279 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 83280 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 83281 | #define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 83282 | //BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 83283 | #define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 83284 | #define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 83285 | //BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 83286 | #define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 83287 | #define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 83288 | //BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 83289 | #define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 83290 | #define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 83291 | #define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 83292 | #define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 83293 | #define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 83294 | #define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 83295 | //BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 83296 | #define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 83297 | #define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 83298 | //BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 83299 | #define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 83300 | #define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 83301 | //BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ |
|---|
| 83302 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 83303 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 83304 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 83305 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 83306 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 83307 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 83308 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 83309 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 83310 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 83311 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 83312 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 83313 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 83314 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 83315 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 83316 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 83317 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 83318 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 83319 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 83320 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 83321 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 83322 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 83323 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 83324 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 83325 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 83326 | //BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE |
|---|
| 83327 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 83328 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 83329 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 83330 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 83331 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 83332 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 83333 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 83334 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 83335 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 83336 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 83337 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 83338 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 83339 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 83340 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 83341 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 83342 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 83343 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 83344 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 83345 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 83346 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 83347 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 83348 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 83349 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 83350 | #define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 83351 | //BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING |
|---|
| 83352 | #define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 83353 | #define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 83354 | #define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 83355 | #define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 83356 | //BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 83357 | #define BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 83358 | #define BIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 83359 | //BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 83360 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83361 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83362 | //BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 83363 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83364 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83365 | //BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 83366 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83367 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83368 | //BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 83369 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83370 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83371 | //BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 83372 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83373 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83374 | //BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 83375 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83376 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83377 | //BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 83378 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83379 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83380 | //BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 83381 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83382 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83383 | //BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL |
|---|
| 83384 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 83385 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 83386 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 83387 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 83388 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 83389 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 83390 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 83391 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 83392 | //BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL |
|---|
| 83393 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 83394 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 83395 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 83396 | #define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 83397 | //BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX |
|---|
| 83398 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 83399 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 83400 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 83401 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 83402 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 83403 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 83404 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 83405 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 83406 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 83407 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 83408 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 83409 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 83410 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 83411 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 83412 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 83413 | #define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 83414 | |
|---|
| 83415 | |
|---|
| 83416 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 |
|---|
| 83417 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO |
|---|
| 83418 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83419 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83420 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI |
|---|
| 83421 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83422 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83423 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA |
|---|
| 83424 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83425 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83426 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL |
|---|
| 83427 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83428 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83429 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO |
|---|
| 83430 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83431 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83432 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI |
|---|
| 83433 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83434 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83435 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA |
|---|
| 83436 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83437 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83438 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL |
|---|
| 83439 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83440 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83441 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO |
|---|
| 83442 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83443 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83444 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI |
|---|
| 83445 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83446 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83447 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA |
|---|
| 83448 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83449 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83450 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL |
|---|
| 83451 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83452 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83453 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO |
|---|
| 83454 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83455 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83456 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI |
|---|
| 83457 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83458 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83459 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA |
|---|
| 83460 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83461 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83462 | //RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL |
|---|
| 83463 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83464 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83465 | //RCC_DEV0_EPF0_VF15_GFXMSIX_PBA |
|---|
| 83466 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 83467 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 83468 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 83469 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 83470 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 83471 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 83472 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 83473 | #define RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 83474 | |
|---|
| 83475 | |
|---|
| 83476 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC |
|---|
| 83477 | //BIF_BX_DEV0_EPF0_VF16_MM_INDEX |
|---|
| 83478 | #define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 83479 | #define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 83480 | #define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 83481 | #define BIF_BX_DEV0_EPF0_VF16_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 83482 | //BIF_BX_DEV0_EPF0_VF16_MM_DATA |
|---|
| 83483 | #define BIF_BX_DEV0_EPF0_VF16_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 83484 | #define BIF_BX_DEV0_EPF0_VF16_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 83485 | //BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI |
|---|
| 83486 | #define BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 83487 | #define BIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 83488 | |
|---|
| 83489 | |
|---|
| 83490 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1 |
|---|
| 83491 | //RCC_DEV0_EPF0_VF16_RCC_ERR_LOG |
|---|
| 83492 | #define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 83493 | #define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 83494 | #define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 83495 | #define RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 83496 | //RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN |
|---|
| 83497 | #define RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 83498 | #define RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 83499 | //RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE |
|---|
| 83500 | #define RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 83501 | #define RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 83502 | //RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED |
|---|
| 83503 | #define RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 83504 | #define RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 83505 | //RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 83506 | #define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 83507 | #define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 83508 | #define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 83509 | #define RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 83510 | |
|---|
| 83511 | |
|---|
| 83512 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1 |
|---|
| 83513 | //BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS |
|---|
| 83514 | #define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 83515 | #define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 83516 | #define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 83517 | #define BIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 83518 | //BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG |
|---|
| 83519 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 83520 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 83521 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 83522 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 83523 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 83524 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 83525 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 83526 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 83527 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 83528 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 83529 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 83530 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 83531 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 83532 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 83533 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 83534 | #define BIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 83535 | //BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 83536 | #define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 83537 | #define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 83538 | //BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 83539 | #define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 83540 | #define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 83541 | //BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 83542 | #define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 83543 | #define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 83544 | #define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 83545 | #define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 83546 | #define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 83547 | #define BIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 83548 | //BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 83549 | #define BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 83550 | #define BIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 83551 | //BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 83552 | #define BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 83553 | #define BIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 83554 | //BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ |
|---|
| 83555 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 83556 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 83557 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 83558 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 83559 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 83560 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 83561 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 83562 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 83563 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 83564 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 83565 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 83566 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 83567 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 83568 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 83569 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 83570 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 83571 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 83572 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 83573 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 83574 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 83575 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 83576 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 83577 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 83578 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 83579 | //BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE |
|---|
| 83580 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 83581 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 83582 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 83583 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 83584 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 83585 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 83586 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 83587 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 83588 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 83589 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 83590 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 83591 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 83592 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 83593 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 83594 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 83595 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 83596 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 83597 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 83598 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 83599 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 83600 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 83601 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 83602 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 83603 | #define BIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 83604 | //BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING |
|---|
| 83605 | #define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 83606 | #define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 83607 | #define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 83608 | #define BIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 83609 | //BIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 83610 | #define BIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 83611 | #define BIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 83612 | //BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 83613 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83614 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83615 | //BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 83616 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83617 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83618 | //BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 83619 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83620 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83621 | //BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 83622 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83623 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83624 | //BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 83625 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83626 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83627 | //BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 83628 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83629 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83630 | //BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 83631 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83632 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83633 | //BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 83634 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83635 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83636 | //BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL |
|---|
| 83637 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 83638 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 83639 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 83640 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 83641 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 83642 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 83643 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 83644 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 83645 | //BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL |
|---|
| 83646 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 83647 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 83648 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 83649 | #define BIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 83650 | //BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX |
|---|
| 83651 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 83652 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 83653 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 83654 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 83655 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 83656 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 83657 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 83658 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 83659 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 83660 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 83661 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 83662 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 83663 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 83664 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 83665 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 83666 | #define BIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 83667 | |
|---|
| 83668 | |
|---|
| 83669 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2 |
|---|
| 83670 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO |
|---|
| 83671 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83672 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83673 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI |
|---|
| 83674 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83675 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83676 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA |
|---|
| 83677 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83678 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83679 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL |
|---|
| 83680 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83681 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83682 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO |
|---|
| 83683 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83684 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83685 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI |
|---|
| 83686 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83687 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83688 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA |
|---|
| 83689 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83690 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83691 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL |
|---|
| 83692 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83693 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83694 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO |
|---|
| 83695 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83696 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83697 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI |
|---|
| 83698 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83699 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83700 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA |
|---|
| 83701 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83702 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83703 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL |
|---|
| 83704 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83705 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83706 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO |
|---|
| 83707 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83708 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83709 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI |
|---|
| 83710 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83711 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83712 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA |
|---|
| 83713 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83714 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83715 | //RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL |
|---|
| 83716 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83717 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83718 | //RCC_DEV0_EPF0_VF16_GFXMSIX_PBA |
|---|
| 83719 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 83720 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 83721 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 83722 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 83723 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 83724 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 83725 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 83726 | #define RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 83727 | |
|---|
| 83728 | |
|---|
| 83729 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC |
|---|
| 83730 | //BIF_BX_DEV0_EPF0_VF17_MM_INDEX |
|---|
| 83731 | #define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 83732 | #define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 83733 | #define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 83734 | #define BIF_BX_DEV0_EPF0_VF17_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 83735 | //BIF_BX_DEV0_EPF0_VF17_MM_DATA |
|---|
| 83736 | #define BIF_BX_DEV0_EPF0_VF17_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 83737 | #define BIF_BX_DEV0_EPF0_VF17_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 83738 | //BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI |
|---|
| 83739 | #define BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 83740 | #define BIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 83741 | |
|---|
| 83742 | |
|---|
| 83743 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1 |
|---|
| 83744 | //RCC_DEV0_EPF0_VF17_RCC_ERR_LOG |
|---|
| 83745 | #define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 83746 | #define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 83747 | #define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 83748 | #define RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 83749 | //RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN |
|---|
| 83750 | #define RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 83751 | #define RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 83752 | //RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE |
|---|
| 83753 | #define RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 83754 | #define RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 83755 | //RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED |
|---|
| 83756 | #define RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 83757 | #define RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 83758 | //RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 83759 | #define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 83760 | #define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 83761 | #define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 83762 | #define RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 83763 | |
|---|
| 83764 | |
|---|
| 83765 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1 |
|---|
| 83766 | //BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS |
|---|
| 83767 | #define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 83768 | #define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 83769 | #define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 83770 | #define BIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 83771 | //BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG |
|---|
| 83772 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 83773 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 83774 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 83775 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 83776 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 83777 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 83778 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 83779 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 83780 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 83781 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 83782 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 83783 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 83784 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 83785 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 83786 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 83787 | #define BIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 83788 | //BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 83789 | #define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 83790 | #define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 83791 | //BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 83792 | #define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 83793 | #define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 83794 | //BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 83795 | #define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 83796 | #define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 83797 | #define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 83798 | #define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 83799 | #define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 83800 | #define BIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 83801 | //BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 83802 | #define BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 83803 | #define BIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 83804 | //BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 83805 | #define BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 83806 | #define BIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 83807 | //BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ |
|---|
| 83808 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 83809 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 83810 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 83811 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 83812 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 83813 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 83814 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 83815 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 83816 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 83817 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 83818 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 83819 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 83820 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 83821 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 83822 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 83823 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 83824 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 83825 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 83826 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 83827 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 83828 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 83829 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 83830 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 83831 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 83832 | //BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE |
|---|
| 83833 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 83834 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 83835 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 83836 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 83837 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 83838 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 83839 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 83840 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 83841 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 83842 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 83843 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 83844 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 83845 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 83846 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 83847 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 83848 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 83849 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 83850 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 83851 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 83852 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 83853 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 83854 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 83855 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 83856 | #define BIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 83857 | //BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING |
|---|
| 83858 | #define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 83859 | #define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 83860 | #define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 83861 | #define BIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 83862 | //BIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 83863 | #define BIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 83864 | #define BIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 83865 | //BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 83866 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83867 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83868 | //BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 83869 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83870 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83871 | //BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 83872 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83873 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83874 | //BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 83875 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83876 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83877 | //BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 83878 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83879 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83880 | //BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 83881 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83882 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83883 | //BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 83884 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83885 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83886 | //BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 83887 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 83888 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 83889 | //BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL |
|---|
| 83890 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 83891 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 83892 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 83893 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 83894 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 83895 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 83896 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 83897 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 83898 | //BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL |
|---|
| 83899 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 83900 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 83901 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 83902 | #define BIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 83903 | //BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX |
|---|
| 83904 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 83905 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 83906 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 83907 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 83908 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 83909 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 83910 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 83911 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 83912 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 83913 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 83914 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 83915 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 83916 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 83917 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 83918 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 83919 | #define BIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 83920 | |
|---|
| 83921 | |
|---|
| 83922 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2 |
|---|
| 83923 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO |
|---|
| 83924 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83925 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83926 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI |
|---|
| 83927 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83928 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83929 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA |
|---|
| 83930 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83931 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83932 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL |
|---|
| 83933 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83934 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83935 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO |
|---|
| 83936 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83937 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83938 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI |
|---|
| 83939 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83940 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83941 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA |
|---|
| 83942 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83943 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83944 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL |
|---|
| 83945 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83946 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83947 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO |
|---|
| 83948 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83949 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83950 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI |
|---|
| 83951 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83952 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83953 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA |
|---|
| 83954 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83955 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83956 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL |
|---|
| 83957 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83958 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83959 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO |
|---|
| 83960 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 83961 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 83962 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI |
|---|
| 83963 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 83964 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 83965 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA |
|---|
| 83966 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 83967 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 83968 | //RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL |
|---|
| 83969 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 83970 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 83971 | //RCC_DEV0_EPF0_VF17_GFXMSIX_PBA |
|---|
| 83972 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 83973 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 83974 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 83975 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 83976 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 83977 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 83978 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 83979 | #define RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 83980 | |
|---|
| 83981 | |
|---|
| 83982 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC |
|---|
| 83983 | //BIF_BX_DEV0_EPF0_VF18_MM_INDEX |
|---|
| 83984 | #define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 83985 | #define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 83986 | #define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 83987 | #define BIF_BX_DEV0_EPF0_VF18_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 83988 | //BIF_BX_DEV0_EPF0_VF18_MM_DATA |
|---|
| 83989 | #define BIF_BX_DEV0_EPF0_VF18_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 83990 | #define BIF_BX_DEV0_EPF0_VF18_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 83991 | //BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI |
|---|
| 83992 | #define BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 83993 | #define BIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 83994 | |
|---|
| 83995 | |
|---|
| 83996 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1 |
|---|
| 83997 | //RCC_DEV0_EPF0_VF18_RCC_ERR_LOG |
|---|
| 83998 | #define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 83999 | #define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 84000 | #define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 84001 | #define RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 84002 | //RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN |
|---|
| 84003 | #define RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 84004 | #define RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 84005 | //RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE |
|---|
| 84006 | #define RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 84007 | #define RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 84008 | //RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED |
|---|
| 84009 | #define RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 84010 | #define RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 84011 | //RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 84012 | #define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 84013 | #define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 84014 | #define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 84015 | #define RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 84016 | |
|---|
| 84017 | |
|---|
| 84018 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1 |
|---|
| 84019 | //BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS |
|---|
| 84020 | #define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 84021 | #define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 84022 | #define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 84023 | #define BIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 84024 | //BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG |
|---|
| 84025 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 84026 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 84027 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 84028 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 84029 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 84030 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 84031 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 84032 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 84033 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 84034 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 84035 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 84036 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 84037 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 84038 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 84039 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 84040 | #define BIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 84041 | //BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 84042 | #define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 84043 | #define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 84044 | //BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 84045 | #define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 84046 | #define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 84047 | //BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 84048 | #define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 84049 | #define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 84050 | #define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 84051 | #define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 84052 | #define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 84053 | #define BIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 84054 | //BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 84055 | #define BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 84056 | #define BIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 84057 | //BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 84058 | #define BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 84059 | #define BIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 84060 | //BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ |
|---|
| 84061 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 84062 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 84063 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 84064 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 84065 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 84066 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 84067 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 84068 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 84069 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 84070 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 84071 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 84072 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 84073 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 84074 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 84075 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 84076 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 84077 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 84078 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 84079 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 84080 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 84081 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 84082 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 84083 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 84084 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 84085 | //BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE |
|---|
| 84086 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 84087 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 84088 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 84089 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 84090 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 84091 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 84092 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 84093 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 84094 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 84095 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 84096 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 84097 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 84098 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 84099 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 84100 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 84101 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 84102 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 84103 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 84104 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 84105 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 84106 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 84107 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 84108 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 84109 | #define BIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 84110 | //BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING |
|---|
| 84111 | #define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 84112 | #define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 84113 | #define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 84114 | #define BIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 84115 | //BIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 84116 | #define BIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 84117 | #define BIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 84118 | //BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 84119 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84120 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84121 | //BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 84122 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84123 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84124 | //BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 84125 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84126 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84127 | //BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 84128 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84129 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84130 | //BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 84131 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84132 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84133 | //BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 84134 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84135 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84136 | //BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 84137 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84138 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84139 | //BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 84140 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84141 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84142 | //BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL |
|---|
| 84143 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 84144 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 84145 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 84146 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 84147 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 84148 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 84149 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 84150 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 84151 | //BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL |
|---|
| 84152 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 84153 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 84154 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 84155 | #define BIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 84156 | //BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX |
|---|
| 84157 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 84158 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 84159 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 84160 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 84161 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 84162 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 84163 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 84164 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 84165 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 84166 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 84167 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 84168 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 84169 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 84170 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 84171 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 84172 | #define BIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 84173 | |
|---|
| 84174 | |
|---|
| 84175 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2 |
|---|
| 84176 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO |
|---|
| 84177 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84178 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84179 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI |
|---|
| 84180 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84181 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84182 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA |
|---|
| 84183 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84184 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84185 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL |
|---|
| 84186 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84187 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84188 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO |
|---|
| 84189 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84190 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84191 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI |
|---|
| 84192 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84193 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84194 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA |
|---|
| 84195 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84196 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84197 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL |
|---|
| 84198 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84199 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84200 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO |
|---|
| 84201 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84202 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84203 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI |
|---|
| 84204 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84205 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84206 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA |
|---|
| 84207 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84208 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84209 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL |
|---|
| 84210 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84211 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84212 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO |
|---|
| 84213 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84214 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84215 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI |
|---|
| 84216 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84217 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84218 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA |
|---|
| 84219 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84220 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84221 | //RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL |
|---|
| 84222 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84223 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84224 | //RCC_DEV0_EPF0_VF18_GFXMSIX_PBA |
|---|
| 84225 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 84226 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 84227 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 84228 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 84229 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 84230 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 84231 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 84232 | #define RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 84233 | |
|---|
| 84234 | |
|---|
| 84235 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC |
|---|
| 84236 | //BIF_BX_DEV0_EPF0_VF19_MM_INDEX |
|---|
| 84237 | #define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 84238 | #define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 84239 | #define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 84240 | #define BIF_BX_DEV0_EPF0_VF19_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 84241 | //BIF_BX_DEV0_EPF0_VF19_MM_DATA |
|---|
| 84242 | #define BIF_BX_DEV0_EPF0_VF19_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 84243 | #define BIF_BX_DEV0_EPF0_VF19_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 84244 | //BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI |
|---|
| 84245 | #define BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 84246 | #define BIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 84247 | |
|---|
| 84248 | |
|---|
| 84249 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1 |
|---|
| 84250 | //RCC_DEV0_EPF0_VF19_RCC_ERR_LOG |
|---|
| 84251 | #define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 84252 | #define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 84253 | #define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 84254 | #define RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 84255 | //RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN |
|---|
| 84256 | #define RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 84257 | #define RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 84258 | //RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE |
|---|
| 84259 | #define RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 84260 | #define RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 84261 | //RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED |
|---|
| 84262 | #define RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 84263 | #define RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 84264 | //RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 84265 | #define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 84266 | #define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 84267 | #define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 84268 | #define RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 84269 | |
|---|
| 84270 | |
|---|
| 84271 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1 |
|---|
| 84272 | //BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS |
|---|
| 84273 | #define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 84274 | #define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 84275 | #define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 84276 | #define BIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 84277 | //BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG |
|---|
| 84278 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 84279 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 84280 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 84281 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 84282 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 84283 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 84284 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 84285 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 84286 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 84287 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 84288 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 84289 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 84290 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 84291 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 84292 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 84293 | #define BIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 84294 | //BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 84295 | #define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 84296 | #define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 84297 | //BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 84298 | #define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 84299 | #define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 84300 | //BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 84301 | #define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 84302 | #define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 84303 | #define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 84304 | #define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 84305 | #define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 84306 | #define BIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 84307 | //BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 84308 | #define BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 84309 | #define BIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 84310 | //BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 84311 | #define BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 84312 | #define BIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 84313 | //BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ |
|---|
| 84314 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 84315 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 84316 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 84317 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 84318 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 84319 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 84320 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 84321 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 84322 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 84323 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 84324 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 84325 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 84326 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 84327 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 84328 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 84329 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 84330 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 84331 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 84332 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 84333 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 84334 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 84335 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 84336 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 84337 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 84338 | //BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE |
|---|
| 84339 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 84340 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 84341 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 84342 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 84343 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 84344 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 84345 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 84346 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 84347 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 84348 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 84349 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 84350 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 84351 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 84352 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 84353 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 84354 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 84355 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 84356 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 84357 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 84358 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 84359 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 84360 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 84361 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 84362 | #define BIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 84363 | //BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING |
|---|
| 84364 | #define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 84365 | #define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 84366 | #define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 84367 | #define BIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 84368 | //BIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 84369 | #define BIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 84370 | #define BIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 84371 | //BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 84372 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84373 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84374 | //BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 84375 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84376 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84377 | //BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 84378 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84379 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84380 | //BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 84381 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84382 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84383 | //BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 84384 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84385 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84386 | //BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 84387 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84388 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84389 | //BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 84390 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84391 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84392 | //BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 84393 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84394 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84395 | //BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL |
|---|
| 84396 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 84397 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 84398 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 84399 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 84400 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 84401 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 84402 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 84403 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 84404 | //BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL |
|---|
| 84405 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 84406 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 84407 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 84408 | #define BIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 84409 | //BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX |
|---|
| 84410 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 84411 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 84412 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 84413 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 84414 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 84415 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 84416 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 84417 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 84418 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 84419 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 84420 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 84421 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 84422 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 84423 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 84424 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 84425 | #define BIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 84426 | |
|---|
| 84427 | |
|---|
| 84428 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2 |
|---|
| 84429 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO |
|---|
| 84430 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84431 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84432 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI |
|---|
| 84433 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84434 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84435 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA |
|---|
| 84436 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84437 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84438 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL |
|---|
| 84439 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84440 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84441 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO |
|---|
| 84442 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84443 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84444 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI |
|---|
| 84445 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84446 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84447 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA |
|---|
| 84448 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84449 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84450 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL |
|---|
| 84451 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84452 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84453 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO |
|---|
| 84454 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84455 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84456 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI |
|---|
| 84457 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84458 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84459 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA |
|---|
| 84460 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84461 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84462 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL |
|---|
| 84463 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84464 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84465 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO |
|---|
| 84466 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84467 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84468 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI |
|---|
| 84469 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84470 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84471 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA |
|---|
| 84472 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84473 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84474 | //RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL |
|---|
| 84475 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84476 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84477 | //RCC_DEV0_EPF0_VF19_GFXMSIX_PBA |
|---|
| 84478 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 84479 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 84480 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 84481 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 84482 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 84483 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 84484 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 84485 | #define RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 84486 | |
|---|
| 84487 | |
|---|
| 84488 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC |
|---|
| 84489 | //BIF_BX_DEV0_EPF0_VF20_MM_INDEX |
|---|
| 84490 | #define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 84491 | #define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 84492 | #define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 84493 | #define BIF_BX_DEV0_EPF0_VF20_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 84494 | //BIF_BX_DEV0_EPF0_VF20_MM_DATA |
|---|
| 84495 | #define BIF_BX_DEV0_EPF0_VF20_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 84496 | #define BIF_BX_DEV0_EPF0_VF20_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 84497 | //BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI |
|---|
| 84498 | #define BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 84499 | #define BIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 84500 | |
|---|
| 84501 | |
|---|
| 84502 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1 |
|---|
| 84503 | //RCC_DEV0_EPF0_VF20_RCC_ERR_LOG |
|---|
| 84504 | #define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 84505 | #define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 84506 | #define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 84507 | #define RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 84508 | //RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN |
|---|
| 84509 | #define RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 84510 | #define RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 84511 | //RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE |
|---|
| 84512 | #define RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 84513 | #define RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 84514 | //RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED |
|---|
| 84515 | #define RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 84516 | #define RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 84517 | //RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 84518 | #define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 84519 | #define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 84520 | #define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 84521 | #define RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 84522 | |
|---|
| 84523 | |
|---|
| 84524 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1 |
|---|
| 84525 | //BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS |
|---|
| 84526 | #define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 84527 | #define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 84528 | #define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 84529 | #define BIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 84530 | //BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG |
|---|
| 84531 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 84532 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 84533 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 84534 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 84535 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 84536 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 84537 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 84538 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 84539 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 84540 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 84541 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 84542 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 84543 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 84544 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 84545 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 84546 | #define BIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 84547 | //BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 84548 | #define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 84549 | #define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 84550 | //BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 84551 | #define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 84552 | #define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 84553 | //BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 84554 | #define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 84555 | #define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 84556 | #define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 84557 | #define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 84558 | #define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 84559 | #define BIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 84560 | //BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 84561 | #define BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 84562 | #define BIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 84563 | //BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 84564 | #define BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 84565 | #define BIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 84566 | //BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ |
|---|
| 84567 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 84568 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 84569 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 84570 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 84571 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 84572 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 84573 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 84574 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 84575 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 84576 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 84577 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 84578 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 84579 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 84580 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 84581 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 84582 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 84583 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 84584 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 84585 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 84586 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 84587 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 84588 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 84589 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 84590 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 84591 | //BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE |
|---|
| 84592 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 84593 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 84594 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 84595 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 84596 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 84597 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 84598 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 84599 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 84600 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 84601 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 84602 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 84603 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 84604 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 84605 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 84606 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 84607 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 84608 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 84609 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 84610 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 84611 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 84612 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 84613 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 84614 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 84615 | #define BIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 84616 | //BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING |
|---|
| 84617 | #define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 84618 | #define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 84619 | #define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 84620 | #define BIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 84621 | //BIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 84622 | #define BIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 84623 | #define BIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 84624 | //BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 84625 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84626 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84627 | //BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 84628 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84629 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84630 | //BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 84631 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84632 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84633 | //BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 84634 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84635 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84636 | //BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 84637 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84638 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84639 | //BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 84640 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84641 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84642 | //BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 84643 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84644 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84645 | //BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 84646 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84647 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84648 | //BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL |
|---|
| 84649 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 84650 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 84651 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 84652 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 84653 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 84654 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 84655 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 84656 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 84657 | //BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL |
|---|
| 84658 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 84659 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 84660 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 84661 | #define BIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 84662 | //BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX |
|---|
| 84663 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 84664 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 84665 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 84666 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 84667 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 84668 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 84669 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 84670 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 84671 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 84672 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 84673 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 84674 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 84675 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 84676 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 84677 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 84678 | #define BIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 84679 | |
|---|
| 84680 | |
|---|
| 84681 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2 |
|---|
| 84682 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO |
|---|
| 84683 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84684 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84685 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI |
|---|
| 84686 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84687 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84688 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA |
|---|
| 84689 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84690 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84691 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL |
|---|
| 84692 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84693 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84694 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO |
|---|
| 84695 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84696 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84697 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI |
|---|
| 84698 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84699 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84700 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA |
|---|
| 84701 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84702 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84703 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL |
|---|
| 84704 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84705 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84706 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO |
|---|
| 84707 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84708 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84709 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI |
|---|
| 84710 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84711 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84712 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA |
|---|
| 84713 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84714 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84715 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL |
|---|
| 84716 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84717 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84718 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO |
|---|
| 84719 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84720 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84721 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI |
|---|
| 84722 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84723 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84724 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA |
|---|
| 84725 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84726 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84727 | //RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL |
|---|
| 84728 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84729 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84730 | //RCC_DEV0_EPF0_VF20_GFXMSIX_PBA |
|---|
| 84731 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 84732 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 84733 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 84734 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 84735 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 84736 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 84737 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 84738 | #define RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 84739 | |
|---|
| 84740 | |
|---|
| 84741 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC |
|---|
| 84742 | //BIF_BX_DEV0_EPF0_VF21_MM_INDEX |
|---|
| 84743 | #define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 84744 | #define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 84745 | #define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 84746 | #define BIF_BX_DEV0_EPF0_VF21_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 84747 | //BIF_BX_DEV0_EPF0_VF21_MM_DATA |
|---|
| 84748 | #define BIF_BX_DEV0_EPF0_VF21_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 84749 | #define BIF_BX_DEV0_EPF0_VF21_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 84750 | //BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI |
|---|
| 84751 | #define BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 84752 | #define BIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 84753 | |
|---|
| 84754 | |
|---|
| 84755 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1 |
|---|
| 84756 | //RCC_DEV0_EPF0_VF21_RCC_ERR_LOG |
|---|
| 84757 | #define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 84758 | #define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 84759 | #define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 84760 | #define RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 84761 | //RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN |
|---|
| 84762 | #define RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 84763 | #define RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 84764 | //RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE |
|---|
| 84765 | #define RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 84766 | #define RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 84767 | //RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED |
|---|
| 84768 | #define RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 84769 | #define RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 84770 | //RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 84771 | #define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 84772 | #define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 84773 | #define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 84774 | #define RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 84775 | |
|---|
| 84776 | |
|---|
| 84777 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1 |
|---|
| 84778 | //BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS |
|---|
| 84779 | #define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 84780 | #define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 84781 | #define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 84782 | #define BIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 84783 | //BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG |
|---|
| 84784 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 84785 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 84786 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 84787 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 84788 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 84789 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 84790 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 84791 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 84792 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 84793 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 84794 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 84795 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 84796 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 84797 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 84798 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 84799 | #define BIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 84800 | //BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 84801 | #define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 84802 | #define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 84803 | //BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 84804 | #define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 84805 | #define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 84806 | //BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 84807 | #define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 84808 | #define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 84809 | #define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 84810 | #define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 84811 | #define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 84812 | #define BIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 84813 | //BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 84814 | #define BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 84815 | #define BIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 84816 | //BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 84817 | #define BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 84818 | #define BIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 84819 | //BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ |
|---|
| 84820 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 84821 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 84822 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 84823 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 84824 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 84825 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 84826 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 84827 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 84828 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 84829 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 84830 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 84831 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 84832 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 84833 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 84834 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 84835 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 84836 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 84837 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 84838 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 84839 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 84840 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 84841 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 84842 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 84843 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 84844 | //BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE |
|---|
| 84845 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 84846 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 84847 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 84848 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 84849 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 84850 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 84851 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 84852 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 84853 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 84854 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 84855 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 84856 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 84857 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 84858 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 84859 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 84860 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 84861 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 84862 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 84863 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 84864 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 84865 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 84866 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 84867 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 84868 | #define BIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 84869 | //BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING |
|---|
| 84870 | #define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 84871 | #define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 84872 | #define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 84873 | #define BIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 84874 | //BIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 84875 | #define BIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 84876 | #define BIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 84877 | //BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 84878 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84879 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84880 | //BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 84881 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84882 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84883 | //BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 84884 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84885 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84886 | //BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 84887 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84888 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84889 | //BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 84890 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84891 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84892 | //BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 84893 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84894 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84895 | //BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 84896 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84897 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84898 | //BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 84899 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 84900 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 84901 | //BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL |
|---|
| 84902 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 84903 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 84904 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 84905 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 84906 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 84907 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 84908 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 84909 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 84910 | //BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL |
|---|
| 84911 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 84912 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 84913 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 84914 | #define BIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 84915 | //BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX |
|---|
| 84916 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 84917 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 84918 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 84919 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 84920 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 84921 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 84922 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 84923 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 84924 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 84925 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 84926 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 84927 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 84928 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 84929 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 84930 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 84931 | #define BIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 84932 | |
|---|
| 84933 | |
|---|
| 84934 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2 |
|---|
| 84935 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO |
|---|
| 84936 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84937 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84938 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI |
|---|
| 84939 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84940 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84941 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA |
|---|
| 84942 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84943 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84944 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL |
|---|
| 84945 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84946 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84947 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO |
|---|
| 84948 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84949 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84950 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI |
|---|
| 84951 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84952 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84953 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA |
|---|
| 84954 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84955 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84956 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL |
|---|
| 84957 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84958 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84959 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO |
|---|
| 84960 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84961 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84962 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI |
|---|
| 84963 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84964 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84965 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA |
|---|
| 84966 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84967 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84968 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL |
|---|
| 84969 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84970 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84971 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO |
|---|
| 84972 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 84973 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 84974 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI |
|---|
| 84975 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 84976 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 84977 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA |
|---|
| 84978 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 84979 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 84980 | //RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL |
|---|
| 84981 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 84982 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 84983 | //RCC_DEV0_EPF0_VF21_GFXMSIX_PBA |
|---|
| 84984 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 84985 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 84986 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 84987 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 84988 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 84989 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 84990 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 84991 | #define RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 84992 | |
|---|
| 84993 | |
|---|
| 84994 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC |
|---|
| 84995 | //BIF_BX_DEV0_EPF0_VF22_MM_INDEX |
|---|
| 84996 | #define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 84997 | #define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 84998 | #define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 84999 | #define BIF_BX_DEV0_EPF0_VF22_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 85000 | //BIF_BX_DEV0_EPF0_VF22_MM_DATA |
|---|
| 85001 | #define BIF_BX_DEV0_EPF0_VF22_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 85002 | #define BIF_BX_DEV0_EPF0_VF22_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 85003 | //BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI |
|---|
| 85004 | #define BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 85005 | #define BIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 85006 | |
|---|
| 85007 | |
|---|
| 85008 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1 |
|---|
| 85009 | //RCC_DEV0_EPF0_VF22_RCC_ERR_LOG |
|---|
| 85010 | #define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 85011 | #define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 85012 | #define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 85013 | #define RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 85014 | //RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN |
|---|
| 85015 | #define RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 85016 | #define RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 85017 | //RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE |
|---|
| 85018 | #define RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 85019 | #define RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 85020 | //RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED |
|---|
| 85021 | #define RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 85022 | #define RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 85023 | //RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 85024 | #define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 85025 | #define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 85026 | #define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 85027 | #define RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 85028 | |
|---|
| 85029 | |
|---|
| 85030 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1 |
|---|
| 85031 | //BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS |
|---|
| 85032 | #define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 85033 | #define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 85034 | #define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 85035 | #define BIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 85036 | //BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG |
|---|
| 85037 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 85038 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 85039 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 85040 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 85041 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 85042 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 85043 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 85044 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 85045 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 85046 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 85047 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 85048 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 85049 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 85050 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 85051 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 85052 | #define BIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 85053 | //BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 85054 | #define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 85055 | #define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 85056 | //BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 85057 | #define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 85058 | #define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 85059 | //BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 85060 | #define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 85061 | #define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 85062 | #define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 85063 | #define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 85064 | #define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 85065 | #define BIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 85066 | //BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 85067 | #define BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 85068 | #define BIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 85069 | //BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 85070 | #define BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 85071 | #define BIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 85072 | //BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ |
|---|
| 85073 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 85074 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 85075 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 85076 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 85077 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 85078 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 85079 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 85080 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 85081 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 85082 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 85083 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 85084 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 85085 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 85086 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 85087 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 85088 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 85089 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 85090 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 85091 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 85092 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 85093 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 85094 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 85095 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 85096 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 85097 | //BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE |
|---|
| 85098 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 85099 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 85100 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 85101 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 85102 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 85103 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 85104 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 85105 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 85106 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 85107 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 85108 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 85109 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 85110 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 85111 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 85112 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 85113 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 85114 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 85115 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 85116 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 85117 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 85118 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 85119 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 85120 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 85121 | #define BIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 85122 | //BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING |
|---|
| 85123 | #define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 85124 | #define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 85125 | #define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 85126 | #define BIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 85127 | //BIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 85128 | #define BIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 85129 | #define BIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 85130 | //BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 85131 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85132 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85133 | //BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 85134 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85135 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85136 | //BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 85137 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85138 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85139 | //BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 85140 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85141 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85142 | //BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 85143 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85144 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85145 | //BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 85146 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85147 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85148 | //BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 85149 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85150 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85151 | //BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 85152 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85153 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85154 | //BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL |
|---|
| 85155 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 85156 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 85157 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 85158 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 85159 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 85160 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 85161 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 85162 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 85163 | //BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL |
|---|
| 85164 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 85165 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 85166 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 85167 | #define BIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 85168 | //BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX |
|---|
| 85169 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 85170 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 85171 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 85172 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 85173 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 85174 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 85175 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 85176 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 85177 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 85178 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 85179 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 85180 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 85181 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 85182 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 85183 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 85184 | #define BIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 85185 | |
|---|
| 85186 | |
|---|
| 85187 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2 |
|---|
| 85188 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO |
|---|
| 85189 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85190 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85191 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI |
|---|
| 85192 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85193 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85194 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA |
|---|
| 85195 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85196 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85197 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL |
|---|
| 85198 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85199 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85200 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO |
|---|
| 85201 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85202 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85203 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI |
|---|
| 85204 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85205 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85206 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA |
|---|
| 85207 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85208 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85209 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL |
|---|
| 85210 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85211 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85212 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO |
|---|
| 85213 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85214 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85215 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI |
|---|
| 85216 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85217 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85218 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA |
|---|
| 85219 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85220 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85221 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL |
|---|
| 85222 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85223 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85224 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO |
|---|
| 85225 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85226 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85227 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI |
|---|
| 85228 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85229 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85230 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA |
|---|
| 85231 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85232 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85233 | //RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL |
|---|
| 85234 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85235 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85236 | //RCC_DEV0_EPF0_VF22_GFXMSIX_PBA |
|---|
| 85237 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 85238 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 85239 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 85240 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 85241 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 85242 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 85243 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 85244 | #define RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 85245 | |
|---|
| 85246 | |
|---|
| 85247 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC |
|---|
| 85248 | //BIF_BX_DEV0_EPF0_VF23_MM_INDEX |
|---|
| 85249 | #define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 85250 | #define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 85251 | #define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 85252 | #define BIF_BX_DEV0_EPF0_VF23_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 85253 | //BIF_BX_DEV0_EPF0_VF23_MM_DATA |
|---|
| 85254 | #define BIF_BX_DEV0_EPF0_VF23_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 85255 | #define BIF_BX_DEV0_EPF0_VF23_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 85256 | //BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI |
|---|
| 85257 | #define BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 85258 | #define BIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 85259 | |
|---|
| 85260 | |
|---|
| 85261 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1 |
|---|
| 85262 | //RCC_DEV0_EPF0_VF23_RCC_ERR_LOG |
|---|
| 85263 | #define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 85264 | #define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 85265 | #define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 85266 | #define RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 85267 | //RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN |
|---|
| 85268 | #define RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 85269 | #define RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 85270 | //RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE |
|---|
| 85271 | #define RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 85272 | #define RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 85273 | //RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED |
|---|
| 85274 | #define RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 85275 | #define RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 85276 | //RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 85277 | #define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 85278 | #define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 85279 | #define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 85280 | #define RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 85281 | |
|---|
| 85282 | |
|---|
| 85283 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1 |
|---|
| 85284 | //BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS |
|---|
| 85285 | #define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 85286 | #define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 85287 | #define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 85288 | #define BIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 85289 | //BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG |
|---|
| 85290 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 85291 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 85292 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 85293 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 85294 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 85295 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 85296 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 85297 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 85298 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 85299 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 85300 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 85301 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 85302 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 85303 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 85304 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 85305 | #define BIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 85306 | //BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 85307 | #define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 85308 | #define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 85309 | //BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 85310 | #define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 85311 | #define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 85312 | //BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 85313 | #define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 85314 | #define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 85315 | #define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 85316 | #define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 85317 | #define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 85318 | #define BIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 85319 | //BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 85320 | #define BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 85321 | #define BIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 85322 | //BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 85323 | #define BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 85324 | #define BIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 85325 | //BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ |
|---|
| 85326 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 85327 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 85328 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 85329 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 85330 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 85331 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 85332 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 85333 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 85334 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 85335 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 85336 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 85337 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 85338 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 85339 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 85340 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 85341 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 85342 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 85343 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 85344 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 85345 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 85346 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 85347 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 85348 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 85349 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 85350 | //BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE |
|---|
| 85351 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 85352 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 85353 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 85354 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 85355 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 85356 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 85357 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 85358 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 85359 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 85360 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 85361 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 85362 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 85363 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 85364 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 85365 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 85366 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 85367 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 85368 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 85369 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 85370 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 85371 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 85372 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 85373 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 85374 | #define BIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 85375 | //BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING |
|---|
| 85376 | #define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 85377 | #define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 85378 | #define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 85379 | #define BIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 85380 | //BIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 85381 | #define BIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 85382 | #define BIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 85383 | //BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 85384 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85385 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85386 | //BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 85387 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85388 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85389 | //BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 85390 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85391 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85392 | //BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 85393 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85394 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85395 | //BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 85396 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85397 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85398 | //BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 85399 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85400 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85401 | //BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 85402 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85403 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85404 | //BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 85405 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85406 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85407 | //BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL |
|---|
| 85408 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 85409 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 85410 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 85411 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 85412 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 85413 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 85414 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 85415 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 85416 | //BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL |
|---|
| 85417 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 85418 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 85419 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 85420 | #define BIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 85421 | //BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX |
|---|
| 85422 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 85423 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 85424 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 85425 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 85426 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 85427 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 85428 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 85429 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 85430 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 85431 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 85432 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 85433 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 85434 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 85435 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 85436 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 85437 | #define BIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 85438 | |
|---|
| 85439 | |
|---|
| 85440 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2 |
|---|
| 85441 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO |
|---|
| 85442 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85443 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85444 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI |
|---|
| 85445 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85446 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85447 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA |
|---|
| 85448 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85449 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85450 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL |
|---|
| 85451 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85452 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85453 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO |
|---|
| 85454 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85455 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85456 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI |
|---|
| 85457 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85458 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85459 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA |
|---|
| 85460 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85461 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85462 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL |
|---|
| 85463 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85464 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85465 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO |
|---|
| 85466 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85467 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85468 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI |
|---|
| 85469 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85470 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85471 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA |
|---|
| 85472 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85473 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85474 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL |
|---|
| 85475 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85476 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85477 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO |
|---|
| 85478 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85479 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85480 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI |
|---|
| 85481 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85482 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85483 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA |
|---|
| 85484 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85485 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85486 | //RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL |
|---|
| 85487 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85488 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85489 | //RCC_DEV0_EPF0_VF23_GFXMSIX_PBA |
|---|
| 85490 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 85491 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 85492 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 85493 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 85494 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 85495 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 85496 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 85497 | #define RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 85498 | |
|---|
| 85499 | |
|---|
| 85500 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC |
|---|
| 85501 | //BIF_BX_DEV0_EPF0_VF24_MM_INDEX |
|---|
| 85502 | #define BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 85503 | #define BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 85504 | #define BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 85505 | #define BIF_BX_DEV0_EPF0_VF24_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 85506 | //BIF_BX_DEV0_EPF0_VF24_MM_DATA |
|---|
| 85507 | #define BIF_BX_DEV0_EPF0_VF24_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 85508 | #define BIF_BX_DEV0_EPF0_VF24_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 85509 | //BIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI |
|---|
| 85510 | #define BIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 85511 | #define BIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 85512 | |
|---|
| 85513 | |
|---|
| 85514 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1 |
|---|
| 85515 | //RCC_DEV0_EPF0_VF24_RCC_ERR_LOG |
|---|
| 85516 | #define RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 85517 | #define RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 85518 | #define RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 85519 | #define RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 85520 | //RCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN |
|---|
| 85521 | #define RCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 85522 | #define RCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 85523 | //RCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE |
|---|
| 85524 | #define RCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 85525 | #define RCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 85526 | //RCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED |
|---|
| 85527 | #define RCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 85528 | #define RCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 85529 | //RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 85530 | #define RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 85531 | #define RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 85532 | #define RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 85533 | #define RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 85534 | |
|---|
| 85535 | |
|---|
| 85536 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1 |
|---|
| 85537 | //BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS |
|---|
| 85538 | #define BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 85539 | #define BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 85540 | #define BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 85541 | #define BIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 85542 | //BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG |
|---|
| 85543 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 85544 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 85545 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 85546 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 85547 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 85548 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 85549 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 85550 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 85551 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 85552 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 85553 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 85554 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 85555 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 85556 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 85557 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 85558 | #define BIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 85559 | //BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 85560 | #define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 85561 | #define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 85562 | //BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 85563 | #define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 85564 | #define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 85565 | //BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 85566 | #define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 85567 | #define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 85568 | #define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 85569 | #define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 85570 | #define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 85571 | #define BIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 85572 | //BIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 85573 | #define BIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 85574 | #define BIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 85575 | //BIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 85576 | #define BIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 85577 | #define BIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 85578 | //BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ |
|---|
| 85579 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 85580 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 85581 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 85582 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 85583 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 85584 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 85585 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 85586 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 85587 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 85588 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 85589 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 85590 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 85591 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 85592 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 85593 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 85594 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 85595 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 85596 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 85597 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 85598 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 85599 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 85600 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 85601 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 85602 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 85603 | //BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE |
|---|
| 85604 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 85605 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 85606 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 85607 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 85608 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 85609 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 85610 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 85611 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 85612 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 85613 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 85614 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 85615 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 85616 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 85617 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 85618 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 85619 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 85620 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 85621 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 85622 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 85623 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 85624 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 85625 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 85626 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 85627 | #define BIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 85628 | //BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING |
|---|
| 85629 | #define BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 85630 | #define BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 85631 | #define BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 85632 | #define BIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 85633 | //BIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 85634 | #define BIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 85635 | #define BIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 85636 | //BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 85637 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85638 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85639 | //BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 85640 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85641 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85642 | //BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 85643 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85644 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85645 | //BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 85646 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85647 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85648 | //BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 85649 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85650 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85651 | //BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 85652 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85653 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85654 | //BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 85655 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85656 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85657 | //BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 85658 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85659 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85660 | //BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL |
|---|
| 85661 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 85662 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 85663 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 85664 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 85665 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 85666 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 85667 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 85668 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 85669 | //BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL |
|---|
| 85670 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 85671 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 85672 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 85673 | #define BIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 85674 | //BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX |
|---|
| 85675 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 85676 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 85677 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 85678 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 85679 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 85680 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 85681 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 85682 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 85683 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 85684 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 85685 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 85686 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 85687 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 85688 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 85689 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 85690 | #define BIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 85691 | |
|---|
| 85692 | |
|---|
| 85693 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2 |
|---|
| 85694 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO |
|---|
| 85695 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85696 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85697 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI |
|---|
| 85698 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85699 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85700 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA |
|---|
| 85701 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85702 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85703 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL |
|---|
| 85704 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85705 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85706 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO |
|---|
| 85707 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85708 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85709 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI |
|---|
| 85710 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85711 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85712 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA |
|---|
| 85713 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85714 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85715 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL |
|---|
| 85716 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85717 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85718 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO |
|---|
| 85719 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85720 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85721 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI |
|---|
| 85722 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85723 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85724 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA |
|---|
| 85725 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85726 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85727 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL |
|---|
| 85728 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85729 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85730 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO |
|---|
| 85731 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85732 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85733 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI |
|---|
| 85734 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85735 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85736 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA |
|---|
| 85737 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85738 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85739 | //RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL |
|---|
| 85740 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85741 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85742 | //RCC_DEV0_EPF0_VF24_GFXMSIX_PBA |
|---|
| 85743 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 85744 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 85745 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 85746 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 85747 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 85748 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 85749 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 85750 | #define RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 85751 | |
|---|
| 85752 | |
|---|
| 85753 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC |
|---|
| 85754 | //BIF_BX_DEV0_EPF0_VF25_MM_INDEX |
|---|
| 85755 | #define BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 85756 | #define BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 85757 | #define BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 85758 | #define BIF_BX_DEV0_EPF0_VF25_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 85759 | //BIF_BX_DEV0_EPF0_VF25_MM_DATA |
|---|
| 85760 | #define BIF_BX_DEV0_EPF0_VF25_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 85761 | #define BIF_BX_DEV0_EPF0_VF25_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 85762 | //BIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI |
|---|
| 85763 | #define BIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 85764 | #define BIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 85765 | |
|---|
| 85766 | |
|---|
| 85767 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1 |
|---|
| 85768 | //RCC_DEV0_EPF0_VF25_RCC_ERR_LOG |
|---|
| 85769 | #define RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 85770 | #define RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 85771 | #define RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 85772 | #define RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 85773 | //RCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN |
|---|
| 85774 | #define RCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 85775 | #define RCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 85776 | //RCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE |
|---|
| 85777 | #define RCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 85778 | #define RCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 85779 | //RCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED |
|---|
| 85780 | #define RCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 85781 | #define RCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 85782 | //RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 85783 | #define RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 85784 | #define RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 85785 | #define RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 85786 | #define RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 85787 | |
|---|
| 85788 | |
|---|
| 85789 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1 |
|---|
| 85790 | //BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS |
|---|
| 85791 | #define BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 85792 | #define BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 85793 | #define BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 85794 | #define BIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 85795 | //BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG |
|---|
| 85796 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 85797 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 85798 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 85799 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 85800 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 85801 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 85802 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 85803 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 85804 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 85805 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 85806 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 85807 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 85808 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 85809 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 85810 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 85811 | #define BIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 85812 | //BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 85813 | #define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 85814 | #define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 85815 | //BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 85816 | #define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 85817 | #define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 85818 | //BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 85819 | #define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 85820 | #define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 85821 | #define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 85822 | #define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 85823 | #define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 85824 | #define BIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 85825 | //BIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 85826 | #define BIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 85827 | #define BIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 85828 | //BIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 85829 | #define BIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 85830 | #define BIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 85831 | //BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ |
|---|
| 85832 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 85833 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 85834 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 85835 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 85836 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 85837 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 85838 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 85839 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 85840 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 85841 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 85842 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 85843 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 85844 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 85845 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 85846 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 85847 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 85848 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 85849 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 85850 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 85851 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 85852 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 85853 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 85854 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 85855 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 85856 | //BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE |
|---|
| 85857 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 85858 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 85859 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 85860 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 85861 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 85862 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 85863 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 85864 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 85865 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 85866 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 85867 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 85868 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 85869 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 85870 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 85871 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 85872 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 85873 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 85874 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 85875 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 85876 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 85877 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 85878 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 85879 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 85880 | #define BIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 85881 | //BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING |
|---|
| 85882 | #define BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 85883 | #define BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 85884 | #define BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 85885 | #define BIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 85886 | //BIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 85887 | #define BIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 85888 | #define BIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 85889 | //BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 85890 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85891 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85892 | //BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 85893 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85894 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85895 | //BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 85896 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85897 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85898 | //BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 85899 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85900 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85901 | //BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 85902 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85903 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85904 | //BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 85905 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85906 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85907 | //BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 85908 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85909 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85910 | //BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 85911 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 85912 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 85913 | //BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL |
|---|
| 85914 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 85915 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 85916 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 85917 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 85918 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 85919 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 85920 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 85921 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 85922 | //BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL |
|---|
| 85923 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 85924 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 85925 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 85926 | #define BIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 85927 | //BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX |
|---|
| 85928 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 85929 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 85930 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 85931 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 85932 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 85933 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 85934 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 85935 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 85936 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 85937 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 85938 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 85939 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 85940 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 85941 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 85942 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 85943 | #define BIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 85944 | |
|---|
| 85945 | |
|---|
| 85946 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2 |
|---|
| 85947 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO |
|---|
| 85948 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85949 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85950 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI |
|---|
| 85951 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85952 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85953 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA |
|---|
| 85954 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85955 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85956 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL |
|---|
| 85957 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85958 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85959 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO |
|---|
| 85960 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85961 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85962 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI |
|---|
| 85963 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85964 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85965 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA |
|---|
| 85966 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85967 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85968 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL |
|---|
| 85969 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85970 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85971 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO |
|---|
| 85972 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85973 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85974 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI |
|---|
| 85975 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85976 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85977 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA |
|---|
| 85978 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85979 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85980 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL |
|---|
| 85981 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85982 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85983 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO |
|---|
| 85984 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 85985 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 85986 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI |
|---|
| 85987 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 85988 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 85989 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA |
|---|
| 85990 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 85991 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 85992 | //RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL |
|---|
| 85993 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 85994 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 85995 | //RCC_DEV0_EPF0_VF25_GFXMSIX_PBA |
|---|
| 85996 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 85997 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 85998 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 85999 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 86000 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 86001 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 86002 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 86003 | #define RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 86004 | |
|---|
| 86005 | |
|---|
| 86006 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC |
|---|
| 86007 | //BIF_BX_DEV0_EPF0_VF26_MM_INDEX |
|---|
| 86008 | #define BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 86009 | #define BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 86010 | #define BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 86011 | #define BIF_BX_DEV0_EPF0_VF26_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 86012 | //BIF_BX_DEV0_EPF0_VF26_MM_DATA |
|---|
| 86013 | #define BIF_BX_DEV0_EPF0_VF26_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 86014 | #define BIF_BX_DEV0_EPF0_VF26_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 86015 | //BIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI |
|---|
| 86016 | #define BIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 86017 | #define BIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 86018 | |
|---|
| 86019 | |
|---|
| 86020 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1 |
|---|
| 86021 | //RCC_DEV0_EPF0_VF26_RCC_ERR_LOG |
|---|
| 86022 | #define RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 86023 | #define RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 86024 | #define RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 86025 | #define RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 86026 | //RCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN |
|---|
| 86027 | #define RCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 86028 | #define RCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 86029 | //RCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE |
|---|
| 86030 | #define RCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 86031 | #define RCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 86032 | //RCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED |
|---|
| 86033 | #define RCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 86034 | #define RCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 86035 | //RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 86036 | #define RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 86037 | #define RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 86038 | #define RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 86039 | #define RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 86040 | |
|---|
| 86041 | |
|---|
| 86042 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1 |
|---|
| 86043 | //BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS |
|---|
| 86044 | #define BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 86045 | #define BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 86046 | #define BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 86047 | #define BIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 86048 | //BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG |
|---|
| 86049 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 86050 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 86051 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 86052 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 86053 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 86054 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 86055 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 86056 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 86057 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 86058 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 86059 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 86060 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 86061 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 86062 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 86063 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 86064 | #define BIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 86065 | //BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 86066 | #define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 86067 | #define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 86068 | //BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 86069 | #define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 86070 | #define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 86071 | //BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 86072 | #define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 86073 | #define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 86074 | #define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 86075 | #define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 86076 | #define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 86077 | #define BIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 86078 | //BIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 86079 | #define BIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 86080 | #define BIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 86081 | //BIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 86082 | #define BIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 86083 | #define BIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 86084 | //BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ |
|---|
| 86085 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 86086 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 86087 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 86088 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 86089 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 86090 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 86091 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 86092 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 86093 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 86094 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 86095 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 86096 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 86097 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 86098 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 86099 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 86100 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 86101 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 86102 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 86103 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 86104 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 86105 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 86106 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 86107 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 86108 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 86109 | //BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE |
|---|
| 86110 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 86111 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 86112 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 86113 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 86114 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 86115 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 86116 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 86117 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 86118 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 86119 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 86120 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 86121 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 86122 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 86123 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 86124 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 86125 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 86126 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 86127 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 86128 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 86129 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 86130 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 86131 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 86132 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 86133 | #define BIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 86134 | //BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING |
|---|
| 86135 | #define BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 86136 | #define BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 86137 | #define BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 86138 | #define BIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 86139 | //BIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 86140 | #define BIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 86141 | #define BIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 86142 | //BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 86143 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86144 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86145 | //BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 86146 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86147 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86148 | //BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 86149 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86150 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86151 | //BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 86152 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86153 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86154 | //BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 86155 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86156 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86157 | //BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 86158 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86159 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86160 | //BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 86161 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86162 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86163 | //BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 86164 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86165 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86166 | //BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL |
|---|
| 86167 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 86168 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 86169 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 86170 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 86171 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 86172 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 86173 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 86174 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 86175 | //BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL |
|---|
| 86176 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 86177 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 86178 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 86179 | #define BIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 86180 | //BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX |
|---|
| 86181 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 86182 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 86183 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 86184 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 86185 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 86186 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 86187 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 86188 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 86189 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 86190 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 86191 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 86192 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 86193 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 86194 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 86195 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 86196 | #define BIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 86197 | |
|---|
| 86198 | |
|---|
| 86199 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2 |
|---|
| 86200 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO |
|---|
| 86201 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86202 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86203 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI |
|---|
| 86204 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86205 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86206 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA |
|---|
| 86207 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86208 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86209 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL |
|---|
| 86210 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86211 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86212 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO |
|---|
| 86213 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86214 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86215 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI |
|---|
| 86216 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86217 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86218 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA |
|---|
| 86219 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86220 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86221 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL |
|---|
| 86222 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86223 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86224 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO |
|---|
| 86225 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86226 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86227 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI |
|---|
| 86228 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86229 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86230 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA |
|---|
| 86231 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86232 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86233 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL |
|---|
| 86234 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86235 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86236 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO |
|---|
| 86237 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86238 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86239 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI |
|---|
| 86240 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86241 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86242 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA |
|---|
| 86243 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86244 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86245 | //RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL |
|---|
| 86246 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86247 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86248 | //RCC_DEV0_EPF0_VF26_GFXMSIX_PBA |
|---|
| 86249 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 86250 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 86251 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 86252 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 86253 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 86254 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 86255 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 86256 | #define RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 86257 | |
|---|
| 86258 | |
|---|
| 86259 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC |
|---|
| 86260 | //BIF_BX_DEV0_EPF0_VF27_MM_INDEX |
|---|
| 86261 | #define BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 86262 | #define BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 86263 | #define BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 86264 | #define BIF_BX_DEV0_EPF0_VF27_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 86265 | //BIF_BX_DEV0_EPF0_VF27_MM_DATA |
|---|
| 86266 | #define BIF_BX_DEV0_EPF0_VF27_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 86267 | #define BIF_BX_DEV0_EPF0_VF27_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 86268 | //BIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI |
|---|
| 86269 | #define BIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 86270 | #define BIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 86271 | |
|---|
| 86272 | |
|---|
| 86273 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1 |
|---|
| 86274 | //RCC_DEV0_EPF0_VF27_RCC_ERR_LOG |
|---|
| 86275 | #define RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 86276 | #define RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 86277 | #define RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 86278 | #define RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 86279 | //RCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN |
|---|
| 86280 | #define RCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 86281 | #define RCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 86282 | //RCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE |
|---|
| 86283 | #define RCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 86284 | #define RCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 86285 | //RCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED |
|---|
| 86286 | #define RCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 86287 | #define RCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 86288 | //RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 86289 | #define RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 86290 | #define RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 86291 | #define RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 86292 | #define RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 86293 | |
|---|
| 86294 | |
|---|
| 86295 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1 |
|---|
| 86296 | //BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS |
|---|
| 86297 | #define BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 86298 | #define BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 86299 | #define BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 86300 | #define BIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 86301 | //BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG |
|---|
| 86302 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 86303 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 86304 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 86305 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 86306 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 86307 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 86308 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 86309 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 86310 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 86311 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 86312 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 86313 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 86314 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 86315 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 86316 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 86317 | #define BIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 86318 | //BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 86319 | #define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 86320 | #define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 86321 | //BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 86322 | #define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 86323 | #define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 86324 | //BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 86325 | #define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 86326 | #define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 86327 | #define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 86328 | #define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 86329 | #define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 86330 | #define BIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 86331 | //BIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 86332 | #define BIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 86333 | #define BIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 86334 | //BIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 86335 | #define BIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 86336 | #define BIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 86337 | //BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ |
|---|
| 86338 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 86339 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 86340 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 86341 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 86342 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 86343 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 86344 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 86345 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 86346 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 86347 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 86348 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 86349 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 86350 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 86351 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 86352 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 86353 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 86354 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 86355 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 86356 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 86357 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 86358 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 86359 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 86360 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 86361 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 86362 | //BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE |
|---|
| 86363 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 86364 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 86365 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 86366 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 86367 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 86368 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 86369 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 86370 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 86371 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 86372 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 86373 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 86374 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 86375 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 86376 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 86377 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 86378 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 86379 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 86380 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 86381 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 86382 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 86383 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 86384 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 86385 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 86386 | #define BIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 86387 | //BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING |
|---|
| 86388 | #define BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 86389 | #define BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 86390 | #define BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 86391 | #define BIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 86392 | //BIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 86393 | #define BIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 86394 | #define BIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 86395 | //BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 86396 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86397 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86398 | //BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 86399 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86400 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86401 | //BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 86402 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86403 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86404 | //BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 86405 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86406 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86407 | //BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 86408 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86409 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86410 | //BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 86411 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86412 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86413 | //BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 86414 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86415 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86416 | //BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 86417 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86418 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86419 | //BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL |
|---|
| 86420 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 86421 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 86422 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 86423 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 86424 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 86425 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 86426 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 86427 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 86428 | //BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL |
|---|
| 86429 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 86430 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 86431 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 86432 | #define BIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 86433 | //BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX |
|---|
| 86434 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 86435 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 86436 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 86437 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 86438 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 86439 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 86440 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 86441 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 86442 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 86443 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 86444 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 86445 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 86446 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 86447 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 86448 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 86449 | #define BIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 86450 | |
|---|
| 86451 | |
|---|
| 86452 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2 |
|---|
| 86453 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO |
|---|
| 86454 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86455 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86456 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI |
|---|
| 86457 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86458 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86459 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA |
|---|
| 86460 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86461 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86462 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL |
|---|
| 86463 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86464 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86465 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO |
|---|
| 86466 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86467 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86468 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI |
|---|
| 86469 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86470 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86471 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA |
|---|
| 86472 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86473 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86474 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL |
|---|
| 86475 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86476 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86477 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO |
|---|
| 86478 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86479 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86480 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI |
|---|
| 86481 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86482 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86483 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA |
|---|
| 86484 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86485 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86486 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL |
|---|
| 86487 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86488 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86489 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO |
|---|
| 86490 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86491 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86492 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI |
|---|
| 86493 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86494 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86495 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA |
|---|
| 86496 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86497 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86498 | //RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL |
|---|
| 86499 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86500 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86501 | //RCC_DEV0_EPF0_VF27_GFXMSIX_PBA |
|---|
| 86502 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 86503 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 86504 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 86505 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 86506 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 86507 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 86508 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 86509 | #define RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 86510 | |
|---|
| 86511 | |
|---|
| 86512 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC |
|---|
| 86513 | //BIF_BX_DEV0_EPF0_VF28_MM_INDEX |
|---|
| 86514 | #define BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 86515 | #define BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 86516 | #define BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 86517 | #define BIF_BX_DEV0_EPF0_VF28_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 86518 | //BIF_BX_DEV0_EPF0_VF28_MM_DATA |
|---|
| 86519 | #define BIF_BX_DEV0_EPF0_VF28_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 86520 | #define BIF_BX_DEV0_EPF0_VF28_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 86521 | //BIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI |
|---|
| 86522 | #define BIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 86523 | #define BIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 86524 | |
|---|
| 86525 | |
|---|
| 86526 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1 |
|---|
| 86527 | //RCC_DEV0_EPF0_VF28_RCC_ERR_LOG |
|---|
| 86528 | #define RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 86529 | #define RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 86530 | #define RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 86531 | #define RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 86532 | //RCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN |
|---|
| 86533 | #define RCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 86534 | #define RCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 86535 | //RCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE |
|---|
| 86536 | #define RCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 86537 | #define RCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 86538 | //RCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED |
|---|
| 86539 | #define RCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 86540 | #define RCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 86541 | //RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 86542 | #define RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 86543 | #define RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 86544 | #define RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 86545 | #define RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 86546 | |
|---|
| 86547 | |
|---|
| 86548 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1 |
|---|
| 86549 | //BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS |
|---|
| 86550 | #define BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 86551 | #define BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 86552 | #define BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 86553 | #define BIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 86554 | //BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG |
|---|
| 86555 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 86556 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 86557 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 86558 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 86559 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 86560 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 86561 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 86562 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 86563 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 86564 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 86565 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 86566 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 86567 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 86568 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 86569 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 86570 | #define BIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 86571 | //BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 86572 | #define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 86573 | #define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 86574 | //BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 86575 | #define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 86576 | #define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 86577 | //BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 86578 | #define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 86579 | #define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 86580 | #define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 86581 | #define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 86582 | #define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 86583 | #define BIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 86584 | //BIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 86585 | #define BIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 86586 | #define BIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 86587 | //BIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 86588 | #define BIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 86589 | #define BIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 86590 | //BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ |
|---|
| 86591 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 86592 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 86593 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 86594 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 86595 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 86596 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 86597 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 86598 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 86599 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 86600 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 86601 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 86602 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 86603 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 86604 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 86605 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 86606 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 86607 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 86608 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 86609 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 86610 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 86611 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 86612 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 86613 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 86614 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 86615 | //BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE |
|---|
| 86616 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 86617 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 86618 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 86619 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 86620 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 86621 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 86622 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 86623 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 86624 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 86625 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 86626 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 86627 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 86628 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 86629 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 86630 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 86631 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 86632 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 86633 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 86634 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 86635 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 86636 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 86637 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 86638 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 86639 | #define BIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 86640 | //BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING |
|---|
| 86641 | #define BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 86642 | #define BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 86643 | #define BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 86644 | #define BIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 86645 | //BIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 86646 | #define BIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 86647 | #define BIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 86648 | //BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 86649 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86650 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86651 | //BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 86652 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86653 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86654 | //BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 86655 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86656 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86657 | //BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 86658 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86659 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86660 | //BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 86661 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86662 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86663 | //BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 86664 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86665 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86666 | //BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 86667 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86668 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86669 | //BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 86670 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86671 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86672 | //BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL |
|---|
| 86673 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 86674 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 86675 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 86676 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 86677 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 86678 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 86679 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 86680 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 86681 | //BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL |
|---|
| 86682 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 86683 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 86684 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 86685 | #define BIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 86686 | //BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX |
|---|
| 86687 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 86688 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 86689 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 86690 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 86691 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 86692 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 86693 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 86694 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 86695 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 86696 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 86697 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 86698 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 86699 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 86700 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 86701 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 86702 | #define BIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 86703 | |
|---|
| 86704 | |
|---|
| 86705 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2 |
|---|
| 86706 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO |
|---|
| 86707 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86708 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86709 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI |
|---|
| 86710 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86711 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86712 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA |
|---|
| 86713 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86714 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86715 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL |
|---|
| 86716 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86717 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86718 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO |
|---|
| 86719 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86720 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86721 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI |
|---|
| 86722 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86723 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86724 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA |
|---|
| 86725 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86726 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86727 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL |
|---|
| 86728 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86729 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86730 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO |
|---|
| 86731 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86732 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86733 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI |
|---|
| 86734 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86735 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86736 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA |
|---|
| 86737 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86738 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86739 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL |
|---|
| 86740 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86741 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86742 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO |
|---|
| 86743 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86744 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86745 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI |
|---|
| 86746 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86747 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86748 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA |
|---|
| 86749 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86750 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86751 | //RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL |
|---|
| 86752 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86753 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86754 | //RCC_DEV0_EPF0_VF28_GFXMSIX_PBA |
|---|
| 86755 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 86756 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 86757 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 86758 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 86759 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 86760 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 86761 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 86762 | #define RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 86763 | |
|---|
| 86764 | |
|---|
| 86765 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC |
|---|
| 86766 | //BIF_BX_DEV0_EPF0_VF29_MM_INDEX |
|---|
| 86767 | #define BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 86768 | #define BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 86769 | #define BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 86770 | #define BIF_BX_DEV0_EPF0_VF29_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 86771 | //BIF_BX_DEV0_EPF0_VF29_MM_DATA |
|---|
| 86772 | #define BIF_BX_DEV0_EPF0_VF29_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 86773 | #define BIF_BX_DEV0_EPF0_VF29_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 86774 | //BIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI |
|---|
| 86775 | #define BIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 86776 | #define BIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 86777 | |
|---|
| 86778 | |
|---|
| 86779 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1 |
|---|
| 86780 | //RCC_DEV0_EPF0_VF29_RCC_ERR_LOG |
|---|
| 86781 | #define RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 86782 | #define RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 86783 | #define RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 86784 | #define RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 86785 | //RCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN |
|---|
| 86786 | #define RCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 86787 | #define RCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 86788 | //RCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE |
|---|
| 86789 | #define RCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 86790 | #define RCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 86791 | //RCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED |
|---|
| 86792 | #define RCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 86793 | #define RCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 86794 | //RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 86795 | #define RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 86796 | #define RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 86797 | #define RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 86798 | #define RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 86799 | |
|---|
| 86800 | |
|---|
| 86801 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1 |
|---|
| 86802 | //BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS |
|---|
| 86803 | #define BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 86804 | #define BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 86805 | #define BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 86806 | #define BIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 86807 | //BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG |
|---|
| 86808 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 86809 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 86810 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 86811 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 86812 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 86813 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 86814 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 86815 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 86816 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 86817 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 86818 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 86819 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 86820 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 86821 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 86822 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 86823 | #define BIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 86824 | //BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 86825 | #define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 86826 | #define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 86827 | //BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 86828 | #define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 86829 | #define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 86830 | //BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 86831 | #define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 86832 | #define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 86833 | #define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 86834 | #define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 86835 | #define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 86836 | #define BIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 86837 | //BIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 86838 | #define BIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 86839 | #define BIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 86840 | //BIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 86841 | #define BIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 86842 | #define BIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 86843 | //BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ |
|---|
| 86844 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 86845 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 86846 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 86847 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 86848 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 86849 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 86850 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 86851 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 86852 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 86853 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 86854 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 86855 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 86856 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 86857 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 86858 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 86859 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 86860 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 86861 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 86862 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 86863 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 86864 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 86865 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 86866 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 86867 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 86868 | //BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE |
|---|
| 86869 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 86870 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 86871 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 86872 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 86873 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 86874 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 86875 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 86876 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 86877 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 86878 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 86879 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 86880 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 86881 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 86882 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 86883 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 86884 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 86885 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 86886 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 86887 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 86888 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 86889 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 86890 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 86891 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 86892 | #define BIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 86893 | //BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING |
|---|
| 86894 | #define BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 86895 | #define BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 86896 | #define BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 86897 | #define BIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 86898 | //BIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 86899 | #define BIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 86900 | #define BIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 86901 | //BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 86902 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86903 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86904 | //BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 86905 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86906 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86907 | //BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 86908 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86909 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86910 | //BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 86911 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86912 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86913 | //BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 86914 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86915 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86916 | //BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 86917 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86918 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86919 | //BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 86920 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86921 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86922 | //BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 86923 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 86924 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 86925 | //BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL |
|---|
| 86926 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 86927 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 86928 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 86929 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 86930 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 86931 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 86932 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 86933 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 86934 | //BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL |
|---|
| 86935 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 86936 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 86937 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 86938 | #define BIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 86939 | //BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX |
|---|
| 86940 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 86941 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 86942 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 86943 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 86944 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 86945 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 86946 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 86947 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 86948 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 86949 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 86950 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 86951 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 86952 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 86953 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 86954 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 86955 | #define BIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 86956 | |
|---|
| 86957 | |
|---|
| 86958 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2 |
|---|
| 86959 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO |
|---|
| 86960 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86961 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86962 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI |
|---|
| 86963 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86964 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86965 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA |
|---|
| 86966 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86967 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86968 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL |
|---|
| 86969 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86970 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86971 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO |
|---|
| 86972 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86973 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86974 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI |
|---|
| 86975 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86976 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86977 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA |
|---|
| 86978 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86979 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86980 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL |
|---|
| 86981 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86982 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86983 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO |
|---|
| 86984 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86985 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86986 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI |
|---|
| 86987 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 86988 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 86989 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA |
|---|
| 86990 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 86991 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 86992 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL |
|---|
| 86993 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 86994 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 86995 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO |
|---|
| 86996 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 86997 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 86998 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI |
|---|
| 86999 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 87000 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 87001 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA |
|---|
| 87002 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 87003 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 87004 | //RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL |
|---|
| 87005 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 87006 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 87007 | //RCC_DEV0_EPF0_VF29_GFXMSIX_PBA |
|---|
| 87008 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 87009 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 87010 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 87011 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 87012 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 87013 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 87014 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 87015 | #define RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 87016 | |
|---|
| 87017 | |
|---|
| 87018 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC |
|---|
| 87019 | //BIF_BX_DEV0_EPF0_VF30_MM_INDEX |
|---|
| 87020 | #define BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 87021 | #define BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 87022 | #define BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 87023 | #define BIF_BX_DEV0_EPF0_VF30_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 87024 | //BIF_BX_DEV0_EPF0_VF30_MM_DATA |
|---|
| 87025 | #define BIF_BX_DEV0_EPF0_VF30_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 87026 | #define BIF_BX_DEV0_EPF0_VF30_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 87027 | //BIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI |
|---|
| 87028 | #define BIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 87029 | #define BIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 87030 | |
|---|
| 87031 | |
|---|
| 87032 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1 |
|---|
| 87033 | //RCC_DEV0_EPF0_VF30_RCC_ERR_LOG |
|---|
| 87034 | #define RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 |
|---|
| 87035 | #define RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 |
|---|
| 87036 | #define RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L |
|---|
| 87037 | #define RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L |
|---|
| 87038 | //RCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN |
|---|
| 87039 | #define RCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 |
|---|
| 87040 | #define RCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L |
|---|
| 87041 | //RCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE |
|---|
| 87042 | #define RCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 |
|---|
| 87043 | #define RCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL |
|---|
| 87044 | //RCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED |
|---|
| 87045 | #define RCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 |
|---|
| 87046 | #define RCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL |
|---|
| 87047 | //RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER |
|---|
| 87048 | #define RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 |
|---|
| 87049 | #define RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f |
|---|
| 87050 | #define RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L |
|---|
| 87051 | #define RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L |
|---|
| 87052 | |
|---|
| 87053 | |
|---|
| 87054 | // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1 |
|---|
| 87055 | //BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS |
|---|
| 87056 | #define BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 |
|---|
| 87057 | #define BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 |
|---|
| 87058 | #define BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L |
|---|
| 87059 | #define BIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L |
|---|
| 87060 | //BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG |
|---|
| 87061 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 |
|---|
| 87062 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 |
|---|
| 87063 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 |
|---|
| 87064 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 |
|---|
| 87065 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 |
|---|
| 87066 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 |
|---|
| 87067 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 |
|---|
| 87068 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 |
|---|
| 87069 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L |
|---|
| 87070 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L |
|---|
| 87071 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L |
|---|
| 87072 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L |
|---|
| 87073 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L |
|---|
| 87074 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L |
|---|
| 87075 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L |
|---|
| 87076 | #define BIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L |
|---|
| 87077 | //BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH |
|---|
| 87078 | #define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 |
|---|
| 87079 | #define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL |
|---|
| 87080 | //BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW |
|---|
| 87081 | #define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 |
|---|
| 87082 | #define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL |
|---|
| 87083 | //BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL |
|---|
| 87084 | #define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 |
|---|
| 87085 | #define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 |
|---|
| 87086 | #define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 |
|---|
| 87087 | #define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L |
|---|
| 87088 | #define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L |
|---|
| 87089 | #define BIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L |
|---|
| 87090 | //BIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL |
|---|
| 87091 | #define BIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 87092 | #define BIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 87093 | //BIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL |
|---|
| 87094 | #define BIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 |
|---|
| 87095 | #define BIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L |
|---|
| 87096 | //BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ |
|---|
| 87097 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 |
|---|
| 87098 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 |
|---|
| 87099 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 |
|---|
| 87100 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 |
|---|
| 87101 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 |
|---|
| 87102 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 |
|---|
| 87103 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 |
|---|
| 87104 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 |
|---|
| 87105 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 |
|---|
| 87106 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 |
|---|
| 87107 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa |
|---|
| 87108 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb |
|---|
| 87109 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L |
|---|
| 87110 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L |
|---|
| 87111 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L |
|---|
| 87112 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L |
|---|
| 87113 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L |
|---|
| 87114 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L |
|---|
| 87115 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L |
|---|
| 87116 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L |
|---|
| 87117 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L |
|---|
| 87118 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L |
|---|
| 87119 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L |
|---|
| 87120 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L |
|---|
| 87121 | //BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE |
|---|
| 87122 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 |
|---|
| 87123 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 |
|---|
| 87124 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 |
|---|
| 87125 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 |
|---|
| 87126 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 |
|---|
| 87127 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 |
|---|
| 87128 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 |
|---|
| 87129 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 |
|---|
| 87130 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 |
|---|
| 87131 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 |
|---|
| 87132 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa |
|---|
| 87133 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb |
|---|
| 87134 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L |
|---|
| 87135 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L |
|---|
| 87136 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L |
|---|
| 87137 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L |
|---|
| 87138 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L |
|---|
| 87139 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L |
|---|
| 87140 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L |
|---|
| 87141 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L |
|---|
| 87142 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L |
|---|
| 87143 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L |
|---|
| 87144 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L |
|---|
| 87145 | #define BIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L |
|---|
| 87146 | //BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING |
|---|
| 87147 | #define BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 |
|---|
| 87148 | #define BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 |
|---|
| 87149 | #define BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L |
|---|
| 87150 | #define BIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L |
|---|
| 87151 | //BIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS |
|---|
| 87152 | #define BIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 |
|---|
| 87153 | #define BIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L |
|---|
| 87154 | //BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0 |
|---|
| 87155 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 87156 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 87157 | //BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1 |
|---|
| 87158 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 87159 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 87160 | //BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2 |
|---|
| 87161 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 87162 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 87163 | //BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3 |
|---|
| 87164 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 87165 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 87166 | //BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0 |
|---|
| 87167 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 87168 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 87169 | //BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1 |
|---|
| 87170 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 87171 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 87172 | //BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2 |
|---|
| 87173 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 87174 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 87175 | //BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3 |
|---|
| 87176 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 |
|---|
| 87177 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL |
|---|
| 87178 | //BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL |
|---|
| 87179 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 |
|---|
| 87180 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 |
|---|
| 87181 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 |
|---|
| 87182 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 |
|---|
| 87183 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L |
|---|
| 87184 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L |
|---|
| 87185 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L |
|---|
| 87186 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L |
|---|
| 87187 | //BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL |
|---|
| 87188 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 |
|---|
| 87189 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 |
|---|
| 87190 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L |
|---|
| 87191 | #define BIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L |
|---|
| 87192 | //BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX |
|---|
| 87193 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 |
|---|
| 87194 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 |
|---|
| 87195 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 87196 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf |
|---|
| 87197 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 87198 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 |
|---|
| 87199 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 |
|---|
| 87200 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 |
|---|
| 87201 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L |
|---|
| 87202 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L |
|---|
| 87203 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 87204 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 87205 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 87206 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L |
|---|
| 87207 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L |
|---|
| 87208 | #define BIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L |
|---|
| 87209 | |
|---|
| 87210 | |
|---|
| 87211 | // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2 |
|---|
| 87212 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO |
|---|
| 87213 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 87214 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 87215 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI |
|---|
| 87216 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 87217 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 87218 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA |
|---|
| 87219 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 87220 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 87221 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL |
|---|
| 87222 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 87223 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 87224 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO |
|---|
| 87225 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 87226 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 87227 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI |
|---|
| 87228 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 87229 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 87230 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA |
|---|
| 87231 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 87232 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 87233 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL |
|---|
| 87234 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 87235 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 87236 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO |
|---|
| 87237 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 87238 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 87239 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI |
|---|
| 87240 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 87241 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 87242 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA |
|---|
| 87243 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 87244 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 87245 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL |
|---|
| 87246 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 87247 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 87248 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO |
|---|
| 87249 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 87250 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 87251 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI |
|---|
| 87252 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 87253 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 87254 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA |
|---|
| 87255 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 |
|---|
| 87256 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL |
|---|
| 87257 | //RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL |
|---|
| 87258 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 |
|---|
| 87259 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L |
|---|
| 87260 | //RCC_DEV0_EPF0_VF30_GFXMSIX_PBA |
|---|
| 87261 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 |
|---|
| 87262 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 |
|---|
| 87263 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 |
|---|
| 87264 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 |
|---|
| 87265 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L |
|---|
| 87266 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L |
|---|
| 87267 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L |
|---|
| 87268 | #define RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L |
|---|
| 87269 | |
|---|
| 87270 | |
|---|
| 87271 | // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp |
|---|
| 87272 | //PSWUSCFG0_1_VENDOR_ID |
|---|
| 87273 | #define PSWUSCFG0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 87274 | #define PSWUSCFG0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 87275 | //PSWUSCFG0_1_DEVICE_ID |
|---|
| 87276 | #define PSWUSCFG0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 87277 | #define PSWUSCFG0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 87278 | //PSWUSCFG0_1_COMMAND |
|---|
| 87279 | #define PSWUSCFG0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 87280 | #define PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 87281 | #define PSWUSCFG0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 87282 | #define PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 87283 | #define PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 87284 | #define PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 87285 | #define PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 87286 | #define PSWUSCFG0_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 87287 | #define PSWUSCFG0_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 87288 | #define PSWUSCFG0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 87289 | #define PSWUSCFG0_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 87290 | #define PSWUSCFG0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 87291 | #define PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 87292 | #define PSWUSCFG0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 87293 | #define PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 87294 | #define PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 87295 | #define PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 87296 | #define PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 87297 | #define PSWUSCFG0_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 87298 | #define PSWUSCFG0_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 87299 | #define PSWUSCFG0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 87300 | #define PSWUSCFG0_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 87301 | //PSWUSCFG0_1_STATUS |
|---|
| 87302 | #define PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 87303 | #define PSWUSCFG0_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 87304 | #define PSWUSCFG0_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 87305 | #define PSWUSCFG0_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 87306 | #define PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 87307 | #define PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 87308 | #define PSWUSCFG0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 87309 | #define PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 87310 | #define PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 87311 | #define PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 87312 | #define PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 87313 | #define PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 87314 | #define PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 87315 | #define PSWUSCFG0_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 87316 | #define PSWUSCFG0_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 87317 | #define PSWUSCFG0_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 87318 | #define PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 87319 | #define PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 87320 | #define PSWUSCFG0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 87321 | #define PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 87322 | #define PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 87323 | #define PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 87324 | #define PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 87325 | #define PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 87326 | //PSWUSCFG0_1_REVISION_ID |
|---|
| 87327 | #define PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 87328 | #define PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 87329 | #define PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 87330 | #define PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 87331 | //PSWUSCFG0_1_PROG_INTERFACE |
|---|
| 87332 | #define PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 87333 | #define PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 87334 | //PSWUSCFG0_1_SUB_CLASS |
|---|
| 87335 | #define PSWUSCFG0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 87336 | #define PSWUSCFG0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 87337 | //PSWUSCFG0_1_BASE_CLASS |
|---|
| 87338 | #define PSWUSCFG0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 87339 | #define PSWUSCFG0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 87340 | //PSWUSCFG0_1_CACHE_LINE |
|---|
| 87341 | #define PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 87342 | #define PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 87343 | //PSWUSCFG0_1_LATENCY |
|---|
| 87344 | #define PSWUSCFG0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 87345 | #define PSWUSCFG0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 87346 | //PSWUSCFG0_1_HEADER |
|---|
| 87347 | #define 0x0 |
|---|
| 87348 | #define 0x7 |
|---|
| 87349 | #define 0x7FL |
|---|
| 87350 | #define 0x80L |
|---|
| 87351 | //PSWUSCFG0_1_BIST |
|---|
| 87352 | #define PSWUSCFG0_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 87353 | #define PSWUSCFG0_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 87354 | #define PSWUSCFG0_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 87355 | #define PSWUSCFG0_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 87356 | #define PSWUSCFG0_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 87357 | #define PSWUSCFG0_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 87358 | //PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY |
|---|
| 87359 | #define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
|---|
| 87360 | #define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
|---|
| 87361 | #define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
|---|
| 87362 | #define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
|---|
| 87363 | #define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
|---|
| 87364 | #define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
|---|
| 87365 | #define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
|---|
| 87366 | #define PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
|---|
| 87367 | //PSWUSCFG0_1_IO_BASE_LIMIT |
|---|
| 87368 | #define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
|---|
| 87369 | #define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
|---|
| 87370 | #define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
|---|
| 87371 | #define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
|---|
| 87372 | #define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
|---|
| 87373 | #define PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
|---|
| 87374 | #define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
|---|
| 87375 | #define PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
|---|
| 87376 | //PSWUSCFG0_1_SECONDARY_STATUS |
|---|
| 87377 | #define PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 87378 | #define PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 87379 | #define PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 87380 | #define PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 87381 | #define PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 87382 | #define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 87383 | #define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 87384 | #define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 87385 | #define PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 87386 | #define PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 87387 | #define PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 87388 | #define PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 87389 | #define PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 87390 | #define PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 87391 | #define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 87392 | #define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 87393 | #define PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 87394 | #define PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 87395 | //PSWUSCFG0_1_MEM_BASE_LIMIT |
|---|
| 87396 | #define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 87397 | #define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
|---|
| 87398 | #define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 87399 | #define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
|---|
| 87400 | #define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 87401 | #define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
|---|
| 87402 | #define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 87403 | #define PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
|---|
| 87404 | //PSWUSCFG0_1_PREF_BASE_LIMIT |
|---|
| 87405 | #define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 87406 | #define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
|---|
| 87407 | #define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 87408 | #define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
|---|
| 87409 | #define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 87410 | #define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
|---|
| 87411 | #define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 87412 | #define PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
|---|
| 87413 | //PSWUSCFG0_1_PREF_BASE_UPPER |
|---|
| 87414 | #define PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
|---|
| 87415 | #define PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
|---|
| 87416 | //PSWUSCFG0_1_PREF_LIMIT_UPPER |
|---|
| 87417 | #define PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
|---|
| 87418 | #define PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
|---|
| 87419 | //PSWUSCFG0_1_IO_BASE_LIMIT_HI |
|---|
| 87420 | #define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
|---|
| 87421 | #define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
|---|
| 87422 | #define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
|---|
| 87423 | #define PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
|---|
| 87424 | //PSWUSCFG0_1_CAP_PTR |
|---|
| 87425 | #define PSWUSCFG0_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 87426 | #define PSWUSCFG0_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 87427 | //PSWUSCFG0_1_ROM_BASE_ADDR |
|---|
| 87428 | #define PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 87429 | #define PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 87430 | //PSWUSCFG0_1_INTERRUPT_LINE |
|---|
| 87431 | #define PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 87432 | #define PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 87433 | //PSWUSCFG0_1_INTERRUPT_PIN |
|---|
| 87434 | #define PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 87435 | #define PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 87436 | //PSWUSCFG0_1_IRQ_BRIDGE_CNTL |
|---|
| 87437 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
|---|
| 87438 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
|---|
| 87439 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
|---|
| 87440 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
|---|
| 87441 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
|---|
| 87442 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
|---|
| 87443 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
|---|
| 87444 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
|---|
| 87445 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
|---|
| 87446 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
|---|
| 87447 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
|---|
| 87448 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
|---|
| 87449 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
|---|
| 87450 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
|---|
| 87451 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
|---|
| 87452 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
|---|
| 87453 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
|---|
| 87454 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
|---|
| 87455 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
|---|
| 87456 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
|---|
| 87457 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
|---|
| 87458 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
|---|
| 87459 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
|---|
| 87460 | #define PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
|---|
| 87461 | //PSWUSCFG0_1_EXT_BRIDGE_CNTL |
|---|
| 87462 | #define PSWUSCFG0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
|---|
| 87463 | #define PSWUSCFG0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
|---|
| 87464 | //PSWUSCFG0_1_VENDOR_CAP_LIST |
|---|
| 87465 | #define PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 87466 | #define PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 87467 | #define PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 87468 | #define PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 87469 | #define PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 87470 | #define PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 87471 | //PSWUSCFG0_1_ADAPTER_ID_W |
|---|
| 87472 | #define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 87473 | #define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 87474 | #define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 87475 | #define PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 87476 | //PSWUSCFG0_1_PMI_CAP_LIST |
|---|
| 87477 | #define PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 87478 | #define PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 87479 | #define PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 87480 | #define PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 87481 | //PSWUSCFG0_1_PMI_CAP |
|---|
| 87482 | #define PSWUSCFG0_1_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 87483 | #define PSWUSCFG0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 87484 | #define PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 87485 | #define PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 87486 | #define PSWUSCFG0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 87487 | #define PSWUSCFG0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 87488 | #define PSWUSCFG0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 87489 | #define PSWUSCFG0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 87490 | #define PSWUSCFG0_1_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 87491 | #define PSWUSCFG0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 87492 | #define PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 87493 | #define PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 87494 | #define PSWUSCFG0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 87495 | #define PSWUSCFG0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 87496 | #define PSWUSCFG0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 87497 | #define PSWUSCFG0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 87498 | //PSWUSCFG0_1_PMI_STATUS_CNTL |
|---|
| 87499 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 87500 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 87501 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 87502 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 87503 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 87504 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 87505 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 87506 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 87507 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 87508 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 87509 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 87510 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 87511 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 87512 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 87513 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 87514 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 87515 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 87516 | #define PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 87517 | //PSWUSCFG0_1_PCIE_CAP_LIST |
|---|
| 87518 | #define PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 87519 | #define PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 87520 | #define PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 87521 | #define PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 87522 | //PSWUSCFG0_1_PCIE_CAP |
|---|
| 87523 | #define PSWUSCFG0_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 87524 | #define PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 87525 | #define PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 87526 | #define PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 87527 | #define PSWUSCFG0_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 87528 | #define PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 87529 | #define PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 87530 | #define PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 87531 | //PSWUSCFG0_1_DEVICE_CAP |
|---|
| 87532 | #define PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 87533 | #define PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 87534 | #define PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 87535 | #define PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 87536 | #define PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 87537 | #define PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 87538 | #define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 87539 | #define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 87540 | #define PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 87541 | #define PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 87542 | #define PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 87543 | #define PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 87544 | #define PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 87545 | #define PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 87546 | #define PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 87547 | #define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 87548 | #define PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 87549 | #define PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 87550 | //PSWUSCFG0_1_DEVICE_CNTL |
|---|
| 87551 | #define PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 87552 | #define PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 87553 | #define PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 87554 | #define PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 87555 | #define PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 87556 | #define PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 87557 | #define PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 87558 | #define PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 87559 | #define PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 87560 | #define PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 87561 | #define PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 87562 | #define PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
|---|
| 87563 | #define PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 87564 | #define PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 87565 | #define PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 87566 | #define PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 87567 | #define PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 87568 | #define PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 87569 | #define PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 87570 | #define PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 87571 | #define PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 87572 | #define PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 87573 | #define PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 87574 | #define PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
|---|
| 87575 | //PSWUSCFG0_1_DEVICE_STATUS |
|---|
| 87576 | #define PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 87577 | #define PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 87578 | #define PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 87579 | #define PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 87580 | #define PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 87581 | #define PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 87582 | #define PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 87583 | #define PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 87584 | #define PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 87585 | #define PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 87586 | #define PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 87587 | #define PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 87588 | //PSWUSCFG0_1_LINK_CAP |
|---|
| 87589 | #define PSWUSCFG0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 87590 | #define PSWUSCFG0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 87591 | #define PSWUSCFG0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 87592 | #define PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 87593 | #define PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 87594 | #define PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 87595 | #define PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 87596 | #define PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 87597 | #define PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 87598 | #define PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 87599 | #define PSWUSCFG0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 87600 | #define PSWUSCFG0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 87601 | #define PSWUSCFG0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 87602 | #define PSWUSCFG0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 87603 | #define PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 87604 | #define PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 87605 | #define PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 87606 | #define PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 87607 | #define PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 87608 | #define PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 87609 | #define PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 87610 | #define PSWUSCFG0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 87611 | //PSWUSCFG0_1_LINK_CNTL |
|---|
| 87612 | #define PSWUSCFG0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 87613 | #define PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 87614 | #define PSWUSCFG0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 87615 | #define PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 87616 | #define PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 87617 | #define PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 87618 | #define PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 87619 | #define PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 87620 | #define PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 87621 | #define PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 87622 | #define PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 87623 | #define PSWUSCFG0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 87624 | #define PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 87625 | #define PSWUSCFG0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 87626 | #define PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 87627 | #define PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 87628 | #define PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 87629 | #define PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 87630 | #define PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 87631 | #define PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 87632 | #define PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 87633 | #define PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 87634 | //PSWUSCFG0_1_LINK_STATUS |
|---|
| 87635 | #define PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 87636 | #define PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 87637 | #define PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 87638 | #define PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 87639 | #define PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 87640 | #define PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 87641 | #define PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 87642 | #define PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 87643 | #define PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 87644 | #define PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 87645 | #define PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 87646 | #define PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 87647 | #define PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 87648 | #define PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 87649 | //PSWUSCFG0_1_DEVICE_CAP2 |
|---|
| 87650 | #define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 87651 | #define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 87652 | #define PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 87653 | #define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 87654 | #define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 87655 | #define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 87656 | #define PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 87657 | #define PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 87658 | #define PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 87659 | #define PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 87660 | #define PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 87661 | #define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 87662 | #define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 87663 | #define PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 87664 | #define PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 87665 | #define PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 87666 | #define PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 87667 | #define PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 87668 | #define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 87669 | #define PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 87670 | #define PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 87671 | #define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 87672 | #define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 87673 | #define PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 87674 | #define PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 87675 | #define PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 87676 | #define PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 87677 | #define PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 87678 | #define PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 87679 | #define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 87680 | #define PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 87681 | #define PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 87682 | #define PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 87683 | #define PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 87684 | #define PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 87685 | #define PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 87686 | //PSWUSCFG0_1_DEVICE_CNTL2 |
|---|
| 87687 | #define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 87688 | #define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 87689 | #define PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 87690 | #define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 87691 | #define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 87692 | #define PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 87693 | #define PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 87694 | #define PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 87695 | #define PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 87696 | #define PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 87697 | #define PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 87698 | #define PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 87699 | #define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 87700 | #define PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 87701 | #define PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 87702 | #define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 87703 | #define PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 87704 | #define PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 87705 | #define PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 87706 | #define PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 87707 | #define PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 87708 | #define PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 87709 | #define PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 87710 | #define PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 87711 | //PSWUSCFG0_1_DEVICE_STATUS2 |
|---|
| 87712 | #define PSWUSCFG0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 87713 | #define PSWUSCFG0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 87714 | //PSWUSCFG0_1_LINK_CAP2 |
|---|
| 87715 | #define PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 87716 | #define PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 87717 | #define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 87718 | #define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 87719 | #define PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 87720 | #define PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 87721 | #define PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f |
|---|
| 87722 | #define PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 87723 | #define PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 87724 | #define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 87725 | #define PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 87726 | #define PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 87727 | #define PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 87728 | #define PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L |
|---|
| 87729 | //PSWUSCFG0_1_LINK_CNTL2 |
|---|
| 87730 | #define PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 87731 | #define PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 87732 | #define PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 87733 | #define PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 87734 | #define PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 87735 | #define PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 87736 | #define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 87737 | #define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 87738 | #define PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 87739 | #define PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 87740 | #define PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 87741 | #define PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 87742 | #define PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 87743 | #define PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 87744 | #define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 87745 | #define PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 87746 | //PSWUSCFG0_1_LINK_STATUS2 |
|---|
| 87747 | #define PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 87748 | #define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 87749 | #define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 87750 | #define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 87751 | #define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 87752 | #define PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 87753 | #define PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 87754 | #define PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 87755 | #define PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 87756 | #define PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 87757 | #define PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 87758 | #define PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 87759 | #define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 87760 | #define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 87761 | #define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 87762 | #define PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 87763 | #define PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 87764 | #define PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 87765 | #define PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 87766 | #define PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 87767 | #define PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 87768 | #define PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 87769 | //PSWUSCFG0_1_MSI_CAP_LIST |
|---|
| 87770 | #define PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 87771 | #define PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 87772 | #define PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 87773 | #define PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 87774 | //PSWUSCFG0_1_MSI_MSG_CNTL |
|---|
| 87775 | #define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 87776 | #define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 87777 | #define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 87778 | #define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 87779 | #define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 87780 | #define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 87781 | #define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 87782 | #define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 87783 | #define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 87784 | #define PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 87785 | //PSWUSCFG0_1_MSI_MSG_ADDR_LO |
|---|
| 87786 | #define PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 87787 | #define PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 87788 | //PSWUSCFG0_1_MSI_MSG_ADDR_HI |
|---|
| 87789 | #define PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 87790 | #define PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 87791 | //PSWUSCFG0_1_MSI_MSG_DATA |
|---|
| 87792 | #define PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 87793 | #define PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 87794 | //PSWUSCFG0_1_MSI_MSG_DATA_64 |
|---|
| 87795 | #define PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 87796 | #define PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 87797 | //PSWUSCFG0_1_SSID_CAP_LIST |
|---|
| 87798 | #define PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 87799 | #define PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 87800 | #define PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 87801 | #define PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 87802 | //PSWUSCFG0_1_SSID_CAP |
|---|
| 87803 | #define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 87804 | #define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 87805 | #define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 87806 | #define PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 87807 | //PSWUSCFG0_1_MSI_MAP_CAP_LIST |
|---|
| 87808 | #define PSWUSCFG0_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 87809 | #define PSWUSCFG0_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 87810 | #define PSWUSCFG0_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 87811 | #define PSWUSCFG0_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 87812 | //PSWUSCFG0_1_MSI_MAP_CAP |
|---|
| 87813 | #define PSWUSCFG0_1_MSI_MAP_CAP__EN__SHIFT 0x0 |
|---|
| 87814 | #define PSWUSCFG0_1_MSI_MAP_CAP__FIXD__SHIFT 0x1 |
|---|
| 87815 | #define PSWUSCFG0_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
|---|
| 87816 | #define PSWUSCFG0_1_MSI_MAP_CAP__EN_MASK 0x0001L |
|---|
| 87817 | #define PSWUSCFG0_1_MSI_MAP_CAP__FIXD_MASK 0x0002L |
|---|
| 87818 | #define PSWUSCFG0_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
|---|
| 87819 | //PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 87820 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 87821 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 87822 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 87823 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 87824 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 87825 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 87826 | //PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 87827 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 87828 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 87829 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 87830 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 87831 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 87832 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 87833 | //PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 87834 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 87835 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 87836 | //PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 87837 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 87838 | #define PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 87839 | //PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST |
|---|
| 87840 | #define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 87841 | #define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 87842 | #define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 87843 | #define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 87844 | #define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 87845 | #define PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 87846 | //PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1 |
|---|
| 87847 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 87848 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 87849 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 87850 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 87851 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 87852 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 87853 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 87854 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 87855 | //PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2 |
|---|
| 87856 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 87857 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 87858 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 87859 | #define PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 87860 | //PSWUSCFG0_1_PCIE_PORT_VC_CNTL |
|---|
| 87861 | #define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 87862 | #define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 87863 | #define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 87864 | #define PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 87865 | //PSWUSCFG0_1_PCIE_PORT_VC_STATUS |
|---|
| 87866 | #define PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 87867 | #define PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 87868 | //PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP |
|---|
| 87869 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 87870 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 87871 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 87872 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 87873 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 87874 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 87875 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
|---|
| 87876 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 87877 | //PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL |
|---|
| 87878 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 87879 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 87880 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 87881 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 87882 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 87883 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 87884 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 87885 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 87886 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 87887 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 87888 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 87889 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 87890 | //PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS |
|---|
| 87891 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 87892 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 87893 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 87894 | #define PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 87895 | //PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP |
|---|
| 87896 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 87897 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 87898 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 87899 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 87900 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 87901 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 87902 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L |
|---|
| 87903 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 87904 | //PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL |
|---|
| 87905 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 87906 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 87907 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 87908 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 87909 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 87910 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 87911 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 87912 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 87913 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 87914 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 87915 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 87916 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 87917 | //PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS |
|---|
| 87918 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 87919 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 87920 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 87921 | #define PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 87922 | //PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 87923 | #define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 87924 | #define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 87925 | #define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 87926 | #define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 87927 | #define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 87928 | #define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 87929 | //PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 87930 | #define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 87931 | #define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 87932 | //PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 87933 | #define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 87934 | #define PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 87935 | //PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 87936 | #define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 87937 | #define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 87938 | #define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 87939 | #define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 87940 | #define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 87941 | #define PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 87942 | //PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 87943 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 87944 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 87945 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 87946 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 87947 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 87948 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 87949 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 87950 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 87951 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 87952 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 87953 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 87954 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 87955 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 87956 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 87957 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 87958 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 87959 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
|---|
| 87960 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 87961 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 87962 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 87963 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 87964 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 87965 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 87966 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 87967 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 87968 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 87969 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 87970 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 87971 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 87972 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 87973 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 87974 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 87975 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 87976 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
|---|
| 87977 | //PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK |
|---|
| 87978 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 87979 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 87980 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 87981 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 87982 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 87983 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 87984 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 87985 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 87986 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 87987 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 87988 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 87989 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 87990 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 87991 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 87992 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 87993 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 87994 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
|---|
| 87995 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 87996 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 87997 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 87998 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 87999 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 88000 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 88001 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 88002 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 88003 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 88004 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 88005 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 88006 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 88007 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 88008 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 88009 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 88010 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 88011 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
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| 88012 | //PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY |
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| 88013 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 88014 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 88015 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 88016 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 88017 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 88018 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 88019 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 88020 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 88021 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 88022 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 88023 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 88024 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 88025 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 88026 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 88027 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 88028 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 88029 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
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| 88030 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 88031 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 88032 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 88033 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 88034 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 88035 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 88036 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 88037 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 88038 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 88039 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 88040 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 88041 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 88042 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 88043 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 88044 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 88045 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 88046 | #define PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
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| 88047 | //PSWUSCFG0_1_PCIE_CORR_ERR_STATUS |
|---|
| 88048 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 88049 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 88050 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 88051 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 88052 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 88053 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 88054 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 88055 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 88056 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 88057 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 88058 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 88059 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 88060 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 88061 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 88062 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 88063 | #define PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 88064 | //PSWUSCFG0_1_PCIE_CORR_ERR_MASK |
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| 88065 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 88066 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 88067 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 88068 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 88069 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 88070 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 88071 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 88072 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 88073 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 88074 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 88075 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 88076 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
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| 88077 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
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| 88078 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
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| 88079 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
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| 88080 | #define PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 88081 | //PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL |
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| 88082 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 88083 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 88084 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 88085 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
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| 88086 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
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| 88087 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
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| 88088 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
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| 88089 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
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| 88090 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
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| 88091 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
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| 88092 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
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| 88093 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
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| 88094 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
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| 88095 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
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| 88096 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
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| 88097 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
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| 88098 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
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| 88099 | #define PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
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| 88100 | //PSWUSCFG0_1_PCIE_HDR_LOG0 |
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| 88101 | #define PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
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| 88102 | #define PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
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| 88103 | //PSWUSCFG0_1_PCIE_HDR_LOG1 |
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| 88104 | #define PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
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| 88105 | #define PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
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| 88106 | //PSWUSCFG0_1_PCIE_HDR_LOG2 |
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| 88107 | #define PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
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| 88108 | #define PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
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| 88109 | //PSWUSCFG0_1_PCIE_HDR_LOG3 |
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| 88110 | #define PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
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| 88111 | #define PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
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| 88112 | //PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0 |
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| 88113 | #define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
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| 88114 | #define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 88115 | //PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1 |
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| 88116 | #define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
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| 88117 | #define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 88118 | //PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2 |
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| 88119 | #define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
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| 88120 | #define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 88121 | //PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3 |
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| 88122 | #define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
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| 88123 | #define PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 88124 | //PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST |
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| 88125 | #define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 88126 | #define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 88127 | #define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 88128 | #define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 88129 | #define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 88130 | #define PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 88131 | //PSWUSCFG0_1_PCIE_LINK_CNTL3 |
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| 88132 | #define PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
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| 88133 | #define PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
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| 88134 | #define PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
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| 88135 | #define PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
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| 88136 | #define PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
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| 88137 | #define PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
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| 88138 | //PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS |
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| 88139 | #define PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
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| 88140 | #define PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
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| 88141 | //PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL |
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| 88142 | #define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 88143 | #define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 88144 | #define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 88145 | #define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 88146 | #define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 88147 | #define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 88148 | #define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 88149 | #define PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 88150 | //PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL |
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| 88151 | #define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 88152 | #define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 88153 | #define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 88154 | #define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 88155 | #define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 88156 | #define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 88157 | #define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 88158 | #define PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 88159 | //PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL |
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| 88160 | #define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 88161 | #define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 88162 | #define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 88163 | #define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 88164 | #define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 88165 | #define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 88166 | #define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 88167 | #define PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 88168 | //PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL |
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| 88169 | #define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 88170 | #define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88171 | #define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 88172 | #define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 88173 | #define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88174 | #define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88175 | #define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88176 | #define PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 88177 | //PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL |
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| 88178 | #define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88179 | #define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88180 | #define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88181 | #define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88182 | #define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88183 | #define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88184 | #define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88185 | #define PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88186 | //PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 88187 | #define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88188 | #define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88189 | #define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88190 | #define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88191 | #define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88192 | #define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88193 | #define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88194 | #define PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88195 | //PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 88196 | #define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88197 | #define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88198 | #define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88199 | #define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88200 | #define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88201 | #define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88202 | #define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88203 | #define PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88204 | //PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 88205 | #define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88206 | #define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88207 | #define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88208 | #define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88209 | #define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88210 | #define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88211 | #define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88212 | #define PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88213 | //PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 88214 | #define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88215 | #define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88216 | #define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88217 | #define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88218 | #define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88219 | #define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88220 | #define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88221 | #define PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88222 | //PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 88223 | #define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88224 | #define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88225 | #define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88226 | #define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88227 | #define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88228 | #define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88229 | #define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88230 | #define PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88231 | //PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 88232 | #define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88233 | #define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88234 | #define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88235 | #define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88236 | #define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88237 | #define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88238 | #define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88239 | #define PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88240 | //PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 88241 | #define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88242 | #define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88243 | #define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88244 | #define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88245 | #define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88246 | #define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88247 | #define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88248 | #define PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88249 | //PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 88250 | #define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88251 | #define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88252 | #define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88253 | #define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88254 | #define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88255 | #define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88256 | #define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88257 | #define PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88258 | //PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 88259 | #define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88260 | #define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88261 | #define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88262 | #define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88263 | #define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88264 | #define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88265 | #define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88266 | #define PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88267 | //PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 88268 | #define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88269 | #define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88270 | #define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88271 | #define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88272 | #define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88273 | #define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88274 | #define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88275 | #define PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88276 | //PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 88277 | #define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 88278 | #define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 88279 | #define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 88280 | #define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 88281 | #define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 88282 | #define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 88283 | #define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 88284 | #define PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 88285 | //PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST |
|---|
| 88286 | #define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 88287 | #define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 88288 | #define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 88289 | #define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 88290 | #define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 88291 | #define PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 88292 | //PSWUSCFG0_1_PCIE_ACS_CAP |
|---|
| 88293 | #define PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 88294 | #define PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 88295 | #define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 88296 | #define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 88297 | #define PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 88298 | #define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 88299 | #define PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 88300 | #define PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 88301 | #define PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 88302 | #define PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 88303 | #define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 88304 | #define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 88305 | #define PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 88306 | #define PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 88307 | #define PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 88308 | #define PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 88309 | //PSWUSCFG0_1_PCIE_ACS_CNTL |
|---|
| 88310 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 88311 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 88312 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 88313 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 88314 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 88315 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 88316 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 88317 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 88318 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 88319 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 88320 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 88321 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 88322 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 88323 | #define PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 88324 | //PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST |
|---|
| 88325 | #define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 88326 | #define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 88327 | #define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 88328 | #define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 88329 | #define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 88330 | #define PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 88331 | //PSWUSCFG0_1_PCIE_MC_CAP |
|---|
| 88332 | #define PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
|---|
| 88333 | #define PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
|---|
| 88334 | #define PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
|---|
| 88335 | #define PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
|---|
| 88336 | #define PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
|---|
| 88337 | #define PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
|---|
| 88338 | //PSWUSCFG0_1_PCIE_MC_CNTL |
|---|
| 88339 | #define PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
|---|
| 88340 | #define PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
|---|
| 88341 | #define PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
|---|
| 88342 | #define PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
|---|
| 88343 | //PSWUSCFG0_1_PCIE_MC_ADDR0 |
|---|
| 88344 | #define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
|---|
| 88345 | #define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
|---|
| 88346 | #define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
|---|
| 88347 | #define PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
|---|
| 88348 | //PSWUSCFG0_1_PCIE_MC_ADDR1 |
|---|
| 88349 | #define PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
|---|
| 88350 | #define PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
|---|
| 88351 | //PSWUSCFG0_1_PCIE_MC_RCV0 |
|---|
| 88352 | #define PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
|---|
| 88353 | #define PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
|---|
| 88354 | //PSWUSCFG0_1_PCIE_MC_RCV1 |
|---|
| 88355 | #define PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
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| 88356 | #define PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
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| 88357 | //PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0 |
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| 88358 | #define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
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| 88359 | #define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
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| 88360 | //PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1 |
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| 88361 | #define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
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| 88362 | #define PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
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| 88363 | //PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
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| 88364 | #define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
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| 88365 | #define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
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| 88366 | //PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
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| 88367 | #define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
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| 88368 | #define PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
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| 88369 | //PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0 |
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| 88370 | #define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
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| 88371 | #define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
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| 88372 | #define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
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| 88373 | #define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
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| 88374 | //PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1 |
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| 88375 | #define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
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| 88376 | #define PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
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| 88377 | //PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST |
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| 88378 | #define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 88379 | #define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 88380 | #define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 88381 | #define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 88382 | #define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 88383 | #define PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 88384 | //PSWUSCFG0_1_PCIE_LTR_CAP |
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| 88385 | #define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
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| 88386 | #define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
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| 88387 | #define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
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| 88388 | #define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
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| 88389 | #define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
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| 88390 | #define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
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| 88391 | #define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
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| 88392 | #define PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
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| 88393 | //PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST |
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| 88394 | #define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 88395 | #define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 88396 | #define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 88397 | #define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 88398 | #define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 88399 | #define PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 88400 | //PSWUSCFG0_1_PCIE_ARI_CAP |
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| 88401 | #define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
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| 88402 | #define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
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| 88403 | #define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
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| 88404 | #define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
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| 88405 | #define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
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| 88406 | #define PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
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| 88407 | //PSWUSCFG0_1_PCIE_ARI_CNTL |
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| 88408 | #define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
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| 88409 | #define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
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| 88410 | #define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 88411 | #define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 88412 | #define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
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| 88413 | #define PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
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| 88414 | //PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST |
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| 88415 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 88416 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 88417 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 88418 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 88419 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 88420 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 88421 | //PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP |
|---|
| 88422 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
|---|
| 88423 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
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| 88424 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
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| 88425 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
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| 88426 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
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| 88427 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
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| 88428 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
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| 88429 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
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| 88430 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
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| 88431 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
|---|
| 88432 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
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| 88433 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
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| 88434 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
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| 88435 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
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| 88436 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
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| 88437 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
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| 88438 | //PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL |
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| 88439 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
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| 88440 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
|---|
| 88441 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
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| 88442 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
|---|
| 88443 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
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| 88444 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
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| 88445 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
|---|
| 88446 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
|---|
| 88447 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
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| 88448 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
|---|
| 88449 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
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| 88450 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
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| 88451 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
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| 88452 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
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| 88453 | //PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2 |
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| 88454 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
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| 88455 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
|---|
| 88456 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
|---|
| 88457 | #define PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
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| 88458 | //PSWUSCFG0_1_PCIE_ESM_CAP_LIST |
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| 88459 | #define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 88460 | #define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 88461 | #define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 88462 | #define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 88463 | #define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 88464 | #define PSWUSCFG0_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 88465 | //PSWUSCFG0_1_PCIE_ESM_HEADER_1 |
|---|
| 88466 | #define 0x0 |
|---|
| 88467 | #define 0x10 |
|---|
| 88468 | #define 0x14 |
|---|
| 88469 | #define 0x0000FFFFL |
|---|
| 88470 | #define 0x000F0000L |
|---|
| 88471 | #define 0xFFF00000L |
|---|
| 88472 | //PSWUSCFG0_1_PCIE_ESM_HEADER_2 |
|---|
| 88473 | #define 0x0 |
|---|
| 88474 | #define 0xFFFFL |
|---|
| 88475 | //PSWUSCFG0_1_PCIE_ESM_STATUS |
|---|
| 88476 | #define PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
|---|
| 88477 | #define PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
|---|
| 88478 | #define PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
|---|
| 88479 | #define PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
|---|
| 88480 | //PSWUSCFG0_1_PCIE_ESM_CTRL |
|---|
| 88481 | #define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
|---|
| 88482 | #define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
|---|
| 88483 | #define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
|---|
| 88484 | #define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
|---|
| 88485 | #define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
|---|
| 88486 | #define PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
|---|
| 88487 | //PSWUSCFG0_1_PCIE_ESM_CAP_1 |
|---|
| 88488 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
|---|
| 88489 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
|---|
| 88490 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
|---|
| 88491 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
|---|
| 88492 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
|---|
| 88493 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
|---|
| 88494 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
|---|
| 88495 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
|---|
| 88496 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
|---|
| 88497 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
|---|
| 88498 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
|---|
| 88499 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
|---|
| 88500 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
|---|
| 88501 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
|---|
| 88502 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
|---|
| 88503 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
|---|
| 88504 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
|---|
| 88505 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
|---|
| 88506 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
|---|
| 88507 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
|---|
| 88508 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
|---|
| 88509 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
|---|
| 88510 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
|---|
| 88511 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
|---|
| 88512 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
|---|
| 88513 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
|---|
| 88514 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
|---|
| 88515 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
|---|
| 88516 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
|---|
| 88517 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
|---|
| 88518 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
|---|
| 88519 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
|---|
| 88520 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
|---|
| 88521 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
|---|
| 88522 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
|---|
| 88523 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
|---|
| 88524 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
|---|
| 88525 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
|---|
| 88526 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
|---|
| 88527 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
|---|
| 88528 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
|---|
| 88529 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
|---|
| 88530 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
|---|
| 88531 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
|---|
| 88532 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
|---|
| 88533 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
|---|
| 88534 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
|---|
| 88535 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
|---|
| 88536 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
|---|
| 88537 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
|---|
| 88538 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
|---|
| 88539 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
|---|
| 88540 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
|---|
| 88541 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
|---|
| 88542 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
|---|
| 88543 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
|---|
| 88544 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
|---|
| 88545 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
|---|
| 88546 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
|---|
| 88547 | #define PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
|---|
| 88548 | //PSWUSCFG0_1_PCIE_ESM_CAP_2 |
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| 88549 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
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| 88550 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
|---|
| 88551 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
|---|
| 88552 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
|---|
| 88553 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
|---|
| 88554 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
|---|
| 88555 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
|---|
| 88556 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
|---|
| 88557 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
|---|
| 88558 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
|---|
| 88559 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
|---|
| 88560 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
|---|
| 88561 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
|---|
| 88562 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
|---|
| 88563 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
|---|
| 88564 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
|---|
| 88565 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
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| 88566 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
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| 88567 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
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| 88568 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
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| 88569 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
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| 88570 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
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| 88571 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
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| 88572 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
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| 88573 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
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| 88574 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
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| 88575 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
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| 88576 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
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| 88577 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
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| 88578 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
|---|
| 88579 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
|---|
| 88580 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
|---|
| 88581 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
|---|
| 88582 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
|---|
| 88583 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
|---|
| 88584 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
|---|
| 88585 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
|---|
| 88586 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
|---|
| 88587 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
|---|
| 88588 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
|---|
| 88589 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
|---|
| 88590 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
|---|
| 88591 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
|---|
| 88592 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
|---|
| 88593 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
|---|
| 88594 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
|---|
| 88595 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
|---|
| 88596 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
|---|
| 88597 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
|---|
| 88598 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
|---|
| 88599 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
|---|
| 88600 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
|---|
| 88601 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
|---|
| 88602 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
|---|
| 88603 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
|---|
| 88604 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
|---|
| 88605 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
|---|
| 88606 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
|---|
| 88607 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
|---|
| 88608 | #define PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
|---|
| 88609 | //PSWUSCFG0_1_PCIE_ESM_CAP_3 |
|---|
| 88610 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
|---|
| 88611 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
|---|
| 88612 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
|---|
| 88613 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
|---|
| 88614 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
|---|
| 88615 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
|---|
| 88616 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
|---|
| 88617 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
|---|
| 88618 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
|---|
| 88619 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
|---|
| 88620 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
|---|
| 88621 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
|---|
| 88622 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
|---|
| 88623 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
|---|
| 88624 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
|---|
| 88625 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
|---|
| 88626 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
|---|
| 88627 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
|---|
| 88628 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
|---|
| 88629 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
|---|
| 88630 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
|---|
| 88631 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
|---|
| 88632 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
|---|
| 88633 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
|---|
| 88634 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
|---|
| 88635 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
|---|
| 88636 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
|---|
| 88637 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
|---|
| 88638 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
|---|
| 88639 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
|---|
| 88640 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
|---|
| 88641 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
|---|
| 88642 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
|---|
| 88643 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
|---|
| 88644 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
|---|
| 88645 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
|---|
| 88646 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
|---|
| 88647 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
|---|
| 88648 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
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| 88649 | #define PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
|---|
| 88650 | //PSWUSCFG0_1_PCIE_ESM_CAP_4 |
|---|
| 88651 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
|---|
| 88652 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
|---|
| 88653 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
|---|
| 88654 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
|---|
| 88655 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
|---|
| 88656 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
|---|
| 88657 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
|---|
| 88658 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
|---|
| 88659 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
|---|
| 88660 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
|---|
| 88661 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
|---|
| 88662 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
|---|
| 88663 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
|---|
| 88664 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
|---|
| 88665 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
|---|
| 88666 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
|---|
| 88667 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
|---|
| 88668 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
|---|
| 88669 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
|---|
| 88670 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
|---|
| 88671 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
|---|
| 88672 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
|---|
| 88673 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
|---|
| 88674 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
|---|
| 88675 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
|---|
| 88676 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
|---|
| 88677 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
|---|
| 88678 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
|---|
| 88679 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
|---|
| 88680 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
|---|
| 88681 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
|---|
| 88682 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
|---|
| 88683 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
|---|
| 88684 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
|---|
| 88685 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
|---|
| 88686 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
|---|
| 88687 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
|---|
| 88688 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
|---|
| 88689 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
|---|
| 88690 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
|---|
| 88691 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
|---|
| 88692 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
|---|
| 88693 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
|---|
| 88694 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
|---|
| 88695 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
|---|
| 88696 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
|---|
| 88697 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
|---|
| 88698 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
|---|
| 88699 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
|---|
| 88700 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
|---|
| 88701 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
|---|
| 88702 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
|---|
| 88703 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
|---|
| 88704 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
|---|
| 88705 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
|---|
| 88706 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
|---|
| 88707 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
|---|
| 88708 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
|---|
| 88709 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
|---|
| 88710 | #define PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
|---|
| 88711 | //PSWUSCFG0_1_PCIE_ESM_CAP_5 |
|---|
| 88712 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
|---|
| 88713 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
|---|
| 88714 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
|---|
| 88715 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
|---|
| 88716 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
|---|
| 88717 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
|---|
| 88718 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
|---|
| 88719 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
|---|
| 88720 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
|---|
| 88721 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
|---|
| 88722 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
|---|
| 88723 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
|---|
| 88724 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
|---|
| 88725 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
|---|
| 88726 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
|---|
| 88727 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
|---|
| 88728 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
|---|
| 88729 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
|---|
| 88730 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
|---|
| 88731 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
|---|
| 88732 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
|---|
| 88733 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
|---|
| 88734 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
|---|
| 88735 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
|---|
| 88736 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
|---|
| 88737 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
|---|
| 88738 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
|---|
| 88739 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
|---|
| 88740 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
|---|
| 88741 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
|---|
| 88742 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
|---|
| 88743 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
|---|
| 88744 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
|---|
| 88745 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
|---|
| 88746 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
|---|
| 88747 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
|---|
| 88748 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
|---|
| 88749 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
|---|
| 88750 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
|---|
| 88751 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
|---|
| 88752 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
|---|
| 88753 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
|---|
| 88754 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
|---|
| 88755 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
|---|
| 88756 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
|---|
| 88757 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
|---|
| 88758 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
|---|
| 88759 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
|---|
| 88760 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
|---|
| 88761 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
|---|
| 88762 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
|---|
| 88763 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
|---|
| 88764 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
|---|
| 88765 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
|---|
| 88766 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
|---|
| 88767 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
|---|
| 88768 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
|---|
| 88769 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
|---|
| 88770 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
|---|
| 88771 | #define PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
|---|
| 88772 | //PSWUSCFG0_1_PCIE_ESM_CAP_6 |
|---|
| 88773 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
|---|
| 88774 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
|---|
| 88775 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
|---|
| 88776 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
|---|
| 88777 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
|---|
| 88778 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
|---|
| 88779 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
|---|
| 88780 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
|---|
| 88781 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
|---|
| 88782 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
|---|
| 88783 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
|---|
| 88784 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
|---|
| 88785 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
|---|
| 88786 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
|---|
| 88787 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
|---|
| 88788 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
|---|
| 88789 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
|---|
| 88790 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
|---|
| 88791 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
|---|
| 88792 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
|---|
| 88793 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
|---|
| 88794 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
|---|
| 88795 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
|---|
| 88796 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
|---|
| 88797 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
|---|
| 88798 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
|---|
| 88799 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
|---|
| 88800 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
|---|
| 88801 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
|---|
| 88802 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
|---|
| 88803 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
|---|
| 88804 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
|---|
| 88805 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
|---|
| 88806 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
|---|
| 88807 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
|---|
| 88808 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
|---|
| 88809 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
|---|
| 88810 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
|---|
| 88811 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
|---|
| 88812 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
|---|
| 88813 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
|---|
| 88814 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
|---|
| 88815 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
|---|
| 88816 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
|---|
| 88817 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
|---|
| 88818 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
|---|
| 88819 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
|---|
| 88820 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
|---|
| 88821 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
|---|
| 88822 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
|---|
| 88823 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
|---|
| 88824 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
|---|
| 88825 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
|---|
| 88826 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
|---|
| 88827 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
|---|
| 88828 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
|---|
| 88829 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
|---|
| 88830 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
|---|
| 88831 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
|---|
| 88832 | #define PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
|---|
| 88833 | //PSWUSCFG0_1_PCIE_ESM_CAP_7 |
|---|
| 88834 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
|---|
| 88835 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
|---|
| 88836 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
|---|
| 88837 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
|---|
| 88838 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
|---|
| 88839 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
|---|
| 88840 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
|---|
| 88841 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
|---|
| 88842 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
|---|
| 88843 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
|---|
| 88844 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
|---|
| 88845 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
|---|
| 88846 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
|---|
| 88847 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
|---|
| 88848 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
|---|
| 88849 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
|---|
| 88850 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
|---|
| 88851 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
|---|
| 88852 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
|---|
| 88853 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
|---|
| 88854 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
|---|
| 88855 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
|---|
| 88856 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
|---|
| 88857 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
|---|
| 88858 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
|---|
| 88859 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
|---|
| 88860 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
|---|
| 88861 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
|---|
| 88862 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
|---|
| 88863 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
|---|
| 88864 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
|---|
| 88865 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
|---|
| 88866 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
|---|
| 88867 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
|---|
| 88868 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
|---|
| 88869 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
|---|
| 88870 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
|---|
| 88871 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
|---|
| 88872 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
|---|
| 88873 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
|---|
| 88874 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
|---|
| 88875 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
|---|
| 88876 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
|---|
| 88877 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
|---|
| 88878 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
|---|
| 88879 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
|---|
| 88880 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
|---|
| 88881 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
|---|
| 88882 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
|---|
| 88883 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
|---|
| 88884 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
|---|
| 88885 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
|---|
| 88886 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
|---|
| 88887 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
|---|
| 88888 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
|---|
| 88889 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
|---|
| 88890 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
|---|
| 88891 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
|---|
| 88892 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
|---|
| 88893 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
|---|
| 88894 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
|---|
| 88895 | #define PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
|---|
| 88896 | //PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST |
|---|
| 88897 | #define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 88898 | #define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 88899 | #define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 88900 | #define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 88901 | #define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 88902 | #define PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 88903 | //PSWUSCFG0_1_DATA_LINK_FEATURE_CAP |
|---|
| 88904 | #define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0 |
|---|
| 88905 | #define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1 |
|---|
| 88906 | #define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
|---|
| 88907 | #define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L |
|---|
| 88908 | #define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL |
|---|
| 88909 | #define PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
|---|
| 88910 | //PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS |
|---|
| 88911 | #define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 88912 | #define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
|---|
| 88913 | #define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 88914 | #define PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
|---|
| 88915 | //PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST |
|---|
| 88916 | #define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 88917 | #define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 88918 | #define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 88919 | #define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 88920 | #define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 88921 | #define PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 88922 | //PSWUSCFG0_1_LINK_CAP_16GT |
|---|
| 88923 | #define PSWUSCFG0_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
|---|
| 88924 | #define PSWUSCFG0_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 88925 | //PSWUSCFG0_1_LINK_CNTL_16GT |
|---|
| 88926 | #define PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
|---|
| 88927 | #define PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 88928 | //PSWUSCFG0_1_LINK_STATUS_16GT |
|---|
| 88929 | #define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
|---|
| 88930 | #define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
|---|
| 88931 | #define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
|---|
| 88932 | #define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
|---|
| 88933 | #define PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
|---|
| 88934 | #define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
|---|
| 88935 | #define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
|---|
| 88936 | #define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
|---|
| 88937 | #define PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
|---|
| 88938 | #define PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
|---|
| 88939 | //PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT |
|---|
| 88940 | #define PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 88941 | #define PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 88942 | //PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT |
|---|
| 88943 | #define PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 88944 | #define PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 88945 | //PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT |
|---|
| 88946 | #define PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 88947 | #define PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 88948 | //PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT |
|---|
| 88949 | #define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 88950 | #define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 88951 | #define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 88952 | #define PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 88953 | //PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT |
|---|
| 88954 | #define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 88955 | #define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 88956 | #define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 88957 | #define PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 88958 | //PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT |
|---|
| 88959 | #define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 88960 | #define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 88961 | #define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 88962 | #define PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 88963 | //PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT |
|---|
| 88964 | #define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 88965 | #define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 88966 | #define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 88967 | #define PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 88968 | //PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT |
|---|
| 88969 | #define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 88970 | #define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 88971 | #define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 88972 | #define PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 88973 | //PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT |
|---|
| 88974 | #define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 88975 | #define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 88976 | #define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 88977 | #define PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 88978 | //PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT |
|---|
| 88979 | #define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 88980 | #define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 88981 | #define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 88982 | #define PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 88983 | //PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT |
|---|
| 88984 | #define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 88985 | #define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 88986 | #define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 88987 | #define PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 88988 | //PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT |
|---|
| 88989 | #define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 88990 | #define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 88991 | #define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 88992 | #define PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 88993 | //PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT |
|---|
| 88994 | #define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 88995 | #define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 88996 | #define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 88997 | #define PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 88998 | //PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT |
|---|
| 88999 | #define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89000 | #define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89001 | #define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 89002 | #define PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 89003 | //PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT |
|---|
| 89004 | #define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89005 | #define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89006 | #define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 89007 | #define PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 89008 | //PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT |
|---|
| 89009 | #define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89010 | #define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89011 | #define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 89012 | #define PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 89013 | //PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT |
|---|
| 89014 | #define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89015 | #define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89016 | #define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 89017 | #define PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 89018 | //PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 89019 | #define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89020 | #define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89021 | #define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 89022 | #define PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 89023 | //PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 89024 | #define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89025 | #define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89026 | #define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 89027 | #define PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 89028 | //PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 89029 | #define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 89030 | #define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 89031 | #define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 89032 | #define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 89033 | #define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 89034 | #define PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 89035 | //PSWUSCFG0_1_MARGINING_PORT_CAP |
|---|
| 89036 | #define PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 89037 | #define PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 89038 | //PSWUSCFG0_1_MARGINING_PORT_STATUS |
|---|
| 89039 | #define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
|---|
| 89040 | #define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
|---|
| 89041 | #define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
|---|
| 89042 | #define PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
|---|
| 89043 | //PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL |
|---|
| 89044 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89045 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89046 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89047 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89048 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89049 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89050 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 89051 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89052 | //PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS |
|---|
| 89053 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89054 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89055 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89056 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89057 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89058 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89059 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89060 | #define PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89061 | //PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL |
|---|
| 89062 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89063 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89064 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89065 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89066 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89067 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89068 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 89069 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89070 | //PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS |
|---|
| 89071 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89072 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89073 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89074 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89075 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89076 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89077 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89078 | #define PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89079 | //PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL |
|---|
| 89080 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89081 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89082 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89083 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89084 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89085 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89086 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 89087 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89088 | //PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS |
|---|
| 89089 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89090 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89091 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89092 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89093 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89094 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89095 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89096 | #define PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89097 | //PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL |
|---|
| 89098 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89099 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89100 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89101 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89102 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89103 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89104 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 89105 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89106 | //PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS |
|---|
| 89107 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89108 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89109 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89110 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89111 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89112 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89113 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89114 | #define PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89115 | //PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL |
|---|
| 89116 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89117 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89118 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89119 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89120 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89121 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89122 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 89123 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89124 | //PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS |
|---|
| 89125 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89126 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89127 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89128 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89129 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89130 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89131 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89132 | #define PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89133 | //PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL |
|---|
| 89134 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89135 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89136 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89137 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89138 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89139 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89140 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 89141 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89142 | //PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS |
|---|
| 89143 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89144 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89145 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89146 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89147 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89148 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89149 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89150 | #define PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89151 | //PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL |
|---|
| 89152 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89153 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89154 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89155 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89156 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89157 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89158 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 89159 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89160 | //PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS |
|---|
| 89161 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89162 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89163 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89164 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89165 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89166 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89167 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89168 | #define PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89169 | //PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL |
|---|
| 89170 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89171 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89172 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89173 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89174 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89175 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89176 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 89177 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89178 | //PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS |
|---|
| 89179 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89180 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89181 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89182 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89183 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89184 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89185 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89186 | #define PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89187 | //PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL |
|---|
| 89188 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89189 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89190 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89191 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89192 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89193 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89194 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 89195 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89196 | //PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS |
|---|
| 89197 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89198 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89199 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89200 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89201 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89202 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89203 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89204 | #define PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89205 | //PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL |
|---|
| 89206 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89207 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89208 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89209 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89210 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89211 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89212 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 89213 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89214 | //PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS |
|---|
| 89215 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89216 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89217 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89218 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89219 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89220 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89221 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89222 | #define PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89223 | //PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL |
|---|
| 89224 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89225 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89226 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89227 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89228 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89229 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89230 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 89231 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89232 | //PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS |
|---|
| 89233 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89234 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89235 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89236 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89237 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89238 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89239 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89240 | #define PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89241 | //PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL |
|---|
| 89242 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89243 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89244 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89245 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89246 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89247 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89248 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 89249 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89250 | //PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS |
|---|
| 89251 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89252 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89253 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89254 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89255 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89256 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89257 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89258 | #define PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89259 | //PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL |
|---|
| 89260 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89261 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89262 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89263 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89264 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89265 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89266 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 89267 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89268 | //PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS |
|---|
| 89269 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89270 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89271 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89272 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89273 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89274 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89275 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89276 | #define PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89277 | //PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL |
|---|
| 89278 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89279 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89280 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89281 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89282 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89283 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89284 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 89285 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89286 | //PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS |
|---|
| 89287 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89288 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89289 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89290 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89291 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89292 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89293 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89294 | #define PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89295 | //PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL |
|---|
| 89296 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89297 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89298 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89299 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89300 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89301 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89302 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 89303 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89304 | //PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS |
|---|
| 89305 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89306 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89307 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89308 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89309 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89310 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89311 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89312 | #define PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89313 | //PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL |
|---|
| 89314 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 89315 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 89316 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 89317 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 89318 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 89319 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 89320 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 89321 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 89322 | //PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS |
|---|
| 89323 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 89324 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 89325 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 89326 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 89327 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 89328 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 89329 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 89330 | #define PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 89331 | //PSWUSCFG0_1_PCIE_CCIX_CAP_LIST |
|---|
| 89332 | #define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 89333 | #define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 89334 | #define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 89335 | #define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 89336 | #define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 89337 | #define PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 89338 | //PSWUSCFG0_1_PCIE_CCIX_HEADER_1 |
|---|
| 89339 | #define 0x0 |
|---|
| 89340 | #define 0x10 |
|---|
| 89341 | #define 0x14 |
|---|
| 89342 | #define 0x0000FFFFL |
|---|
| 89343 | #define 0x000F0000L |
|---|
| 89344 | #define 0xFFF00000L |
|---|
| 89345 | //PSWUSCFG0_1_PCIE_CCIX_HEADER_2 |
|---|
| 89346 | #define 0x0 |
|---|
| 89347 | #define 0xFFFFL |
|---|
| 89348 | //PSWUSCFG0_1_PCIE_CCIX_CAP |
|---|
| 89349 | #define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 89350 | #define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1 |
|---|
| 89351 | #define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3 |
|---|
| 89352 | #define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4 |
|---|
| 89353 | #define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8 |
|---|
| 89354 | #define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L |
|---|
| 89355 | #define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L |
|---|
| 89356 | #define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L |
|---|
| 89357 | #define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L |
|---|
| 89358 | #define PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L |
|---|
| 89359 | //PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP |
|---|
| 89360 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0 |
|---|
| 89361 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1 |
|---|
| 89362 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2 |
|---|
| 89363 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5 |
|---|
| 89364 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9 |
|---|
| 89365 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe |
|---|
| 89366 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L |
|---|
| 89367 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L |
|---|
| 89368 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L |
|---|
| 89369 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L |
|---|
| 89370 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L |
|---|
| 89371 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L |
|---|
| 89372 | //PSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP |
|---|
| 89373 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0 |
|---|
| 89374 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 89375 | //PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS |
|---|
| 89376 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0 |
|---|
| 89377 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7 |
|---|
| 89378 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL |
|---|
| 89379 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L |
|---|
| 89380 | //PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL |
|---|
| 89381 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0 |
|---|
| 89382 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7 |
|---|
| 89383 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8 |
|---|
| 89384 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf |
|---|
| 89385 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10 |
|---|
| 89386 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14 |
|---|
| 89387 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18 |
|---|
| 89388 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19 |
|---|
| 89389 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a |
|---|
| 89390 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL |
|---|
| 89391 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L |
|---|
| 89392 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L |
|---|
| 89393 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L |
|---|
| 89394 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L |
|---|
| 89395 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L |
|---|
| 89396 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L |
|---|
| 89397 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L |
|---|
| 89398 | #define PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L |
|---|
| 89399 | //PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT |
|---|
| 89400 | #define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89401 | #define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89402 | #define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89403 | #define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89404 | //PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT |
|---|
| 89405 | #define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89406 | #define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89407 | #define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89408 | #define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89409 | //PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT |
|---|
| 89410 | #define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89411 | #define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89412 | #define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89413 | #define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89414 | //PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT |
|---|
| 89415 | #define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89416 | #define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89417 | #define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89418 | #define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89419 | //PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT |
|---|
| 89420 | #define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89421 | #define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89422 | #define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89423 | #define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89424 | //PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT |
|---|
| 89425 | #define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89426 | #define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89427 | #define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89428 | #define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89429 | //PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT |
|---|
| 89430 | #define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89431 | #define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89432 | #define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89433 | #define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89434 | //PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT |
|---|
| 89435 | #define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89436 | #define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89437 | #define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89438 | #define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89439 | //PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT |
|---|
| 89440 | #define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89441 | #define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89442 | #define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89443 | #define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89444 | //PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT |
|---|
| 89445 | #define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89446 | #define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89447 | #define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89448 | #define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89449 | //PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT |
|---|
| 89450 | #define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89451 | #define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89452 | #define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89453 | #define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89454 | //PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT |
|---|
| 89455 | #define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89456 | #define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89457 | #define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89458 | #define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89459 | //PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT |
|---|
| 89460 | #define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89461 | #define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89462 | #define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89463 | #define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89464 | //PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT |
|---|
| 89465 | #define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89466 | #define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89467 | #define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89468 | #define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89469 | //PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT |
|---|
| 89470 | #define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89471 | #define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89472 | #define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89473 | #define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89474 | //PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT |
|---|
| 89475 | #define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89476 | #define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89477 | #define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL |
|---|
| 89478 | #define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L |
|---|
| 89479 | //PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT |
|---|
| 89480 | #define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89481 | #define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89482 | #define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89483 | #define PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89484 | //PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT |
|---|
| 89485 | #define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89486 | #define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89487 | #define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89488 | #define PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89489 | //PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT |
|---|
| 89490 | #define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89491 | #define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89492 | #define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89493 | #define PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89494 | //PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT |
|---|
| 89495 | #define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89496 | #define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89497 | #define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89498 | #define PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89499 | //PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT |
|---|
| 89500 | #define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89501 | #define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89502 | #define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89503 | #define PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89504 | //PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT |
|---|
| 89505 | #define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89506 | #define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89507 | #define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89508 | #define PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89509 | //PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT |
|---|
| 89510 | #define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89511 | #define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89512 | #define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89513 | #define PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89514 | //PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT |
|---|
| 89515 | #define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89516 | #define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89517 | #define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89518 | #define PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89519 | //PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT |
|---|
| 89520 | #define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89521 | #define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89522 | #define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89523 | #define PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89524 | //PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT |
|---|
| 89525 | #define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89526 | #define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89527 | #define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89528 | #define PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89529 | //PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT |
|---|
| 89530 | #define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89531 | #define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89532 | #define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89533 | #define PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89534 | //PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT |
|---|
| 89535 | #define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89536 | #define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89537 | #define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89538 | #define PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89539 | //PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT |
|---|
| 89540 | #define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89541 | #define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89542 | #define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89543 | #define PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89544 | //PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT |
|---|
| 89545 | #define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89546 | #define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89547 | #define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89548 | #define PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89549 | //PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT |
|---|
| 89550 | #define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89551 | #define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89552 | #define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89553 | #define PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89554 | //PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT |
|---|
| 89555 | #define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0 |
|---|
| 89556 | #define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4 |
|---|
| 89557 | #define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL |
|---|
| 89558 | #define PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L |
|---|
| 89559 | //PSWUSCFG0_1_PCIE_CCIX_TRANS_CAP |
|---|
| 89560 | #define PSWUSCFG0_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0 |
|---|
| 89561 | #define PSWUSCFG0_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L |
|---|
| 89562 | //PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL |
|---|
| 89563 | #define PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0 |
|---|
| 89564 | #define PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE__SHIFT 0x1 |
|---|
| 89565 | #define PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L |
|---|
| 89566 | #define PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE_MASK 0x00000002L |
|---|
| 89567 | |
|---|
| 89568 | |
|---|
| 89569 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1 |
|---|
| 89570 | //BIF_BX_PF0_MM_INDEX |
|---|
| 89571 | #define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 89572 | #define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 89573 | #define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 89574 | #define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 89575 | //BIF_BX_PF0_MM_DATA |
|---|
| 89576 | #define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 89577 | #define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 89578 | //BIF_BX_PF0_MM_INDEX_HI |
|---|
| 89579 | #define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 89580 | #define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 89581 | |
|---|
| 89582 | |
|---|
| 89583 | // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp |
|---|
| 89584 | //BIF_CFG_DEV0_SWDS1_VENDOR_ID |
|---|
| 89585 | #define BIF_CFG_DEV0_SWDS1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 89586 | #define BIF_CFG_DEV0_SWDS1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 89587 | //BIF_CFG_DEV0_SWDS1_DEVICE_ID |
|---|
| 89588 | #define BIF_CFG_DEV0_SWDS1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 89589 | #define BIF_CFG_DEV0_SWDS1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 89590 | //BIF_CFG_DEV0_SWDS1_COMMAND |
|---|
| 89591 | #define BIF_CFG_DEV0_SWDS1_COMMAND__IOEN_DN__SHIFT 0x0 |
|---|
| 89592 | #define BIF_CFG_DEV0_SWDS1_COMMAND__MEMEN_DN__SHIFT 0x1 |
|---|
| 89593 | #define BIF_CFG_DEV0_SWDS1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 89594 | #define BIF_CFG_DEV0_SWDS1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 89595 | #define BIF_CFG_DEV0_SWDS1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 89596 | #define BIF_CFG_DEV0_SWDS1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 89597 | #define BIF_CFG_DEV0_SWDS1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 89598 | #define BIF_CFG_DEV0_SWDS1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 89599 | #define BIF_CFG_DEV0_SWDS1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 89600 | #define BIF_CFG_DEV0_SWDS1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 89601 | #define BIF_CFG_DEV0_SWDS1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 89602 | #define BIF_CFG_DEV0_SWDS1_COMMAND__IOEN_DN_MASK 0x0001L |
|---|
| 89603 | #define BIF_CFG_DEV0_SWDS1_COMMAND__MEMEN_DN_MASK 0x0002L |
|---|
| 89604 | #define BIF_CFG_DEV0_SWDS1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 89605 | #define BIF_CFG_DEV0_SWDS1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 89606 | #define BIF_CFG_DEV0_SWDS1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 89607 | #define BIF_CFG_DEV0_SWDS1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 89608 | #define BIF_CFG_DEV0_SWDS1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 89609 | #define BIF_CFG_DEV0_SWDS1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 89610 | #define BIF_CFG_DEV0_SWDS1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 89611 | #define BIF_CFG_DEV0_SWDS1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 89612 | #define BIF_CFG_DEV0_SWDS1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 89613 | //BIF_CFG_DEV0_SWDS1_STATUS |
|---|
| 89614 | #define BIF_CFG_DEV0_SWDS1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 89615 | #define BIF_CFG_DEV0_SWDS1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 89616 | #define BIF_CFG_DEV0_SWDS1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 89617 | #define BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 89618 | #define BIF_CFG_DEV0_SWDS1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 89619 | #define BIF_CFG_DEV0_SWDS1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 89620 | #define BIF_CFG_DEV0_SWDS1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 89621 | #define BIF_CFG_DEV0_SWDS1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 89622 | #define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 89623 | #define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 89624 | #define BIF_CFG_DEV0_SWDS1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 89625 | #define BIF_CFG_DEV0_SWDS1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 89626 | #define BIF_CFG_DEV0_SWDS1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 89627 | #define BIF_CFG_DEV0_SWDS1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 89628 | #define BIF_CFG_DEV0_SWDS1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 89629 | #define BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 89630 | #define BIF_CFG_DEV0_SWDS1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 89631 | #define BIF_CFG_DEV0_SWDS1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 89632 | #define BIF_CFG_DEV0_SWDS1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 89633 | #define BIF_CFG_DEV0_SWDS1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 89634 | #define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 89635 | #define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 89636 | #define BIF_CFG_DEV0_SWDS1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 89637 | #define BIF_CFG_DEV0_SWDS1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 89638 | //BIF_CFG_DEV0_SWDS1_REVISION_ID |
|---|
| 89639 | #define BIF_CFG_DEV0_SWDS1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 89640 | #define BIF_CFG_DEV0_SWDS1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 89641 | #define BIF_CFG_DEV0_SWDS1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 89642 | #define BIF_CFG_DEV0_SWDS1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 89643 | //BIF_CFG_DEV0_SWDS1_PROG_INTERFACE |
|---|
| 89644 | #define BIF_CFG_DEV0_SWDS1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 89645 | #define BIF_CFG_DEV0_SWDS1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 89646 | //BIF_CFG_DEV0_SWDS1_SUB_CLASS |
|---|
| 89647 | #define BIF_CFG_DEV0_SWDS1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 89648 | #define BIF_CFG_DEV0_SWDS1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 89649 | //BIF_CFG_DEV0_SWDS1_BASE_CLASS |
|---|
| 89650 | #define BIF_CFG_DEV0_SWDS1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 89651 | #define BIF_CFG_DEV0_SWDS1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 89652 | //BIF_CFG_DEV0_SWDS1_CACHE_LINE |
|---|
| 89653 | #define BIF_CFG_DEV0_SWDS1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 89654 | #define BIF_CFG_DEV0_SWDS1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 89655 | //BIF_CFG_DEV0_SWDS1_LATENCY |
|---|
| 89656 | #define BIF_CFG_DEV0_SWDS1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 89657 | #define BIF_CFG_DEV0_SWDS1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 89658 | //BIF_CFG_DEV0_SWDS1_HEADER |
|---|
| 89659 | #define 0x0 |
|---|
| 89660 | #define 0x7 |
|---|
| 89661 | #define 0x7FL |
|---|
| 89662 | #define 0x80L |
|---|
| 89663 | //BIF_CFG_DEV0_SWDS1_BIST |
|---|
| 89664 | #define BIF_CFG_DEV0_SWDS1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 89665 | #define BIF_CFG_DEV0_SWDS1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 89666 | #define BIF_CFG_DEV0_SWDS1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 89667 | #define BIF_CFG_DEV0_SWDS1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 89668 | #define BIF_CFG_DEV0_SWDS1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 89669 | #define BIF_CFG_DEV0_SWDS1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 89670 | //BIF_CFG_DEV0_SWDS1_BASE_ADDR_1 |
|---|
| 89671 | #define BIF_CFG_DEV0_SWDS1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 89672 | #define BIF_CFG_DEV0_SWDS1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 89673 | //BIF_CFG_DEV0_SWDS1_BASE_ADDR_2 |
|---|
| 89674 | #define BIF_CFG_DEV0_SWDS1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 89675 | #define BIF_CFG_DEV0_SWDS1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 89676 | //BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY |
|---|
| 89677 | #define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
|---|
| 89678 | #define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
|---|
| 89679 | #define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
|---|
| 89680 | #define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
|---|
| 89681 | #define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
|---|
| 89682 | #define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
|---|
| 89683 | #define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
|---|
| 89684 | #define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
|---|
| 89685 | //BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT |
|---|
| 89686 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
|---|
| 89687 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
|---|
| 89688 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
|---|
| 89689 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
|---|
| 89690 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
|---|
| 89691 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
|---|
| 89692 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
|---|
| 89693 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
|---|
| 89694 | //BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS |
|---|
| 89695 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 89696 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 89697 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 89698 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 89699 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 89700 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 89701 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 89702 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 89703 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 89704 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 89705 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 89706 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 89707 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 89708 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 89709 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 89710 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 89711 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 89712 | #define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 89713 | //BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT |
|---|
| 89714 | #define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 89715 | #define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
|---|
| 89716 | #define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 89717 | #define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
|---|
| 89718 | #define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 89719 | #define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
|---|
| 89720 | #define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 89721 | #define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
|---|
| 89722 | //BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT |
|---|
| 89723 | #define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
|---|
| 89724 | #define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
|---|
| 89725 | #define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
|---|
| 89726 | #define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
|---|
| 89727 | #define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
|---|
| 89728 | #define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
|---|
| 89729 | #define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
|---|
| 89730 | #define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
|---|
| 89731 | //BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER |
|---|
| 89732 | #define BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
|---|
| 89733 | #define BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
|---|
| 89734 | //BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER |
|---|
| 89735 | #define BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
|---|
| 89736 | #define BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
|---|
| 89737 | //BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI |
|---|
| 89738 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
|---|
| 89739 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
|---|
| 89740 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
|---|
| 89741 | #define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
|---|
| 89742 | //BIF_CFG_DEV0_SWDS1_CAP_PTR |
|---|
| 89743 | #define BIF_CFG_DEV0_SWDS1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 89744 | #define BIF_CFG_DEV0_SWDS1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 89745 | //BIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR |
|---|
| 89746 | #define BIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 89747 | #define BIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 89748 | //BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE |
|---|
| 89749 | #define BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 89750 | #define BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 89751 | //BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN |
|---|
| 89752 | #define BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 89753 | #define BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 89754 | //BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL |
|---|
| 89755 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
|---|
| 89756 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
|---|
| 89757 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
|---|
| 89758 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
|---|
| 89759 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
|---|
| 89760 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
|---|
| 89761 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
|---|
| 89762 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
|---|
| 89763 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 |
|---|
| 89764 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 |
|---|
| 89765 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa |
|---|
| 89766 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb |
|---|
| 89767 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
|---|
| 89768 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
|---|
| 89769 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
|---|
| 89770 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
|---|
| 89771 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
|---|
| 89772 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
|---|
| 89773 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
|---|
| 89774 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
|---|
| 89775 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L |
|---|
| 89776 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L |
|---|
| 89777 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L |
|---|
| 89778 | #define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L |
|---|
| 89779 | //BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST |
|---|
| 89780 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 89781 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 89782 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 89783 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 89784 | //BIF_CFG_DEV0_SWDS1_PMI_CAP |
|---|
| 89785 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 89786 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 89787 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 89788 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 89789 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 89790 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 89791 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 89792 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 89793 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 89794 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 89795 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 89796 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 89797 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 89798 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 89799 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 89800 | #define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 89801 | //BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL |
|---|
| 89802 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 89803 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 89804 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 89805 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 89806 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 89807 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 89808 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 89809 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 89810 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 89811 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 89812 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 89813 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 89814 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 89815 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 89816 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 89817 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 89818 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 89819 | #define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 89820 | //BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST |
|---|
| 89821 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 89822 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 89823 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 89824 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 89825 | //BIF_CFG_DEV0_SWDS1_PCIE_CAP |
|---|
| 89826 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 89827 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 89828 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 89829 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 89830 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 89831 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 89832 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 89833 | #define BIF_CFG_DEV0_SWDS1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 89834 | //BIF_CFG_DEV0_SWDS1_DEVICE_CAP |
|---|
| 89835 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 89836 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 89837 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 89838 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 89839 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 89840 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 89841 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 89842 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 89843 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 89844 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 89845 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 89846 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 89847 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 89848 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 89849 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 89850 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 89851 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 89852 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 89853 | //BIF_CFG_DEV0_SWDS1_DEVICE_CNTL |
|---|
| 89854 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 89855 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 89856 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 89857 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 89858 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 89859 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 89860 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 89861 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 89862 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 89863 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 89864 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 89865 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
|---|
| 89866 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 89867 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 89868 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 89869 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 89870 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 89871 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 89872 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 89873 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 89874 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 89875 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 89876 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 89877 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
|---|
| 89878 | //BIF_CFG_DEV0_SWDS1_DEVICE_STATUS |
|---|
| 89879 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 89880 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 89881 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 89882 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 89883 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 89884 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 89885 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 89886 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 89887 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 89888 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 89889 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 89890 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 89891 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 89892 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 89893 | //BIF_CFG_DEV0_SWDS1_LINK_CAP |
|---|
| 89894 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 89895 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 89896 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 89897 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 89898 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 89899 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 89900 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 89901 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 89902 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 89903 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 89904 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 89905 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 89906 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 89907 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 89908 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 89909 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 89910 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 89911 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 89912 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 89913 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 89914 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 89915 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 89916 | //BIF_CFG_DEV0_SWDS1_LINK_CNTL |
|---|
| 89917 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 89918 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 89919 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 89920 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 89921 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 89922 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 89923 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 89924 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 89925 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 89926 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 89927 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 89928 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 89929 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 89930 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 89931 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 89932 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 89933 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 89934 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 89935 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 89936 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 89937 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 89938 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 89939 | //BIF_CFG_DEV0_SWDS1_LINK_STATUS |
|---|
| 89940 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 89941 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 89942 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 89943 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 89944 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 89945 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 89946 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 89947 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 89948 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 89949 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 89950 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 89951 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 89952 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 89953 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 89954 | //BIF_CFG_DEV0_SWDS1_SLOT_CAP |
|---|
| 89955 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 |
|---|
| 89956 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 |
|---|
| 89957 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 |
|---|
| 89958 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 |
|---|
| 89959 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 |
|---|
| 89960 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 |
|---|
| 89961 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 |
|---|
| 89962 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 |
|---|
| 89963 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf |
|---|
| 89964 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 |
|---|
| 89965 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 |
|---|
| 89966 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 |
|---|
| 89967 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L |
|---|
| 89968 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L |
|---|
| 89969 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L |
|---|
| 89970 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L |
|---|
| 89971 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L |
|---|
| 89972 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L |
|---|
| 89973 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L |
|---|
| 89974 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L |
|---|
| 89975 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L |
|---|
| 89976 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L |
|---|
| 89977 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L |
|---|
| 89978 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L |
|---|
| 89979 | //BIF_CFG_DEV0_SWDS1_SLOT_CNTL |
|---|
| 89980 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 |
|---|
| 89981 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 |
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| 89982 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 |
|---|
| 89983 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 |
|---|
| 89984 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 |
|---|
| 89985 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 |
|---|
| 89986 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 |
|---|
| 89987 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 |
|---|
| 89988 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa |
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| 89989 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb |
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| 89990 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc |
|---|
| 89991 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd |
|---|
| 89992 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L |
|---|
| 89993 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L |
|---|
| 89994 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L |
|---|
| 89995 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L |
|---|
| 89996 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L |
|---|
| 89997 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L |
|---|
| 89998 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L |
|---|
| 89999 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L |
|---|
| 90000 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L |
|---|
| 90001 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L |
|---|
| 90002 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L |
|---|
| 90003 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L |
|---|
| 90004 | //BIF_CFG_DEV0_SWDS1_SLOT_STATUS |
|---|
| 90005 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 |
|---|
| 90006 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 |
|---|
| 90007 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 |
|---|
| 90008 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 |
|---|
| 90009 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 |
|---|
| 90010 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 |
|---|
| 90011 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 |
|---|
| 90012 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 |
|---|
| 90013 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 |
|---|
| 90014 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L |
|---|
| 90015 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L |
|---|
| 90016 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L |
|---|
| 90017 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L |
|---|
| 90018 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L |
|---|
| 90019 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L |
|---|
| 90020 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L |
|---|
| 90021 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L |
|---|
| 90022 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L |
|---|
| 90023 | //BIF_CFG_DEV0_SWDS1_DEVICE_CAP2 |
|---|
| 90024 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 90025 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 90026 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 90027 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 90028 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 90029 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 90030 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
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| 90031 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 90032 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
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| 90033 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 90034 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 90035 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 90036 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 90037 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 90038 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 90039 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 90040 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 90041 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 90042 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 90043 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 90044 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 90045 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 90046 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 90047 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 90048 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 90049 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 90050 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 90051 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 90052 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 90053 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 90054 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 90055 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 90056 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 90057 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 90058 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 90059 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 90060 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 90061 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 90062 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 90063 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 90064 | //BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2 |
|---|
| 90065 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 90066 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 90067 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 90068 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 90069 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 90070 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 90071 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 90072 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 90073 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 90074 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 90075 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 90076 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 90077 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 90078 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 90079 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 90080 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 90081 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 90082 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 90083 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 90084 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 90085 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 90086 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 90087 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 90088 | #define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 90089 | //BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2 |
|---|
| 90090 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 90091 | #define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 90092 | //BIF_CFG_DEV0_SWDS1_LINK_CAP2 |
|---|
| 90093 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 90094 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 90095 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 90096 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 90097 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 90098 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 90099 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 90100 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 90101 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 90102 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 90103 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 90104 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 90105 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 90106 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 90107 | //BIF_CFG_DEV0_SWDS1_LINK_CNTL2 |
|---|
| 90108 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 90109 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 90110 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 90111 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 90112 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 90113 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 90114 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 90115 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 90116 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 90117 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 90118 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 90119 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 90120 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 90121 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 90122 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 90123 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 90124 | //BIF_CFG_DEV0_SWDS1_LINK_STATUS2 |
|---|
| 90125 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 90126 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 90127 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 90128 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 90129 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 90130 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 90131 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 90132 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 90133 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 90134 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 90135 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 90136 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 90137 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 90138 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 90139 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 90140 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 90141 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 90142 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 90143 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 90144 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 90145 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 90146 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 90147 | //BIF_CFG_DEV0_SWDS1_SLOT_CAP2 |
|---|
| 90148 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP2__RESERVED__SHIFT 0x0 |
|---|
| 90149 | #define BIF_CFG_DEV0_SWDS1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 90150 | //BIF_CFG_DEV0_SWDS1_SLOT_CNTL2 |
|---|
| 90151 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
|---|
| 90152 | #define BIF_CFG_DEV0_SWDS1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
|---|
| 90153 | //BIF_CFG_DEV0_SWDS1_SLOT_STATUS2 |
|---|
| 90154 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 90155 | #define BIF_CFG_DEV0_SWDS1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
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| 90156 | //BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST |
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| 90157 | #define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 90158 | #define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 90159 | #define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 90160 | #define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 90161 | //BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL |
|---|
| 90162 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 90163 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 90164 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 90165 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 90166 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 90167 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 90168 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 90169 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 90170 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 90171 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 90172 | //BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO |
|---|
| 90173 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
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| 90174 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
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| 90175 | //BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI |
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| 90176 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 90177 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 90178 | //BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA |
|---|
| 90179 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 90180 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
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| 90181 | //BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64 |
|---|
| 90182 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 90183 | #define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 90184 | //BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST |
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| 90185 | #define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 90186 | #define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 90187 | #define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 90188 | #define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 90189 | //BIF_CFG_DEV0_SWDS1_SSID_CAP |
|---|
| 90190 | #define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 90191 | #define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
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| 90192 | #define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 90193 | #define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 90194 | //BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 90195 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 90196 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 90197 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 90198 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 90199 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 90200 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 90201 | //BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 90202 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
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| 90203 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 90204 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 90205 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 90206 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 90207 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 90208 | //BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 90209 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 90210 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 90211 | //BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 90212 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 90213 | #define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
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| 90214 | //BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST |
|---|
| 90215 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 90216 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 90217 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 90218 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 90219 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 90220 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 90221 | //BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1 |
|---|
| 90222 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 90223 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 90224 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
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| 90225 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 90226 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 90227 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 90228 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
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| 90229 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
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| 90230 | //BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2 |
|---|
| 90231 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
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| 90232 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
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| 90233 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
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| 90234 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
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| 90235 | //BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL |
|---|
| 90236 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
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| 90237 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
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| 90238 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
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| 90239 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 90240 | //BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS |
|---|
| 90241 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
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| 90242 | #define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
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| 90243 | //BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP |
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| 90244 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
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| 90245 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
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| 90246 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
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| 90247 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
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| 90248 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
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| 90249 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
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| 90250 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 90251 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
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| 90252 | //BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL |
|---|
| 90253 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 90254 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 90255 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 90256 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 90257 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 90258 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 90259 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 90260 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 90261 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 90262 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 90263 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 90264 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 90265 | //BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS |
|---|
| 90266 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 90267 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 90268 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 90269 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 90270 | //BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP |
|---|
| 90271 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 90272 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 90273 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 90274 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 90275 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 90276 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 90277 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 90278 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 90279 | //BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL |
|---|
| 90280 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 90281 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 90282 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 90283 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 90284 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 90285 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 90286 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 90287 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 90288 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 90289 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 90290 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 90291 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 90292 | //BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS |
|---|
| 90293 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 90294 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 90295 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 90296 | #define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 90297 | //BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 90298 | #define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 90299 | #define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 90300 | #define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 90301 | #define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 90302 | #define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 90303 | #define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 90304 | //BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 90305 | #define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 90306 | #define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 90307 | //BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 90308 | #define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 90309 | #define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 90310 | //BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 90311 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 90312 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 90313 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 90314 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 90315 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 90316 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 90317 | //BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS |
|---|
| 90318 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 90319 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 90320 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 90321 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 90322 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 90323 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 90324 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 90325 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 90326 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 90327 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 90328 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 90329 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 90330 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 90331 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 90332 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 90333 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 90334 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 90335 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 90336 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 90337 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 90338 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 90339 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 90340 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 90341 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 90342 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 90343 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 90344 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 90345 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 90346 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 90347 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 90348 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 90349 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 90350 | //BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK |
|---|
| 90351 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 90352 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 90353 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 90354 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 90355 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 90356 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 90357 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 90358 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 90359 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 90360 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 90361 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 90362 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 90363 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 90364 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 90365 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 90366 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 90367 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 90368 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 90369 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 90370 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 90371 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 90372 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 90373 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 90374 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 90375 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 90376 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 90377 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 90378 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 90379 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 90380 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 90381 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 90382 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 90383 | //BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 90384 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 90385 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 90386 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 90387 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 90388 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 90389 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 90390 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 90391 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 90392 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 90393 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 90394 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 90395 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 90396 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 90397 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 90398 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 90399 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 90400 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 90401 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 90402 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 90403 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 90404 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 90405 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 90406 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 90407 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 90408 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 90409 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 90410 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 90411 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 90412 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 90413 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 90414 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 90415 | #define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 90416 | //BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS |
|---|
| 90417 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 90418 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 90419 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 90420 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 90421 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 90422 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 90423 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 90424 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 90425 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 90426 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 90427 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 90428 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 90429 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 90430 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 90431 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 90432 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 90433 | //BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK |
|---|
| 90434 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 90435 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 90436 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 90437 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 90438 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 90439 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 90440 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 90441 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 90442 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 90443 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 90444 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 90445 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 90446 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 90447 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 90448 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 90449 | #define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 90450 | //BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 90451 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 90452 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 90453 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 90454 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 90455 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 90456 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 90457 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 90458 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 90459 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 90460 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 90461 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 90462 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 90463 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 90464 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 90465 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 90466 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 90467 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 90468 | #define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 90469 | //BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0 |
|---|
| 90470 | #define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 90471 | #define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 90472 | //BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1 |
|---|
| 90473 | #define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 90474 | #define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 90475 | //BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2 |
|---|
| 90476 | #define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 90477 | #define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 90478 | //BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3 |
|---|
| 90479 | #define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 90480 | #define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 90481 | //BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 90482 | #define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 90483 | #define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 90484 | //BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 90485 | #define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 90486 | #define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 90487 | //BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 90488 | #define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 90489 | #define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 90490 | //BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 90491 | #define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 90492 | #define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 90493 | //BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 90494 | #define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 90495 | #define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 90496 | #define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 90497 | #define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 90498 | #define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 90499 | #define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 90500 | //BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3 |
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| 90501 | #define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
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| 90502 | #define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
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| 90503 | #define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
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| 90504 | #define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
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| 90505 | #define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
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| 90506 | #define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
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| 90507 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS |
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| 90508 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
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| 90509 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
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| 90510 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
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| 90511 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
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| 90512 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL |
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| 90513 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90514 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90515 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90516 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90517 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90518 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90519 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90520 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90521 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90522 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90523 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL |
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| 90524 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90525 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90526 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90527 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90528 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90529 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90530 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90531 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90532 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90533 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90534 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL |
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| 90535 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90536 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90537 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90538 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90539 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90540 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90541 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90542 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90543 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90544 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90545 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL |
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| 90546 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90547 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90548 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90549 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90550 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90551 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90552 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90553 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90554 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90555 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90556 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL |
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| 90557 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90558 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90559 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90560 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90561 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90562 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90563 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90564 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90565 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90566 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90567 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL |
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| 90568 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90569 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90570 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90571 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90572 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90573 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90574 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90575 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90576 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90577 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90578 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL |
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| 90579 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90580 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90581 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90582 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90583 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90584 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90585 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90586 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90587 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90588 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90589 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL |
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| 90590 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90591 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90592 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90593 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90594 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90595 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90596 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90597 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90598 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90599 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90600 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL |
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| 90601 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90602 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90603 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90604 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90605 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90606 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90607 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90608 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90609 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90610 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90611 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL |
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| 90612 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90613 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90614 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90615 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90616 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90617 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90618 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90619 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90620 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90621 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90622 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL |
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| 90623 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90624 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90625 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90626 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90627 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90628 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90629 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90630 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90631 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90632 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90633 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL |
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| 90634 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90635 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
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| 90636 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
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| 90637 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
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| 90638 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
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| 90639 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
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| 90640 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
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| 90641 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
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| 90642 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
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| 90643 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
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| 90644 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL |
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| 90645 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
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| 90646 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 90647 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 90648 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 90649 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 90650 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 90651 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 90652 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 90653 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 90654 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 90655 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 90656 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 90657 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 90658 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 90659 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 90660 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 90661 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 90662 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 90663 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 90664 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 90665 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 90666 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 90667 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 90668 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 90669 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 90670 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 90671 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 90672 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 90673 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 90674 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 90675 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 90676 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 90677 | //BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 90678 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 90679 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 90680 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 90681 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 90682 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 90683 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 90684 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 90685 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 90686 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 90687 | #define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 90688 | //BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST |
|---|
| 90689 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 90690 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 90691 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 90692 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 90693 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 90694 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 90695 | //BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP |
|---|
| 90696 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 90697 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 90698 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 90699 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 90700 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 90701 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 90702 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 90703 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 90704 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 90705 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 90706 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 90707 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 90708 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 90709 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 90710 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 90711 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 90712 | //BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL |
|---|
| 90713 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 90714 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 90715 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 90716 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 90717 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 90718 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 90719 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 90720 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 90721 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 90722 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 90723 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 90724 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 90725 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 90726 | #define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 90727 | //BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST |
|---|
| 90728 | #define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 90729 | #define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 90730 | #define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 90731 | #define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 90732 | #define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 90733 | #define BIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 90734 | //BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP |
|---|
| 90735 | #define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 90736 | #define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
|---|
| 90737 | #define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 90738 | #define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
|---|
| 90739 | //BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS |
|---|
| 90740 | #define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 90741 | #define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
|---|
| 90742 | #define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 90743 | #define BIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
|---|
| 90744 | //BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST |
|---|
| 90745 | #define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 90746 | #define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 90747 | #define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 90748 | #define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 90749 | #define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 90750 | #define BIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 90751 | //BIF_CFG_DEV0_SWDS1_LINK_CAP_16GT |
|---|
| 90752 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
|---|
| 90753 | #define BIF_CFG_DEV0_SWDS1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 90754 | //BIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT |
|---|
| 90755 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
|---|
| 90756 | #define BIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 90757 | //BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT |
|---|
| 90758 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
|---|
| 90759 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
|---|
| 90760 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
|---|
| 90761 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
|---|
| 90762 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
|---|
| 90763 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
|---|
| 90764 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
|---|
| 90765 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
|---|
| 90766 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
|---|
| 90767 | #define BIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
|---|
| 90768 | //BIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT |
|---|
| 90769 | #define BIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 90770 | #define BIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 90771 | //BIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT |
|---|
| 90772 | #define BIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 90773 | #define BIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 90774 | //BIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT |
|---|
| 90775 | #define BIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 90776 | #define BIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 90777 | //BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT |
|---|
| 90778 | #define BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 90779 | #define BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 90780 | #define BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 90781 | #define BIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 90782 | //BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT |
|---|
| 90783 | #define BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 90784 | #define BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 90785 | #define BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 90786 | #define BIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 90787 | //BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT |
|---|
| 90788 | #define BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 90789 | #define BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 90790 | #define BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 90791 | #define BIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 90792 | //BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT |
|---|
| 90793 | #define BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 90794 | #define BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 90795 | #define BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 90796 | #define BIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 90797 | //BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT |
|---|
| 90798 | #define BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 90799 | #define BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 90800 | #define BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 90801 | #define BIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 90802 | //BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT |
|---|
| 90803 | #define BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 90804 | #define BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 90805 | #define BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 90806 | #define BIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 90807 | //BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT |
|---|
| 90808 | #define BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 90809 | #define BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 90810 | #define BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 90811 | #define BIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 90812 | //BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT |
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| 90813 | #define BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 90814 | #define BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 90815 | #define BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 90816 | #define BIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 90817 | //BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT |
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| 90818 | #define BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 90819 | #define BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 90820 | #define BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 90821 | #define BIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 90822 | //BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT |
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| 90823 | #define BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 90824 | #define BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 90825 | #define BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 90826 | #define BIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 90827 | //BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT |
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| 90828 | #define BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 90829 | #define BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 90830 | #define BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 90831 | #define BIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 90832 | //BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT |
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| 90833 | #define BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 90834 | #define BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 90835 | #define BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 90836 | #define BIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 90837 | //BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT |
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| 90838 | #define BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 90839 | #define BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 90840 | #define BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 90841 | #define BIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 90842 | //BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT |
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| 90843 | #define BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 90844 | #define BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 90845 | #define BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 90846 | #define BIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
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| 90847 | //BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 90848 | #define BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 90849 | #define BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 90850 | #define BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 90851 | #define BIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 90852 | //BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 90853 | #define BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
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| 90854 | #define BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
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| 90855 | #define BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
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| 90856 | #define BIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 90857 | //BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 90858 | #define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 90859 | #define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 90860 | #define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 90861 | #define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 90862 | #define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 90863 | #define BIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 90864 | //BIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP |
|---|
| 90865 | #define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 90866 | #define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 90867 | //BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS |
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| 90868 | #define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
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| 90869 | #define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
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| 90870 | #define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
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| 90871 | #define BIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
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| 90872 | //BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL |
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| 90873 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
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| 90874 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 90875 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 90876 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
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| 90877 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
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| 90878 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 90879 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 90880 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
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| 90881 | //BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS |
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| 90882 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
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| 90883 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 90884 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 90885 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
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| 90886 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
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| 90887 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 90888 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 90889 | #define BIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
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| 90890 | //BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL |
|---|
| 90891 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 90892 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 90893 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 90894 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 90895 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 90896 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 90897 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 90898 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 90899 | //BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS |
|---|
| 90900 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 90901 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 90902 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 90903 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 90904 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 90905 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 90906 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 90907 | #define BIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 90908 | //BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL |
|---|
| 90909 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 90910 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 90911 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 90912 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 90913 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 90914 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 90915 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 90916 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 90917 | //BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS |
|---|
| 90918 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 90919 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 90920 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 90921 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 90922 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 90923 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 90924 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 90925 | #define BIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 90926 | //BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL |
|---|
| 90927 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 90928 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 90929 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 90930 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 90931 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 90932 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 90933 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 90934 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 90935 | //BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS |
|---|
| 90936 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 90937 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 90938 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 90939 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 90940 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 90941 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 90942 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 90943 | #define BIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 90944 | //BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL |
|---|
| 90945 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 90946 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 90947 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 90948 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 90949 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 90950 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 90951 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 90952 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 90953 | //BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS |
|---|
| 90954 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 90955 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 90956 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 90957 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 90958 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 90959 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 90960 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 90961 | #define BIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 90962 | //BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL |
|---|
| 90963 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 90964 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 90965 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 90966 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 90967 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 90968 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 90969 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 90970 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 90971 | //BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS |
|---|
| 90972 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 90973 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 90974 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 90975 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 90976 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 90977 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 90978 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 90979 | #define BIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 90980 | //BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL |
|---|
| 90981 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 90982 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 90983 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 90984 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 90985 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 90986 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 90987 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 90988 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 90989 | //BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS |
|---|
| 90990 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 90991 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 90992 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 90993 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 90994 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 90995 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 90996 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 90997 | #define BIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 90998 | //BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL |
|---|
| 90999 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 91000 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 91001 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 91002 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 91003 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 91004 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 91005 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 91006 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 91007 | //BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS |
|---|
| 91008 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 91009 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 91010 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 91011 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 91012 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 91013 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 91014 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 91015 | #define BIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 91016 | //BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL |
|---|
| 91017 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 91018 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 91019 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 91020 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 91021 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 91022 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 91023 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 91024 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 91025 | //BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS |
|---|
| 91026 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 91027 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 91028 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 91029 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 91030 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 91031 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 91032 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 91033 | #define BIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 91034 | //BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL |
|---|
| 91035 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 91036 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 91037 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 91038 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 91039 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 91040 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 91041 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 91042 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 91043 | //BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS |
|---|
| 91044 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 91045 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 91046 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 91047 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 91048 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 91049 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 91050 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 91051 | #define BIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 91052 | //BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL |
|---|
| 91053 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 91054 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 91055 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 91056 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 91057 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 91058 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 91059 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 91060 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 91061 | //BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS |
|---|
| 91062 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 91063 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 91064 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 91065 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 91066 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 91067 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 91068 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 91069 | #define BIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 91070 | //BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL |
|---|
| 91071 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 91072 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 91073 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 91074 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 91075 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 91076 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 91077 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 91078 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 91079 | //BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS |
|---|
| 91080 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 91081 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 91082 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 91083 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 91084 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 91085 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 91086 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 91087 | #define BIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 91088 | //BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL |
|---|
| 91089 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 91090 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 91091 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 91092 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 91093 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 91094 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 91095 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 91096 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 91097 | //BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS |
|---|
| 91098 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 91099 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 91100 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 91101 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 91102 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 91103 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 91104 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 91105 | #define BIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 91106 | //BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL |
|---|
| 91107 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 91108 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 91109 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 91110 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 91111 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 91112 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 91113 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 91114 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 91115 | //BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS |
|---|
| 91116 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 91117 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 91118 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 91119 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 91120 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 91121 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 91122 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 91123 | #define BIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 91124 | //BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL |
|---|
| 91125 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 91126 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 91127 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 91128 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 91129 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 91130 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 91131 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 91132 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 91133 | //BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS |
|---|
| 91134 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 91135 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 91136 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 91137 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 91138 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 91139 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 91140 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 91141 | #define BIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 91142 | //BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL |
|---|
| 91143 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 91144 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 91145 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 91146 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 91147 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 91148 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 91149 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 91150 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 91151 | //BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS |
|---|
| 91152 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 91153 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 91154 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 91155 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 91156 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 91157 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 91158 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 91159 | #define BIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 91160 | |
|---|
| 91161 | |
|---|
| 91162 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
|---|
| 91163 | //BIF_CFG_DEV0_EPF0_1_VENDOR_ID |
|---|
| 91164 | #define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 91165 | #define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 91166 | //BIF_CFG_DEV0_EPF0_1_DEVICE_ID |
|---|
| 91167 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 91168 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 91169 | //BIF_CFG_DEV0_EPF0_1_COMMAND |
|---|
| 91170 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 91171 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 91172 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 91173 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 91174 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 91175 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 91176 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 91177 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 91178 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 91179 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 91180 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 91181 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 91182 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 91183 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 91184 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 91185 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 91186 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 91187 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 91188 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 91189 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 91190 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 91191 | #define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 91192 | //BIF_CFG_DEV0_EPF0_1_STATUS |
|---|
| 91193 | #define BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 91194 | #define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 91195 | #define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 91196 | #define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 91197 | #define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 91198 | #define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 91199 | #define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 91200 | #define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 91201 | #define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 91202 | #define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 91203 | #define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 91204 | #define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 91205 | #define BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 91206 | #define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 91207 | #define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 91208 | #define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 91209 | #define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 91210 | #define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 91211 | #define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 91212 | #define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 91213 | #define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 91214 | #define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 91215 | #define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 91216 | #define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 91217 | //BIF_CFG_DEV0_EPF0_1_REVISION_ID |
|---|
| 91218 | #define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 91219 | #define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 91220 | #define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 91221 | #define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 91222 | //BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE |
|---|
| 91223 | #define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 91224 | #define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 91225 | //BIF_CFG_DEV0_EPF0_1_SUB_CLASS |
|---|
| 91226 | #define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 91227 | #define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 91228 | //BIF_CFG_DEV0_EPF0_1_BASE_CLASS |
|---|
| 91229 | #define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 91230 | #define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 91231 | //BIF_CFG_DEV0_EPF0_1_CACHE_LINE |
|---|
| 91232 | #define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 91233 | #define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 91234 | //BIF_CFG_DEV0_EPF0_1_LATENCY |
|---|
| 91235 | #define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 91236 | #define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 91237 | //BIF_CFG_DEV0_EPF0_1_HEADER |
|---|
| 91238 | #define 0x0 |
|---|
| 91239 | #define 0x7 |
|---|
| 91240 | #define 0x7FL |
|---|
| 91241 | #define 0x80L |
|---|
| 91242 | //BIF_CFG_DEV0_EPF0_1_BIST |
|---|
| 91243 | #define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 91244 | #define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 91245 | #define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 91246 | #define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 91247 | #define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 91248 | #define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 91249 | //BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 |
|---|
| 91250 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 91251 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 91252 | //BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 |
|---|
| 91253 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 91254 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 91255 | //BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 |
|---|
| 91256 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 91257 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 91258 | //BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 |
|---|
| 91259 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 91260 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 91261 | //BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 |
|---|
| 91262 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 91263 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 91264 | //BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 |
|---|
| 91265 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 91266 | #define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 91267 | //BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR |
|---|
| 91268 | #define BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 91269 | #define BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 91270 | //BIF_CFG_DEV0_EPF0_1_ADAPTER_ID |
|---|
| 91271 | #define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 91272 | #define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 91273 | #define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 91274 | #define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 91275 | //BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR |
|---|
| 91276 | #define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 91277 | #define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 91278 | //BIF_CFG_DEV0_EPF0_1_CAP_PTR |
|---|
| 91279 | #define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 91280 | #define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 91281 | //BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE |
|---|
| 91282 | #define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 91283 | #define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 91284 | //BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN |
|---|
| 91285 | #define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 91286 | #define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 91287 | //BIF_CFG_DEV0_EPF0_1_MIN_GRANT |
|---|
| 91288 | #define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 91289 | #define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 91290 | //BIF_CFG_DEV0_EPF0_1_MAX_LATENCY |
|---|
| 91291 | #define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 91292 | #define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 91293 | //BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST |
|---|
| 91294 | #define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 91295 | #define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 91296 | #define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 91297 | #define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 91298 | #define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 91299 | #define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 91300 | //BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W |
|---|
| 91301 | #define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 91302 | #define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 91303 | #define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 91304 | #define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 91305 | //BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST |
|---|
| 91306 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 91307 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 91308 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 91309 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 91310 | //BIF_CFG_DEV0_EPF0_1_PMI_CAP |
|---|
| 91311 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 91312 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 91313 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 91314 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 91315 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 91316 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 91317 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 91318 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 91319 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 91320 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 91321 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 91322 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 91323 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 91324 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 91325 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 91326 | #define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 91327 | //BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL |
|---|
| 91328 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 91329 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 91330 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 91331 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 91332 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 91333 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 91334 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 91335 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 91336 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 91337 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 91338 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 91339 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 91340 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 91341 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 91342 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 91343 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 91344 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 91345 | #define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 91346 | //BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST |
|---|
| 91347 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 91348 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 91349 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 91350 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 91351 | //BIF_CFG_DEV0_EPF0_1_PCIE_CAP |
|---|
| 91352 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 91353 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 91354 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 91355 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 91356 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 91357 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 91358 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 91359 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 91360 | //BIF_CFG_DEV0_EPF0_1_DEVICE_CAP |
|---|
| 91361 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 91362 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 91363 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 91364 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 91365 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 91366 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 91367 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 91368 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 91369 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 91370 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 91371 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 91372 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 91373 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 91374 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 91375 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 91376 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 91377 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 91378 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 91379 | //BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL |
|---|
| 91380 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 91381 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 91382 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 91383 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 91384 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 91385 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 91386 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 91387 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 91388 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 91389 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 91390 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 91391 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 91392 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 91393 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 91394 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 91395 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 91396 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 91397 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 91398 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 91399 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 91400 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 91401 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 91402 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 91403 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 91404 | //BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS |
|---|
| 91405 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 91406 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 91407 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 91408 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 91409 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 91410 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 91411 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 91412 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 91413 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 91414 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 91415 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 91416 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 91417 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 91418 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 91419 | //BIF_CFG_DEV0_EPF0_1_LINK_CAP |
|---|
| 91420 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 91421 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 91422 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 91423 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 91424 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 91425 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 91426 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 91427 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 91428 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 91429 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 91430 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 91431 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 91432 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 91433 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 91434 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 91435 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 91436 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 91437 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 91438 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 91439 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 91440 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 91441 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 91442 | //BIF_CFG_DEV0_EPF0_1_LINK_CNTL |
|---|
| 91443 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 91444 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 91445 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 91446 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 91447 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 91448 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 91449 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 91450 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 91451 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 91452 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 91453 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 91454 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 91455 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 91456 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 91457 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 91458 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 91459 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 91460 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 91461 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 91462 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 91463 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 91464 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 91465 | //BIF_CFG_DEV0_EPF0_1_LINK_STATUS |
|---|
| 91466 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 91467 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 91468 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 91469 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 91470 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 91471 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 91472 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 91473 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 91474 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 91475 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 91476 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 91477 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 91478 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 91479 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 91480 | //BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 |
|---|
| 91481 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 91482 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 91483 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 91484 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 91485 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 91486 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 91487 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 91488 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 91489 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 91490 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 91491 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 91492 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 91493 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 91494 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 91495 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 91496 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 91497 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 91498 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 91499 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 91500 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 91501 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 91502 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 91503 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 91504 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 91505 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 91506 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 91507 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 91508 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 91509 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 91510 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 91511 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 91512 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 91513 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 91514 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 91515 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 91516 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 91517 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 91518 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 91519 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 91520 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 91521 | //BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 |
|---|
| 91522 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 91523 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 91524 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 91525 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 91526 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 91527 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 91528 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 91529 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 91530 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 91531 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 91532 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 91533 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 91534 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 91535 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 91536 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 91537 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 91538 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 91539 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 91540 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 91541 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 91542 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 91543 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 91544 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 91545 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 91546 | //BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 |
|---|
| 91547 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 91548 | #define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 91549 | //BIF_CFG_DEV0_EPF0_1_LINK_CAP2 |
|---|
| 91550 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 91551 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 91552 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 91553 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 91554 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 91555 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 91556 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 91557 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 91558 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 91559 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 91560 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 91561 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 91562 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 91563 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 91564 | //BIF_CFG_DEV0_EPF0_1_LINK_CNTL2 |
|---|
| 91565 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 91566 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 91567 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 91568 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 91569 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 91570 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 91571 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 91572 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 91573 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 91574 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 91575 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 91576 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 91577 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 91578 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 91579 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 91580 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 91581 | //BIF_CFG_DEV0_EPF0_1_LINK_STATUS2 |
|---|
| 91582 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 91583 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 91584 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 91585 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 91586 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 91587 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 91588 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 91589 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 91590 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 91591 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 91592 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 91593 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 91594 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 91595 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 91596 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 91597 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 91598 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 91599 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 91600 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 91601 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 91602 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 91603 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 91604 | //BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST |
|---|
| 91605 | #define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 91606 | #define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 91607 | #define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 91608 | #define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 91609 | //BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL |
|---|
| 91610 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 91611 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 91612 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 91613 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 91614 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 91615 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 91616 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 91617 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 91618 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 91619 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 91620 | //BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO |
|---|
| 91621 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 91622 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 91623 | //BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI |
|---|
| 91624 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 91625 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 91626 | //BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA |
|---|
| 91627 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 91628 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 91629 | //BIF_CFG_DEV0_EPF0_1_MSI_MASK |
|---|
| 91630 | #define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 91631 | #define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 91632 | //BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 |
|---|
| 91633 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 91634 | #define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 91635 | //BIF_CFG_DEV0_EPF0_1_MSI_MASK_64 |
|---|
| 91636 | #define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 91637 | #define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 91638 | //BIF_CFG_DEV0_EPF0_1_MSI_PENDING |
|---|
| 91639 | #define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 91640 | #define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 91641 | //BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 |
|---|
| 91642 | #define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 91643 | #define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 91644 | //BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST |
|---|
| 91645 | #define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 91646 | #define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 91647 | #define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 91648 | #define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 91649 | //BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL |
|---|
| 91650 | #define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 91651 | #define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 91652 | #define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 91653 | #define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 91654 | #define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 91655 | #define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 91656 | //BIF_CFG_DEV0_EPF0_1_MSIX_TABLE |
|---|
| 91657 | #define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 91658 | #define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 91659 | #define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 91660 | #define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 91661 | //BIF_CFG_DEV0_EPF0_1_MSIX_PBA |
|---|
| 91662 | #define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 91663 | #define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 91664 | #define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 91665 | #define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 91666 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 91667 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 91668 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 91669 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 91670 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 91671 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 91672 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 91673 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 91674 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 91675 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 91676 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 91677 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 91678 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 91679 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 91680 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 91681 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 91682 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 91683 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 91684 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 91685 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 91686 | //BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST |
|---|
| 91687 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 91688 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 91689 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 91690 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 91691 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 91692 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 91693 | //BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 |
|---|
| 91694 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 91695 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 91696 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 91697 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 91698 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 91699 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 91700 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 91701 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 91702 | //BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 |
|---|
| 91703 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 91704 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 91705 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 91706 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 91707 | //BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL |
|---|
| 91708 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 91709 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 91710 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 91711 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 91712 | //BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS |
|---|
| 91713 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 91714 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 91715 | //BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP |
|---|
| 91716 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 91717 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 91718 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 91719 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 91720 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 91721 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 91722 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 91723 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 91724 | //BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL |
|---|
| 91725 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 91726 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 91727 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 91728 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 91729 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 91730 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 91731 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 91732 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 91733 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 91734 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 91735 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 91736 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 91737 | //BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS |
|---|
| 91738 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 91739 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 91740 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 91741 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 91742 | //BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP |
|---|
| 91743 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 91744 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 91745 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 91746 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 91747 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 91748 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 91749 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 91750 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 91751 | //BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL |
|---|
| 91752 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 91753 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 91754 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 91755 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 91756 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 91757 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 91758 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 91759 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 91760 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 91761 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 91762 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 91763 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 91764 | //BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS |
|---|
| 91765 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 91766 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 91767 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 91768 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 91769 | //BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 91770 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 91771 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 91772 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 91773 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 91774 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 91775 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 91776 | //BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 91777 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 91778 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 91779 | //BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 91780 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 91781 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 91782 | //BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 91783 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 91784 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 91785 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 91786 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 91787 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 91788 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 91789 | //BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 91790 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 91791 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 91792 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 91793 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 91794 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 91795 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 91796 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 91797 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 91798 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 91799 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 91800 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 91801 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 91802 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 91803 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 91804 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 91805 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 91806 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 91807 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 91808 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 91809 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 91810 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 91811 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 91812 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 91813 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 91814 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 91815 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 91816 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 91817 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 91818 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 91819 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 91820 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 91821 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 91822 | //BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK |
|---|
| 91823 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 91824 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 91825 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 91826 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 91827 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 91828 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 91829 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 91830 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 91831 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 91832 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 91833 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 91834 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 91835 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 91836 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 91837 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 91838 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 91839 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 91840 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 91841 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 91842 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 91843 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 91844 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 91845 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 91846 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 91847 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 91848 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 91849 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 91850 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 91851 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 91852 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 91853 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 91854 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 91855 | //BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 91856 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 91857 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 91858 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 91859 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 91860 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 91861 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 91862 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 91863 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 91864 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 91865 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 91866 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 91867 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 91868 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 91869 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 91870 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 91871 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 91872 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 91873 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 91874 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 91875 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 91876 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 91877 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 91878 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 91879 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 91880 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 91881 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 91882 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 91883 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 91884 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 91885 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 91886 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 91887 | #define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 91888 | //BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS |
|---|
| 91889 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 91890 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 91891 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 91892 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 91893 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 91894 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 91895 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 91896 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 91897 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 91898 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 91899 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 91900 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 91901 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 91902 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 91903 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 91904 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 91905 | //BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK |
|---|
| 91906 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 91907 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 91908 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 91909 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 91910 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 91911 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 91912 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 91913 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 91914 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 91915 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 91916 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 91917 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 91918 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 91919 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 91920 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 91921 | #define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 91922 | //BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 91923 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 91924 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 91925 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 91926 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 91927 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 91928 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 91929 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 91930 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 91931 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 91932 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 91933 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 91934 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 91935 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 91936 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 91937 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 91938 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 91939 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 91940 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 91941 | //BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 |
|---|
| 91942 | #define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 91943 | #define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 91944 | //BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 |
|---|
| 91945 | #define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 91946 | #define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 91947 | //BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 |
|---|
| 91948 | #define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 91949 | #define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 91950 | //BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 |
|---|
| 91951 | #define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 91952 | #define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 91953 | //BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 91954 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 91955 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 91956 | //BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 91957 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 91958 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 91959 | //BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 91960 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 91961 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 91962 | //BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 91963 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 91964 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 91965 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST |
|---|
| 91966 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 91967 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 91968 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 91969 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 91970 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 91971 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 91972 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP |
|---|
| 91973 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 91974 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 91975 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL |
|---|
| 91976 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 91977 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 91978 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 91979 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 91980 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 91981 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 91982 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP |
|---|
| 91983 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 91984 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 91985 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL |
|---|
| 91986 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 91987 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 91988 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 91989 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 91990 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
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| 91991 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
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| 91992 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP |
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| 91993 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 91994 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 91995 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL |
|---|
| 91996 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 91997 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 91998 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 91999 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 92000 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 92001 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
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| 92002 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP |
|---|
| 92003 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 92004 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 92005 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL |
|---|
| 92006 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 92007 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 92008 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 92009 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 92010 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 92011 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 92012 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP |
|---|
| 92013 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 92014 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 92015 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL |
|---|
| 92016 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 92017 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 92018 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 92019 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 92020 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 92021 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 92022 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP |
|---|
| 92023 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 92024 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 92025 | //BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL |
|---|
| 92026 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 92027 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 92028 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 92029 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 92030 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 92031 | #define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 92032 | //BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 92033 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92034 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92035 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92036 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92037 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92038 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92039 | //BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 92040 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 92041 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 92042 | //BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA |
|---|
| 92043 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 92044 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 92045 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 92046 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 92047 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 92048 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 92049 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 92050 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 92051 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 92052 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 92053 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 92054 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 92055 | //BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP |
|---|
| 92056 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 92057 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 92058 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST |
|---|
| 92059 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92060 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92061 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92062 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92063 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92064 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92065 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP |
|---|
| 92066 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 92067 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 92068 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 92069 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 92070 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 92071 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 92072 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 92073 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 92074 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 92075 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 92076 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 92077 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 92078 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 92079 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS |
|---|
| 92080 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 92081 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 92082 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 92083 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 92084 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL |
|---|
| 92085 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 92086 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 92087 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 92088 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 92089 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 92090 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 92091 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 92092 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 92093 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 92094 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 92095 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 92096 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 92097 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 92098 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 92099 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 92100 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 92101 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 92102 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 92103 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 92104 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 92105 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 92106 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 92107 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 92108 | //BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 92109 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 92110 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 92111 | //BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 92112 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92113 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92114 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92115 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92116 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92117 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92118 | //BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 |
|---|
| 92119 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 92120 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
|---|
| 92121 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
|---|
| 92122 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 92123 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 92124 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
|---|
| 92125 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS |
|---|
| 92126 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 92127 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
|---|
| 92128 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 92129 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
|---|
| 92130 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 92131 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92132 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92133 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92134 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92135 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92136 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92137 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92138 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92139 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92140 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92141 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL |
|---|
| 92142 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92143 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92144 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92145 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92146 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92147 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92148 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92149 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92150 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92151 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92152 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL |
|---|
| 92153 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92154 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92155 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92156 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92157 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92158 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92159 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92160 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92161 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92162 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92163 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL |
|---|
| 92164 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92165 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92166 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92167 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92168 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92169 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92170 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92171 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92172 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92173 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92174 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL |
|---|
| 92175 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92176 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92177 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92178 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92179 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92180 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92181 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92182 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92183 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92184 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92185 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 92186 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92187 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92188 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92189 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92190 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92191 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92192 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92193 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92194 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92195 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92196 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 92197 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92198 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92199 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92200 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92201 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92202 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92203 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92204 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92205 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92206 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92207 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 92208 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92209 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92210 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92211 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92212 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92213 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92214 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92215 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92216 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92217 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92218 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 92219 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92220 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92221 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92222 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92223 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92224 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92225 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92226 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92227 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92228 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92229 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 92230 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92231 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92232 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92233 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92234 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92235 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92236 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92237 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92238 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92239 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92240 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 92241 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92242 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92243 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92244 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92245 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92246 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92247 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92248 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92249 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92250 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92251 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 92252 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92253 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92254 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92255 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92256 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92257 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92258 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92259 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92260 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92261 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92262 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 92263 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92264 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92265 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92266 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92267 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92268 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92269 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92270 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92271 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92272 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92273 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 92274 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92275 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92276 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92277 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92278 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92279 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92280 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92281 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92282 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92283 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92284 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 92285 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92286 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92287 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92288 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92289 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92290 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92291 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92292 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92293 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92294 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92295 | //BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 92296 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 92297 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 92298 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 92299 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 92300 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 92301 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 92302 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 92303 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 92304 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 92305 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 92306 | //BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST |
|---|
| 92307 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92308 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92309 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92310 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92311 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92312 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92313 | //BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP |
|---|
| 92314 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 92315 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 92316 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 92317 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 92318 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 92319 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 92320 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 92321 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 92322 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 92323 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 92324 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 92325 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 92326 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 92327 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 92328 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 92329 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 92330 | //BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL |
|---|
| 92331 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 92332 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 92333 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 92334 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 92335 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 92336 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 92337 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 92338 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 92339 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 92340 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 92341 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 92342 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 92343 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 92344 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 92345 | //BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 92346 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92347 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92348 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92349 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92350 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92351 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92352 | //BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP |
|---|
| 92353 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 92354 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 92355 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 92356 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 92357 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 92358 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 92359 | //BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL |
|---|
| 92360 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 92361 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 92362 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 92363 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 92364 | //BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST |
|---|
| 92365 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92366 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92367 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92368 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92369 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92370 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92371 | //BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL |
|---|
| 92372 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
|---|
| 92373 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
|---|
| 92374 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
|---|
| 92375 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
|---|
| 92376 | //BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS |
|---|
| 92377 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
|---|
| 92378 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
|---|
| 92379 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
|---|
| 92380 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
|---|
| 92381 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
|---|
| 92382 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
|---|
| 92383 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
|---|
| 92384 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
|---|
| 92385 | //BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
|---|
| 92386 | #define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
|---|
| 92387 | #define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
|---|
| 92388 | //BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
|---|
| 92389 | #define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
|---|
| 92390 | #define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
|---|
| 92391 | //BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST |
|---|
| 92392 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92393 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92394 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92395 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92396 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92397 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92398 | //BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP |
|---|
| 92399 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 92400 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 92401 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 92402 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 92403 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 92404 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 92405 | //BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL |
|---|
| 92406 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 92407 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 92408 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 92409 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 92410 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 92411 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 92412 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST |
|---|
| 92413 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92414 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92415 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92416 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92417 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92418 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92419 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP |
|---|
| 92420 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
|---|
| 92421 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
|---|
| 92422 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
|---|
| 92423 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
|---|
| 92424 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
|---|
| 92425 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
|---|
| 92426 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL |
|---|
| 92427 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
|---|
| 92428 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
|---|
| 92429 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
|---|
| 92430 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
|---|
| 92431 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 |
|---|
| 92432 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
|---|
| 92433 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
|---|
| 92434 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
|---|
| 92435 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
|---|
| 92436 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 |
|---|
| 92437 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
|---|
| 92438 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
|---|
| 92439 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 |
|---|
| 92440 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
|---|
| 92441 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
|---|
| 92442 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 |
|---|
| 92443 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
|---|
| 92444 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
|---|
| 92445 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 |
|---|
| 92446 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
|---|
| 92447 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
|---|
| 92448 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 |
|---|
| 92449 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
|---|
| 92450 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
|---|
| 92451 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
|---|
| 92452 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
|---|
| 92453 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
|---|
| 92454 | //BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
|---|
| 92455 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
|---|
| 92456 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
|---|
| 92457 | //BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST |
|---|
| 92458 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92459 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92460 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92461 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92462 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92463 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92464 | //BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP |
|---|
| 92465 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 92466 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
|---|
| 92467 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 92468 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 92469 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 92470 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 92471 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 92472 | #define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 92473 | //BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 92474 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92475 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92476 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92477 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92478 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92479 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92480 | //BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP |
|---|
| 92481 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 92482 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 92483 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 92484 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 92485 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 92486 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 92487 | //BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL |
|---|
| 92488 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 92489 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 92490 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 92491 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 92492 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 92493 | #define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 92494 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST |
|---|
| 92495 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92496 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92497 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92498 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92499 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92500 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92501 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP |
|---|
| 92502 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
|---|
| 92503 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
|---|
| 92504 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
|---|
| 92505 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
|---|
| 92506 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
|---|
| 92507 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
|---|
| 92508 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
|---|
| 92509 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
|---|
| 92510 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL |
|---|
| 92511 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
|---|
| 92512 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
|---|
| 92513 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
|---|
| 92514 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
|---|
| 92515 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
|---|
| 92516 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
|---|
| 92517 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
|---|
| 92518 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
|---|
| 92519 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
|---|
| 92520 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
|---|
| 92521 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
|---|
| 92522 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
|---|
| 92523 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS |
|---|
| 92524 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
|---|
| 92525 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
|---|
| 92526 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS |
|---|
| 92527 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
|---|
| 92528 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
|---|
| 92529 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS |
|---|
| 92530 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
|---|
| 92531 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
|---|
| 92532 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS |
|---|
| 92533 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
|---|
| 92534 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
|---|
| 92535 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK |
|---|
| 92536 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
|---|
| 92537 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
|---|
| 92538 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET |
|---|
| 92539 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
|---|
| 92540 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
|---|
| 92541 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE |
|---|
| 92542 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
|---|
| 92543 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
|---|
| 92544 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID |
|---|
| 92545 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
|---|
| 92546 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
|---|
| 92547 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
|---|
| 92548 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
|---|
| 92549 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 92550 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
|---|
| 92551 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
|---|
| 92552 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 92553 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 |
|---|
| 92554 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 92555 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 92556 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 |
|---|
| 92557 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 92558 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 92559 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 |
|---|
| 92560 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 92561 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 92562 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 |
|---|
| 92563 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 92564 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 92565 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 |
|---|
| 92566 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 92567 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 92568 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 |
|---|
| 92569 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 92570 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 92571 | //BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
|---|
| 92572 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 |
|---|
| 92573 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
|---|
| 92574 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L |
|---|
| 92575 | #define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 92576 | //BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 92577 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92578 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92579 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92580 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92581 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92582 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92583 | //BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP |
|---|
| 92584 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 92585 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 92586 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 92587 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 92588 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 92589 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 92590 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 92591 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 92592 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 92593 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 92594 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 92595 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 92596 | //BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL |
|---|
| 92597 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 92598 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 92599 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 92600 | #define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 92601 | //BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST |
|---|
| 92602 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92603 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92604 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92605 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92606 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92607 | #define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92608 | //BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP |
|---|
| 92609 | #define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 92610 | #define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
|---|
| 92611 | #define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 92612 | #define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
|---|
| 92613 | //BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS |
|---|
| 92614 | #define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 92615 | #define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
|---|
| 92616 | #define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 92617 | #define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
|---|
| 92618 | //BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST |
|---|
| 92619 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92620 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92621 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92622 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92623 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92624 | #define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92625 | //BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT |
|---|
| 92626 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
|---|
| 92627 | #define BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 92628 | //BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT |
|---|
| 92629 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
|---|
| 92630 | #define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 92631 | //BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT |
|---|
| 92632 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
|---|
| 92633 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
|---|
| 92634 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
|---|
| 92635 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
|---|
| 92636 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
|---|
| 92637 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
|---|
| 92638 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
|---|
| 92639 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
|---|
| 92640 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
|---|
| 92641 | #define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
|---|
| 92642 | //BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT |
|---|
| 92643 | #define BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 92644 | #define BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 92645 | //BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT |
|---|
| 92646 | #define BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 92647 | #define BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 92648 | //BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT |
|---|
| 92649 | #define BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 92650 | #define BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 92651 | //BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT |
|---|
| 92652 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92653 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92654 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92655 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92656 | //BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT |
|---|
| 92657 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92658 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92659 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92660 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92661 | //BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT |
|---|
| 92662 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92663 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92664 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92665 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92666 | //BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT |
|---|
| 92667 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92668 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92669 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92670 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92671 | //BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT |
|---|
| 92672 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92673 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92674 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92675 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92676 | //BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT |
|---|
| 92677 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92678 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92679 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92680 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92681 | //BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT |
|---|
| 92682 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92683 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92684 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92685 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92686 | //BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT |
|---|
| 92687 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92688 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92689 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92690 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92691 | //BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT |
|---|
| 92692 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92693 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92694 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92695 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92696 | //BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT |
|---|
| 92697 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92698 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92699 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92700 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92701 | //BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT |
|---|
| 92702 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92703 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92704 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92705 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92706 | //BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT |
|---|
| 92707 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92708 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92709 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92710 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92711 | //BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT |
|---|
| 92712 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92713 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92714 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92715 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92716 | //BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT |
|---|
| 92717 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92718 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92719 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92720 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92721 | //BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 92722 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92723 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92724 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92725 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92726 | //BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 92727 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 92728 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 92729 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 92730 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 92731 | //BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 92732 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 92733 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 92734 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 92735 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 92736 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 92737 | #define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 92738 | //BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP |
|---|
| 92739 | #define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 92740 | #define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 92741 | //BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS |
|---|
| 92742 | #define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
|---|
| 92743 | #define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
|---|
| 92744 | #define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
|---|
| 92745 | #define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
|---|
| 92746 | //BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL |
|---|
| 92747 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92748 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92749 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92750 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92751 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92752 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92753 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 92754 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92755 | //BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS |
|---|
| 92756 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92757 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92758 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92759 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92760 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92761 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92762 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92763 | #define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92764 | //BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL |
|---|
| 92765 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92766 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92767 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92768 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92769 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92770 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92771 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 92772 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92773 | //BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS |
|---|
| 92774 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92775 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92776 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92777 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92778 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92779 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92780 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92781 | #define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92782 | //BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL |
|---|
| 92783 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92784 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92785 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92786 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92787 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92788 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92789 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 92790 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92791 | //BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS |
|---|
| 92792 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92793 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92794 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92795 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92796 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92797 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92798 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92799 | #define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92800 | //BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL |
|---|
| 92801 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92802 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92803 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92804 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92805 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92806 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92807 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 92808 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92809 | //BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS |
|---|
| 92810 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92811 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92812 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92813 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92814 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92815 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92816 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92817 | #define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92818 | //BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL |
|---|
| 92819 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92820 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92821 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92822 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92823 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92824 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92825 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 92826 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92827 | //BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS |
|---|
| 92828 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92829 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92830 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92831 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92832 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92833 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92834 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92835 | #define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92836 | //BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL |
|---|
| 92837 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92838 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92839 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92840 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92841 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92842 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92843 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 92844 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92845 | //BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS |
|---|
| 92846 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92847 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92848 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92849 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92850 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92851 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92852 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92853 | #define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92854 | //BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL |
|---|
| 92855 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92856 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92857 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92858 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92859 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92860 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92861 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 92862 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92863 | //BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS |
|---|
| 92864 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92865 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92866 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92867 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92868 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92869 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92870 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92871 | #define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92872 | //BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL |
|---|
| 92873 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92874 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92875 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92876 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92877 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92878 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92879 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 92880 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92881 | //BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS |
|---|
| 92882 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92883 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92884 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92885 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92886 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92887 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92888 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92889 | #define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92890 | //BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL |
|---|
| 92891 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92892 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92893 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92894 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92895 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92896 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92897 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 92898 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92899 | //BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS |
|---|
| 92900 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92901 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92902 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92903 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92904 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92905 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92906 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92907 | #define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92908 | //BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL |
|---|
| 92909 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92910 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92911 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92912 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92913 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92914 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92915 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 92916 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92917 | //BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS |
|---|
| 92918 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92919 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92920 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92921 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92922 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92923 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92924 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92925 | #define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92926 | //BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL |
|---|
| 92927 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92928 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92929 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92930 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92931 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92932 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92933 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 92934 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92935 | //BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS |
|---|
| 92936 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92937 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92938 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92939 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92940 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92941 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92942 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92943 | #define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92944 | //BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL |
|---|
| 92945 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92946 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92947 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92948 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92949 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92950 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92951 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 92952 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92953 | //BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS |
|---|
| 92954 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92955 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92956 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92957 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92958 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92959 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92960 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92961 | #define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92962 | //BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL |
|---|
| 92963 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92964 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92965 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92966 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92967 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92968 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92969 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 92970 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92971 | //BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS |
|---|
| 92972 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92973 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92974 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92975 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92976 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92977 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92978 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92979 | #define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92980 | //BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL |
|---|
| 92981 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 92982 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 92983 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 92984 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 92985 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 92986 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 92987 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 92988 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 92989 | //BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS |
|---|
| 92990 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 92991 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 92992 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 92993 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 92994 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 92995 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 92996 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 92997 | #define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 92998 | //BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL |
|---|
| 92999 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 93000 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 93001 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 93002 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 93003 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 93004 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 93005 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 93006 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 93007 | //BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS |
|---|
| 93008 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 93009 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 93010 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 93011 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 93012 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 93013 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 93014 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 93015 | #define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 93016 | //BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL |
|---|
| 93017 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 93018 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 93019 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 93020 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 93021 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 93022 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 93023 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 93024 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 93025 | //BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS |
|---|
| 93026 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 93027 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 93028 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 93029 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 93030 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 93031 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 93032 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 93033 | #define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 93034 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
|---|
| 93035 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 93036 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 93037 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 93038 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 93039 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 93040 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 93041 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP |
|---|
| 93042 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 93043 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 93044 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL |
|---|
| 93045 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 93046 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 93047 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 93048 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 93049 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 93050 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 93051 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP |
|---|
| 93052 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 93053 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 93054 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL |
|---|
| 93055 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 93056 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 93057 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 93058 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 93059 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 93060 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 93061 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP |
|---|
| 93062 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 93063 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 93064 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL |
|---|
| 93065 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 93066 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 93067 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 93068 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 93069 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 93070 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 93071 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP |
|---|
| 93072 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 93073 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 93074 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL |
|---|
| 93075 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 93076 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 93077 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 93078 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 93079 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 93080 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 93081 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP |
|---|
| 93082 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 93083 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 93084 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL |
|---|
| 93085 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 93086 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 93087 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 93088 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 93089 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 93090 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 93091 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP |
|---|
| 93092 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 93093 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 93094 | //BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL |
|---|
| 93095 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 93096 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 93097 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 93098 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 93099 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 93100 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 93101 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
|---|
| 93102 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
|---|
| 93103 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
|---|
| 93104 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
|---|
| 93105 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
|---|
| 93106 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
|---|
| 93107 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 93108 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
|---|
| 93109 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
|---|
| 93110 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
|---|
| 93111 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 93112 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 93113 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
|---|
| 93114 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 93115 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
|---|
| 93116 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
|---|
| 93117 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
|---|
| 93118 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
|---|
| 93119 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
|---|
| 93120 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
|---|
| 93121 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
|---|
| 93122 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
|---|
| 93123 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
|---|
| 93124 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
|---|
| 93125 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
|---|
| 93126 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
|---|
| 93127 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
|---|
| 93128 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
|---|
| 93129 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc |
|---|
| 93130 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd |
|---|
| 93131 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe |
|---|
| 93132 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf |
|---|
| 93133 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
|---|
| 93134 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
|---|
| 93135 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
|---|
| 93136 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
|---|
| 93137 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
|---|
| 93138 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
|---|
| 93139 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
|---|
| 93140 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
|---|
| 93141 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
|---|
| 93142 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
|---|
| 93143 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
|---|
| 93144 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
|---|
| 93145 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
|---|
| 93146 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
|---|
| 93147 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L |
|---|
| 93148 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L |
|---|
| 93149 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L |
|---|
| 93150 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L |
|---|
| 93151 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
|---|
| 93152 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
|---|
| 93153 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
|---|
| 93154 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
|---|
| 93155 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
|---|
| 93156 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
|---|
| 93157 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
|---|
| 93158 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
|---|
| 93159 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
|---|
| 93160 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
|---|
| 93161 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
|---|
| 93162 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
|---|
| 93163 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
|---|
| 93164 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
|---|
| 93165 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
|---|
| 93166 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc |
|---|
| 93167 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd |
|---|
| 93168 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe |
|---|
| 93169 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf |
|---|
| 93170 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
|---|
| 93171 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
|---|
| 93172 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
|---|
| 93173 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
|---|
| 93174 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
|---|
| 93175 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
|---|
| 93176 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
|---|
| 93177 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
|---|
| 93178 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
|---|
| 93179 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
|---|
| 93180 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
|---|
| 93181 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
|---|
| 93182 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
|---|
| 93183 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
|---|
| 93184 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L |
|---|
| 93185 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L |
|---|
| 93186 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L |
|---|
| 93187 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L |
|---|
| 93188 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
|---|
| 93189 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
|---|
| 93190 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
|---|
| 93191 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
|---|
| 93192 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
|---|
| 93193 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
|---|
| 93194 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
|---|
| 93195 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
|---|
| 93196 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
|---|
| 93197 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
|---|
| 93198 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
|---|
| 93199 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 93200 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
|---|
| 93201 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 93202 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
|---|
| 93203 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
|---|
| 93204 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 93205 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 93206 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 93207 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
|---|
| 93208 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
|---|
| 93209 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
|---|
| 93210 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
|---|
| 93211 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
|---|
| 93212 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
|---|
| 93213 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
|---|
| 93214 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
|---|
| 93215 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
|---|
| 93216 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
|---|
| 93217 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
|---|
| 93218 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
|---|
| 93219 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
|---|
| 93220 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
|---|
| 93221 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
|---|
| 93222 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
|---|
| 93223 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
|---|
| 93224 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
|---|
| 93225 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
|---|
| 93226 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
|---|
| 93227 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
|---|
| 93228 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
|---|
| 93229 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
|---|
| 93230 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
|---|
| 93231 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
|---|
| 93232 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
|---|
| 93233 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
|---|
| 93234 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
|---|
| 93235 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
|---|
| 93236 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
|---|
| 93237 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
|---|
| 93238 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
|---|
| 93239 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
|---|
| 93240 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
|---|
| 93241 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
|---|
| 93242 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
|---|
| 93243 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
|---|
| 93244 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
|---|
| 93245 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
|---|
| 93246 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
|---|
| 93247 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
|---|
| 93248 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
|---|
| 93249 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
|---|
| 93250 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
|---|
| 93251 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
|---|
| 93252 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
|---|
| 93253 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
|---|
| 93254 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
|---|
| 93255 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
|---|
| 93256 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
|---|
| 93257 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
|---|
| 93258 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
|---|
| 93259 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
|---|
| 93260 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
|---|
| 93261 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
|---|
| 93262 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
|---|
| 93263 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
|---|
| 93264 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
|---|
| 93265 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
|---|
| 93266 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
|---|
| 93267 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
|---|
| 93268 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
|---|
| 93269 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
|---|
| 93270 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
|---|
| 93271 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
|---|
| 93272 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
|---|
| 93273 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
|---|
| 93274 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 |
|---|
| 93275 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 |
|---|
| 93276 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 |
|---|
| 93277 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 |
|---|
| 93278 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 |
|---|
| 93279 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 |
|---|
| 93280 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 |
|---|
| 93281 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 |
|---|
| 93282 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 |
|---|
| 93283 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 |
|---|
| 93284 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa |
|---|
| 93285 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb |
|---|
| 93286 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc |
|---|
| 93287 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd |
|---|
| 93288 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe |
|---|
| 93289 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf |
|---|
| 93290 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 |
|---|
| 93291 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 |
|---|
| 93292 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 |
|---|
| 93293 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 |
|---|
| 93294 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 |
|---|
| 93295 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 |
|---|
| 93296 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 |
|---|
| 93297 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 |
|---|
| 93298 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 |
|---|
| 93299 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 |
|---|
| 93300 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a |
|---|
| 93301 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b |
|---|
| 93302 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c |
|---|
| 93303 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d |
|---|
| 93304 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e |
|---|
| 93305 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f |
|---|
| 93306 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L |
|---|
| 93307 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L |
|---|
| 93308 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L |
|---|
| 93309 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L |
|---|
| 93310 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L |
|---|
| 93311 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L |
|---|
| 93312 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L |
|---|
| 93313 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L |
|---|
| 93314 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L |
|---|
| 93315 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L |
|---|
| 93316 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L |
|---|
| 93317 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L |
|---|
| 93318 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L |
|---|
| 93319 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L |
|---|
| 93320 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L |
|---|
| 93321 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L |
|---|
| 93322 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L |
|---|
| 93323 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L |
|---|
| 93324 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L |
|---|
| 93325 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L |
|---|
| 93326 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L |
|---|
| 93327 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L |
|---|
| 93328 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L |
|---|
| 93329 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L |
|---|
| 93330 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L |
|---|
| 93331 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L |
|---|
| 93332 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L |
|---|
| 93333 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L |
|---|
| 93334 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L |
|---|
| 93335 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L |
|---|
| 93336 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L |
|---|
| 93337 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L |
|---|
| 93338 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
|---|
| 93339 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
|---|
| 93340 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
|---|
| 93341 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
|---|
| 93342 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
|---|
| 93343 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
|---|
| 93344 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
|---|
| 93345 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
|---|
| 93346 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
|---|
| 93347 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
|---|
| 93348 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
|---|
| 93349 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
|---|
| 93350 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
|---|
| 93351 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
|---|
| 93352 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
|---|
| 93353 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
|---|
| 93354 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18 |
|---|
| 93355 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
|---|
| 93356 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
|---|
| 93357 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
|---|
| 93358 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L |
|---|
| 93359 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION |
|---|
| 93360 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 |
|---|
| 93361 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 |
|---|
| 93362 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L |
|---|
| 93363 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L |
|---|
| 93364 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE |
|---|
| 93365 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 |
|---|
| 93366 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f |
|---|
| 93367 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL |
|---|
| 93368 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L |
|---|
| 93369 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
|---|
| 93370 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
|---|
| 93371 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
|---|
| 93372 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93373 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93374 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
|---|
| 93375 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
|---|
| 93376 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
|---|
| 93377 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93378 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93379 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
|---|
| 93380 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
|---|
| 93381 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
|---|
| 93382 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93383 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93384 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
|---|
| 93385 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
|---|
| 93386 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
|---|
| 93387 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93388 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93389 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
|---|
| 93390 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
|---|
| 93391 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
|---|
| 93392 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93393 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93394 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
|---|
| 93395 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
|---|
| 93396 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
|---|
| 93397 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93398 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93399 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
|---|
| 93400 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
|---|
| 93401 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
|---|
| 93402 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93403 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93404 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
|---|
| 93405 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
|---|
| 93406 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
|---|
| 93407 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93408 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93409 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
|---|
| 93410 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
|---|
| 93411 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
|---|
| 93412 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93413 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93414 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
|---|
| 93415 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
|---|
| 93416 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
|---|
| 93417 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93418 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93419 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
|---|
| 93420 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
|---|
| 93421 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
|---|
| 93422 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93423 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93424 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
|---|
| 93425 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
|---|
| 93426 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
|---|
| 93427 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93428 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93429 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
|---|
| 93430 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
|---|
| 93431 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
|---|
| 93432 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93433 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93434 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
|---|
| 93435 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
|---|
| 93436 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
|---|
| 93437 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93438 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93439 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
|---|
| 93440 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
|---|
| 93441 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
|---|
| 93442 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93443 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93444 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
|---|
| 93445 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
|---|
| 93446 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
|---|
| 93447 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93448 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93449 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB |
|---|
| 93450 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0 |
|---|
| 93451 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10 |
|---|
| 93452 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93453 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93454 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB |
|---|
| 93455 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0 |
|---|
| 93456 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10 |
|---|
| 93457 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93458 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93459 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB |
|---|
| 93460 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0 |
|---|
| 93461 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10 |
|---|
| 93462 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93463 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93464 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB |
|---|
| 93465 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0 |
|---|
| 93466 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10 |
|---|
| 93467 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93468 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93469 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB |
|---|
| 93470 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0 |
|---|
| 93471 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10 |
|---|
| 93472 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93473 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93474 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB |
|---|
| 93475 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0 |
|---|
| 93476 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10 |
|---|
| 93477 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93478 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93479 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB |
|---|
| 93480 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0 |
|---|
| 93481 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10 |
|---|
| 93482 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93483 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93484 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB |
|---|
| 93485 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0 |
|---|
| 93486 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10 |
|---|
| 93487 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93488 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93489 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB |
|---|
| 93490 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0 |
|---|
| 93491 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10 |
|---|
| 93492 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93493 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93494 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB |
|---|
| 93495 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0 |
|---|
| 93496 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10 |
|---|
| 93497 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93498 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93499 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB |
|---|
| 93500 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0 |
|---|
| 93501 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10 |
|---|
| 93502 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93503 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93504 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB |
|---|
| 93505 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0 |
|---|
| 93506 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10 |
|---|
| 93507 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93508 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93509 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB |
|---|
| 93510 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0 |
|---|
| 93511 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10 |
|---|
| 93512 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93513 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93514 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB |
|---|
| 93515 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0 |
|---|
| 93516 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10 |
|---|
| 93517 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93518 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93519 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB |
|---|
| 93520 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0 |
|---|
| 93521 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10 |
|---|
| 93522 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 93523 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 93524 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
|---|
| 93525 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 93526 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 93527 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
|---|
| 93528 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 93529 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 93530 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
|---|
| 93531 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 93532 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 93533 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
|---|
| 93534 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 93535 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 93536 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
|---|
| 93537 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 93538 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 93539 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
|---|
| 93540 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 93541 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 93542 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
|---|
| 93543 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 93544 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 93545 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
|---|
| 93546 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 93547 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 93548 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
|---|
| 93549 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 93550 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 93551 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
|---|
| 93552 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
|---|
| 93553 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 93554 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
|---|
| 93555 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
|---|
| 93556 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 93557 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
|---|
| 93558 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
|---|
| 93559 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 93560 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
|---|
| 93561 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
|---|
| 93562 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 93563 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
|---|
| 93564 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
|---|
| 93565 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 93566 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
|---|
| 93567 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
|---|
| 93568 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 93569 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
|---|
| 93570 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
|---|
| 93571 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 93572 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
|---|
| 93573 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
|---|
| 93574 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 93575 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
|---|
| 93576 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
|---|
| 93577 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 93578 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
|---|
| 93579 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 93580 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 93581 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
|---|
| 93582 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 93583 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 93584 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
|---|
| 93585 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 93586 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 93587 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
|---|
| 93588 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 93589 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 93590 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
|---|
| 93591 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 93592 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 93593 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
|---|
| 93594 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 93595 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 93596 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
|---|
| 93597 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 93598 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 93599 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
|---|
| 93600 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 93601 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 93602 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
|---|
| 93603 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 93604 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 93605 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 |
|---|
| 93606 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0 |
|---|
| 93607 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 93608 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 |
|---|
| 93609 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0 |
|---|
| 93610 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 93611 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 |
|---|
| 93612 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0 |
|---|
| 93613 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 93614 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 |
|---|
| 93615 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0 |
|---|
| 93616 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 93617 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 |
|---|
| 93618 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0 |
|---|
| 93619 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 93620 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 |
|---|
| 93621 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0 |
|---|
| 93622 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 93623 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 |
|---|
| 93624 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0 |
|---|
| 93625 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 93626 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 |
|---|
| 93627 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0 |
|---|
| 93628 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 93629 | //BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 |
|---|
| 93630 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0 |
|---|
| 93631 | #define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 93632 | |
|---|
| 93633 | |
|---|
| 93634 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
|---|
| 93635 | //BIF_CFG_DEV0_EPF1_1_VENDOR_ID |
|---|
| 93636 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 93637 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 93638 | //BIF_CFG_DEV0_EPF1_1_DEVICE_ID |
|---|
| 93639 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 93640 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 93641 | //BIF_CFG_DEV0_EPF1_1_COMMAND |
|---|
| 93642 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 93643 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 93644 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 93645 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 93646 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 93647 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 93648 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 93649 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 93650 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 93651 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 93652 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 93653 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 93654 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 93655 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 93656 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 93657 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 93658 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 93659 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 93660 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 93661 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 93662 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 93663 | #define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 93664 | //BIF_CFG_DEV0_EPF1_1_STATUS |
|---|
| 93665 | #define BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 93666 | #define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 93667 | #define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 93668 | #define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 93669 | #define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 93670 | #define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 93671 | #define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 93672 | #define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 93673 | #define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 93674 | #define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 93675 | #define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 93676 | #define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 93677 | #define BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 93678 | #define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 93679 | #define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 93680 | #define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 93681 | #define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 93682 | #define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 93683 | #define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 93684 | #define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 93685 | #define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 93686 | #define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 93687 | #define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 93688 | #define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 93689 | //BIF_CFG_DEV0_EPF1_1_REVISION_ID |
|---|
| 93690 | #define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 93691 | #define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 93692 | #define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 93693 | #define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 93694 | //BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE |
|---|
| 93695 | #define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 93696 | #define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 93697 | //BIF_CFG_DEV0_EPF1_1_SUB_CLASS |
|---|
| 93698 | #define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 93699 | #define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 93700 | //BIF_CFG_DEV0_EPF1_1_BASE_CLASS |
|---|
| 93701 | #define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 93702 | #define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 93703 | //BIF_CFG_DEV0_EPF1_1_CACHE_LINE |
|---|
| 93704 | #define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 93705 | #define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 93706 | //BIF_CFG_DEV0_EPF1_1_LATENCY |
|---|
| 93707 | #define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 93708 | #define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 93709 | //BIF_CFG_DEV0_EPF1_1_HEADER |
|---|
| 93710 | #define 0x0 |
|---|
| 93711 | #define 0x7 |
|---|
| 93712 | #define 0x7FL |
|---|
| 93713 | #define 0x80L |
|---|
| 93714 | //BIF_CFG_DEV0_EPF1_1_BIST |
|---|
| 93715 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 93716 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 93717 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 93718 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 93719 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 93720 | #define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 93721 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 |
|---|
| 93722 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 93723 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 93724 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 |
|---|
| 93725 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 93726 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 93727 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 |
|---|
| 93728 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 93729 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 93730 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 |
|---|
| 93731 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 93732 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 93733 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 |
|---|
| 93734 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 93735 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 93736 | //BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 |
|---|
| 93737 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 93738 | #define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 93739 | //BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR |
|---|
| 93740 | #define BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 93741 | #define BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 93742 | //BIF_CFG_DEV0_EPF1_1_ADAPTER_ID |
|---|
| 93743 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 93744 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 93745 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 93746 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 93747 | //BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR |
|---|
| 93748 | #define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 93749 | #define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 93750 | //BIF_CFG_DEV0_EPF1_1_CAP_PTR |
|---|
| 93751 | #define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 93752 | #define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 93753 | //BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE |
|---|
| 93754 | #define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 93755 | #define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 93756 | //BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN |
|---|
| 93757 | #define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 93758 | #define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 93759 | //BIF_CFG_DEV0_EPF1_1_MIN_GRANT |
|---|
| 93760 | #define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 93761 | #define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 93762 | //BIF_CFG_DEV0_EPF1_1_MAX_LATENCY |
|---|
| 93763 | #define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 93764 | #define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 93765 | //BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST |
|---|
| 93766 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 93767 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 93768 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 93769 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 93770 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 93771 | #define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 93772 | //BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W |
|---|
| 93773 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 93774 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 93775 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 93776 | #define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 93777 | //BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST |
|---|
| 93778 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 93779 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 93780 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 93781 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 93782 | //BIF_CFG_DEV0_EPF1_1_PMI_CAP |
|---|
| 93783 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 93784 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 93785 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 93786 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 93787 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 93788 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 93789 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 93790 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 93791 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 93792 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 93793 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 93794 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 93795 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 93796 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 93797 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 93798 | #define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 93799 | //BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL |
|---|
| 93800 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 93801 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 93802 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 93803 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 93804 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 93805 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 93806 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 93807 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 93808 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 93809 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 93810 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 93811 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 93812 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 93813 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 93814 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 93815 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 93816 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 93817 | #define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 93818 | //BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST |
|---|
| 93819 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 93820 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 93821 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 93822 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 93823 | //BIF_CFG_DEV0_EPF1_1_PCIE_CAP |
|---|
| 93824 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 93825 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 93826 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 93827 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 93828 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 93829 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 93830 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 93831 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 93832 | //BIF_CFG_DEV0_EPF1_1_DEVICE_CAP |
|---|
| 93833 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 93834 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 93835 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 93836 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 93837 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 93838 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 93839 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 93840 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 93841 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 93842 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 93843 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 93844 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 93845 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 93846 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 93847 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 93848 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 93849 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 93850 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 93851 | //BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL |
|---|
| 93852 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 93853 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 93854 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 93855 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 93856 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 93857 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 93858 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 93859 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 93860 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 93861 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 93862 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 93863 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 93864 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 93865 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 93866 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 93867 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 93868 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 93869 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 93870 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 93871 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 93872 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 93873 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 93874 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 93875 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 93876 | //BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS |
|---|
| 93877 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 93878 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 93879 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 93880 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 93881 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 93882 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 93883 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 93884 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 93885 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 93886 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 93887 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 93888 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 93889 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 93890 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 93891 | //BIF_CFG_DEV0_EPF1_1_LINK_CAP |
|---|
| 93892 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 93893 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 93894 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 93895 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 93896 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 93897 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 93898 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 93899 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 93900 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 93901 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 93902 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 93903 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 93904 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 93905 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 93906 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 93907 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 93908 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 93909 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 93910 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 93911 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 93912 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 93913 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 93914 | //BIF_CFG_DEV0_EPF1_1_LINK_CNTL |
|---|
| 93915 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 93916 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 93917 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 93918 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 93919 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 93920 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 93921 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 93922 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 93923 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 93924 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 93925 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 93926 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 93927 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 93928 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 93929 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 93930 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 93931 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 93932 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 93933 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 93934 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 93935 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 93936 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 93937 | //BIF_CFG_DEV0_EPF1_1_LINK_STATUS |
|---|
| 93938 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 93939 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 93940 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 93941 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 93942 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 93943 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 93944 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 93945 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 93946 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 93947 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 93948 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 93949 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 93950 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 93951 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 93952 | //BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 |
|---|
| 93953 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 93954 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 93955 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 93956 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 93957 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 93958 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 93959 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 93960 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 93961 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 93962 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 93963 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 93964 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 93965 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 93966 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 93967 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 93968 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 93969 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 93970 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 93971 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 93972 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 93973 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 93974 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 93975 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 93976 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 93977 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 93978 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 93979 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 93980 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 93981 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 93982 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 93983 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 93984 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 93985 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 93986 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 93987 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 93988 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 93989 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 93990 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 93991 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 93992 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 93993 | //BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 |
|---|
| 93994 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 93995 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 93996 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 93997 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 93998 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 93999 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 94000 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 94001 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 94002 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 94003 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 94004 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 94005 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 94006 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 94007 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 94008 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 94009 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 94010 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 94011 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 94012 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 94013 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 94014 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 94015 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 94016 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 94017 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 94018 | //BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 |
|---|
| 94019 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 94020 | #define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 94021 | //BIF_CFG_DEV0_EPF1_1_LINK_CAP2 |
|---|
| 94022 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 94023 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 94024 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 94025 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 94026 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 94027 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 94028 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 94029 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 94030 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 94031 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 94032 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 94033 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 94034 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 94035 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 94036 | //BIF_CFG_DEV0_EPF1_1_LINK_CNTL2 |
|---|
| 94037 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 94038 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 94039 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 94040 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 94041 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 94042 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 94043 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 94044 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 94045 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 94046 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 94047 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 94048 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 94049 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 94050 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 94051 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 94052 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 94053 | //BIF_CFG_DEV0_EPF1_1_LINK_STATUS2 |
|---|
| 94054 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 94055 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 94056 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 94057 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 94058 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 94059 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 94060 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 94061 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 94062 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 94063 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 94064 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 94065 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 94066 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 94067 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 94068 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 94069 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 94070 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 94071 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 94072 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 94073 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 94074 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 94075 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 94076 | //BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST |
|---|
| 94077 | #define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94078 | #define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 94079 | #define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 94080 | #define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 94081 | //BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL |
|---|
| 94082 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 94083 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 94084 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 94085 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 94086 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 94087 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 94088 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 94089 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 94090 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 94091 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 94092 | //BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO |
|---|
| 94093 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 94094 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 94095 | //BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI |
|---|
| 94096 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 94097 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 94098 | //BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA |
|---|
| 94099 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 94100 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 94101 | //BIF_CFG_DEV0_EPF1_1_MSI_MASK |
|---|
| 94102 | #define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 94103 | #define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 94104 | //BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 |
|---|
| 94105 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 94106 | #define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 94107 | //BIF_CFG_DEV0_EPF1_1_MSI_MASK_64 |
|---|
| 94108 | #define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 94109 | #define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 94110 | //BIF_CFG_DEV0_EPF1_1_MSI_PENDING |
|---|
| 94111 | #define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 94112 | #define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 94113 | //BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 |
|---|
| 94114 | #define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 94115 | #define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 94116 | //BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST |
|---|
| 94117 | #define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94118 | #define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 94119 | #define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 94120 | #define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 94121 | //BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL |
|---|
| 94122 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 94123 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 94124 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 94125 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 94126 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 94127 | #define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 94128 | //BIF_CFG_DEV0_EPF1_1_MSIX_TABLE |
|---|
| 94129 | #define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 94130 | #define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 94131 | #define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 94132 | #define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 94133 | //BIF_CFG_DEV0_EPF1_1_MSIX_PBA |
|---|
| 94134 | #define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 94135 | #define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 94136 | #define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 94137 | #define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 94138 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 94139 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94140 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94141 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94142 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94143 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94144 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94145 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 94146 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 94147 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 94148 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 94149 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 94150 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 94151 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 94152 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 94153 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 94154 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 94155 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 94156 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 94157 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 94158 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST |
|---|
| 94159 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94160 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94161 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94162 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94163 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94164 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94165 | //BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1 |
|---|
| 94166 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 94167 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 94168 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 94169 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 94170 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 94171 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 94172 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 94173 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 94174 | //BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2 |
|---|
| 94175 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 94176 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 94177 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 94178 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 94179 | //BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL |
|---|
| 94180 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 94181 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 94182 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 94183 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 94184 | //BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS |
|---|
| 94185 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 94186 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 94187 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP |
|---|
| 94188 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 94189 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 94190 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 94191 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 94192 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 94193 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 94194 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 94195 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 94196 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL |
|---|
| 94197 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 94198 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 94199 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 94200 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 94201 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 94202 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 94203 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 94204 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 94205 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 94206 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 94207 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 94208 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 94209 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS |
|---|
| 94210 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 94211 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 94212 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 94213 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 94214 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP |
|---|
| 94215 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 94216 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 94217 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 94218 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 94219 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 94220 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 94221 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 94222 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 94223 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL |
|---|
| 94224 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 94225 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 94226 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 94227 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 94228 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 94229 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 94230 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 94231 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 94232 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 94233 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 94234 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 94235 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 94236 | //BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS |
|---|
| 94237 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 94238 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 94239 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 94240 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 94241 | //BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 94242 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94243 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94244 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94245 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94246 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94247 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94248 | //BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 94249 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 94250 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 94251 | //BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 94252 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 94253 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 94254 | //BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 94255 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94256 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94257 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94258 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94259 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94260 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94261 | //BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 94262 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 94263 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 94264 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 94265 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 94266 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 94267 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 94268 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 94269 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 94270 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 94271 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 94272 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 94273 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 94274 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 94275 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 94276 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 94277 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 94278 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 94279 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 94280 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 94281 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 94282 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 94283 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 94284 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 94285 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 94286 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 94287 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 94288 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 94289 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 94290 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 94291 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 94292 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 94293 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 94294 | //BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK |
|---|
| 94295 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 94296 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 94297 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 94298 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 94299 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 94300 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 94301 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 94302 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 94303 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 94304 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 94305 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 94306 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 94307 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 94308 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 94309 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 94310 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 94311 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 94312 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 94313 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 94314 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 94315 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 94316 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 94317 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 94318 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 94319 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 94320 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 94321 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 94322 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 94323 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 94324 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 94325 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 94326 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 94327 | //BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 94328 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 94329 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 94330 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 94331 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 94332 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 94333 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 94334 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 94335 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 94336 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 94337 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 94338 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 94339 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 94340 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 94341 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 94342 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 94343 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 94344 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 94345 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 94346 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 94347 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 94348 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 94349 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 94350 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 94351 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 94352 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 94353 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 94354 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 94355 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 94356 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 94357 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 94358 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 94359 | #define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 94360 | //BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS |
|---|
| 94361 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 94362 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 94363 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 94364 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 94365 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 94366 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 94367 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 94368 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 94369 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 94370 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 94371 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 94372 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 94373 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 94374 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 94375 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 94376 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 94377 | //BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK |
|---|
| 94378 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 94379 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 94380 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 94381 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 94382 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 94383 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 94384 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 94385 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 94386 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 94387 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 94388 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 94389 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 94390 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 94391 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 94392 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 94393 | #define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 94394 | //BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 94395 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 94396 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 94397 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 94398 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 94399 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 94400 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 94401 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 94402 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 94403 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 94404 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 94405 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 94406 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 94407 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 94408 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 94409 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 94410 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 94411 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 94412 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 94413 | //BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 |
|---|
| 94414 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 94415 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 94416 | //BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 |
|---|
| 94417 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 94418 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 94419 | //BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 |
|---|
| 94420 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 94421 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 94422 | //BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 |
|---|
| 94423 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 94424 | #define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 94425 | //BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 94426 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 94427 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 94428 | //BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 94429 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 94430 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 94431 | //BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 94432 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 94433 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 94434 | //BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 94435 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 94436 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 94437 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST |
|---|
| 94438 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94439 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94440 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94441 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94442 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94443 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94444 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP |
|---|
| 94445 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 94446 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 94447 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL |
|---|
| 94448 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 94449 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 94450 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 94451 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 94452 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 94453 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 94454 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP |
|---|
| 94455 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 94456 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 94457 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL |
|---|
| 94458 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 94459 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 94460 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 94461 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 94462 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 94463 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 94464 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP |
|---|
| 94465 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 94466 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 94467 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL |
|---|
| 94468 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 94469 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 94470 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 94471 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 94472 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 94473 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 94474 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP |
|---|
| 94475 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 94476 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 94477 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL |
|---|
| 94478 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 94479 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 94480 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 94481 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 94482 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 94483 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 94484 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP |
|---|
| 94485 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 94486 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 94487 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL |
|---|
| 94488 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 94489 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 94490 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 94491 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 94492 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 94493 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 94494 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP |
|---|
| 94495 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 94496 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 94497 | //BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL |
|---|
| 94498 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 94499 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 94500 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 94501 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 94502 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 94503 | #define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 94504 | //BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 94505 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94506 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94507 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94508 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94509 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94510 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94511 | //BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 94512 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 94513 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 94514 | //BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA |
|---|
| 94515 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 94516 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 94517 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 94518 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 94519 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 94520 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 94521 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 94522 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 94523 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 94524 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 94525 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 94526 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 94527 | //BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP |
|---|
| 94528 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 94529 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 94530 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST |
|---|
| 94531 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94532 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94533 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94534 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94535 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94536 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94537 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP |
|---|
| 94538 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 94539 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 94540 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 94541 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 94542 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 94543 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 94544 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 94545 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 94546 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 94547 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 94548 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 94549 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 94550 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 94551 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS |
|---|
| 94552 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 94553 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 94554 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 94555 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 94556 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL |
|---|
| 94557 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 94558 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 94559 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 94560 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 94561 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 94562 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 94563 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 94564 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 94565 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 94566 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 94567 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 94568 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 94569 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 94570 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 94571 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 94572 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 94573 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 94574 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 94575 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 94576 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 94577 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 94578 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 94579 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 94580 | //BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 94581 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 94582 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 94583 | //BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 94584 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94585 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94586 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94587 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94588 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94589 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94590 | //BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 |
|---|
| 94591 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 94592 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
|---|
| 94593 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
|---|
| 94594 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 94595 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 94596 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
|---|
| 94597 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS |
|---|
| 94598 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 94599 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
|---|
| 94600 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 94601 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
|---|
| 94602 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 94603 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94604 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94605 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94606 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94607 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94608 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94609 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94610 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94611 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94612 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94613 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL |
|---|
| 94614 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94615 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94616 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94617 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94618 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94619 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94620 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94621 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94622 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94623 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94624 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL |
|---|
| 94625 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94626 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94627 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94628 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94629 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94630 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94631 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94632 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94633 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94634 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94635 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL |
|---|
| 94636 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94637 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94638 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94639 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94640 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94641 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94642 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94643 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94644 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94645 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94646 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL |
|---|
| 94647 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94648 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94649 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94650 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94651 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94652 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94653 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94654 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94655 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94656 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94657 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 94658 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94659 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94660 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94661 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94662 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94663 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94664 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94665 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94666 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94667 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94668 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 94669 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94670 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94671 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94672 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94673 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94674 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94675 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94676 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94677 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94678 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94679 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 94680 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94681 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94682 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94683 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94684 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94685 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94686 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94687 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94688 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94689 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94690 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 94691 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94692 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94693 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94694 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94695 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94696 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94697 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94698 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94699 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94700 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94701 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 94702 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94703 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94704 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94705 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94706 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94707 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94708 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94709 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94710 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94711 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94712 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 94713 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94714 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94715 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94716 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94717 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94718 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94719 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94720 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94721 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94722 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94723 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 94724 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94725 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94726 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94727 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94728 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94729 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94730 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94731 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94732 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94733 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94734 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 94735 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94736 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94737 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94738 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94739 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94740 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94741 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94742 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94743 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94744 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94745 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 94746 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94747 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94748 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94749 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94750 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94751 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94752 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94753 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94754 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94755 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94756 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 94757 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94758 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94759 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94760 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94761 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94762 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94763 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94764 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94765 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94766 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94767 | //BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 94768 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 94769 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 94770 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 94771 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 94772 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 94773 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 94774 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 94775 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 94776 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 94777 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 94778 | //BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST |
|---|
| 94779 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94780 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94781 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94782 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94783 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94784 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94785 | //BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP |
|---|
| 94786 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 94787 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 94788 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 94789 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 94790 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 94791 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 94792 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 94793 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 94794 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 94795 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 94796 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 94797 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 94798 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 94799 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 94800 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 94801 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 94802 | //BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL |
|---|
| 94803 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 94804 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 94805 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 94806 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 94807 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 94808 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 94809 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 94810 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 94811 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 94812 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 94813 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 94814 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 94815 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 94816 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 94817 | //BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 94818 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94819 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94820 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94821 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94822 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94823 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94824 | //BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP |
|---|
| 94825 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 94826 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 94827 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 94828 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 94829 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 94830 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 94831 | //BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL |
|---|
| 94832 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 94833 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 94834 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 94835 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 94836 | //BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST |
|---|
| 94837 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94838 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94839 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94840 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94841 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94842 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94843 | //BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL |
|---|
| 94844 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
|---|
| 94845 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
|---|
| 94846 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
|---|
| 94847 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
|---|
| 94848 | //BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS |
|---|
| 94849 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
|---|
| 94850 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
|---|
| 94851 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
|---|
| 94852 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
|---|
| 94853 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
|---|
| 94854 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
|---|
| 94855 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
|---|
| 94856 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
|---|
| 94857 | //BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
|---|
| 94858 | #define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
|---|
| 94859 | #define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
|---|
| 94860 | //BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
|---|
| 94861 | #define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
|---|
| 94862 | #define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
|---|
| 94863 | //BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST |
|---|
| 94864 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94865 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94866 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94867 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94868 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94869 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94870 | //BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP |
|---|
| 94871 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 94872 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 94873 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 94874 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 94875 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 94876 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 94877 | //BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL |
|---|
| 94878 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 94879 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 94880 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 94881 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 94882 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 94883 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 94884 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST |
|---|
| 94885 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94886 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94887 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94888 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94889 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94890 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94891 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP |
|---|
| 94892 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
|---|
| 94893 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
|---|
| 94894 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
|---|
| 94895 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
|---|
| 94896 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
|---|
| 94897 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
|---|
| 94898 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL |
|---|
| 94899 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
|---|
| 94900 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
|---|
| 94901 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
|---|
| 94902 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
|---|
| 94903 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 |
|---|
| 94904 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
|---|
| 94905 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
|---|
| 94906 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
|---|
| 94907 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
|---|
| 94908 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 |
|---|
| 94909 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
|---|
| 94910 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
|---|
| 94911 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 |
|---|
| 94912 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
|---|
| 94913 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
|---|
| 94914 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 |
|---|
| 94915 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
|---|
| 94916 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
|---|
| 94917 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 |
|---|
| 94918 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
|---|
| 94919 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
|---|
| 94920 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 |
|---|
| 94921 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
|---|
| 94922 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
|---|
| 94923 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 |
|---|
| 94924 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
|---|
| 94925 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
|---|
| 94926 | //BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 |
|---|
| 94927 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
|---|
| 94928 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
|---|
| 94929 | //BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST |
|---|
| 94930 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94931 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94932 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94933 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94934 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94935 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94936 | //BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP |
|---|
| 94937 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 94938 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
|---|
| 94939 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 94940 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 94941 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 94942 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 94943 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 94944 | #define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 94945 | //BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 94946 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94947 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94948 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94949 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94950 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94951 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94952 | //BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP |
|---|
| 94953 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 94954 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 94955 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 94956 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 94957 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 94958 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 94959 | //BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL |
|---|
| 94960 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 94961 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 94962 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 94963 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 94964 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 94965 | #define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 94966 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST |
|---|
| 94967 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 94968 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 94969 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 94970 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 94971 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 94972 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 94973 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP |
|---|
| 94974 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
|---|
| 94975 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
|---|
| 94976 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 |
|---|
| 94977 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
|---|
| 94978 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
|---|
| 94979 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
|---|
| 94980 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L |
|---|
| 94981 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
|---|
| 94982 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL |
|---|
| 94983 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
|---|
| 94984 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
|---|
| 94985 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
|---|
| 94986 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
|---|
| 94987 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
|---|
| 94988 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 |
|---|
| 94989 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
|---|
| 94990 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
|---|
| 94991 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
|---|
| 94992 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
|---|
| 94993 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
|---|
| 94994 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L |
|---|
| 94995 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS |
|---|
| 94996 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
|---|
| 94997 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
|---|
| 94998 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS |
|---|
| 94999 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
|---|
| 95000 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
|---|
| 95001 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS |
|---|
| 95002 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
|---|
| 95003 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
|---|
| 95004 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS |
|---|
| 95005 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
|---|
| 95006 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
|---|
| 95007 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK |
|---|
| 95008 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
|---|
| 95009 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL |
|---|
| 95010 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET |
|---|
| 95011 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
|---|
| 95012 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
|---|
| 95013 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE |
|---|
| 95014 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
|---|
| 95015 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
|---|
| 95016 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID |
|---|
| 95017 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
|---|
| 95018 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
|---|
| 95019 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
|---|
| 95020 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
|---|
| 95021 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 95022 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
|---|
| 95023 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
|---|
| 95024 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 95025 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 |
|---|
| 95026 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 95027 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 95028 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 |
|---|
| 95029 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 95030 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 95031 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 |
|---|
| 95032 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 95033 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 95034 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 |
|---|
| 95035 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 95036 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 95037 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 |
|---|
| 95038 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 95039 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 95040 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 |
|---|
| 95041 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 95042 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 95043 | //BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
|---|
| 95044 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 |
|---|
| 95045 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
|---|
| 95046 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L |
|---|
| 95047 | #define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 95048 | //BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 95049 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 95050 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 95051 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 95052 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 95053 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 95054 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 95055 | //BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP |
|---|
| 95056 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 95057 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 95058 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 95059 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 95060 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 95061 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 95062 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 95063 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 95064 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 95065 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 95066 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 95067 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 95068 | //BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL |
|---|
| 95069 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 95070 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 95071 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 95072 | #define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 95073 | //BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST |
|---|
| 95074 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 95075 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 95076 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 95077 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 95078 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 95079 | #define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 95080 | //BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP |
|---|
| 95081 | #define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 95082 | #define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f |
|---|
| 95083 | #define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 95084 | #define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L |
|---|
| 95085 | //BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS |
|---|
| 95086 | #define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 |
|---|
| 95087 | #define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f |
|---|
| 95088 | #define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL |
|---|
| 95089 | #define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L |
|---|
| 95090 | //BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST |
|---|
| 95091 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 95092 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 95093 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 95094 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 95095 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 95096 | #define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 95097 | //BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT |
|---|
| 95098 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0 |
|---|
| 95099 | #define BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 95100 | //BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT |
|---|
| 95101 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 |
|---|
| 95102 | #define BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 95103 | //BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT |
|---|
| 95104 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 |
|---|
| 95105 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 |
|---|
| 95106 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 |
|---|
| 95107 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 |
|---|
| 95108 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 |
|---|
| 95109 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L |
|---|
| 95110 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L |
|---|
| 95111 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L |
|---|
| 95112 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L |
|---|
| 95113 | #define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L |
|---|
| 95114 | //BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT |
|---|
| 95115 | #define BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 95116 | #define BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 95117 | //BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT |
|---|
| 95118 | #define BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 95119 | #define BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 95120 | //BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT |
|---|
| 95121 | #define BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 |
|---|
| 95122 | #define BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 95123 | //BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT |
|---|
| 95124 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95125 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95126 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95127 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95128 | //BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT |
|---|
| 95129 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95130 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95131 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95132 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95133 | //BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT |
|---|
| 95134 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95135 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95136 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95137 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95138 | //BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT |
|---|
| 95139 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95140 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95141 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95142 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95143 | //BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT |
|---|
| 95144 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95145 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95146 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95147 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95148 | //BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT |
|---|
| 95149 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95150 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95151 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95152 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95153 | //BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT |
|---|
| 95154 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95155 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95156 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95157 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95158 | //BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT |
|---|
| 95159 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95160 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95161 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95162 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95163 | //BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT |
|---|
| 95164 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95165 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95166 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95167 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95168 | //BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT |
|---|
| 95169 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95170 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95171 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95172 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95173 | //BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT |
|---|
| 95174 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95175 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95176 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95177 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95178 | //BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT |
|---|
| 95179 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95180 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95181 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95182 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95183 | //BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT |
|---|
| 95184 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95185 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95186 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95187 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95188 | //BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT |
|---|
| 95189 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95190 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95191 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95192 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95193 | //BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT |
|---|
| 95194 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95195 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95196 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95197 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95198 | //BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT |
|---|
| 95199 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 |
|---|
| 95200 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 |
|---|
| 95201 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL |
|---|
| 95202 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L |
|---|
| 95203 | //BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST |
|---|
| 95204 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 95205 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 95206 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 95207 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 95208 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 95209 | #define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 95210 | //BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP |
|---|
| 95211 | #define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 |
|---|
| 95212 | #define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L |
|---|
| 95213 | //BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS |
|---|
| 95214 | #define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 |
|---|
| 95215 | #define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 |
|---|
| 95216 | #define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L |
|---|
| 95217 | #define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L |
|---|
| 95218 | //BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL |
|---|
| 95219 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95220 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95221 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95222 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95223 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95224 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95225 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L |
|---|
| 95226 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95227 | //BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS |
|---|
| 95228 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95229 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95230 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95231 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95232 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95233 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95234 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95235 | #define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95236 | //BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL |
|---|
| 95237 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95238 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95239 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95240 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95241 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95242 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95243 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L |
|---|
| 95244 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95245 | //BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS |
|---|
| 95246 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95247 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95248 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95249 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95250 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95251 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95252 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95253 | #define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95254 | //BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL |
|---|
| 95255 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95256 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95257 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95258 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95259 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95260 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95261 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L |
|---|
| 95262 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95263 | //BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS |
|---|
| 95264 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95265 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95266 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95267 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95268 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95269 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95270 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95271 | #define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95272 | //BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL |
|---|
| 95273 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95274 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95275 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95276 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95277 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95278 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95279 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L |
|---|
| 95280 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95281 | //BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS |
|---|
| 95282 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95283 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95284 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95285 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95286 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95287 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95288 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95289 | #define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95290 | //BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL |
|---|
| 95291 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95292 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95293 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95294 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95295 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95296 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95297 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L |
|---|
| 95298 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95299 | //BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS |
|---|
| 95300 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95301 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95302 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95303 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95304 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95305 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95306 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95307 | #define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95308 | //BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL |
|---|
| 95309 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95310 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95311 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95312 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95313 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95314 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95315 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L |
|---|
| 95316 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95317 | //BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS |
|---|
| 95318 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95319 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95320 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95321 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95322 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95323 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95324 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95325 | #define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95326 | //BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL |
|---|
| 95327 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95328 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95329 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95330 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95331 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95332 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95333 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L |
|---|
| 95334 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95335 | //BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS |
|---|
| 95336 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95337 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95338 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95339 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95340 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95341 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95342 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95343 | #define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95344 | //BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL |
|---|
| 95345 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95346 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95347 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95348 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95349 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95350 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95351 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L |
|---|
| 95352 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95353 | //BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS |
|---|
| 95354 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95355 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95356 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95357 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95358 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95359 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95360 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95361 | #define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95362 | //BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL |
|---|
| 95363 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95364 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95365 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95366 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95367 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95368 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95369 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L |
|---|
| 95370 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95371 | //BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS |
|---|
| 95372 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95373 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95374 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95375 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95376 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95377 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95378 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95379 | #define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95380 | //BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL |
|---|
| 95381 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95382 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95383 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95384 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95385 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95386 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95387 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L |
|---|
| 95388 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95389 | //BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS |
|---|
| 95390 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95391 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95392 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95393 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95394 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95395 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95396 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95397 | #define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95398 | //BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL |
|---|
| 95399 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95400 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95401 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95402 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95403 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95404 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95405 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L |
|---|
| 95406 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95407 | //BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS |
|---|
| 95408 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95409 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95410 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95411 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95412 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95413 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95414 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95415 | #define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95416 | //BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL |
|---|
| 95417 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95418 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95419 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95420 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95421 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95422 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95423 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L |
|---|
| 95424 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95425 | //BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS |
|---|
| 95426 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95427 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95428 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95429 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95430 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95431 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95432 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95433 | #define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95434 | //BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL |
|---|
| 95435 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95436 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95437 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95438 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95439 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95440 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95441 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L |
|---|
| 95442 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95443 | //BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS |
|---|
| 95444 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95445 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95446 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95447 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95448 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95449 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95450 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95451 | #define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95452 | //BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL |
|---|
| 95453 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95454 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95455 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95456 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95457 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95458 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95459 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L |
|---|
| 95460 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95461 | //BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS |
|---|
| 95462 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95463 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95464 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95465 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95466 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95467 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95468 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95469 | #define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95470 | //BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL |
|---|
| 95471 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95472 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95473 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95474 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95475 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95476 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95477 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L |
|---|
| 95478 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95479 | //BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS |
|---|
| 95480 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95481 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95482 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95483 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95484 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95485 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95486 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95487 | #define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95488 | //BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL |
|---|
| 95489 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 |
|---|
| 95490 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 |
|---|
| 95491 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 |
|---|
| 95492 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 |
|---|
| 95493 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L |
|---|
| 95494 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L |
|---|
| 95495 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L |
|---|
| 95496 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L |
|---|
| 95497 | //BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS |
|---|
| 95498 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 |
|---|
| 95499 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 |
|---|
| 95500 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 |
|---|
| 95501 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 |
|---|
| 95502 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L |
|---|
| 95503 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L |
|---|
| 95504 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L |
|---|
| 95505 | #define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L |
|---|
| 95506 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST |
|---|
| 95507 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 95508 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 95509 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 95510 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 95511 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 95512 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 95513 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP |
|---|
| 95514 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 95515 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 95516 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL |
|---|
| 95517 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 95518 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 95519 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 95520 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 95521 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 95522 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 95523 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP |
|---|
| 95524 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 95525 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 95526 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL |
|---|
| 95527 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 95528 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 95529 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 95530 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 95531 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 95532 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 95533 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP |
|---|
| 95534 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 95535 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 95536 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL |
|---|
| 95537 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 95538 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 95539 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 95540 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 95541 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 95542 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 95543 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP |
|---|
| 95544 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 95545 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 95546 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL |
|---|
| 95547 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 95548 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 95549 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 95550 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 95551 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 95552 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 95553 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP |
|---|
| 95554 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 95555 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 95556 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL |
|---|
| 95557 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 95558 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 95559 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 95560 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 95561 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 95562 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 95563 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP |
|---|
| 95564 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 95565 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 95566 | //BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL |
|---|
| 95567 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0 |
|---|
| 95568 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 95569 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8 |
|---|
| 95570 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L |
|---|
| 95571 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 95572 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L |
|---|
| 95573 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
|---|
| 95574 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
|---|
| 95575 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
|---|
| 95576 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
|---|
| 95577 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
|---|
| 95578 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
|---|
| 95579 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 95580 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
|---|
| 95581 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
|---|
| 95582 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
|---|
| 95583 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 95584 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 95585 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
|---|
| 95586 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 95587 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
|---|
| 95588 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
|---|
| 95589 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
|---|
| 95590 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
|---|
| 95591 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
|---|
| 95592 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
|---|
| 95593 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
|---|
| 95594 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
|---|
| 95595 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
|---|
| 95596 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
|---|
| 95597 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
|---|
| 95598 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
|---|
| 95599 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
|---|
| 95600 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
|---|
| 95601 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc |
|---|
| 95602 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd |
|---|
| 95603 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe |
|---|
| 95604 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf |
|---|
| 95605 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
|---|
| 95606 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
|---|
| 95607 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
|---|
| 95608 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
|---|
| 95609 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
|---|
| 95610 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
|---|
| 95611 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
|---|
| 95612 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
|---|
| 95613 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
|---|
| 95614 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
|---|
| 95615 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
|---|
| 95616 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
|---|
| 95617 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
|---|
| 95618 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
|---|
| 95619 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L |
|---|
| 95620 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L |
|---|
| 95621 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L |
|---|
| 95622 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L |
|---|
| 95623 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
|---|
| 95624 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
|---|
| 95625 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
|---|
| 95626 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
|---|
| 95627 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
|---|
| 95628 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
|---|
| 95629 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
|---|
| 95630 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
|---|
| 95631 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
|---|
| 95632 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
|---|
| 95633 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
|---|
| 95634 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
|---|
| 95635 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
|---|
| 95636 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
|---|
| 95637 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
|---|
| 95638 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc |
|---|
| 95639 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd |
|---|
| 95640 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe |
|---|
| 95641 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf |
|---|
| 95642 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
|---|
| 95643 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
|---|
| 95644 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
|---|
| 95645 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
|---|
| 95646 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
|---|
| 95647 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
|---|
| 95648 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
|---|
| 95649 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
|---|
| 95650 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
|---|
| 95651 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
|---|
| 95652 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
|---|
| 95653 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
|---|
| 95654 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
|---|
| 95655 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
|---|
| 95656 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L |
|---|
| 95657 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L |
|---|
| 95658 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L |
|---|
| 95659 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L |
|---|
| 95660 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
|---|
| 95661 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
|---|
| 95662 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
|---|
| 95663 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
|---|
| 95664 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
|---|
| 95665 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
|---|
| 95666 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
|---|
| 95667 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
|---|
| 95668 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
|---|
| 95669 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
|---|
| 95670 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
|---|
| 95671 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 95672 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
|---|
| 95673 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 95674 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
|---|
| 95675 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
|---|
| 95676 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 95677 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 95678 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 95679 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
|---|
| 95680 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
|---|
| 95681 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
|---|
| 95682 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
|---|
| 95683 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
|---|
| 95684 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
|---|
| 95685 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
|---|
| 95686 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
|---|
| 95687 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
|---|
| 95688 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
|---|
| 95689 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
|---|
| 95690 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
|---|
| 95691 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
|---|
| 95692 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
|---|
| 95693 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
|---|
| 95694 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
|---|
| 95695 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
|---|
| 95696 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
|---|
| 95697 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
|---|
| 95698 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
|---|
| 95699 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
|---|
| 95700 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
|---|
| 95701 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
|---|
| 95702 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
|---|
| 95703 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
|---|
| 95704 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
|---|
| 95705 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
|---|
| 95706 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
|---|
| 95707 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
|---|
| 95708 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
|---|
| 95709 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
|---|
| 95710 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
|---|
| 95711 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
|---|
| 95712 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
|---|
| 95713 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
|---|
| 95714 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
|---|
| 95715 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
|---|
| 95716 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
|---|
| 95717 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
|---|
| 95718 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
|---|
| 95719 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
|---|
| 95720 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
|---|
| 95721 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
|---|
| 95722 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
|---|
| 95723 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
|---|
| 95724 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
|---|
| 95725 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
|---|
| 95726 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
|---|
| 95727 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
|---|
| 95728 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
|---|
| 95729 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
|---|
| 95730 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
|---|
| 95731 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
|---|
| 95732 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
|---|
| 95733 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
|---|
| 95734 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
|---|
| 95735 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
|---|
| 95736 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
|---|
| 95737 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
|---|
| 95738 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
|---|
| 95739 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
|---|
| 95740 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
|---|
| 95741 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
|---|
| 95742 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
|---|
| 95743 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
|---|
| 95744 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
|---|
| 95745 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
|---|
| 95746 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 |
|---|
| 95747 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 |
|---|
| 95748 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 |
|---|
| 95749 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 |
|---|
| 95750 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 |
|---|
| 95751 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 |
|---|
| 95752 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 |
|---|
| 95753 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 |
|---|
| 95754 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 |
|---|
| 95755 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 |
|---|
| 95756 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa |
|---|
| 95757 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb |
|---|
| 95758 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc |
|---|
| 95759 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd |
|---|
| 95760 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe |
|---|
| 95761 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf |
|---|
| 95762 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 |
|---|
| 95763 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 |
|---|
| 95764 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 |
|---|
| 95765 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 |
|---|
| 95766 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 |
|---|
| 95767 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 |
|---|
| 95768 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 |
|---|
| 95769 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 |
|---|
| 95770 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 |
|---|
| 95771 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 |
|---|
| 95772 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a |
|---|
| 95773 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b |
|---|
| 95774 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c |
|---|
| 95775 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d |
|---|
| 95776 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e |
|---|
| 95777 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f |
|---|
| 95778 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L |
|---|
| 95779 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L |
|---|
| 95780 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L |
|---|
| 95781 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L |
|---|
| 95782 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L |
|---|
| 95783 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L |
|---|
| 95784 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L |
|---|
| 95785 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L |
|---|
| 95786 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L |
|---|
| 95787 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L |
|---|
| 95788 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L |
|---|
| 95789 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L |
|---|
| 95790 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L |
|---|
| 95791 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L |
|---|
| 95792 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L |
|---|
| 95793 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L |
|---|
| 95794 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L |
|---|
| 95795 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L |
|---|
| 95796 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L |
|---|
| 95797 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L |
|---|
| 95798 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L |
|---|
| 95799 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L |
|---|
| 95800 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L |
|---|
| 95801 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L |
|---|
| 95802 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L |
|---|
| 95803 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L |
|---|
| 95804 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L |
|---|
| 95805 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L |
|---|
| 95806 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L |
|---|
| 95807 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L |
|---|
| 95808 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L |
|---|
| 95809 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L |
|---|
| 95810 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
|---|
| 95811 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
|---|
| 95812 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
|---|
| 95813 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
|---|
| 95814 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
|---|
| 95815 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
|---|
| 95816 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
|---|
| 95817 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
|---|
| 95818 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
|---|
| 95819 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
|---|
| 95820 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
|---|
| 95821 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
|---|
| 95822 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
|---|
| 95823 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
|---|
| 95824 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
|---|
| 95825 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
|---|
| 95826 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET__SHIFT 0x18 |
|---|
| 95827 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
|---|
| 95828 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
|---|
| 95829 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
|---|
| 95830 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVD1SCH_OFFSET_MASK 0xFF000000L |
|---|
| 95831 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION |
|---|
| 95832 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 |
|---|
| 95833 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 |
|---|
| 95834 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L |
|---|
| 95835 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L |
|---|
| 95836 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE |
|---|
| 95837 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 |
|---|
| 95838 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f |
|---|
| 95839 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL |
|---|
| 95840 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L |
|---|
| 95841 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
|---|
| 95842 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
|---|
| 95843 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
|---|
| 95844 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95845 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95846 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
|---|
| 95847 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
|---|
| 95848 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
|---|
| 95849 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95850 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95851 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
|---|
| 95852 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
|---|
| 95853 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
|---|
| 95854 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95855 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95856 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
|---|
| 95857 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
|---|
| 95858 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
|---|
| 95859 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95860 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95861 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
|---|
| 95862 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
|---|
| 95863 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
|---|
| 95864 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95865 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95866 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
|---|
| 95867 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
|---|
| 95868 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
|---|
| 95869 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95870 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95871 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
|---|
| 95872 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
|---|
| 95873 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
|---|
| 95874 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95875 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95876 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
|---|
| 95877 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
|---|
| 95878 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
|---|
| 95879 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95880 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95881 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
|---|
| 95882 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
|---|
| 95883 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
|---|
| 95884 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95885 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95886 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
|---|
| 95887 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
|---|
| 95888 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
|---|
| 95889 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95890 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95891 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
|---|
| 95892 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
|---|
| 95893 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
|---|
| 95894 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95895 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95896 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
|---|
| 95897 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
|---|
| 95898 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
|---|
| 95899 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95900 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95901 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
|---|
| 95902 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
|---|
| 95903 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
|---|
| 95904 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95905 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95906 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
|---|
| 95907 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
|---|
| 95908 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
|---|
| 95909 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95910 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95911 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
|---|
| 95912 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
|---|
| 95913 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
|---|
| 95914 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95915 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95916 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
|---|
| 95917 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
|---|
| 95918 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
|---|
| 95919 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95920 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95921 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB |
|---|
| 95922 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0 |
|---|
| 95923 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10 |
|---|
| 95924 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95925 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95926 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB |
|---|
| 95927 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0 |
|---|
| 95928 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10 |
|---|
| 95929 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95930 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95931 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB |
|---|
| 95932 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0 |
|---|
| 95933 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10 |
|---|
| 95934 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95935 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95936 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB |
|---|
| 95937 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0 |
|---|
| 95938 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10 |
|---|
| 95939 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95940 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95941 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB |
|---|
| 95942 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0 |
|---|
| 95943 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10 |
|---|
| 95944 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95945 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95946 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB |
|---|
| 95947 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0 |
|---|
| 95948 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10 |
|---|
| 95949 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95950 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95951 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB |
|---|
| 95952 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0 |
|---|
| 95953 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10 |
|---|
| 95954 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95955 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95956 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB |
|---|
| 95957 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0 |
|---|
| 95958 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10 |
|---|
| 95959 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95960 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95961 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB |
|---|
| 95962 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0 |
|---|
| 95963 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10 |
|---|
| 95964 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95965 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95966 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB |
|---|
| 95967 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0 |
|---|
| 95968 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10 |
|---|
| 95969 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95970 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95971 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB |
|---|
| 95972 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0 |
|---|
| 95973 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10 |
|---|
| 95974 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95975 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95976 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB |
|---|
| 95977 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0 |
|---|
| 95978 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10 |
|---|
| 95979 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95980 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95981 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB |
|---|
| 95982 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0 |
|---|
| 95983 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10 |
|---|
| 95984 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95985 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95986 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB |
|---|
| 95987 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0 |
|---|
| 95988 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10 |
|---|
| 95989 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95990 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95991 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB |
|---|
| 95992 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0 |
|---|
| 95993 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10 |
|---|
| 95994 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 95995 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 95996 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
|---|
| 95997 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 95998 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 95999 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
|---|
| 96000 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 96001 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 96002 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
|---|
| 96003 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 96004 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 96005 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
|---|
| 96006 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 96007 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 96008 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
|---|
| 96009 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 96010 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 96011 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
|---|
| 96012 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 96013 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 96014 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
|---|
| 96015 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 96016 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 96017 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
|---|
| 96018 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 96019 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 96020 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
|---|
| 96021 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 96022 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 96023 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
|---|
| 96024 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
|---|
| 96025 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 96026 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
|---|
| 96027 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
|---|
| 96028 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 96029 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
|---|
| 96030 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
|---|
| 96031 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 96032 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
|---|
| 96033 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
|---|
| 96034 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 96035 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
|---|
| 96036 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
|---|
| 96037 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 96038 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
|---|
| 96039 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
|---|
| 96040 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 96041 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
|---|
| 96042 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
|---|
| 96043 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 96044 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
|---|
| 96045 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
|---|
| 96046 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 96047 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
|---|
| 96048 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
|---|
| 96049 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 96050 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
|---|
| 96051 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 96052 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 96053 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
|---|
| 96054 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 96055 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 96056 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
|---|
| 96057 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 96058 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 96059 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
|---|
| 96060 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 96061 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 96062 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
|---|
| 96063 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 96064 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 96065 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
|---|
| 96066 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 96067 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 96068 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
|---|
| 96069 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 96070 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 96071 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
|---|
| 96072 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 96073 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 96074 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
|---|
| 96075 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 96076 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 96077 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 |
|---|
| 96078 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0 |
|---|
| 96079 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 96080 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 |
|---|
| 96081 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0 |
|---|
| 96082 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 96083 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 |
|---|
| 96084 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0 |
|---|
| 96085 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 96086 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 |
|---|
| 96087 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0 |
|---|
| 96088 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 96089 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 |
|---|
| 96090 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0 |
|---|
| 96091 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 96092 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 |
|---|
| 96093 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0 |
|---|
| 96094 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 96095 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 |
|---|
| 96096 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0 |
|---|
| 96097 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 96098 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 |
|---|
| 96099 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0 |
|---|
| 96100 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 96101 | //BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 |
|---|
| 96102 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0 |
|---|
| 96103 | #define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 96104 | |
|---|
| 96105 | |
|---|
| 96106 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
|---|
| 96107 | //BIF_CFG_DEV0_EPF2_1_VENDOR_ID |
|---|
| 96108 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 96109 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 96110 | //BIF_CFG_DEV0_EPF2_1_DEVICE_ID |
|---|
| 96111 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 96112 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 96113 | //BIF_CFG_DEV0_EPF2_1_COMMAND |
|---|
| 96114 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 96115 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 96116 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 96117 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 96118 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 96119 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 96120 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 96121 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 96122 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 96123 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 96124 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 96125 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 96126 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 96127 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 96128 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 96129 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 96130 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 96131 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 96132 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 96133 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 96134 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 96135 | #define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 96136 | //BIF_CFG_DEV0_EPF2_1_STATUS |
|---|
| 96137 | #define BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 96138 | #define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 96139 | #define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 96140 | #define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 96141 | #define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 96142 | #define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 96143 | #define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 96144 | #define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 96145 | #define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 96146 | #define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 96147 | #define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 96148 | #define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 96149 | #define BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 96150 | #define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 96151 | #define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 96152 | #define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 96153 | #define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 96154 | #define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 96155 | #define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 96156 | #define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 96157 | #define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 96158 | #define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 96159 | #define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 96160 | #define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 96161 | //BIF_CFG_DEV0_EPF2_1_REVISION_ID |
|---|
| 96162 | #define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 96163 | #define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 96164 | #define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 96165 | #define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 96166 | //BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE |
|---|
| 96167 | #define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 96168 | #define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 96169 | //BIF_CFG_DEV0_EPF2_1_SUB_CLASS |
|---|
| 96170 | #define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 96171 | #define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 96172 | //BIF_CFG_DEV0_EPF2_1_BASE_CLASS |
|---|
| 96173 | #define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 96174 | #define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 96175 | //BIF_CFG_DEV0_EPF2_1_CACHE_LINE |
|---|
| 96176 | #define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 96177 | #define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 96178 | //BIF_CFG_DEV0_EPF2_1_LATENCY |
|---|
| 96179 | #define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 96180 | #define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 96181 | //BIF_CFG_DEV0_EPF2_1_HEADER |
|---|
| 96182 | #define 0x0 |
|---|
| 96183 | #define 0x7 |
|---|
| 96184 | #define 0x7FL |
|---|
| 96185 | #define 0x80L |
|---|
| 96186 | //BIF_CFG_DEV0_EPF2_1_BIST |
|---|
| 96187 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 96188 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 96189 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 96190 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 96191 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 96192 | #define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 96193 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 |
|---|
| 96194 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 96195 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 96196 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 |
|---|
| 96197 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 96198 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 96199 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 |
|---|
| 96200 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 96201 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 96202 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 |
|---|
| 96203 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 96204 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 96205 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 |
|---|
| 96206 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 96207 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 96208 | //BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 |
|---|
| 96209 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 96210 | #define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 96211 | //BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR |
|---|
| 96212 | #define BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 96213 | #define BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 96214 | //BIF_CFG_DEV0_EPF2_1_ADAPTER_ID |
|---|
| 96215 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 96216 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 96217 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 96218 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 96219 | //BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR |
|---|
| 96220 | #define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 96221 | #define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 96222 | //BIF_CFG_DEV0_EPF2_1_CAP_PTR |
|---|
| 96223 | #define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 96224 | #define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 96225 | //BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE |
|---|
| 96226 | #define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 96227 | #define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 96228 | //BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN |
|---|
| 96229 | #define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 96230 | #define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 96231 | //BIF_CFG_DEV0_EPF2_1_MIN_GRANT |
|---|
| 96232 | #define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 96233 | #define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 96234 | //BIF_CFG_DEV0_EPF2_1_MAX_LATENCY |
|---|
| 96235 | #define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 96236 | #define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 96237 | //BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST |
|---|
| 96238 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 96239 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 96240 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 96241 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 96242 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 96243 | #define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 96244 | //BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W |
|---|
| 96245 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 96246 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 96247 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 96248 | #define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 96249 | //BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST |
|---|
| 96250 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 96251 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 96252 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 96253 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 96254 | //BIF_CFG_DEV0_EPF2_1_PMI_CAP |
|---|
| 96255 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 96256 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 96257 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 96258 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 96259 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 96260 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 96261 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 96262 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 96263 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 96264 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 96265 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 96266 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 96267 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 96268 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 96269 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 96270 | #define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 96271 | //BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL |
|---|
| 96272 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 96273 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 96274 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 96275 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 96276 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 96277 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 96278 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 96279 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 96280 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 96281 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 96282 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 96283 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 96284 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 96285 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 96286 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 96287 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 96288 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 96289 | #define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 96290 | //BIF_CFG_DEV0_EPF2_1_SBRN |
|---|
| 96291 | #define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT 0x0 |
|---|
| 96292 | #define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK 0xFFL |
|---|
| 96293 | //BIF_CFG_DEV0_EPF2_1_FLADJ |
|---|
| 96294 | #define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT 0x0 |
|---|
| 96295 | #define BIF_CFG_DEV0_EPF2_1_FLADJ__NFC__SHIFT 0x6 |
|---|
| 96296 | #define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK 0x3FL |
|---|
| 96297 | #define BIF_CFG_DEV0_EPF2_1_FLADJ__NFC_MASK 0x40L |
|---|
| 96298 | //BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD |
|---|
| 96299 | #define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
|---|
| 96300 | #define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
|---|
| 96301 | #define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL |
|---|
| 96302 | #define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
|---|
| 96303 | //BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST |
|---|
| 96304 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 96305 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 96306 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 96307 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 96308 | //BIF_CFG_DEV0_EPF2_1_PCIE_CAP |
|---|
| 96309 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 96310 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 96311 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 96312 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 96313 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 96314 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 96315 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 96316 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 96317 | //BIF_CFG_DEV0_EPF2_1_DEVICE_CAP |
|---|
| 96318 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 96319 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 96320 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 96321 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 96322 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 96323 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 96324 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 96325 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 96326 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 96327 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 96328 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 96329 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 96330 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 96331 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 96332 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 96333 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 96334 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 96335 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 96336 | //BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL |
|---|
| 96337 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 96338 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 96339 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 96340 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 96341 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 96342 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 96343 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 96344 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 96345 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 96346 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 96347 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 96348 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 96349 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 96350 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 96351 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 96352 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 96353 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 96354 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 96355 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 96356 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 96357 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 96358 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 96359 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 96360 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 96361 | //BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS |
|---|
| 96362 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 96363 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 96364 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 96365 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 96366 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 96367 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 96368 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 96369 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 96370 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 96371 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 96372 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 96373 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 96374 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 96375 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 96376 | //BIF_CFG_DEV0_EPF2_1_LINK_CAP |
|---|
| 96377 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 96378 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 96379 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 96380 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 96381 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 96382 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 96383 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 96384 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 96385 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 96386 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 96387 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 96388 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 96389 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 96390 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 96391 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 96392 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 96393 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 96394 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 96395 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 96396 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 96397 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 96398 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 96399 | //BIF_CFG_DEV0_EPF2_1_LINK_CNTL |
|---|
| 96400 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 96401 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 96402 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 96403 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 96404 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 96405 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 96406 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 96407 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 96408 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 96409 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 96410 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 96411 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 96412 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 96413 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 96414 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 96415 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 96416 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 96417 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 96418 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 96419 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 96420 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 96421 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 96422 | //BIF_CFG_DEV0_EPF2_1_LINK_STATUS |
|---|
| 96423 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 96424 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 96425 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 96426 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 96427 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 96428 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 96429 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 96430 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 96431 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 96432 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 96433 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 96434 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 96435 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 96436 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 96437 | //BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 |
|---|
| 96438 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 96439 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 96440 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 96441 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 96442 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 96443 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 96444 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 96445 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 96446 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 96447 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 96448 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 96449 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 96450 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 96451 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 96452 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 96453 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 96454 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 96455 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 96456 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 96457 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 96458 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 96459 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 96460 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 96461 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 96462 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 96463 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 96464 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 96465 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 96466 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 96467 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 96468 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 96469 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 96470 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 96471 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 96472 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 96473 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 96474 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 96475 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 96476 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 96477 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 96478 | //BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 |
|---|
| 96479 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 96480 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 96481 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 96482 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 96483 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 96484 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 96485 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 96486 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 96487 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 96488 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 96489 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 96490 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 96491 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 96492 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 96493 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 96494 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 96495 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 96496 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 96497 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 96498 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 96499 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 96500 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 96501 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 96502 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 96503 | //BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 |
|---|
| 96504 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 96505 | #define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 96506 | //BIF_CFG_DEV0_EPF2_1_LINK_CAP2 |
|---|
| 96507 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 96508 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 96509 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 96510 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 96511 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 96512 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 96513 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 96514 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 96515 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 96516 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 96517 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 96518 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 96519 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 96520 | #define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 96521 | //BIF_CFG_DEV0_EPF2_1_LINK_CNTL2 |
|---|
| 96522 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 96523 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 96524 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 96525 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 96526 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 96527 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 96528 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 96529 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 96530 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 96531 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 96532 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 96533 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 96534 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 96535 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 96536 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 96537 | #define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 96538 | //BIF_CFG_DEV0_EPF2_1_LINK_STATUS2 |
|---|
| 96539 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 96540 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 96541 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 96542 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 96543 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 96544 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 96545 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 96546 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 96547 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 96548 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 96549 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 96550 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 96551 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 96552 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 96553 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 96554 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 96555 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 96556 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 96557 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 96558 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 96559 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 96560 | #define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 96561 | //BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST |
|---|
| 96562 | #define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 96563 | #define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 96564 | #define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 96565 | #define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 96566 | //BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL |
|---|
| 96567 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 96568 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 96569 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 96570 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 96571 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 96572 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 96573 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 96574 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 96575 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 96576 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 96577 | //BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO |
|---|
| 96578 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 96579 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 96580 | //BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI |
|---|
| 96581 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 96582 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 96583 | //BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA |
|---|
| 96584 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 96585 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 96586 | //BIF_CFG_DEV0_EPF2_1_MSI_MASK |
|---|
| 96587 | #define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 96588 | #define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 96589 | //BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 |
|---|
| 96590 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 96591 | #define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 96592 | //BIF_CFG_DEV0_EPF2_1_MSI_MASK_64 |
|---|
| 96593 | #define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 96594 | #define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 96595 | //BIF_CFG_DEV0_EPF2_1_MSI_PENDING |
|---|
| 96596 | #define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 96597 | #define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 96598 | //BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 |
|---|
| 96599 | #define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 96600 | #define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 96601 | //BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST |
|---|
| 96602 | #define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 96603 | #define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 96604 | #define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 96605 | #define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 96606 | //BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL |
|---|
| 96607 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 96608 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 96609 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 96610 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 96611 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 96612 | #define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 96613 | //BIF_CFG_DEV0_EPF2_1_MSIX_TABLE |
|---|
| 96614 | #define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 96615 | #define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 96616 | #define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 96617 | #define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 96618 | //BIF_CFG_DEV0_EPF2_1_MSIX_PBA |
|---|
| 96619 | #define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 96620 | #define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 96621 | #define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 96622 | #define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 96623 | //BIF_CFG_DEV0_EPF2_1_SATA_CAP_0 |
|---|
| 96624 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
|---|
| 96625 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
|---|
| 96626 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
|---|
| 96627 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
|---|
| 96628 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
|---|
| 96629 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
|---|
| 96630 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 96631 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
|---|
| 96632 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
|---|
| 96633 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
|---|
| 96634 | //BIF_CFG_DEV0_EPF2_1_SATA_CAP_1 |
|---|
| 96635 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
|---|
| 96636 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
|---|
| 96637 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
|---|
| 96638 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
|---|
| 96639 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
|---|
| 96640 | #define BIF_CFG_DEV0_EPF2_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
|---|
| 96641 | //BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX |
|---|
| 96642 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
|---|
| 96643 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
|---|
| 96644 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
|---|
| 96645 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
|---|
| 96646 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
|---|
| 96647 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
|---|
| 96648 | //BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA |
|---|
| 96649 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
|---|
| 96650 | #define BIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
|---|
| 96651 | //BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 96652 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 96653 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 96654 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 96655 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 96656 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 96657 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 96658 | //BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 96659 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 96660 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 96661 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 96662 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 96663 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 96664 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 96665 | //BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 96666 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 96667 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 96668 | //BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 96669 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 96670 | #define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 96671 | //BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 96672 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 96673 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 96674 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 96675 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 96676 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 96677 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 96678 | //BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 96679 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 96680 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 96681 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 96682 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 96683 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 96684 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 96685 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 96686 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 96687 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 96688 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 96689 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 96690 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 96691 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 96692 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 96693 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 96694 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 96695 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 96696 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 96697 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 96698 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 96699 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 96700 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 96701 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 96702 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 96703 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 96704 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 96705 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 96706 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 96707 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 96708 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 96709 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 96710 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 96711 | //BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK |
|---|
| 96712 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 96713 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 96714 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 96715 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 96716 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 96717 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 96718 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 96719 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 96720 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 96721 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 96722 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 96723 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 96724 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 96725 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 96726 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 96727 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 96728 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 96729 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 96730 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 96731 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 96732 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 96733 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 96734 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 96735 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 96736 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 96737 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 96738 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 96739 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 96740 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 96741 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 96742 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 96743 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 96744 | //BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 96745 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 96746 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 96747 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 96748 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 96749 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 96750 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 96751 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 96752 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 96753 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 96754 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 96755 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 96756 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 96757 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 96758 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 96759 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 96760 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 96761 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 96762 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 96763 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 96764 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 96765 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 96766 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 96767 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 96768 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 96769 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 96770 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 96771 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 96772 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 96773 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 96774 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 96775 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 96776 | #define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 96777 | //BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS |
|---|
| 96778 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 96779 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 96780 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 96781 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 96782 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 96783 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 96784 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 96785 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 96786 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 96787 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 96788 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 96789 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 96790 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 96791 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 96792 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 96793 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 96794 | //BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK |
|---|
| 96795 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 96796 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 96797 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 96798 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 96799 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 96800 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 96801 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 96802 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 96803 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 96804 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 96805 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 96806 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 96807 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 96808 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 96809 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 96810 | #define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 96811 | //BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 96812 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 96813 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 96814 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 96815 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 96816 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 96817 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 96818 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 96819 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 96820 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 96821 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 96822 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 96823 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 96824 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 96825 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 96826 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 96827 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 96828 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 96829 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 96830 | //BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 |
|---|
| 96831 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 96832 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 96833 | //BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 |
|---|
| 96834 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 96835 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 96836 | //BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 |
|---|
| 96837 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 96838 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 96839 | //BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 |
|---|
| 96840 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 96841 | #define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 96842 | //BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 96843 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 96844 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 96845 | //BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 96846 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 96847 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 96848 | //BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 96849 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 96850 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 96851 | //BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 96852 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 96853 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 96854 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST |
|---|
| 96855 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 96856 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 96857 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 96858 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 96859 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 96860 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 96861 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP |
|---|
| 96862 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 96863 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 96864 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL |
|---|
| 96865 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 96866 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 96867 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 96868 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 96869 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 96870 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 96871 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP |
|---|
| 96872 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 96873 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 96874 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL |
|---|
| 96875 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 96876 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 96877 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 96878 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 96879 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 96880 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 96881 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP |
|---|
| 96882 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 96883 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 96884 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL |
|---|
| 96885 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 96886 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 96887 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 96888 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 96889 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 96890 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 96891 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP |
|---|
| 96892 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 96893 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 96894 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL |
|---|
| 96895 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 96896 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 96897 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 96898 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 96899 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 96900 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 96901 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP |
|---|
| 96902 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 96903 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 96904 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL |
|---|
| 96905 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 96906 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 96907 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 96908 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 96909 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 96910 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 96911 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP |
|---|
| 96912 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 96913 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 96914 | //BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL |
|---|
| 96915 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 96916 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 96917 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 96918 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 96919 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 96920 | #define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 96921 | //BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 96922 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 96923 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 96924 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 96925 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 96926 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 96927 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 96928 | //BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 96929 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 96930 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 96931 | //BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA |
|---|
| 96932 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 96933 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 96934 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 96935 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 96936 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 96937 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 96938 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 96939 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 96940 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 96941 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 96942 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 96943 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 96944 | //BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP |
|---|
| 96945 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 96946 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 96947 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST |
|---|
| 96948 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 96949 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 96950 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 96951 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 96952 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 96953 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 96954 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP |
|---|
| 96955 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 96956 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 96957 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 96958 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 96959 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 96960 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 96961 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 96962 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 96963 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 96964 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 96965 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 96966 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 96967 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 96968 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS |
|---|
| 96969 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 96970 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 96971 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 96972 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 96973 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL |
|---|
| 96974 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 96975 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 96976 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 96977 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 96978 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 96979 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 96980 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 96981 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 96982 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 96983 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 96984 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 96985 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 96986 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 96987 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 96988 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 96989 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 96990 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 96991 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 96992 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 96993 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 96994 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 96995 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 96996 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 96997 | //BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 96998 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 96999 | #define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 97000 | //BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST |
|---|
| 97001 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 97002 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 97003 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 97004 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 97005 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 97006 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 97007 | //BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP |
|---|
| 97008 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 97009 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 97010 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 97011 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 97012 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 97013 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 97014 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 97015 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 97016 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 97017 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 97018 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 97019 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 97020 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 97021 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 97022 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 97023 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 97024 | //BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL |
|---|
| 97025 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 97026 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 97027 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 97028 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 97029 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 97030 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 97031 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 97032 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 97033 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 97034 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 97035 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 97036 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 97037 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 97038 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 97039 | //BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST |
|---|
| 97040 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 97041 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 97042 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 97043 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 97044 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 97045 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 97046 | //BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP |
|---|
| 97047 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 97048 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 97049 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 97050 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 97051 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 97052 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 97053 | //BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL |
|---|
| 97054 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 97055 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 97056 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 97057 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 97058 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 97059 | #define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 97060 | //BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 97061 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 97062 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 97063 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 97064 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 97065 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 97066 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 97067 | //BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP |
|---|
| 97068 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 97069 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 97070 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 97071 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 97072 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 97073 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 97074 | //BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL |
|---|
| 97075 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 97076 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 97077 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 97078 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 97079 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 97080 | #define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 97081 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 97082 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 97083 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 97084 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 97085 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 97086 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 97087 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 97088 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP |
|---|
| 97089 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 97090 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 97091 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 97092 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 97093 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 97094 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 97095 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 97096 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 97097 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 97098 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 97099 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 97100 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 97101 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL |
|---|
| 97102 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 97103 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 97104 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 97105 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 97106 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0 |
|---|
| 97107 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97108 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97109 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97110 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97111 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1 |
|---|
| 97112 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97113 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97114 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97115 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97116 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2 |
|---|
| 97117 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97118 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97119 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97120 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97121 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3 |
|---|
| 97122 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97123 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97124 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97125 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97126 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4 |
|---|
| 97127 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97128 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97129 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97130 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97131 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5 |
|---|
| 97132 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97133 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97134 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97135 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97136 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6 |
|---|
| 97137 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97138 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97139 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97140 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97141 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7 |
|---|
| 97142 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97143 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97144 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97145 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97146 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8 |
|---|
| 97147 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97148 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97149 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97150 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97151 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9 |
|---|
| 97152 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97153 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97154 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97155 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97156 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10 |
|---|
| 97157 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97158 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97159 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97160 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97161 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11 |
|---|
| 97162 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97163 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97164 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97165 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97166 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12 |
|---|
| 97167 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97168 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97169 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97170 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97171 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13 |
|---|
| 97172 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97173 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97174 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97175 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97176 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14 |
|---|
| 97177 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97178 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97179 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97180 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97181 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15 |
|---|
| 97182 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97183 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97184 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97185 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97186 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16 |
|---|
| 97187 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97188 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97189 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97190 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97191 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17 |
|---|
| 97192 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97193 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97194 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97195 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97196 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18 |
|---|
| 97197 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97198 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97199 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97200 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97201 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19 |
|---|
| 97202 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97203 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97204 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97205 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97206 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20 |
|---|
| 97207 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97208 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97209 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97210 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97211 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21 |
|---|
| 97212 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97213 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97214 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97215 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97216 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22 |
|---|
| 97217 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97218 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97219 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97220 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97221 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23 |
|---|
| 97222 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97223 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97224 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97225 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97226 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24 |
|---|
| 97227 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97228 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97229 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97230 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97231 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25 |
|---|
| 97232 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97233 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97234 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97235 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97236 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26 |
|---|
| 97237 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97238 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97239 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97240 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97241 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27 |
|---|
| 97242 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97243 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97244 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97245 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97246 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28 |
|---|
| 97247 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97248 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97249 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97250 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97251 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29 |
|---|
| 97252 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97253 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97254 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97255 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97256 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30 |
|---|
| 97257 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97258 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97259 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97260 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97261 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31 |
|---|
| 97262 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97263 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97264 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97265 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97266 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32 |
|---|
| 97267 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97268 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
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| 97269 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
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| 97270 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
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| 97271 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33 |
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| 97272 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97273 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
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| 97274 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97275 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
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| 97276 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34 |
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| 97277 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97278 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
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| 97279 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
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| 97280 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
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| 97281 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35 |
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| 97282 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97283 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
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| 97284 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
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| 97285 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
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| 97286 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36 |
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| 97287 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97288 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97289 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
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| 97290 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
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| 97291 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37 |
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| 97292 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97293 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
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| 97294 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
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| 97295 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
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| 97296 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38 |
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| 97297 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97298 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97299 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97300 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
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| 97301 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39 |
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| 97302 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97303 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97304 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
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| 97305 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
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| 97306 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40 |
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| 97307 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97308 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97309 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97310 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97311 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41 |
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| 97312 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97313 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97314 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97315 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97316 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42 |
|---|
| 97317 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97318 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97319 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97320 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97321 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43 |
|---|
| 97322 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97323 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97324 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97325 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97326 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44 |
|---|
| 97327 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97328 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97329 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97330 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97331 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45 |
|---|
| 97332 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97333 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97334 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97335 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97336 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46 |
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| 97337 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97338 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97339 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97340 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97341 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47 |
|---|
| 97342 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97343 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97344 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97345 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97346 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48 |
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| 97347 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97348 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97349 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97350 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97351 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49 |
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| 97352 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97353 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97354 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97355 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97356 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50 |
|---|
| 97357 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97358 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97359 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97360 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97361 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51 |
|---|
| 97362 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97363 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97364 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97365 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97366 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52 |
|---|
| 97367 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
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| 97368 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97369 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97370 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97371 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53 |
|---|
| 97372 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97373 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97374 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97375 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97376 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54 |
|---|
| 97377 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97378 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97379 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97380 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97381 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55 |
|---|
| 97382 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97383 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97384 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97385 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97386 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56 |
|---|
| 97387 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97388 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97389 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97390 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97391 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57 |
|---|
| 97392 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97393 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97394 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97395 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97396 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58 |
|---|
| 97397 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97398 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97399 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97400 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97401 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59 |
|---|
| 97402 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97403 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97404 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97405 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97406 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60 |
|---|
| 97407 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97408 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97409 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97410 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97411 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61 |
|---|
| 97412 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97413 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97414 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97415 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97416 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62 |
|---|
| 97417 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97418 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97419 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97420 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97421 | //BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63 |
|---|
| 97422 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 97423 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 97424 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 97425 | #define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 97426 | |
|---|
| 97427 | |
|---|
| 97428 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
|---|
| 97429 | //BIF_CFG_DEV0_EPF3_1_VENDOR_ID |
|---|
| 97430 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 97431 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 97432 | //BIF_CFG_DEV0_EPF3_1_DEVICE_ID |
|---|
| 97433 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 97434 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 97435 | //BIF_CFG_DEV0_EPF3_1_COMMAND |
|---|
| 97436 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 97437 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 97438 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 97439 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 97440 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 97441 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 97442 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 97443 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 97444 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 97445 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 97446 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 97447 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 97448 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 97449 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 97450 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 97451 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 97452 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 97453 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 97454 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 97455 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 97456 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 97457 | #define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 97458 | //BIF_CFG_DEV0_EPF3_1_STATUS |
|---|
| 97459 | #define BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 97460 | #define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 97461 | #define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 97462 | #define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 97463 | #define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 97464 | #define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 97465 | #define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 97466 | #define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 97467 | #define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 97468 | #define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 97469 | #define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 97470 | #define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 97471 | #define BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 97472 | #define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 97473 | #define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 97474 | #define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 97475 | #define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 97476 | #define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 97477 | #define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 97478 | #define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 97479 | #define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 97480 | #define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 97481 | #define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 97482 | #define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 97483 | //BIF_CFG_DEV0_EPF3_1_REVISION_ID |
|---|
| 97484 | #define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 97485 | #define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 97486 | #define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 97487 | #define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 97488 | //BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE |
|---|
| 97489 | #define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 97490 | #define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 97491 | //BIF_CFG_DEV0_EPF3_1_SUB_CLASS |
|---|
| 97492 | #define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 97493 | #define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 97494 | //BIF_CFG_DEV0_EPF3_1_BASE_CLASS |
|---|
| 97495 | #define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 97496 | #define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 97497 | //BIF_CFG_DEV0_EPF3_1_CACHE_LINE |
|---|
| 97498 | #define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 97499 | #define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 97500 | //BIF_CFG_DEV0_EPF3_1_LATENCY |
|---|
| 97501 | #define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 97502 | #define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 97503 | //BIF_CFG_DEV0_EPF3_1_HEADER |
|---|
| 97504 | #define 0x0 |
|---|
| 97505 | #define 0x7 |
|---|
| 97506 | #define 0x7FL |
|---|
| 97507 | #define 0x80L |
|---|
| 97508 | //BIF_CFG_DEV0_EPF3_1_BIST |
|---|
| 97509 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 97510 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 97511 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 97512 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 97513 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 97514 | #define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 97515 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 |
|---|
| 97516 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 97517 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 97518 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 |
|---|
| 97519 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 97520 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 97521 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 |
|---|
| 97522 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 97523 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 97524 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 |
|---|
| 97525 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 97526 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 97527 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 |
|---|
| 97528 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 97529 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 97530 | //BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 |
|---|
| 97531 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 97532 | #define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 97533 | //BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR |
|---|
| 97534 | #define BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 97535 | #define BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 97536 | //BIF_CFG_DEV0_EPF3_1_ADAPTER_ID |
|---|
| 97537 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 97538 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 97539 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 97540 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 97541 | //BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR |
|---|
| 97542 | #define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 97543 | #define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 97544 | //BIF_CFG_DEV0_EPF3_1_CAP_PTR |
|---|
| 97545 | #define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 97546 | #define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 97547 | //BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE |
|---|
| 97548 | #define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 97549 | #define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 97550 | //BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN |
|---|
| 97551 | #define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 97552 | #define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 97553 | //BIF_CFG_DEV0_EPF3_1_MIN_GRANT |
|---|
| 97554 | #define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 97555 | #define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 97556 | //BIF_CFG_DEV0_EPF3_1_MAX_LATENCY |
|---|
| 97557 | #define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 97558 | #define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 97559 | //BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST |
|---|
| 97560 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 97561 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 97562 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 97563 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 97564 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 97565 | #define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 97566 | //BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W |
|---|
| 97567 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 97568 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 97569 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 97570 | #define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 97571 | //BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST |
|---|
| 97572 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 97573 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 97574 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 97575 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 97576 | //BIF_CFG_DEV0_EPF3_1_PMI_CAP |
|---|
| 97577 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 97578 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 97579 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 |
|---|
| 97580 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 97581 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 97582 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 97583 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 97584 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 97585 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 97586 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 97587 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L |
|---|
| 97588 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 97589 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 97590 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 97591 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 97592 | #define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 97593 | //BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL |
|---|
| 97594 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 97595 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 97596 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 97597 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 97598 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 97599 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 97600 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 97601 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 97602 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 97603 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 97604 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 97605 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 97606 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 97607 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 97608 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 97609 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 97610 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 97611 | #define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 97612 | //BIF_CFG_DEV0_EPF3_1_SBRN |
|---|
| 97613 | #define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT 0x0 |
|---|
| 97614 | #define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK 0xFFL |
|---|
| 97615 | //BIF_CFG_DEV0_EPF3_1_FLADJ |
|---|
| 97616 | #define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT 0x0 |
|---|
| 97617 | #define BIF_CFG_DEV0_EPF3_1_FLADJ__NFC__SHIFT 0x6 |
|---|
| 97618 | #define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK 0x3FL |
|---|
| 97619 | #define BIF_CFG_DEV0_EPF3_1_FLADJ__NFC_MASK 0x40L |
|---|
| 97620 | //BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD |
|---|
| 97621 | #define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT 0x0 |
|---|
| 97622 | #define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT 0x4 |
|---|
| 97623 | #define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK 0x0FL |
|---|
| 97624 | #define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK 0xF0L |
|---|
| 97625 | //BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST |
|---|
| 97626 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 97627 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 97628 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 97629 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 97630 | //BIF_CFG_DEV0_EPF3_1_PCIE_CAP |
|---|
| 97631 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 97632 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 97633 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 97634 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 97635 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 97636 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 97637 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 97638 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 97639 | //BIF_CFG_DEV0_EPF3_1_DEVICE_CAP |
|---|
| 97640 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 97641 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 97642 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 97643 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 97644 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 97645 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 97646 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 97647 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 97648 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 97649 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 97650 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 97651 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 97652 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 97653 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 97654 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 97655 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 97656 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 97657 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 97658 | //BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL |
|---|
| 97659 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 97660 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 97661 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 97662 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 97663 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 97664 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 97665 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 97666 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 97667 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 97668 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 97669 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 97670 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 97671 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 97672 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 97673 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 97674 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 97675 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 97676 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 97677 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 97678 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 97679 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 97680 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 97681 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 97682 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 97683 | //BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS |
|---|
| 97684 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 97685 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 97686 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 97687 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 97688 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 97689 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 97690 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 97691 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 97692 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 97693 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 97694 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 97695 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 97696 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 97697 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 97698 | //BIF_CFG_DEV0_EPF3_1_LINK_CAP |
|---|
| 97699 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 97700 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 97701 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 97702 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 97703 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 97704 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 97705 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 97706 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 97707 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 97708 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 97709 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 97710 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 97711 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 97712 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 97713 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 97714 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 97715 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 97716 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 97717 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 97718 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 97719 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 97720 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 97721 | //BIF_CFG_DEV0_EPF3_1_LINK_CNTL |
|---|
| 97722 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 97723 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 97724 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 97725 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 97726 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 97727 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 97728 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 97729 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 97730 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 97731 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 97732 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 97733 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 97734 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 97735 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 97736 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 97737 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 97738 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 97739 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 97740 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 97741 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 97742 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 97743 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 97744 | //BIF_CFG_DEV0_EPF3_1_LINK_STATUS |
|---|
| 97745 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 97746 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 97747 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 97748 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 97749 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 97750 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 97751 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 97752 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 97753 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 97754 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 97755 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 97756 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 97757 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 97758 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 97759 | //BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 |
|---|
| 97760 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 97761 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 97762 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 97763 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 97764 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 97765 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 97766 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 97767 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 97768 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 97769 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 97770 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 97771 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 97772 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 97773 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 97774 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 97775 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 97776 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 97777 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 97778 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 97779 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 97780 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 97781 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 97782 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 97783 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 97784 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 97785 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 97786 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 97787 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 97788 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 97789 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 97790 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 97791 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 97792 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 97793 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 97794 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 97795 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 97796 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 97797 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 97798 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 97799 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 97800 | //BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 |
|---|
| 97801 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 97802 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 97803 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 97804 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 97805 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 97806 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 97807 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 97808 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 97809 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 97810 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 97811 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 97812 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 97813 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 97814 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 97815 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 97816 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 97817 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 97818 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 97819 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 97820 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 97821 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 97822 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 97823 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 97824 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 97825 | //BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 |
|---|
| 97826 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 97827 | #define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 97828 | //BIF_CFG_DEV0_EPF3_1_LINK_CAP2 |
|---|
| 97829 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 97830 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 97831 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 97832 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 97833 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 97834 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 97835 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 97836 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 97837 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 97838 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 97839 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 97840 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 97841 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 97842 | #define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 97843 | //BIF_CFG_DEV0_EPF3_1_LINK_CNTL2 |
|---|
| 97844 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 97845 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 97846 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 97847 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 97848 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 97849 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 97850 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 97851 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 97852 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 97853 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 97854 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 97855 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 97856 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 97857 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 97858 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 97859 | #define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 97860 | //BIF_CFG_DEV0_EPF3_1_LINK_STATUS2 |
|---|
| 97861 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 97862 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 97863 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 97864 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 97865 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 97866 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 97867 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 97868 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 97869 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 97870 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 97871 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 97872 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 97873 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 97874 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 97875 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 97876 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 97877 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 97878 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 97879 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 97880 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 97881 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 97882 | #define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 97883 | //BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST |
|---|
| 97884 | #define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 97885 | #define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 97886 | #define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 97887 | #define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 97888 | //BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL |
|---|
| 97889 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 97890 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 97891 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 97892 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 97893 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 97894 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 97895 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 97896 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 97897 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 97898 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 97899 | //BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO |
|---|
| 97900 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 97901 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 97902 | //BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI |
|---|
| 97903 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 97904 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 97905 | //BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA |
|---|
| 97906 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 97907 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 97908 | //BIF_CFG_DEV0_EPF3_1_MSI_MASK |
|---|
| 97909 | #define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 97910 | #define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 97911 | //BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 |
|---|
| 97912 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 97913 | #define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 97914 | //BIF_CFG_DEV0_EPF3_1_MSI_MASK_64 |
|---|
| 97915 | #define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 97916 | #define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 97917 | //BIF_CFG_DEV0_EPF3_1_MSI_PENDING |
|---|
| 97918 | #define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 97919 | #define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 97920 | //BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 |
|---|
| 97921 | #define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 97922 | #define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 97923 | //BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST |
|---|
| 97924 | #define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 97925 | #define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 97926 | #define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 97927 | #define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 97928 | //BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL |
|---|
| 97929 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 97930 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 97931 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 97932 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 97933 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 97934 | #define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 97935 | //BIF_CFG_DEV0_EPF3_1_MSIX_TABLE |
|---|
| 97936 | #define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 97937 | #define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 97938 | #define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 97939 | #define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 97940 | //BIF_CFG_DEV0_EPF3_1_MSIX_PBA |
|---|
| 97941 | #define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 97942 | #define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 97943 | #define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 97944 | #define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 97945 | //BIF_CFG_DEV0_EPF3_1_SATA_CAP_0 |
|---|
| 97946 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID__SHIFT 0x0 |
|---|
| 97947 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR__SHIFT 0x8 |
|---|
| 97948 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV__SHIFT 0x10 |
|---|
| 97949 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV__SHIFT 0x14 |
|---|
| 97950 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1__SHIFT 0x18 |
|---|
| 97951 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__CAP_ID_MASK 0x000000FFL |
|---|
| 97952 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 97953 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MINOR_REV_MASK 0x000F0000L |
|---|
| 97954 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_MAJOR_REV_MASK 0x00F00000L |
|---|
| 97955 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_0__SATA_CAP_RESERVED1_MASK 0xFF000000L |
|---|
| 97956 | //BIF_CFG_DEV0_EPF3_1_SATA_CAP_1 |
|---|
| 97957 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC__SHIFT 0x0 |
|---|
| 97958 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET__SHIFT 0x4 |
|---|
| 97959 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2__SHIFT 0x18 |
|---|
| 97960 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_LOC_MASK 0x0000000FL |
|---|
| 97961 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_BAR_OFFSET_MASK 0x00FFFFF0L |
|---|
| 97962 | #define BIF_CFG_DEV0_EPF3_1_SATA_CAP_1__SATA_CAP_RESERVED2_MASK 0xFF000000L |
|---|
| 97963 | //BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX |
|---|
| 97964 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1__SHIFT 0x0 |
|---|
| 97965 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX__SHIFT 0x2 |
|---|
| 97966 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2__SHIFT 0xc |
|---|
| 97967 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED1_MASK 0x00000003L |
|---|
| 97968 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_INDEX_MASK 0x00000FFCL |
|---|
| 97969 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX__IDP_RESERVED2_MASK 0xFFFFF000L |
|---|
| 97970 | //BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA |
|---|
| 97971 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA__SHIFT 0x0 |
|---|
| 97972 | #define BIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA__IDP_DATA_MASK 0xFFFFFFFFL |
|---|
| 97973 | //BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 97974 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 97975 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 97976 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 97977 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 97978 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 97979 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 97980 | //BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 97981 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 97982 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 97983 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 97984 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 97985 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 97986 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 97987 | //BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 |
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| 97988 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 97989 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 97990 | //BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 |
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| 97991 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 97992 | #define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
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| 97993 | //BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 97994 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 97995 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 97996 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 97997 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 97998 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 97999 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 98000 | //BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS |
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| 98001 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 98002 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 98003 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 98004 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 98005 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 98006 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 98007 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 98008 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 98009 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 98010 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 98011 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 98012 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 98013 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 98014 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 98015 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 98016 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 98017 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 98018 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 98019 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 98020 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 98021 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 98022 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 98023 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 98024 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 98025 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 98026 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 98027 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 98028 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 98029 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 98030 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 98031 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 98032 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 98033 | //BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK |
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| 98034 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 98035 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 98036 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 98037 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 98038 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 98039 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 98040 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 98041 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 98042 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 98043 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 98044 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 98045 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 98046 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 98047 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 98048 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 98049 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 98050 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 98051 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 98052 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 98053 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 98054 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 98055 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 98056 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 98057 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 98058 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 98059 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 98060 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 98061 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 98062 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 98063 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 98064 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 98065 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 98066 | //BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY |
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| 98067 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 98068 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 98069 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 98070 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 98071 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 98072 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 98073 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 98074 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 98075 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 98076 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 98077 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 98078 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 98079 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 98080 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 98081 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 98082 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 98083 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 98084 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 98085 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 98086 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 98087 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 98088 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 98089 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 98090 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 98091 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 98092 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 98093 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 98094 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 98095 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 98096 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 98097 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 98098 | #define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 98099 | //BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS |
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| 98100 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 98101 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 98102 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 98103 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 98104 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 98105 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 98106 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 98107 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 98108 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 98109 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 98110 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 98111 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 98112 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 98113 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 98114 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 98115 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 98116 | //BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK |
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| 98117 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 98118 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 98119 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 98120 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 98121 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 98122 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 98123 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 98124 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 98125 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 98126 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 98127 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 98128 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
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| 98129 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
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| 98130 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
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| 98131 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
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| 98132 | #define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 98133 | //BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL |
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| 98134 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 98135 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 98136 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 98137 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
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| 98138 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
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| 98139 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
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| 98140 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
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| 98141 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
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| 98142 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
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| 98143 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
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| 98144 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 98145 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 98146 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 98147 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 98148 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 98149 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 98150 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 98151 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 98152 | //BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 |
|---|
| 98153 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 98154 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 98155 | //BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 |
|---|
| 98156 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 98157 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 98158 | //BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 |
|---|
| 98159 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 98160 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 98161 | //BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 |
|---|
| 98162 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 98163 | #define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 98164 | //BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 98165 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 98166 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 98167 | //BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 98168 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 98169 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 98170 | //BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 98171 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 98172 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 98173 | //BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 98174 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 98175 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 98176 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST |
|---|
| 98177 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 98178 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 98179 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 98180 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 98181 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 98182 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 98183 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP |
|---|
| 98184 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 98185 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 98186 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL |
|---|
| 98187 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 98188 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 98189 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 98190 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 98191 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 98192 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 98193 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP |
|---|
| 98194 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 98195 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 98196 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL |
|---|
| 98197 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 98198 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 98199 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 98200 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 98201 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 98202 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 98203 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP |
|---|
| 98204 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 98205 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 98206 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL |
|---|
| 98207 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 98208 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 98209 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 98210 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 98211 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 98212 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 98213 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP |
|---|
| 98214 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 98215 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 98216 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL |
|---|
| 98217 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 98218 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 98219 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 98220 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 98221 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 98222 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 98223 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP |
|---|
| 98224 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 98225 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 98226 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL |
|---|
| 98227 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 98228 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 98229 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 98230 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 98231 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 98232 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 98233 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP |
|---|
| 98234 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 98235 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L |
|---|
| 98236 | //BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL |
|---|
| 98237 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 98238 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 98239 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 98240 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L |
|---|
| 98241 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L |
|---|
| 98242 | #define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L |
|---|
| 98243 | //BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 98244 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 98245 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 98246 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 98247 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 98248 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 98249 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 98250 | //BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 98251 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 98252 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 98253 | //BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA |
|---|
| 98254 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 98255 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 98256 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 98257 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 98258 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 98259 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 98260 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 98261 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 98262 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 98263 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 98264 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 98265 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 98266 | //BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP |
|---|
| 98267 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 98268 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 98269 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST |
|---|
| 98270 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 98271 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 98272 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 98273 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 98274 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 98275 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 98276 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP |
|---|
| 98277 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 98278 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 98279 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 98280 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 98281 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 98282 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 98283 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 98284 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 98285 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 98286 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 98287 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 98288 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 98289 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL |
|---|
| 98290 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS |
|---|
| 98291 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 98292 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 98293 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 98294 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 98295 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL |
|---|
| 98296 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 98297 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL |
|---|
| 98298 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 98299 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 98300 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 98301 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 98302 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 98303 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 98304 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 98305 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 98306 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 98307 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 98308 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 98309 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 98310 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 98311 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 98312 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 98313 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 98314 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 98315 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 98316 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 98317 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 98318 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 98319 | //BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 98320 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 98321 | #define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 98322 | //BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST |
|---|
| 98323 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 98324 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 98325 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 98326 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 98327 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 98328 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 98329 | //BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP |
|---|
| 98330 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 98331 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 98332 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 98333 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 98334 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 98335 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 98336 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 98337 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 98338 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 98339 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 98340 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 98341 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 98342 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 98343 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 98344 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 98345 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 98346 | //BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL |
|---|
| 98347 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 98348 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 98349 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 98350 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 98351 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 98352 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 98353 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 98354 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 98355 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 98356 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 98357 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 98358 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 98359 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 98360 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 98361 | //BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST |
|---|
| 98362 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 98363 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 98364 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 98365 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 98366 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 98367 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 98368 | //BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP |
|---|
| 98369 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 98370 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 98371 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 98372 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 98373 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 98374 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 98375 | //BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL |
|---|
| 98376 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 98377 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 98378 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 98379 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 98380 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 98381 | #define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 98382 | //BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 98383 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 98384 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 98385 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 98386 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 98387 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 98388 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 98389 | //BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP |
|---|
| 98390 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 98391 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 98392 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 98393 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 98394 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 98395 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 98396 | //BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL |
|---|
| 98397 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 98398 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 98399 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 98400 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 98401 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 98402 | #define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 98403 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 98404 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 98405 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 98406 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 98407 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 98408 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 98409 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 98410 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP |
|---|
| 98411 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 98412 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 98413 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 98414 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 98415 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 98416 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 98417 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 98418 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 98419 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 98420 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 98421 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 98422 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 98423 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL |
|---|
| 98424 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 98425 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 98426 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 98427 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 98428 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0 |
|---|
| 98429 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98430 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98431 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98432 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98433 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1 |
|---|
| 98434 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98435 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98436 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98437 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98438 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2 |
|---|
| 98439 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98440 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98441 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98442 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98443 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3 |
|---|
| 98444 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98445 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98446 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98447 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98448 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4 |
|---|
| 98449 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98450 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98451 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98452 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98453 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5 |
|---|
| 98454 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98455 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98456 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98457 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98458 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6 |
|---|
| 98459 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98460 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98461 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98462 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98463 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7 |
|---|
| 98464 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98465 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98466 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98467 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98468 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8 |
|---|
| 98469 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98470 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98471 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98472 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98473 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9 |
|---|
| 98474 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98475 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98476 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98477 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98478 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10 |
|---|
| 98479 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98480 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98481 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98482 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98483 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11 |
|---|
| 98484 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98485 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98486 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98487 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98488 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12 |
|---|
| 98489 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98490 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98491 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98492 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98493 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13 |
|---|
| 98494 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98495 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98496 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98497 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98498 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14 |
|---|
| 98499 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98500 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98501 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98502 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98503 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15 |
|---|
| 98504 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98505 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98506 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98507 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98508 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16 |
|---|
| 98509 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98510 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98511 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98512 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98513 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17 |
|---|
| 98514 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98515 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98516 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98517 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98518 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18 |
|---|
| 98519 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98520 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98521 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98522 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98523 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19 |
|---|
| 98524 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98525 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98526 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98527 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98528 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20 |
|---|
| 98529 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98530 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98531 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98532 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98533 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21 |
|---|
| 98534 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98535 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98536 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98537 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98538 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22 |
|---|
| 98539 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98540 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98541 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98542 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98543 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23 |
|---|
| 98544 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98545 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98546 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98547 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98548 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24 |
|---|
| 98549 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98550 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98551 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98552 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98553 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25 |
|---|
| 98554 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98555 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98556 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98557 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98558 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26 |
|---|
| 98559 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98560 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98561 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98562 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98563 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27 |
|---|
| 98564 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98565 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98566 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98567 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98568 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28 |
|---|
| 98569 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98570 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98571 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98572 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98573 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29 |
|---|
| 98574 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98575 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98576 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98577 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98578 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30 |
|---|
| 98579 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98580 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98581 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98582 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98583 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31 |
|---|
| 98584 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98585 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98586 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98587 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98588 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32 |
|---|
| 98589 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98590 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98591 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98592 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98593 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33 |
|---|
| 98594 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98595 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98596 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98597 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98598 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34 |
|---|
| 98599 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98600 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98601 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98602 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98603 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35 |
|---|
| 98604 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98605 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98606 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98607 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98608 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36 |
|---|
| 98609 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98610 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98611 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98612 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98613 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37 |
|---|
| 98614 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98615 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98616 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98617 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98618 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38 |
|---|
| 98619 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98620 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98621 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98622 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98623 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39 |
|---|
| 98624 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98625 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98626 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98627 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98628 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40 |
|---|
| 98629 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98630 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98631 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98632 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98633 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41 |
|---|
| 98634 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98635 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98636 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98637 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98638 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42 |
|---|
| 98639 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98640 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98641 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98642 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98643 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43 |
|---|
| 98644 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98645 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98646 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98647 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98648 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44 |
|---|
| 98649 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98650 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98651 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98652 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98653 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45 |
|---|
| 98654 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98655 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98656 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98657 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98658 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46 |
|---|
| 98659 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98660 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98661 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98662 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98663 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47 |
|---|
| 98664 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98665 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98666 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98667 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98668 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48 |
|---|
| 98669 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98670 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98671 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98672 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98673 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49 |
|---|
| 98674 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98675 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98676 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98677 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98678 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50 |
|---|
| 98679 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98680 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98681 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98682 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98683 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51 |
|---|
| 98684 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98685 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98686 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98687 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98688 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52 |
|---|
| 98689 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98690 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98691 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98692 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98693 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53 |
|---|
| 98694 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98695 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98696 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98697 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98698 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54 |
|---|
| 98699 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98700 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98701 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98702 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98703 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55 |
|---|
| 98704 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98705 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98706 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98707 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98708 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56 |
|---|
| 98709 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98710 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98711 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98712 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98713 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57 |
|---|
| 98714 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98715 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98716 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98717 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98718 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58 |
|---|
| 98719 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98720 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98721 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98722 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98723 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59 |
|---|
| 98724 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98725 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98726 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98727 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98728 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60 |
|---|
| 98729 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98730 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98731 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98732 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98733 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61 |
|---|
| 98734 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98735 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98736 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98737 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98738 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62 |
|---|
| 98739 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98740 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98741 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98742 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98743 | //BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63 |
|---|
| 98744 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0 |
|---|
| 98745 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8 |
|---|
| 98746 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL |
|---|
| 98747 | #define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L |
|---|
| 98748 | |
|---|
| 98749 | |
|---|
| 98750 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp |
|---|
| 98751 | //BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID |
|---|
| 98752 | #define BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 98753 | #define BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 98754 | //BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID |
|---|
| 98755 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 98756 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 98757 | //BIF_CFG_DEV0_EPF0_VF0_1_COMMAND |
|---|
| 98758 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 98759 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 98760 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 98761 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 98762 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 98763 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 98764 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 98765 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 98766 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 98767 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 98768 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 98769 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 98770 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 98771 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 98772 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 98773 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 98774 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 98775 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 98776 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 98777 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 98778 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 98779 | #define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 98780 | //BIF_CFG_DEV0_EPF0_VF0_1_STATUS |
|---|
| 98781 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 98782 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 98783 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 98784 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 98785 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 98786 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 98787 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 98788 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 98789 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 98790 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 98791 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 98792 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 98793 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 98794 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 98795 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 98796 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 98797 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 98798 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 98799 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 98800 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 98801 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 98802 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 98803 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 98804 | #define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 98805 | //BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID |
|---|
| 98806 | #define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 98807 | #define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 98808 | #define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 98809 | #define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 98810 | //BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE |
|---|
| 98811 | #define BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 98812 | #define BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 98813 | //BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS |
|---|
| 98814 | #define BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 98815 | #define BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 98816 | //BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS |
|---|
| 98817 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 98818 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 98819 | //BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE |
|---|
| 98820 | #define BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 98821 | #define BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 98822 | //BIF_CFG_DEV0_EPF0_VF0_1_LATENCY |
|---|
| 98823 | #define BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 98824 | #define BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 98825 | //BIF_CFG_DEV0_EPF0_VF0_1_HEADER |
|---|
| 98826 | #define 0x0 |
|---|
| 98827 | #define 0x7 |
|---|
| 98828 | #define 0x7FL |
|---|
| 98829 | #define 0x80L |
|---|
| 98830 | //BIF_CFG_DEV0_EPF0_VF0_1_BIST |
|---|
| 98831 | #define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 98832 | #define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 98833 | #define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 98834 | #define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 98835 | #define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 98836 | #define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 98837 | //BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1 |
|---|
| 98838 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 98839 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 98840 | //BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2 |
|---|
| 98841 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 98842 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 98843 | //BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3 |
|---|
| 98844 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 98845 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 98846 | //BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4 |
|---|
| 98847 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 98848 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 98849 | //BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5 |
|---|
| 98850 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 98851 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 98852 | //BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6 |
|---|
| 98853 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 98854 | #define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 98855 | //BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR |
|---|
| 98856 | #define BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 98857 | #define BIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 98858 | //BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID |
|---|
| 98859 | #define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 98860 | #define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 98861 | #define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 98862 | #define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 98863 | //BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR |
|---|
| 98864 | #define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 98865 | #define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 98866 | //BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR |
|---|
| 98867 | #define BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 98868 | #define BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 98869 | //BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE |
|---|
| 98870 | #define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 98871 | #define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 98872 | //BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN |
|---|
| 98873 | #define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 98874 | #define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 98875 | //BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT |
|---|
| 98876 | #define BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 98877 | #define BIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 98878 | //BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY |
|---|
| 98879 | #define BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 98880 | #define BIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 98881 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST |
|---|
| 98882 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 98883 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 98884 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 98885 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 98886 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP |
|---|
| 98887 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 98888 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 98889 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 98890 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 98891 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 98892 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 98893 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 98894 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 98895 | //BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP |
|---|
| 98896 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 98897 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 98898 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 98899 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 98900 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 98901 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 98902 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 98903 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 98904 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 98905 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 98906 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 98907 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 98908 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 98909 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 98910 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 98911 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 98912 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 98913 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 98914 | //BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL |
|---|
| 98915 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 98916 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 98917 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 98918 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 98919 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 98920 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 98921 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 98922 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 98923 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 98924 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 98925 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 98926 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 98927 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 98928 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 98929 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 98930 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 98931 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 98932 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 98933 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 98934 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 98935 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 98936 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 98937 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 98938 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 98939 | //BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS |
|---|
| 98940 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 98941 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 98942 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 98943 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 98944 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 98945 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 98946 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 98947 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 98948 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 98949 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 98950 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 98951 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 98952 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 98953 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 98954 | //BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP |
|---|
| 98955 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 98956 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 98957 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 98958 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 98959 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 98960 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 98961 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 98962 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 98963 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 98964 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 98965 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 98966 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 98967 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 98968 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 98969 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 98970 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 98971 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 98972 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 98973 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 98974 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 98975 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 98976 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 98977 | //BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL |
|---|
| 98978 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 98979 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 98980 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 98981 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 98982 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 98983 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 98984 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 98985 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 98986 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 98987 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 98988 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 98989 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 98990 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 98991 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 98992 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 98993 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 98994 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 98995 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 98996 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 98997 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 98998 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 98999 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 99000 | //BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS |
|---|
| 99001 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 99002 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 99003 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 99004 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 99005 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 99006 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 99007 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 99008 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 99009 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 99010 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 99011 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 99012 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 99013 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 99014 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 99015 | //BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2 |
|---|
| 99016 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 99017 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 99018 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 99019 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 99020 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 99021 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 99022 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 99023 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 99024 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 99025 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 99026 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 99027 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 99028 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 99029 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 99030 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 99031 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 99032 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 99033 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 99034 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 99035 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 99036 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 99037 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 99038 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 99039 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 99040 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 99041 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 99042 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 99043 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 99044 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 99045 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 99046 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 99047 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 99048 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 99049 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 99050 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 99051 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 99052 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 99053 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 99054 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 99055 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 99056 | //BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2 |
|---|
| 99057 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 99058 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 99059 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 99060 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 99061 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 99062 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 99063 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 99064 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 99065 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 99066 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 99067 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 99068 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 99069 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 99070 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 99071 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 99072 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 99073 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 99074 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 99075 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 99076 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 99077 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 99078 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 99079 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 99080 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 99081 | //BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2 |
|---|
| 99082 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 99083 | #define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 99084 | //BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2 |
|---|
| 99085 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 99086 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 99087 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 99088 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 99089 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 99090 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 99091 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 99092 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 99093 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 99094 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 99095 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 99096 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 99097 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 99098 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 99099 | //BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2 |
|---|
| 99100 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 99101 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 99102 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 99103 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 99104 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 99105 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 99106 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 99107 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 99108 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 99109 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 99110 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 99111 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 99112 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 99113 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 99114 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 99115 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 99116 | //BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2 |
|---|
| 99117 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 99118 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 99119 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 99120 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 99121 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 99122 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 99123 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 99124 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 99125 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 99126 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 99127 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 99128 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 99129 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 99130 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 99131 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 99132 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 99133 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 99134 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 99135 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 99136 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 99137 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 99138 | #define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 99139 | //BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST |
|---|
| 99140 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99141 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 99142 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 99143 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 99144 | //BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL |
|---|
| 99145 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 99146 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 99147 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 99148 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 99149 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 99150 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 99151 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 99152 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 99153 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 99154 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 99155 | //BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO |
|---|
| 99156 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 99157 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 99158 | //BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI |
|---|
| 99159 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 99160 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 99161 | //BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA |
|---|
| 99162 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 99163 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 99164 | //BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK |
|---|
| 99165 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 99166 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 99167 | //BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64 |
|---|
| 99168 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 99169 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 99170 | //BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64 |
|---|
| 99171 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 99172 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 99173 | //BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING |
|---|
| 99174 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 99175 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 99176 | //BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64 |
|---|
| 99177 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 99178 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 99179 | //BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST |
|---|
| 99180 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99181 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 99182 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 99183 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 99184 | //BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL |
|---|
| 99185 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 99186 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 99187 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 99188 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 99189 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 99190 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 99191 | //BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE |
|---|
| 99192 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 99193 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 99194 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 99195 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 99196 | //BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA |
|---|
| 99197 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 99198 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 99199 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 99200 | #define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 99201 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 99202 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99203 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 99204 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 99205 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 99206 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 99207 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 99208 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 99209 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 99210 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 99211 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 99212 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 99213 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 99214 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 99215 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 99216 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 99217 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 99218 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 99219 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 99220 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 99221 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 99222 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99223 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 99224 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 99225 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 99226 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 99227 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 99228 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 99229 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 99230 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 99231 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 99232 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 99233 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 99234 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 99235 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 99236 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 99237 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 99238 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 99239 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 99240 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 99241 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 99242 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 99243 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 99244 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 99245 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 99246 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 99247 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 99248 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 99249 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 99250 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 99251 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 99252 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 99253 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 99254 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 99255 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 99256 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 99257 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 99258 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 99259 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 99260 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 99261 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK |
|---|
| 99262 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 99263 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 99264 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 99265 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 99266 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 99267 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 99268 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 99269 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 99270 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 99271 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 99272 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 99273 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 99274 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 99275 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 99276 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 99277 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 99278 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 99279 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 99280 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 99281 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 99282 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 99283 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 99284 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 99285 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 99286 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 99287 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 99288 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 99289 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 99290 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 99291 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 99292 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 99293 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 99294 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 99295 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 99296 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 99297 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 99298 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 99299 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 99300 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 99301 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 99302 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 99303 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 99304 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 99305 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 99306 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 99307 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 99308 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 99309 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 99310 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 99311 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 99312 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 99313 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 99314 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 99315 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 99316 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 99317 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 99318 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 99319 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 99320 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 99321 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 99322 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 99323 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 99324 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 99325 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 99326 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 99327 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS |
|---|
| 99328 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 99329 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 99330 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 99331 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 99332 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 99333 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 99334 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 99335 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 99336 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 99337 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 99338 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 99339 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 99340 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 99341 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 99342 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 99343 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 99344 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK |
|---|
| 99345 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 99346 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 99347 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 99348 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 99349 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 99350 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 99351 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 99352 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 99353 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 99354 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 99355 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 99356 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 99357 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 99358 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 99359 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 99360 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 99361 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 99362 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 99363 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 99364 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 99365 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 99366 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 99367 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 99368 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 99369 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 99370 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 99371 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 99372 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 99373 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 99374 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 99375 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 99376 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 99377 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 99378 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 99379 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 99380 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0 |
|---|
| 99381 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 99382 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 99383 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1 |
|---|
| 99384 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 99385 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 99386 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2 |
|---|
| 99387 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 99388 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 99389 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3 |
|---|
| 99390 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 99391 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 99392 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 99393 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 99394 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 99395 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 99396 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 99397 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 99398 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 99399 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 99400 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 99401 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 99402 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 99403 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 99404 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 99405 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99406 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 99407 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 99408 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 99409 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 99410 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 99411 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP |
|---|
| 99412 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 99413 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 99414 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 99415 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 99416 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 99417 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 99418 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL |
|---|
| 99419 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 99420 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 99421 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 99422 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 99423 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 99424 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99425 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 99426 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 99427 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 99428 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 99429 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 99430 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP |
|---|
| 99431 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 99432 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 99433 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 99434 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 99435 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 99436 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 99437 | //BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL |
|---|
| 99438 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 99439 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 99440 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 99441 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 99442 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 99443 | #define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 99444 | |
|---|
| 99445 | |
|---|
| 99446 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp |
|---|
| 99447 | //BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID |
|---|
| 99448 | #define BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 99449 | #define BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 99450 | //BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID |
|---|
| 99451 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 99452 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 99453 | //BIF_CFG_DEV0_EPF0_VF1_1_COMMAND |
|---|
| 99454 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 99455 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 99456 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 99457 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 99458 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 99459 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 99460 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 99461 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 99462 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 99463 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 99464 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 99465 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 99466 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 99467 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 99468 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 99469 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 99470 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 99471 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 99472 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 99473 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 99474 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 99475 | #define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 99476 | //BIF_CFG_DEV0_EPF0_VF1_1_STATUS |
|---|
| 99477 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 99478 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 99479 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 99480 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 99481 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 99482 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 99483 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 99484 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 99485 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 99486 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 99487 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 99488 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 99489 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 99490 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 99491 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 99492 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 99493 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 99494 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 99495 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 99496 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 99497 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 99498 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 99499 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 99500 | #define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 99501 | //BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID |
|---|
| 99502 | #define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 99503 | #define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 99504 | #define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 99505 | #define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 99506 | //BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE |
|---|
| 99507 | #define BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 99508 | #define BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 99509 | //BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS |
|---|
| 99510 | #define BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 99511 | #define BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 99512 | //BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS |
|---|
| 99513 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 99514 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 99515 | //BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE |
|---|
| 99516 | #define BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 99517 | #define BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 99518 | //BIF_CFG_DEV0_EPF0_VF1_1_LATENCY |
|---|
| 99519 | #define BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 99520 | #define BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 99521 | //BIF_CFG_DEV0_EPF0_VF1_1_HEADER |
|---|
| 99522 | #define 0x0 |
|---|
| 99523 | #define 0x7 |
|---|
| 99524 | #define 0x7FL |
|---|
| 99525 | #define 0x80L |
|---|
| 99526 | //BIF_CFG_DEV0_EPF0_VF1_1_BIST |
|---|
| 99527 | #define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 99528 | #define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 99529 | #define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 99530 | #define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 99531 | #define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 99532 | #define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 99533 | //BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1 |
|---|
| 99534 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 99535 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 99536 | //BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2 |
|---|
| 99537 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 99538 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 99539 | //BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3 |
|---|
| 99540 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 99541 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 99542 | //BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4 |
|---|
| 99543 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 99544 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 99545 | //BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5 |
|---|
| 99546 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 99547 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 99548 | //BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6 |
|---|
| 99549 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 99550 | #define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 99551 | //BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR |
|---|
| 99552 | #define BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 99553 | #define BIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 99554 | //BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID |
|---|
| 99555 | #define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 99556 | #define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 99557 | #define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 99558 | #define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 99559 | //BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR |
|---|
| 99560 | #define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 99561 | #define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 99562 | //BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR |
|---|
| 99563 | #define BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 99564 | #define BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 99565 | //BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE |
|---|
| 99566 | #define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 99567 | #define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 99568 | //BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN |
|---|
| 99569 | #define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 99570 | #define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 99571 | //BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT |
|---|
| 99572 | #define BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 99573 | #define BIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 99574 | //BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY |
|---|
| 99575 | #define BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 99576 | #define BIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 99577 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST |
|---|
| 99578 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99579 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 99580 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 99581 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 99582 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP |
|---|
| 99583 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 99584 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 99585 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 99586 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 99587 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 99588 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 99589 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 99590 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 99591 | //BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP |
|---|
| 99592 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 99593 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 99594 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 99595 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 99596 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 99597 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 99598 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 99599 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 99600 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 99601 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 99602 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 99603 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 99604 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 99605 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 99606 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 99607 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 99608 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 99609 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 99610 | //BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL |
|---|
| 99611 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 99612 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 99613 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 99614 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 99615 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 99616 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 99617 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 99618 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 99619 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 99620 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 99621 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 99622 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 99623 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 99624 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 99625 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 99626 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 99627 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 99628 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 99629 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 99630 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 99631 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 99632 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 99633 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 99634 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 99635 | //BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS |
|---|
| 99636 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 99637 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 99638 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 99639 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 99640 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 99641 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 99642 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 99643 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 99644 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 99645 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 99646 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 99647 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 99648 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 99649 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 99650 | //BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP |
|---|
| 99651 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 99652 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 99653 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 99654 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 99655 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 99656 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 99657 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 99658 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 99659 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 99660 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 99661 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 99662 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 99663 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 99664 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 99665 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 99666 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 99667 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 99668 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 99669 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 99670 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 99671 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 99672 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 99673 | //BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL |
|---|
| 99674 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 99675 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 99676 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 99677 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 99678 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 99679 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 99680 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 99681 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 99682 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 99683 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 99684 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 99685 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 99686 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 99687 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 99688 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 99689 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 99690 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 99691 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 99692 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 99693 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 99694 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 99695 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 99696 | //BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS |
|---|
| 99697 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 99698 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 99699 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 99700 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 99701 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 99702 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 99703 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 99704 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 99705 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 99706 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 99707 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 99708 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 99709 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 99710 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 99711 | //BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2 |
|---|
| 99712 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 99713 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 99714 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 99715 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 99716 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 99717 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 99718 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 99719 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 99720 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 99721 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 99722 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 99723 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 99724 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 99725 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 99726 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 99727 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 99728 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 99729 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 99730 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 99731 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 99732 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 99733 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 99734 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 99735 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 99736 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 99737 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 99738 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 99739 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 99740 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 99741 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 99742 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 99743 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 99744 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 99745 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 99746 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 99747 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 99748 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 99749 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 99750 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 99751 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 99752 | //BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2 |
|---|
| 99753 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 99754 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 99755 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 99756 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 99757 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 99758 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 99759 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 99760 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 99761 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 99762 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 99763 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 99764 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 99765 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 99766 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 99767 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 99768 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 99769 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 99770 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 99771 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 99772 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 99773 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 99774 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 99775 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 99776 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 99777 | //BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2 |
|---|
| 99778 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 99779 | #define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 99780 | //BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2 |
|---|
| 99781 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 99782 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 99783 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 99784 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 99785 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 99786 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 99787 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 99788 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 99789 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 99790 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 99791 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 99792 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 99793 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 99794 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 99795 | //BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2 |
|---|
| 99796 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 99797 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 99798 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 99799 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 99800 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 99801 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 99802 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 99803 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 99804 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 99805 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 99806 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 99807 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 99808 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 99809 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 99810 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 99811 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 99812 | //BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2 |
|---|
| 99813 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 99814 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 99815 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 99816 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 99817 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 99818 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 99819 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 99820 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 99821 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 99822 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 99823 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 99824 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 99825 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 99826 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 99827 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 99828 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 99829 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 99830 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 99831 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 99832 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 99833 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 99834 | #define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 99835 | //BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST |
|---|
| 99836 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99837 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 99838 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 99839 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 99840 | //BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL |
|---|
| 99841 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 99842 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 99843 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 99844 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 99845 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 99846 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 99847 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 99848 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 99849 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 99850 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 99851 | //BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO |
|---|
| 99852 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 99853 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 99854 | //BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI |
|---|
| 99855 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 99856 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 99857 | //BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA |
|---|
| 99858 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 99859 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 99860 | //BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK |
|---|
| 99861 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 99862 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 99863 | //BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64 |
|---|
| 99864 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 99865 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 99866 | //BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64 |
|---|
| 99867 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 99868 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 99869 | //BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING |
|---|
| 99870 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 99871 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 99872 | //BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64 |
|---|
| 99873 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 99874 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 99875 | //BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST |
|---|
| 99876 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99877 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 99878 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 99879 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 99880 | //BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL |
|---|
| 99881 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 99882 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 99883 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 99884 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 99885 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 99886 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 99887 | //BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE |
|---|
| 99888 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 99889 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 99890 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 99891 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 99892 | //BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA |
|---|
| 99893 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 99894 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 99895 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 99896 | #define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 99897 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 99898 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99899 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 99900 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 99901 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 99902 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 99903 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 99904 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 99905 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 99906 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 99907 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 99908 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 99909 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 99910 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 99911 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 99912 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 99913 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 99914 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 99915 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 99916 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 99917 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 99918 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 99919 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 99920 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 99921 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 99922 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 99923 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 99924 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 99925 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 99926 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 99927 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 99928 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 99929 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 99930 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 99931 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 99932 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 99933 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 99934 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 99935 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 99936 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 99937 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 99938 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 99939 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 99940 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 99941 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 99942 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 99943 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 99944 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 99945 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 99946 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 99947 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 99948 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 99949 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 99950 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 99951 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 99952 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 99953 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 99954 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 99955 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 99956 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 99957 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK |
|---|
| 99958 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 99959 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 99960 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 99961 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 99962 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 99963 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 99964 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 99965 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 99966 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 99967 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 99968 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 99969 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 99970 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 99971 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 99972 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 99973 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 99974 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 99975 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 99976 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 99977 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 99978 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 99979 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 99980 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 99981 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 99982 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 99983 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 99984 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 99985 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 99986 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 99987 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 99988 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 99989 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 99990 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY |
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| 99991 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 99992 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 99993 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 99994 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 99995 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 99996 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 99997 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 99998 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 99999 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 100000 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 100001 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 100002 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 100003 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 100004 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 100005 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 100006 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 100007 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 100008 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 100009 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 100010 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 100011 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 100012 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 100013 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 100014 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 100015 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 100016 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 100017 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 100018 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 100019 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 100020 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 100021 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 100022 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 100023 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS |
|---|
| 100024 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 100025 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 100026 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 100027 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 100028 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 100029 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 100030 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 100031 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 100032 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 100033 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 100034 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 100035 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 100036 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 100037 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 100038 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 100039 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 100040 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK |
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| 100041 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 100042 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 100043 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 100044 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 100045 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 100046 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 100047 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 100048 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 100049 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 100050 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 100051 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 100052 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
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| 100053 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
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| 100054 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
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| 100055 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
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| 100056 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 100057 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL |
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| 100058 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 100059 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 100060 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 100061 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
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| 100062 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
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| 100063 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
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| 100064 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
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| 100065 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
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| 100066 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
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| 100067 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
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| 100068 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
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| 100069 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
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| 100070 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
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| 100071 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
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| 100072 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
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| 100073 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
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| 100074 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
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| 100075 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
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| 100076 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0 |
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| 100077 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
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| 100078 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
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| 100079 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1 |
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| 100080 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
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| 100081 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
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| 100082 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2 |
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| 100083 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
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| 100084 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
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| 100085 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3 |
|---|
| 100086 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
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| 100087 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
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| 100088 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 100089 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
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| 100090 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 100091 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 100092 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 100093 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 100094 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 100095 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 100096 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 100097 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 100098 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 100099 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 100100 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 100101 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 100102 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 100103 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 100104 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 100105 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 100106 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 100107 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP |
|---|
| 100108 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 100109 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 100110 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 100111 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 100112 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 100113 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 100114 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL |
|---|
| 100115 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 100116 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 100117 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 100118 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 100119 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 100120 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 100121 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 100122 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 100123 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 100124 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 100125 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 100126 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP |
|---|
| 100127 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 100128 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 100129 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 100130 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 100131 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 100132 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 100133 | //BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL |
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| 100134 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
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| 100135 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
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| 100136 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
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| 100137 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
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| 100138 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
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| 100139 | #define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
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| 100140 | |
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| 100141 | |
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| 100142 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp |
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| 100143 | //BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID |
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| 100144 | #define BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
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| 100145 | #define BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
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| 100146 | //BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID |
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| 100147 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
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| 100148 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
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| 100149 | //BIF_CFG_DEV0_EPF0_VF2_1_COMMAND |
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| 100150 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
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| 100151 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
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| 100152 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
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| 100153 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
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| 100154 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
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| 100155 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
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| 100156 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
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| 100157 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
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| 100158 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN__SHIFT 0x8 |
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| 100159 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
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| 100160 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS__SHIFT 0xa |
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| 100161 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
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| 100162 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
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| 100163 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
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| 100164 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
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| 100165 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
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| 100166 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
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| 100167 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
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| 100168 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING_MASK 0x0080L |
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| 100169 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN_MASK 0x0100L |
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| 100170 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
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| 100171 | #define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS_MASK 0x0400L |
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| 100172 | //BIF_CFG_DEV0_EPF0_VF2_1_STATUS |
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| 100173 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
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| 100174 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS__SHIFT 0x3 |
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| 100175 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST__SHIFT 0x4 |
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| 100176 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
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| 100177 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
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| 100178 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
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| 100179 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
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| 100180 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
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| 100181 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
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| 100182 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
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| 100183 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
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| 100184 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
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| 100185 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
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| 100186 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS_MASK 0x0008L |
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| 100187 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST_MASK 0x0010L |
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| 100188 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_CAP_MASK 0x0020L |
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| 100189 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
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| 100190 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
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| 100191 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
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| 100192 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
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| 100193 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
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| 100194 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
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| 100195 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
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| 100196 | #define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
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| 100197 | //BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID |
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| 100198 | #define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
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| 100199 | #define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
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| 100200 | #define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
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| 100201 | #define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
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| 100202 | //BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE |
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| 100203 | #define BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
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| 100204 | #define BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
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| 100205 | //BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS |
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| 100206 | #define BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
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| 100207 | #define BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
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| 100208 | //BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS |
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| 100209 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
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| 100210 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
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| 100211 | //BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE |
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| 100212 | #define BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
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| 100213 | #define BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
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| 100214 | //BIF_CFG_DEV0_EPF0_VF2_1_LATENCY |
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| 100215 | #define BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
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| 100216 | #define BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
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| 100217 | //BIF_CFG_DEV0_EPF0_VF2_1_HEADER |
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| 100218 | #define 0x0 |
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| 100219 | #define 0x7 |
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| 100220 | #define 0x7FL |
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| 100221 | #define 0x80L |
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| 100222 | //BIF_CFG_DEV0_EPF0_VF2_1_BIST |
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| 100223 | #define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP__SHIFT 0x0 |
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| 100224 | #define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT__SHIFT 0x6 |
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| 100225 | #define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP__SHIFT 0x7 |
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| 100226 | #define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP_MASK 0x0FL |
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| 100227 | #define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT_MASK 0x40L |
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| 100228 | #define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP_MASK 0x80L |
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| 100229 | //BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1 |
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| 100230 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
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| 100231 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 100232 | //BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2 |
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| 100233 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
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| 100234 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 100235 | //BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3 |
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| 100236 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
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| 100237 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 100238 | //BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4 |
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| 100239 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
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| 100240 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 100241 | //BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5 |
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| 100242 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
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| 100243 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 100244 | //BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6 |
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| 100245 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
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| 100246 | #define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 100247 | //BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR |
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| 100248 | #define BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
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| 100249 | #define BIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
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| 100250 | //BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID |
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| 100251 | #define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
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| 100252 | #define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
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| 100253 | #define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
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| 100254 | #define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
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| 100255 | //BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR |
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| 100256 | #define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
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| 100257 | #define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 100258 | //BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR |
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| 100259 | #define BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
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| 100260 | #define BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
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| 100261 | //BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE |
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| 100262 | #define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
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| 100263 | #define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
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| 100264 | //BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN |
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| 100265 | #define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
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| 100266 | #define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
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| 100267 | //BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT |
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| 100268 | #define BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
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| 100269 | #define BIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
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| 100270 | //BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY |
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| 100271 | #define BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
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| 100272 | #define BIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
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| 100273 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST |
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| 100274 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 100275 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 100276 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 100277 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 100278 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP |
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| 100279 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION__SHIFT 0x0 |
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| 100280 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 100281 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 100282 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
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| 100283 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION_MASK 0x000FL |
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| 100284 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
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| 100285 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
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| 100286 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
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| 100287 | //BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP |
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| 100288 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
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| 100289 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
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| 100290 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
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| 100291 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
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| 100292 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
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| 100293 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
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| 100294 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
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| 100295 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
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| 100296 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
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| 100297 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 100298 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 100299 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
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| 100300 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
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| 100301 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
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| 100302 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
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| 100303 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
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| 100304 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
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| 100305 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
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| 100306 | //BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL |
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| 100307 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
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| 100308 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
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| 100309 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
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| 100310 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
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| 100311 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 100312 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 100313 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
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| 100314 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
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| 100315 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
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| 100316 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 100317 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 100318 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
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| 100319 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
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| 100320 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
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| 100321 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
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| 100322 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
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| 100323 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
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| 100324 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 100325 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 100326 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 100327 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 100328 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
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| 100329 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
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| 100330 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 100331 | //BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS |
|---|
| 100332 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
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| 100333 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
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| 100334 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
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| 100335 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 100336 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 100337 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 100338 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
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| 100339 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
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| 100340 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 100341 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 100342 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 100343 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 100344 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
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| 100345 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
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| 100346 | //BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP |
|---|
| 100347 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 100348 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 100349 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 100350 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
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| 100351 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 100352 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 100353 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 100354 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 100355 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
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| 100356 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 100357 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 100358 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 100359 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 100360 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 100361 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 100362 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 100363 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 100364 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 100365 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 100366 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
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| 100367 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 100368 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 100369 | //BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL |
|---|
| 100370 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 100371 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 100372 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 100373 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
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| 100374 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 100375 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
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| 100376 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
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| 100377 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
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| 100378 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 100379 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 100380 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
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| 100381 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 100382 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 100383 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 100384 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 100385 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 100386 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 100387 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 100388 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 100389 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 100390 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 100391 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 100392 | //BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS |
|---|
| 100393 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 100394 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 100395 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 100396 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 100397 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 100398 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 100399 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 100400 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 100401 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 100402 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 100403 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 100404 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 100405 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 100406 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 100407 | //BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2 |
|---|
| 100408 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 100409 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 100410 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 100411 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 100412 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 100413 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 100414 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 100415 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 100416 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 100417 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 100418 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 100419 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 100420 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 100421 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 100422 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 100423 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 100424 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 100425 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 100426 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 100427 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 100428 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 100429 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 100430 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 100431 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 100432 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 100433 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 100434 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 100435 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 100436 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 100437 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 100438 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 100439 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 100440 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 100441 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 100442 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 100443 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 100444 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 100445 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 100446 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 100447 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 100448 | //BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2 |
|---|
| 100449 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 100450 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 100451 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 100452 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 100453 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 100454 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 100455 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 100456 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 100457 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 100458 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 100459 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 100460 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 100461 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 100462 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 100463 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 100464 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 100465 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 100466 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 100467 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 100468 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 100469 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 100470 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 100471 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 100472 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 100473 | //BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2 |
|---|
| 100474 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 100475 | #define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 100476 | //BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2 |
|---|
| 100477 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 100478 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 100479 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 100480 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 100481 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 100482 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 100483 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 100484 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 100485 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 100486 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 100487 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 100488 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 100489 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 100490 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 100491 | //BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2 |
|---|
| 100492 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
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| 100493 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
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| 100494 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
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| 100495 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
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| 100496 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
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| 100497 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
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| 100498 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
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| 100499 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
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| 100500 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
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| 100501 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
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| 100502 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
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| 100503 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
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| 100504 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
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| 100505 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
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| 100506 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
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| 100507 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
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| 100508 | //BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2 |
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| 100509 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
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| 100510 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
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| 100511 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
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| 100512 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
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| 100513 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
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| 100514 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
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| 100515 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
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| 100516 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
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| 100517 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
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| 100518 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
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| 100519 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
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| 100520 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
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| 100521 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
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| 100522 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
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| 100523 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
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| 100524 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
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| 100525 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
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| 100526 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
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| 100527 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
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| 100528 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
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| 100529 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
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| 100530 | #define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
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| 100531 | //BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST |
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| 100532 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 100533 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 100534 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 100535 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 100536 | //BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL |
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| 100537 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
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| 100538 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
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| 100539 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
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| 100540 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
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| 100541 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
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| 100542 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
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| 100543 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
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| 100544 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
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| 100545 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
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| 100546 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
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| 100547 | //BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO |
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| 100548 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
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| 100549 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
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| 100550 | //BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI |
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| 100551 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
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| 100552 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 100553 | //BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA |
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| 100554 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
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| 100555 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
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| 100556 | //BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK |
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| 100557 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
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| 100558 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
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| 100559 | //BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64 |
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| 100560 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
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| 100561 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
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| 100562 | //BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64 |
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| 100563 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
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| 100564 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
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| 100565 | //BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING |
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| 100566 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
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| 100567 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
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| 100568 | //BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64 |
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| 100569 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
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| 100570 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
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| 100571 | //BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST |
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| 100572 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 100573 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 100574 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 100575 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 100576 | //BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL |
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| 100577 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
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| 100578 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
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| 100579 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
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| 100580 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
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| 100581 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
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| 100582 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
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| 100583 | //BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE |
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| 100584 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
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| 100585 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
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| 100586 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
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| 100587 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
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| 100588 | //BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA |
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| 100589 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
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| 100590 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
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| 100591 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
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| 100592 | #define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
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| 100593 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
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| 100594 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 100595 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 100596 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 100597 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 100598 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 100599 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 100600 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR |
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| 100601 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
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| 100602 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
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| 100603 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
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| 100604 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
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| 100605 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
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| 100606 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
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| 100607 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1 |
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| 100608 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 100609 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 100610 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2 |
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| 100611 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 100612 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
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| 100613 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 100614 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 100615 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 100616 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 100617 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 100618 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 100619 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 100620 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS |
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| 100621 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 100622 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 100623 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 100624 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 100625 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 100626 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 100627 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 100628 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 100629 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 100630 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 100631 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 100632 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 100633 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 100634 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 100635 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 100636 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 100637 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 100638 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 100639 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 100640 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 100641 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 100642 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 100643 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 100644 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 100645 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 100646 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 100647 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 100648 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 100649 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 100650 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 100651 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 100652 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 100653 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK |
|---|
| 100654 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 100655 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 100656 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 100657 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 100658 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 100659 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 100660 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 100661 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 100662 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 100663 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 100664 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 100665 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 100666 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 100667 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 100668 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 100669 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 100670 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 100671 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 100672 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 100673 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 100674 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 100675 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 100676 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 100677 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 100678 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 100679 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 100680 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 100681 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 100682 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 100683 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 100684 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 100685 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 100686 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 100687 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 100688 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 100689 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 100690 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 100691 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 100692 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 100693 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 100694 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 100695 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 100696 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 100697 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 100698 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 100699 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 100700 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 100701 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 100702 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 100703 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 100704 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 100705 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 100706 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 100707 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 100708 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 100709 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 100710 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 100711 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 100712 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 100713 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 100714 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 100715 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 100716 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 100717 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 100718 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 100719 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS |
|---|
| 100720 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 100721 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 100722 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 100723 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 100724 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 100725 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 100726 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 100727 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 100728 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 100729 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 100730 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 100731 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 100732 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 100733 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 100734 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 100735 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 100736 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK |
|---|
| 100737 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 100738 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 100739 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 100740 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 100741 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 100742 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 100743 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 100744 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 100745 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 100746 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 100747 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 100748 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 100749 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 100750 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 100751 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 100752 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 100753 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 100754 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 100755 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 100756 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 100757 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 100758 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 100759 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 100760 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 100761 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 100762 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 100763 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 100764 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 100765 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 100766 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 100767 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 100768 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 100769 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 100770 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 100771 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 100772 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0 |
|---|
| 100773 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 100774 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 100775 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1 |
|---|
| 100776 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 100777 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 100778 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2 |
|---|
| 100779 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 100780 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 100781 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3 |
|---|
| 100782 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 100783 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 100784 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 100785 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 100786 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 100787 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 100788 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 100789 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 100790 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 100791 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 100792 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 100793 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 100794 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 100795 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 100796 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 100797 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 100798 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 100799 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 100800 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 100801 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 100802 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 100803 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP |
|---|
| 100804 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 100805 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 100806 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 100807 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 100808 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 100809 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 100810 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL |
|---|
| 100811 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 100812 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 100813 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 100814 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 100815 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 100816 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 100817 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 100818 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 100819 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 100820 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 100821 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 100822 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP |
|---|
| 100823 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 100824 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 100825 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 100826 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 100827 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 100828 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 100829 | //BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL |
|---|
| 100830 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 100831 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 100832 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 100833 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 100834 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 100835 | #define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 100836 | |
|---|
| 100837 | |
|---|
| 100838 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp |
|---|
| 100839 | //BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID |
|---|
| 100840 | #define BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 100841 | #define BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 100842 | //BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID |
|---|
| 100843 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 100844 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 100845 | //BIF_CFG_DEV0_EPF0_VF3_1_COMMAND |
|---|
| 100846 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 100847 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 100848 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 100849 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 100850 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 100851 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 100852 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 100853 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 100854 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 100855 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 100856 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 100857 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 100858 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 100859 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 100860 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 100861 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 100862 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 100863 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 100864 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 100865 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 100866 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 100867 | #define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 100868 | //BIF_CFG_DEV0_EPF0_VF3_1_STATUS |
|---|
| 100869 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 100870 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 100871 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 100872 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 100873 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 100874 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 100875 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 100876 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 100877 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 100878 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 100879 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 100880 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 100881 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 100882 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 100883 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 100884 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 100885 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 100886 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 100887 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 100888 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 100889 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 100890 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 100891 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 100892 | #define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 100893 | //BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID |
|---|
| 100894 | #define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 100895 | #define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 100896 | #define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 100897 | #define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 100898 | //BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE |
|---|
| 100899 | #define BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 100900 | #define BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 100901 | //BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS |
|---|
| 100902 | #define BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 100903 | #define BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 100904 | //BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS |
|---|
| 100905 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 100906 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 100907 | //BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE |
|---|
| 100908 | #define BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 100909 | #define BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 100910 | //BIF_CFG_DEV0_EPF0_VF3_1_LATENCY |
|---|
| 100911 | #define BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 100912 | #define BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 100913 | //BIF_CFG_DEV0_EPF0_VF3_1_HEADER |
|---|
| 100914 | #define 0x0 |
|---|
| 100915 | #define 0x7 |
|---|
| 100916 | #define 0x7FL |
|---|
| 100917 | #define 0x80L |
|---|
| 100918 | //BIF_CFG_DEV0_EPF0_VF3_1_BIST |
|---|
| 100919 | #define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 100920 | #define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 100921 | #define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 100922 | #define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 100923 | #define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 100924 | #define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 100925 | //BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1 |
|---|
| 100926 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 100927 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 100928 | //BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2 |
|---|
| 100929 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 100930 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 100931 | //BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3 |
|---|
| 100932 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 100933 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 100934 | //BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4 |
|---|
| 100935 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 100936 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 100937 | //BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5 |
|---|
| 100938 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 100939 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 100940 | //BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6 |
|---|
| 100941 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 100942 | #define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 100943 | //BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR |
|---|
| 100944 | #define BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 100945 | #define BIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 100946 | //BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID |
|---|
| 100947 | #define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 100948 | #define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 100949 | #define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 100950 | #define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 100951 | //BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR |
|---|
| 100952 | #define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 100953 | #define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 100954 | //BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR |
|---|
| 100955 | #define BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 100956 | #define BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 100957 | //BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE |
|---|
| 100958 | #define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 100959 | #define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 100960 | //BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN |
|---|
| 100961 | #define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 100962 | #define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 100963 | //BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT |
|---|
| 100964 | #define BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 100965 | #define BIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 100966 | //BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY |
|---|
| 100967 | #define BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 100968 | #define BIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 100969 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST |
|---|
| 100970 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 100971 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 100972 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 100973 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 100974 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP |
|---|
| 100975 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 100976 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 100977 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 100978 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 100979 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 100980 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 100981 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 100982 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 100983 | //BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP |
|---|
| 100984 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 100985 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 100986 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 100987 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 100988 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 100989 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 100990 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 100991 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 100992 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 100993 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 100994 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 100995 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
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| 100996 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
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| 100997 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
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| 100998 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
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| 100999 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
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| 101000 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
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| 101001 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
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| 101002 | //BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL |
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| 101003 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
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| 101004 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
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| 101005 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
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| 101006 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
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| 101007 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 101008 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 101009 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
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| 101010 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
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| 101011 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
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| 101012 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 101013 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 101014 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
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| 101015 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
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| 101016 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
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| 101017 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
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| 101018 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
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| 101019 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
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| 101020 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
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| 101021 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
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| 101022 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
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| 101023 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
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| 101024 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
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| 101025 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
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| 101026 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
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| 101027 | //BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS |
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| 101028 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
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| 101029 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
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| 101030 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
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| 101031 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 101032 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 101033 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 101034 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
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| 101035 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
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| 101036 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 101037 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
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| 101038 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
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| 101039 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
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| 101040 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
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| 101041 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
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| 101042 | //BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP |
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| 101043 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
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| 101044 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 101045 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 101046 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
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| 101047 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 101048 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
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| 101049 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
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| 101050 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 101051 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
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| 101052 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 101053 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 101054 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
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| 101055 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
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| 101056 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
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| 101057 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
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| 101058 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
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| 101059 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
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| 101060 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
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| 101061 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
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| 101062 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
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| 101063 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
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| 101064 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
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| 101065 | //BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL |
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| 101066 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
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| 101067 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
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| 101068 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
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| 101069 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
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| 101070 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
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| 101071 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
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| 101072 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
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| 101073 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
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| 101074 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
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| 101075 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
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| 101076 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
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| 101077 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
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| 101078 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
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| 101079 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
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| 101080 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
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| 101081 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
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| 101082 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
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| 101083 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
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| 101084 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
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| 101085 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
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| 101086 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
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| 101087 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
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| 101088 | //BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS |
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| 101089 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
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| 101090 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
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| 101091 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
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| 101092 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
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| 101093 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
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| 101094 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
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| 101095 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
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| 101096 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
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| 101097 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
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| 101098 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
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| 101099 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
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| 101100 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
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| 101101 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
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| 101102 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
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| 101103 | //BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2 |
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| 101104 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
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| 101105 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
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| 101106 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
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| 101107 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
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| 101108 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
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| 101109 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
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| 101110 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
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| 101111 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
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| 101112 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
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| 101113 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
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| 101114 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
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| 101115 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
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| 101116 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
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| 101117 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
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| 101118 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
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| 101119 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
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| 101120 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
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| 101121 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
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| 101122 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
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| 101123 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
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| 101124 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
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| 101125 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
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| 101126 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
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| 101127 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
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| 101128 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
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| 101129 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
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| 101130 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
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| 101131 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
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| 101132 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
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| 101133 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
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| 101134 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
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| 101135 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
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| 101136 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
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| 101137 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
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| 101138 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
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| 101139 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
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| 101140 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
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| 101141 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
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| 101142 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
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| 101143 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
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| 101144 | //BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2 |
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| 101145 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
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| 101146 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
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| 101147 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
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| 101148 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
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| 101149 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
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| 101150 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
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| 101151 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
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| 101152 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
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| 101153 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
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| 101154 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
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| 101155 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
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| 101156 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
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| 101157 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
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| 101158 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
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| 101159 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
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| 101160 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
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| 101161 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
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| 101162 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
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| 101163 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
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| 101164 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
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| 101165 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
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| 101166 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
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| 101167 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
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| 101168 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
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| 101169 | //BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2 |
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| 101170 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
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| 101171 | #define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
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| 101172 | //BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2 |
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| 101173 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
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| 101174 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
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| 101175 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
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| 101176 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
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| 101177 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
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| 101178 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
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| 101179 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
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| 101180 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
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| 101181 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
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| 101182 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
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| 101183 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
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| 101184 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
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| 101185 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
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| 101186 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
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| 101187 | //BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2 |
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| 101188 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
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| 101189 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
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| 101190 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
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| 101191 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
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| 101192 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
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| 101193 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
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| 101194 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
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| 101195 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
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| 101196 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
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| 101197 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
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| 101198 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
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| 101199 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
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| 101200 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
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| 101201 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 101202 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
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| 101203 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
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| 101204 | //BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2 |
|---|
| 101205 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
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| 101206 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
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| 101207 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
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| 101208 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
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| 101209 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
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| 101210 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
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| 101211 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
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| 101212 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
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| 101213 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
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| 101214 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
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| 101215 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
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| 101216 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
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| 101217 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
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| 101218 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
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| 101219 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
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| 101220 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
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| 101221 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
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| 101222 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
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| 101223 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
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| 101224 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
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| 101225 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
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| 101226 | #define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 101227 | //BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST |
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| 101228 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 101229 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 101230 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 101231 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 101232 | //BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL |
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| 101233 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
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| 101234 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
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| 101235 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
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| 101236 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
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| 101237 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
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| 101238 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
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| 101239 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
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| 101240 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
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| 101241 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
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| 101242 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
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| 101243 | //BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO |
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| 101244 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
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| 101245 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
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| 101246 | //BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI |
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| 101247 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
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| 101248 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
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| 101249 | //BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA |
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| 101250 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
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| 101251 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
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| 101252 | //BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK |
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| 101253 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
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| 101254 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
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| 101255 | //BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64 |
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| 101256 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
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| 101257 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
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| 101258 | //BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64 |
|---|
| 101259 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
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| 101260 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
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| 101261 | //BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING |
|---|
| 101262 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
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| 101263 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
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| 101264 | //BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64 |
|---|
| 101265 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
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| 101266 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 101267 | //BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST |
|---|
| 101268 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 101269 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 101270 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 101271 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 101272 | //BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL |
|---|
| 101273 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 101274 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
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| 101275 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 101276 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 101277 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 101278 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 101279 | //BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE |
|---|
| 101280 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 101281 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 101282 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 101283 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 101284 | //BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA |
|---|
| 101285 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 101286 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 101287 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 101288 | #define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 101289 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 101290 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 101291 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 101292 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 101293 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 101294 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 101295 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 101296 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 101297 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 101298 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 101299 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 101300 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 101301 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 101302 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 101303 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 101304 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 101305 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 101306 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 101307 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 101308 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 101309 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 101310 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 101311 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 101312 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 101313 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 101314 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 101315 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 101316 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 101317 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 101318 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 101319 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 101320 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 101321 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 101322 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 101323 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 101324 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 101325 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 101326 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 101327 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 101328 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 101329 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 101330 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 101331 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 101332 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 101333 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 101334 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 101335 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 101336 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 101337 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 101338 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 101339 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 101340 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 101341 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 101342 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 101343 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 101344 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 101345 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 101346 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 101347 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 101348 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 101349 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK |
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| 101350 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 101351 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 101352 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 101353 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 101354 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 101355 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 101356 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 101357 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 101358 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 101359 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 101360 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 101361 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 101362 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 101363 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 101364 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 101365 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 101366 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 101367 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 101368 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 101369 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 101370 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 101371 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 101372 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 101373 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 101374 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 101375 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 101376 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 101377 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 101378 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 101379 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 101380 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 101381 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 101382 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY |
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| 101383 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 101384 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 101385 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 101386 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 101387 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 101388 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 101389 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 101390 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 101391 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 101392 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 101393 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 101394 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 101395 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 101396 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 101397 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 101398 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 101399 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 101400 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 101401 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 101402 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 101403 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 101404 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 101405 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 101406 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 101407 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 101408 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 101409 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 101410 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 101411 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 101412 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 101413 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 101414 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 101415 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS |
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| 101416 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 101417 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 101418 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 101419 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 101420 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 101421 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 101422 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 101423 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 101424 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 101425 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 101426 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 101427 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 101428 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 101429 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 101430 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 101431 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 101432 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK |
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| 101433 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 101434 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 101435 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 101436 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 101437 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 101438 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 101439 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 101440 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 101441 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 101442 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 101443 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 101444 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
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| 101445 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
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| 101446 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 101447 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 101448 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 101449 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 101450 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 101451 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 101452 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 101453 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
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| 101454 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
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| 101455 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
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| 101456 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 101457 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 101458 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 101459 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 101460 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 101461 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 101462 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 101463 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 101464 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 101465 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 101466 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 101467 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 101468 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0 |
|---|
| 101469 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 101470 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
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| 101471 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1 |
|---|
| 101472 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 101473 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
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| 101474 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2 |
|---|
| 101475 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 101476 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 101477 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3 |
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| 101478 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
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| 101479 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
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| 101480 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0 |
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| 101481 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
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| 101482 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 101483 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1 |
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| 101484 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
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| 101485 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 101486 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2 |
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| 101487 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
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| 101488 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 101489 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3 |
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| 101490 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
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| 101491 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 101492 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST |
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| 101493 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 101494 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 101495 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 101496 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 101497 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 101498 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 101499 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP |
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| 101500 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
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| 101501 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
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| 101502 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
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| 101503 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
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| 101504 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
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| 101505 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
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| 101506 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL |
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| 101507 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
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| 101508 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
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| 101509 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
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| 101510 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
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| 101511 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST |
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| 101512 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 101513 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 101514 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 101515 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 101516 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 101517 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 101518 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP |
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| 101519 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
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| 101520 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
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| 101521 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
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| 101522 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
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| 101523 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
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| 101524 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
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| 101525 | //BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL |
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| 101526 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
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| 101527 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
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| 101528 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
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| 101529 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
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| 101530 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
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| 101531 | #define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
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| 101532 | |
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| 101533 | |
|---|
| 101534 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp |
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| 101535 | //BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID |
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| 101536 | #define BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
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| 101537 | #define BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
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| 101538 | //BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID |
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| 101539 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
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| 101540 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
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| 101541 | //BIF_CFG_DEV0_EPF0_VF4_1_COMMAND |
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| 101542 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
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| 101543 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
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| 101544 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
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| 101545 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
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| 101546 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
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| 101547 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
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| 101548 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
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| 101549 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
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| 101550 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN__SHIFT 0x8 |
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| 101551 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
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| 101552 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS__SHIFT 0xa |
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| 101553 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
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| 101554 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
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| 101555 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
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| 101556 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
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| 101557 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
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| 101558 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
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| 101559 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
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| 101560 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING_MASK 0x0080L |
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| 101561 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN_MASK 0x0100L |
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| 101562 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
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| 101563 | #define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS_MASK 0x0400L |
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| 101564 | //BIF_CFG_DEV0_EPF0_VF4_1_STATUS |
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| 101565 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
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| 101566 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS__SHIFT 0x3 |
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| 101567 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST__SHIFT 0x4 |
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| 101568 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
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| 101569 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
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| 101570 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
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| 101571 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
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| 101572 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
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| 101573 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
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| 101574 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
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| 101575 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
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| 101576 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
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| 101577 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
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| 101578 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS_MASK 0x0008L |
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| 101579 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST_MASK 0x0010L |
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| 101580 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_CAP_MASK 0x0020L |
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| 101581 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
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| 101582 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
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| 101583 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
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| 101584 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
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| 101585 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
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| 101586 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
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| 101587 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
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| 101588 | #define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
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| 101589 | //BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID |
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| 101590 | #define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
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| 101591 | #define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
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| 101592 | #define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
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| 101593 | #define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
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| 101594 | //BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE |
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| 101595 | #define BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 101596 | #define BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
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| 101597 | //BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS |
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| 101598 | #define BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
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| 101599 | #define BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
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| 101600 | //BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS |
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| 101601 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 101602 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 101603 | //BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE |
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| 101604 | #define BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 101605 | #define BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
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| 101606 | //BIF_CFG_DEV0_EPF0_VF4_1_LATENCY |
|---|
| 101607 | #define BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
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| 101608 | #define BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 101609 | //BIF_CFG_DEV0_EPF0_VF4_1_HEADER |
|---|
| 101610 | #define 0x0 |
|---|
| 101611 | #define 0x7 |
|---|
| 101612 | #define 0x7FL |
|---|
| 101613 | #define 0x80L |
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| 101614 | //BIF_CFG_DEV0_EPF0_VF4_1_BIST |
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| 101615 | #define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 101616 | #define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 101617 | #define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 101618 | #define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 101619 | #define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT_MASK 0x40L |
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| 101620 | #define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP_MASK 0x80L |
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| 101621 | //BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1 |
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| 101622 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 101623 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 101624 | //BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2 |
|---|
| 101625 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 101626 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 101627 | //BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3 |
|---|
| 101628 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 101629 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 101630 | //BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4 |
|---|
| 101631 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 101632 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 101633 | //BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5 |
|---|
| 101634 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 101635 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 101636 | //BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6 |
|---|
| 101637 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 101638 | #define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 101639 | //BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR |
|---|
| 101640 | #define BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 101641 | #define BIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 101642 | //BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID |
|---|
| 101643 | #define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 101644 | #define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 101645 | #define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 101646 | #define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 101647 | //BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR |
|---|
| 101648 | #define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 101649 | #define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 101650 | //BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR |
|---|
| 101651 | #define BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 101652 | #define BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 101653 | //BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE |
|---|
| 101654 | #define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 101655 | #define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 101656 | //BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN |
|---|
| 101657 | #define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 101658 | #define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 101659 | //BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT |
|---|
| 101660 | #define BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 101661 | #define BIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 101662 | //BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY |
|---|
| 101663 | #define BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 101664 | #define BIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
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| 101665 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST |
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| 101666 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 101667 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 101668 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 101669 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 101670 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP |
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| 101671 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION__SHIFT 0x0 |
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| 101672 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 101673 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 101674 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
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| 101675 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION_MASK 0x000FL |
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| 101676 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
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| 101677 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
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| 101678 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
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| 101679 | //BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP |
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| 101680 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
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| 101681 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
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| 101682 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
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| 101683 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
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| 101684 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
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| 101685 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
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| 101686 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
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| 101687 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
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| 101688 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
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| 101689 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 101690 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 101691 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
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| 101692 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
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| 101693 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
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| 101694 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
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| 101695 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
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| 101696 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
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| 101697 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
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| 101698 | //BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL |
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| 101699 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
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| 101700 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
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| 101701 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
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| 101702 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
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| 101703 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 101704 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 101705 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
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| 101706 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
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| 101707 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
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| 101708 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 101709 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 101710 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
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| 101711 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
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| 101712 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
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| 101713 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
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| 101714 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
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| 101715 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
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| 101716 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
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| 101717 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
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| 101718 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
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| 101719 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
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| 101720 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
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| 101721 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
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| 101722 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
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| 101723 | //BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS |
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| 101724 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
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| 101725 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
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| 101726 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
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| 101727 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 101728 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 101729 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 101730 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
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| 101731 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
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| 101732 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 101733 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
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| 101734 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
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| 101735 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
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| 101736 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
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| 101737 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
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| 101738 | //BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP |
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| 101739 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
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| 101740 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 101741 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 101742 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
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| 101743 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 101744 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
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| 101745 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
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| 101746 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 101747 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
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| 101748 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 101749 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 101750 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
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| 101751 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
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| 101752 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
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| 101753 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
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| 101754 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
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| 101755 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
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| 101756 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
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| 101757 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
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| 101758 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
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| 101759 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
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| 101760 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
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| 101761 | //BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL |
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| 101762 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
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| 101763 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
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| 101764 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
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| 101765 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
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| 101766 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
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| 101767 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
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| 101768 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
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| 101769 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
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| 101770 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
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| 101771 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
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| 101772 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
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| 101773 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
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| 101774 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
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| 101775 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
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| 101776 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
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| 101777 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
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| 101778 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
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| 101779 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 101780 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
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| 101781 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 101782 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 101783 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
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| 101784 | //BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS |
|---|
| 101785 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 101786 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
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| 101787 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
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| 101788 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
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| 101789 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
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| 101790 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
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| 101791 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
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| 101792 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
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| 101793 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
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| 101794 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 101795 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
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| 101796 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
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| 101797 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 101798 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 101799 | //BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2 |
|---|
| 101800 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 101801 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 101802 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 101803 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 101804 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 101805 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 101806 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 101807 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 101808 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 101809 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 101810 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 101811 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 101812 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 101813 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 101814 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 101815 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 101816 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 101817 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 101818 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 101819 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 101820 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 101821 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 101822 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 101823 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 101824 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 101825 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 101826 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 101827 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 101828 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 101829 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 101830 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 101831 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 101832 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 101833 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 101834 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 101835 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
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| 101836 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
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| 101837 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 101838 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 101839 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
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| 101840 | //BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2 |
|---|
| 101841 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
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| 101842 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
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| 101843 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
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| 101844 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
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| 101845 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
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| 101846 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
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| 101847 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 101848 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 101849 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 101850 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
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| 101851 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
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| 101852 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 101853 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 101854 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 101855 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
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| 101856 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
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| 101857 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 101858 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
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| 101859 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 101860 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
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| 101861 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 101862 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 101863 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 101864 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 101865 | //BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2 |
|---|
| 101866 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 101867 | #define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 101868 | //BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2 |
|---|
| 101869 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 101870 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 101871 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 101872 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 101873 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 101874 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 101875 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 101876 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 101877 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 101878 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 101879 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 101880 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 101881 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 101882 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 101883 | //BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2 |
|---|
| 101884 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 101885 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
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| 101886 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 101887 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 101888 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 101889 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 101890 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 101891 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 101892 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 101893 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 101894 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 101895 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 101896 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 101897 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 101898 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 101899 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 101900 | //BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2 |
|---|
| 101901 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 101902 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 101903 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 101904 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 101905 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 101906 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 101907 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 101908 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 101909 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 101910 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 101911 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 101912 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 101913 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 101914 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 101915 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 101916 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 101917 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 101918 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 101919 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 101920 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 101921 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 101922 | #define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 101923 | //BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST |
|---|
| 101924 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 101925 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 101926 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 101927 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 101928 | //BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL |
|---|
| 101929 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 101930 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 101931 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 101932 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 101933 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 101934 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 101935 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 101936 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 101937 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 101938 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 101939 | //BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO |
|---|
| 101940 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 101941 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 101942 | //BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI |
|---|
| 101943 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 101944 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 101945 | //BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA |
|---|
| 101946 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 101947 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 101948 | //BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK |
|---|
| 101949 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 101950 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 101951 | //BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64 |
|---|
| 101952 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 101953 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 101954 | //BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64 |
|---|
| 101955 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 101956 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 101957 | //BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING |
|---|
| 101958 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 101959 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 101960 | //BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64 |
|---|
| 101961 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 101962 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 101963 | //BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST |
|---|
| 101964 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 101965 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 101966 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 101967 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 101968 | //BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL |
|---|
| 101969 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 101970 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 101971 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 101972 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 101973 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 101974 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 101975 | //BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE |
|---|
| 101976 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 101977 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 101978 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 101979 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 101980 | //BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA |
|---|
| 101981 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 101982 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 101983 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 101984 | #define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 101985 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 101986 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 101987 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 101988 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 101989 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 101990 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 101991 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 101992 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 101993 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 101994 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 101995 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 101996 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 101997 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 101998 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 101999 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 102000 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 102001 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 102002 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2 |
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| 102003 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 102004 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
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| 102005 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 102006 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 102007 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 102008 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 102009 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 102010 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 102011 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 102012 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS |
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| 102013 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 102014 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 102015 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 102016 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 102017 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 102018 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 102019 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 102020 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 102021 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 102022 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 102023 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 102024 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 102025 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 102026 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 102027 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 102028 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 102029 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 102030 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 102031 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 102032 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 102033 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 102034 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 102035 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 102036 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 102037 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 102038 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 102039 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 102040 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 102041 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 102042 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 102043 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 102044 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 102045 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK |
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| 102046 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 102047 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 102048 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 102049 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 102050 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 102051 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 102052 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 102053 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 102054 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 102055 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 102056 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 102057 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 102058 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 102059 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 102060 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 102061 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 102062 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 102063 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 102064 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 102065 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 102066 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 102067 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 102068 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 102069 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 102070 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 102071 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 102072 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 102073 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 102074 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 102075 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 102076 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 102077 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 102078 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY |
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| 102079 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 102080 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 102081 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 102082 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 102083 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 102084 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 102085 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 102086 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 102087 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 102088 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 102089 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 102090 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 102091 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 102092 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 102093 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 102094 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 102095 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 102096 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 102097 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 102098 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 102099 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 102100 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 102101 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 102102 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 102103 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 102104 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 102105 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 102106 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 102107 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 102108 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 102109 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 102110 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 102111 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS |
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| 102112 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 102113 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 102114 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 102115 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 102116 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 102117 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 102118 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 102119 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 102120 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 102121 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 102122 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 102123 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 102124 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 102125 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 102126 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 102127 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 102128 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK |
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| 102129 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 102130 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 102131 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 102132 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 102133 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 102134 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 102135 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 102136 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 102137 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 102138 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 102139 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 102140 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
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| 102141 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
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| 102142 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
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| 102143 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
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| 102144 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 102145 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL |
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| 102146 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 102147 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 102148 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 102149 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 102150 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 102151 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 102152 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 102153 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 102154 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 102155 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 102156 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 102157 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 102158 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 102159 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 102160 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 102161 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 102162 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 102163 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 102164 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0 |
|---|
| 102165 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 102166 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 102167 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1 |
|---|
| 102168 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 102169 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 102170 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2 |
|---|
| 102171 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 102172 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 102173 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3 |
|---|
| 102174 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 102175 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 102176 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 102177 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 102178 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 102179 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 102180 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 102181 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 102182 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 102183 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 102184 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 102185 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 102186 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 102187 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 102188 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 102189 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 102190 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 102191 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 102192 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 102193 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 102194 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 102195 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP |
|---|
| 102196 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 102197 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 102198 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 102199 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 102200 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 102201 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 102202 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL |
|---|
| 102203 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 102204 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 102205 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 102206 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 102207 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 102208 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 102209 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 102210 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 102211 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 102212 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 102213 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 102214 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP |
|---|
| 102215 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 102216 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 102217 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 102218 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 102219 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 102220 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 102221 | //BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL |
|---|
| 102222 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 102223 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 102224 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 102225 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 102226 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 102227 | #define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 102228 | |
|---|
| 102229 | |
|---|
| 102230 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp |
|---|
| 102231 | //BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID |
|---|
| 102232 | #define BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 102233 | #define BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 102234 | //BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID |
|---|
| 102235 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 102236 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 102237 | //BIF_CFG_DEV0_EPF0_VF5_1_COMMAND |
|---|
| 102238 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 102239 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 102240 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 102241 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 102242 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 102243 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 102244 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 102245 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 102246 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 102247 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 102248 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 102249 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 102250 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 102251 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 102252 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 102253 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 102254 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 102255 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 102256 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 102257 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 102258 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 102259 | #define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 102260 | //BIF_CFG_DEV0_EPF0_VF5_1_STATUS |
|---|
| 102261 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 102262 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 102263 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 102264 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 102265 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 102266 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 102267 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 102268 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 102269 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 102270 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 102271 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 102272 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 102273 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 102274 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 102275 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 102276 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 102277 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 102278 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 102279 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 102280 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 102281 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 102282 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 102283 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 102284 | #define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 102285 | //BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID |
|---|
| 102286 | #define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 102287 | #define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 102288 | #define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 102289 | #define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 102290 | //BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE |
|---|
| 102291 | #define BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 102292 | #define BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 102293 | //BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS |
|---|
| 102294 | #define BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 102295 | #define BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 102296 | //BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS |
|---|
| 102297 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 102298 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 102299 | //BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE |
|---|
| 102300 | #define BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 102301 | #define BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 102302 | //BIF_CFG_DEV0_EPF0_VF5_1_LATENCY |
|---|
| 102303 | #define BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 102304 | #define BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 102305 | //BIF_CFG_DEV0_EPF0_VF5_1_HEADER |
|---|
| 102306 | #define 0x0 |
|---|
| 102307 | #define 0x7 |
|---|
| 102308 | #define 0x7FL |
|---|
| 102309 | #define 0x80L |
|---|
| 102310 | //BIF_CFG_DEV0_EPF0_VF5_1_BIST |
|---|
| 102311 | #define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 102312 | #define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 102313 | #define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 102314 | #define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 102315 | #define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 102316 | #define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 102317 | //BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1 |
|---|
| 102318 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 102319 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 102320 | //BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2 |
|---|
| 102321 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 102322 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 102323 | //BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3 |
|---|
| 102324 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 102325 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 102326 | //BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4 |
|---|
| 102327 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 102328 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 102329 | //BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5 |
|---|
| 102330 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
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| 102331 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 102332 | //BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6 |
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| 102333 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
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| 102334 | #define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 102335 | //BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR |
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| 102336 | #define BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
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| 102337 | #define BIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
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| 102338 | //BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID |
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| 102339 | #define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
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| 102340 | #define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
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| 102341 | #define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
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| 102342 | #define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
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| 102343 | //BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR |
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| 102344 | #define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
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| 102345 | #define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 102346 | //BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR |
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| 102347 | #define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
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| 102348 | #define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
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| 102349 | //BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE |
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| 102350 | #define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
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| 102351 | #define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
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| 102352 | //BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN |
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| 102353 | #define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
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| 102354 | #define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
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| 102355 | //BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT |
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| 102356 | #define BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
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| 102357 | #define BIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
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| 102358 | //BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY |
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| 102359 | #define BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
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| 102360 | #define BIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
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| 102361 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST |
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| 102362 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 102363 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 102364 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 102365 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 102366 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP |
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| 102367 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION__SHIFT 0x0 |
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| 102368 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 102369 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 102370 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
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| 102371 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION_MASK 0x000FL |
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| 102372 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
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| 102373 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
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| 102374 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
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| 102375 | //BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP |
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| 102376 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
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| 102377 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
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| 102378 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
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| 102379 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
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| 102380 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
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| 102381 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
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| 102382 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
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| 102383 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
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| 102384 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
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| 102385 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 102386 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 102387 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
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| 102388 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
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| 102389 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
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| 102390 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
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| 102391 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
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| 102392 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
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| 102393 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
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| 102394 | //BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL |
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| 102395 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
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| 102396 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
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| 102397 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
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| 102398 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
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| 102399 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 102400 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 102401 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
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| 102402 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
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| 102403 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
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| 102404 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 102405 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 102406 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
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| 102407 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
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| 102408 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
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| 102409 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
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| 102410 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
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| 102411 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
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| 102412 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
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| 102413 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
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| 102414 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
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| 102415 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
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| 102416 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
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| 102417 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
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| 102418 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
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| 102419 | //BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS |
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| 102420 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
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| 102421 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
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| 102422 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
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| 102423 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 102424 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 102425 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 102426 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
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| 102427 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
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| 102428 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 102429 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
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| 102430 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
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| 102431 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
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| 102432 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
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| 102433 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
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| 102434 | //BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP |
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| 102435 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
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| 102436 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 102437 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 102438 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
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| 102439 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 102440 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
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| 102441 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
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| 102442 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 102443 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
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| 102444 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 102445 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 102446 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
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| 102447 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
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| 102448 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
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| 102449 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
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| 102450 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 102451 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
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| 102452 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 102453 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 102454 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 102455 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 102456 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
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| 102457 | //BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL |
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| 102458 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 102459 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 102460 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
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| 102461 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
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| 102462 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
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| 102463 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
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| 102464 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 102465 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
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| 102466 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 102467 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 102468 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
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| 102469 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
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| 102470 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 102471 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 102472 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 102473 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 102474 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 102475 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 102476 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 102477 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 102478 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 102479 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 102480 | //BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS |
|---|
| 102481 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 102482 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 102483 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 102484 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 102485 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 102486 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 102487 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 102488 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 102489 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 102490 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 102491 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 102492 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
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| 102493 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 102494 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 102495 | //BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2 |
|---|
| 102496 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 102497 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 102498 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 102499 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 102500 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 102501 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 102502 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 102503 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 102504 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 102505 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 102506 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 102507 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 102508 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 102509 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 102510 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 102511 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 102512 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 102513 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 102514 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 102515 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 102516 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 102517 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 102518 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 102519 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 102520 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 102521 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 102522 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 102523 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 102524 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 102525 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 102526 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 102527 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 102528 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 102529 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 102530 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 102531 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 102532 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 102533 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 102534 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 102535 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 102536 | //BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2 |
|---|
| 102537 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 102538 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 102539 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 102540 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 102541 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 102542 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 102543 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 102544 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 102545 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 102546 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 102547 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 102548 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 102549 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 102550 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 102551 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 102552 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 102553 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 102554 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 102555 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 102556 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 102557 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 102558 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 102559 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 102560 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 102561 | //BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2 |
|---|
| 102562 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 102563 | #define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 102564 | //BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2 |
|---|
| 102565 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 102566 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 102567 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 102568 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 102569 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 102570 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 102571 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 102572 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 102573 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 102574 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 102575 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 102576 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 102577 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 102578 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 102579 | //BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2 |
|---|
| 102580 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 102581 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 102582 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 102583 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 102584 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 102585 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 102586 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 102587 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 102588 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 102589 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 102590 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 102591 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 102592 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 102593 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 102594 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 102595 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 102596 | //BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2 |
|---|
| 102597 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 102598 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 102599 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 102600 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 102601 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 102602 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 102603 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 102604 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 102605 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 102606 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 102607 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 102608 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 102609 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 102610 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 102611 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 102612 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 102613 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 102614 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 102615 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 102616 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 102617 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 102618 | #define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 102619 | //BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST |
|---|
| 102620 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 102621 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 102622 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 102623 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 102624 | //BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL |
|---|
| 102625 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 102626 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 102627 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 102628 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 102629 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 102630 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 102631 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 102632 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 102633 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 102634 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 102635 | //BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO |
|---|
| 102636 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 102637 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 102638 | //BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI |
|---|
| 102639 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 102640 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 102641 | //BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA |
|---|
| 102642 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 102643 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 102644 | //BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK |
|---|
| 102645 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 102646 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 102647 | //BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64 |
|---|
| 102648 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 102649 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 102650 | //BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64 |
|---|
| 102651 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 102652 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 102653 | //BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING |
|---|
| 102654 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 102655 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 102656 | //BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64 |
|---|
| 102657 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 102658 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 102659 | //BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST |
|---|
| 102660 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 102661 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 102662 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 102663 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 102664 | //BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL |
|---|
| 102665 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 102666 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 102667 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 102668 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 102669 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 102670 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 102671 | //BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE |
|---|
| 102672 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 102673 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 102674 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 102675 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 102676 | //BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA |
|---|
| 102677 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 102678 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 102679 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 102680 | #define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 102681 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 102682 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 102683 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 102684 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 102685 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 102686 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 102687 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 102688 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 102689 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 102690 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 102691 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 102692 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 102693 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 102694 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 102695 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 102696 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 102697 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 102698 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 102699 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 102700 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 102701 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 102702 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 102703 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 102704 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 102705 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 102706 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 102707 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 102708 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 102709 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 102710 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 102711 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 102712 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 102713 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 102714 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 102715 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 102716 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 102717 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 102718 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 102719 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 102720 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 102721 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 102722 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 102723 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 102724 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 102725 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 102726 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 102727 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 102728 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 102729 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 102730 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 102731 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 102732 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 102733 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 102734 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 102735 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 102736 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 102737 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 102738 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 102739 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 102740 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 102741 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK |
|---|
| 102742 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 102743 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 102744 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 102745 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 102746 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 102747 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 102748 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 102749 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 102750 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 102751 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 102752 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 102753 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 102754 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 102755 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 102756 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 102757 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 102758 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 102759 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 102760 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 102761 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 102762 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 102763 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 102764 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 102765 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 102766 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 102767 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 102768 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 102769 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 102770 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 102771 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 102772 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 102773 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 102774 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 102775 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 102776 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 102777 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 102778 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 102779 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 102780 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 102781 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 102782 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 102783 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 102784 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 102785 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 102786 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 102787 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 102788 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 102789 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 102790 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 102791 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 102792 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 102793 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 102794 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 102795 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 102796 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 102797 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 102798 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 102799 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 102800 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 102801 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 102802 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 102803 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 102804 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 102805 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 102806 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 102807 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS |
|---|
| 102808 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 102809 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 102810 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 102811 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 102812 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 102813 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 102814 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 102815 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 102816 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 102817 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 102818 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 102819 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 102820 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 102821 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 102822 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 102823 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 102824 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK |
|---|
| 102825 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 102826 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 102827 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 102828 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 102829 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 102830 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 102831 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 102832 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 102833 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 102834 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 102835 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 102836 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 102837 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 102838 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 102839 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 102840 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 102841 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 102842 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 102843 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 102844 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 102845 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 102846 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 102847 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 102848 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 102849 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 102850 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 102851 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 102852 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 102853 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 102854 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 102855 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 102856 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 102857 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 102858 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 102859 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 102860 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0 |
|---|
| 102861 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 102862 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 102863 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1 |
|---|
| 102864 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 102865 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 102866 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2 |
|---|
| 102867 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 102868 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 102869 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3 |
|---|
| 102870 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 102871 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 102872 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 102873 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 102874 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 102875 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 102876 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 102877 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 102878 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 102879 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 102880 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 102881 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 102882 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 102883 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 102884 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 102885 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 102886 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 102887 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 102888 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 102889 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 102890 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 102891 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP |
|---|
| 102892 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 102893 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 102894 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 102895 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 102896 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 102897 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 102898 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL |
|---|
| 102899 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 102900 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 102901 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 102902 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 102903 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 102904 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 102905 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 102906 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 102907 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 102908 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 102909 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 102910 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP |
|---|
| 102911 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 102912 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 102913 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 102914 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 102915 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 102916 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 102917 | //BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL |
|---|
| 102918 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 102919 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 102920 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 102921 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 102922 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 102923 | #define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 102924 | |
|---|
| 102925 | |
|---|
| 102926 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp |
|---|
| 102927 | //BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID |
|---|
| 102928 | #define BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 102929 | #define BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 102930 | //BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID |
|---|
| 102931 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 102932 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 102933 | //BIF_CFG_DEV0_EPF0_VF6_1_COMMAND |
|---|
| 102934 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 102935 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 102936 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 102937 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 102938 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 102939 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 102940 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 102941 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 102942 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 102943 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 102944 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 102945 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 102946 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 102947 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 102948 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 102949 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 102950 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 102951 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 102952 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 102953 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 102954 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 102955 | #define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 102956 | //BIF_CFG_DEV0_EPF0_VF6_1_STATUS |
|---|
| 102957 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 102958 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 102959 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 102960 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 102961 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 102962 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 102963 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 102964 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 102965 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 102966 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 102967 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 102968 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 102969 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 102970 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 102971 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 102972 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 102973 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 102974 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 102975 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 102976 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 102977 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 102978 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 102979 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 102980 | #define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 102981 | //BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID |
|---|
| 102982 | #define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 102983 | #define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 102984 | #define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 102985 | #define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 102986 | //BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE |
|---|
| 102987 | #define BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 102988 | #define BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 102989 | //BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS |
|---|
| 102990 | #define BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 102991 | #define BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 102992 | //BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS |
|---|
| 102993 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 102994 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 102995 | //BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE |
|---|
| 102996 | #define BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 102997 | #define BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 102998 | //BIF_CFG_DEV0_EPF0_VF6_1_LATENCY |
|---|
| 102999 | #define BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 103000 | #define BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 103001 | //BIF_CFG_DEV0_EPF0_VF6_1_HEADER |
|---|
| 103002 | #define 0x0 |
|---|
| 103003 | #define 0x7 |
|---|
| 103004 | #define 0x7FL |
|---|
| 103005 | #define 0x80L |
|---|
| 103006 | //BIF_CFG_DEV0_EPF0_VF6_1_BIST |
|---|
| 103007 | #define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 103008 | #define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 103009 | #define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 103010 | #define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 103011 | #define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 103012 | #define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 103013 | //BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1 |
|---|
| 103014 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 103015 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103016 | //BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2 |
|---|
| 103017 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 103018 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103019 | //BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3 |
|---|
| 103020 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 103021 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103022 | //BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4 |
|---|
| 103023 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 103024 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103025 | //BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5 |
|---|
| 103026 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 103027 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103028 | //BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6 |
|---|
| 103029 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 103030 | #define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103031 | //BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR |
|---|
| 103032 | #define BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 103033 | #define BIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 103034 | //BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID |
|---|
| 103035 | #define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 103036 | #define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 103037 | #define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 103038 | #define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 103039 | //BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR |
|---|
| 103040 | #define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 103041 | #define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103042 | //BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR |
|---|
| 103043 | #define BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 103044 | #define BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 103045 | //BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE |
|---|
| 103046 | #define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 103047 | #define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 103048 | //BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN |
|---|
| 103049 | #define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 103050 | #define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 103051 | //BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT |
|---|
| 103052 | #define BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 103053 | #define BIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 103054 | //BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY |
|---|
| 103055 | #define BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 103056 | #define BIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 103057 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST |
|---|
| 103058 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 103059 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 103060 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 103061 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 103062 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP |
|---|
| 103063 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 103064 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 103065 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 103066 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 103067 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 103068 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 103069 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 103070 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 103071 | //BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP |
|---|
| 103072 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 103073 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 103074 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 103075 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 103076 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 103077 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 103078 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 103079 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 103080 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 103081 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 103082 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 103083 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 103084 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 103085 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 103086 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 103087 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 103088 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 103089 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 103090 | //BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL |
|---|
| 103091 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 103092 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 103093 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 103094 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 103095 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 103096 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 103097 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 103098 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 103099 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 103100 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 103101 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 103102 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 103103 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 103104 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 103105 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 103106 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 103107 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 103108 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 103109 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 103110 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 103111 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 103112 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 103113 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 103114 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 103115 | //BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS |
|---|
| 103116 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 103117 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 103118 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 103119 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 103120 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 103121 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 103122 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 103123 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 103124 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 103125 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 103126 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 103127 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 103128 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 103129 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 103130 | //BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP |
|---|
| 103131 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 103132 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 103133 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 103134 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 103135 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 103136 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 103137 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 103138 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 103139 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 103140 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 103141 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 103142 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 103143 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 103144 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 103145 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 103146 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 103147 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 103148 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 103149 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 103150 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 103151 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 103152 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 103153 | //BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL |
|---|
| 103154 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 103155 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 103156 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 103157 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 103158 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 103159 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 103160 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 103161 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 103162 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 103163 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 103164 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 103165 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 103166 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 103167 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 103168 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 103169 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 103170 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 103171 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 103172 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 103173 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 103174 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 103175 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 103176 | //BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS |
|---|
| 103177 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 103178 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 103179 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 103180 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 103181 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 103182 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 103183 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 103184 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 103185 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 103186 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 103187 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 103188 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 103189 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 103190 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 103191 | //BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2 |
|---|
| 103192 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 103193 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 103194 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 103195 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 103196 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 103197 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 103198 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 103199 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 103200 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 103201 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 103202 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 103203 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 103204 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 103205 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 103206 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 103207 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 103208 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 103209 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 103210 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 103211 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 103212 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 103213 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 103214 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 103215 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 103216 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 103217 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 103218 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 103219 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 103220 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 103221 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 103222 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 103223 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 103224 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 103225 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 103226 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 103227 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 103228 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 103229 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 103230 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 103231 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 103232 | //BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2 |
|---|
| 103233 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 103234 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 103235 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 103236 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 103237 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 103238 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 103239 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 103240 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 103241 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 103242 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 103243 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 103244 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 103245 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 103246 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 103247 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 103248 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 103249 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 103250 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 103251 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 103252 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 103253 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 103254 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 103255 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 103256 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 103257 | //BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2 |
|---|
| 103258 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 103259 | #define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 103260 | //BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2 |
|---|
| 103261 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 103262 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 103263 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 103264 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 103265 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 103266 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 103267 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 103268 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 103269 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 103270 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 103271 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 103272 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 103273 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 103274 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 103275 | //BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2 |
|---|
| 103276 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 103277 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 103278 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 103279 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 103280 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 103281 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 103282 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 103283 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 103284 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 103285 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 103286 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 103287 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 103288 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 103289 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 103290 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 103291 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 103292 | //BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2 |
|---|
| 103293 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 103294 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 103295 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 103296 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 103297 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 103298 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 103299 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 103300 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 103301 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 103302 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 103303 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 103304 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 103305 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 103306 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 103307 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 103308 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 103309 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 103310 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 103311 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 103312 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 103313 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 103314 | #define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 103315 | //BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST |
|---|
| 103316 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 103317 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 103318 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 103319 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 103320 | //BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL |
|---|
| 103321 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 103322 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 103323 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 103324 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 103325 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 103326 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 103327 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 103328 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 103329 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 103330 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 103331 | //BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO |
|---|
| 103332 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 103333 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 103334 | //BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI |
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| 103335 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 103336 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 103337 | //BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA |
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| 103338 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 103339 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 103340 | //BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK |
|---|
| 103341 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 103342 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 103343 | //BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64 |
|---|
| 103344 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
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| 103345 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 103346 | //BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64 |
|---|
| 103347 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 103348 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 103349 | //BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING |
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| 103350 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
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| 103351 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 103352 | //BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64 |
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| 103353 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
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| 103354 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
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| 103355 | //BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST |
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| 103356 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 103357 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 103358 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 103359 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 103360 | //BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL |
|---|
| 103361 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 103362 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 103363 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 103364 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 103365 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 103366 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 103367 | //BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE |
|---|
| 103368 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 103369 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 103370 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 103371 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 103372 | //BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA |
|---|
| 103373 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 103374 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 103375 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 103376 | #define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 103377 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 103378 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 103379 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 103380 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 103381 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 103382 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 103383 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 103384 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 103385 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 103386 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 103387 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 103388 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 103389 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 103390 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 103391 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 103392 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 103393 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 103394 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 103395 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 103396 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 103397 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 103398 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 103399 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 103400 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 103401 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 103402 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 103403 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 103404 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 103405 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 103406 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 103407 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 103408 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 103409 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 103410 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 103411 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 103412 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 103413 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 103414 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 103415 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 103416 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 103417 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 103418 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 103419 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 103420 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 103421 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 103422 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 103423 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 103424 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 103425 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 103426 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 103427 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 103428 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 103429 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 103430 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 103431 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 103432 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 103433 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 103434 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 103435 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 103436 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 103437 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK |
|---|
| 103438 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 103439 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 103440 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 103441 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 103442 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 103443 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 103444 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 103445 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 103446 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 103447 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 103448 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 103449 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 103450 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 103451 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 103452 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 103453 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 103454 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 103455 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 103456 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 103457 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 103458 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 103459 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 103460 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 103461 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 103462 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 103463 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 103464 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 103465 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 103466 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 103467 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 103468 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 103469 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 103470 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 103471 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 103472 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 103473 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 103474 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 103475 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 103476 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 103477 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 103478 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 103479 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 103480 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 103481 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 103482 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 103483 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 103484 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 103485 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 103486 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 103487 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 103488 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 103489 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 103490 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 103491 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 103492 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 103493 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 103494 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 103495 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 103496 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 103497 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 103498 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 103499 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 103500 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 103501 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 103502 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 103503 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS |
|---|
| 103504 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 103505 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 103506 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 103507 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 103508 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 103509 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 103510 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 103511 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 103512 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 103513 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 103514 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 103515 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 103516 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 103517 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 103518 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 103519 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 103520 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK |
|---|
| 103521 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 103522 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 103523 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 103524 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 103525 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 103526 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 103527 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 103528 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 103529 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 103530 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 103531 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 103532 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 103533 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 103534 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 103535 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 103536 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 103537 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 103538 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 103539 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 103540 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 103541 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 103542 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 103543 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 103544 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 103545 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 103546 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 103547 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 103548 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 103549 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 103550 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 103551 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 103552 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 103553 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 103554 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 103555 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 103556 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0 |
|---|
| 103557 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 103558 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 103559 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1 |
|---|
| 103560 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 103561 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 103562 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2 |
|---|
| 103563 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 103564 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 103565 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3 |
|---|
| 103566 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 103567 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 103568 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 103569 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 103570 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 103571 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 103572 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 103573 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 103574 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 103575 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 103576 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 103577 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 103578 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 103579 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 103580 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 103581 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 103582 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 103583 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 103584 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 103585 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 103586 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 103587 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP |
|---|
| 103588 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 103589 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 103590 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 103591 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 103592 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 103593 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 103594 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL |
|---|
| 103595 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 103596 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 103597 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 103598 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 103599 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 103600 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 103601 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 103602 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 103603 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 103604 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 103605 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 103606 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP |
|---|
| 103607 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 103608 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 103609 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 103610 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 103611 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 103612 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 103613 | //BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL |
|---|
| 103614 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 103615 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 103616 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 103617 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 103618 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 103619 | #define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 103620 | |
|---|
| 103621 | |
|---|
| 103622 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp |
|---|
| 103623 | //BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID |
|---|
| 103624 | #define BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 103625 | #define BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 103626 | //BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID |
|---|
| 103627 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 103628 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 103629 | //BIF_CFG_DEV0_EPF0_VF7_1_COMMAND |
|---|
| 103630 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 103631 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 103632 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 103633 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 103634 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 103635 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 103636 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 103637 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 103638 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 103639 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 103640 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 103641 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 103642 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 103643 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 103644 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 103645 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 103646 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 103647 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 103648 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 103649 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 103650 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 103651 | #define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 103652 | //BIF_CFG_DEV0_EPF0_VF7_1_STATUS |
|---|
| 103653 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 103654 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 103655 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 103656 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 103657 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 103658 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 103659 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 103660 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 103661 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 103662 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 103663 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 103664 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 103665 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 103666 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 103667 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 103668 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 103669 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 103670 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 103671 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 103672 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 103673 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 103674 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 103675 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 103676 | #define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 103677 | //BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID |
|---|
| 103678 | #define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 103679 | #define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 103680 | #define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 103681 | #define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 103682 | //BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE |
|---|
| 103683 | #define BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 103684 | #define BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 103685 | //BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS |
|---|
| 103686 | #define BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 103687 | #define BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 103688 | //BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS |
|---|
| 103689 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 103690 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 103691 | //BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE |
|---|
| 103692 | #define BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 103693 | #define BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 103694 | //BIF_CFG_DEV0_EPF0_VF7_1_LATENCY |
|---|
| 103695 | #define BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 103696 | #define BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 103697 | //BIF_CFG_DEV0_EPF0_VF7_1_HEADER |
|---|
| 103698 | #define 0x0 |
|---|
| 103699 | #define 0x7 |
|---|
| 103700 | #define 0x7FL |
|---|
| 103701 | #define 0x80L |
|---|
| 103702 | //BIF_CFG_DEV0_EPF0_VF7_1_BIST |
|---|
| 103703 | #define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 103704 | #define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 103705 | #define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 103706 | #define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 103707 | #define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 103708 | #define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 103709 | //BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1 |
|---|
| 103710 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 103711 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103712 | //BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2 |
|---|
| 103713 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 103714 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103715 | //BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3 |
|---|
| 103716 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 103717 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103718 | //BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4 |
|---|
| 103719 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 103720 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103721 | //BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5 |
|---|
| 103722 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 103723 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103724 | //BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6 |
|---|
| 103725 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 103726 | #define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103727 | //BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR |
|---|
| 103728 | #define BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 103729 | #define BIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 103730 | //BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID |
|---|
| 103731 | #define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 103732 | #define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 103733 | #define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 103734 | #define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 103735 | //BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR |
|---|
| 103736 | #define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 103737 | #define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 103738 | //BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR |
|---|
| 103739 | #define BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 103740 | #define BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 103741 | //BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE |
|---|
| 103742 | #define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 103743 | #define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 103744 | //BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN |
|---|
| 103745 | #define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 103746 | #define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 103747 | //BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT |
|---|
| 103748 | #define BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 103749 | #define BIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 103750 | //BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY |
|---|
| 103751 | #define BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 103752 | #define BIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 103753 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST |
|---|
| 103754 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 103755 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 103756 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 103757 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 103758 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP |
|---|
| 103759 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 103760 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 103761 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 103762 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 103763 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 103764 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 103765 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 103766 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 103767 | //BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP |
|---|
| 103768 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 103769 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 103770 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 103771 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 103772 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 103773 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 103774 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 103775 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 103776 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 103777 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 103778 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 103779 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 103780 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 103781 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 103782 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 103783 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 103784 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 103785 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 103786 | //BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL |
|---|
| 103787 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 103788 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 103789 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 103790 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 103791 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 103792 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 103793 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 103794 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 103795 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 103796 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 103797 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 103798 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 103799 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 103800 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 103801 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 103802 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 103803 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 103804 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 103805 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 103806 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 103807 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 103808 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 103809 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 103810 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 103811 | //BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS |
|---|
| 103812 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 103813 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 103814 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 103815 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 103816 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 103817 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 103818 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 103819 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 103820 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 103821 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 103822 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 103823 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 103824 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 103825 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 103826 | //BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP |
|---|
| 103827 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 103828 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 103829 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 103830 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 103831 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 103832 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 103833 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 103834 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 103835 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 103836 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 103837 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 103838 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 103839 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 103840 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 103841 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 103842 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 103843 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 103844 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 103845 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 103846 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 103847 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 103848 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 103849 | //BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL |
|---|
| 103850 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 103851 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 103852 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 103853 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 103854 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 103855 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 103856 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 103857 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 103858 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 103859 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 103860 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 103861 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 103862 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 103863 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 103864 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 103865 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 103866 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 103867 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 103868 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 103869 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 103870 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 103871 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 103872 | //BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS |
|---|
| 103873 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 103874 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 103875 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 103876 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 103877 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 103878 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 103879 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 103880 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 103881 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 103882 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 103883 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 103884 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 103885 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 103886 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 103887 | //BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2 |
|---|
| 103888 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 103889 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 103890 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 103891 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 103892 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 103893 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 103894 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 103895 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 103896 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 103897 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 103898 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 103899 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 103900 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 103901 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 103902 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 103903 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 103904 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 103905 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 103906 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 103907 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 103908 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 103909 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 103910 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 103911 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 103912 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 103913 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 103914 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 103915 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 103916 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 103917 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 103918 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 103919 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 103920 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 103921 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 103922 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 103923 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 103924 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 103925 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 103926 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 103927 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 103928 | //BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2 |
|---|
| 103929 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 103930 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 103931 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 103932 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 103933 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 103934 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 103935 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 103936 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 103937 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 103938 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 103939 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 103940 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 103941 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 103942 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 103943 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 103944 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 103945 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 103946 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 103947 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 103948 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 103949 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 103950 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 103951 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 103952 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 103953 | //BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2 |
|---|
| 103954 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 103955 | #define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 103956 | //BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2 |
|---|
| 103957 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 103958 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 103959 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 103960 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 103961 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 103962 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 103963 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 103964 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 103965 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 103966 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 103967 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 103968 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 103969 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 103970 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 103971 | //BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2 |
|---|
| 103972 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 103973 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 103974 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 103975 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 103976 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 103977 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 103978 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 103979 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 103980 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 103981 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 103982 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 103983 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 103984 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 103985 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 103986 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 103987 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 103988 | //BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2 |
|---|
| 103989 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 103990 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 103991 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 103992 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 103993 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 103994 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 103995 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 103996 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 103997 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 103998 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 103999 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 104000 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 104001 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 104002 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 104003 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 104004 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 104005 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 104006 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 104007 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 104008 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 104009 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 104010 | #define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 104011 | //BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST |
|---|
| 104012 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104013 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 104014 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 104015 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 104016 | //BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL |
|---|
| 104017 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 104018 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 104019 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 104020 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 104021 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 104022 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 104023 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 104024 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 104025 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 104026 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 104027 | //BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO |
|---|
| 104028 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 104029 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 104030 | //BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI |
|---|
| 104031 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 104032 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 104033 | //BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA |
|---|
| 104034 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 104035 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 104036 | //BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK |
|---|
| 104037 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 104038 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 104039 | //BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64 |
|---|
| 104040 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 104041 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 104042 | //BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64 |
|---|
| 104043 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 104044 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 104045 | //BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING |
|---|
| 104046 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 104047 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 104048 | //BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64 |
|---|
| 104049 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 104050 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 104051 | //BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST |
|---|
| 104052 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104053 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 104054 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 104055 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 104056 | //BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL |
|---|
| 104057 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 104058 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 104059 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 104060 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 104061 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 104062 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 104063 | //BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE |
|---|
| 104064 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 104065 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 104066 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 104067 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 104068 | //BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA |
|---|
| 104069 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 104070 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 104071 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 104072 | #define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 104073 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 104074 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104075 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 104076 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 104077 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 104078 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 104079 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 104080 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 104081 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 104082 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 104083 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 104084 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 104085 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 104086 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 104087 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 104088 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 104089 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 104090 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 104091 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 104092 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 104093 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 104094 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104095 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 104096 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 104097 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 104098 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 104099 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 104100 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 104101 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 104102 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 104103 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 104104 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 104105 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 104106 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 104107 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 104108 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 104109 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 104110 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 104111 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 104112 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 104113 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 104114 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 104115 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 104116 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 104117 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 104118 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 104119 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 104120 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 104121 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 104122 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 104123 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 104124 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 104125 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 104126 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 104127 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 104128 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 104129 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 104130 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 104131 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 104132 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 104133 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK |
|---|
| 104134 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 104135 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 104136 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 104137 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 104138 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 104139 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 104140 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 104141 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 104142 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 104143 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 104144 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 104145 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 104146 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 104147 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 104148 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 104149 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 104150 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 104151 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 104152 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 104153 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 104154 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 104155 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 104156 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 104157 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 104158 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 104159 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 104160 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 104161 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 104162 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 104163 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 104164 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 104165 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 104166 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 104167 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 104168 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 104169 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 104170 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 104171 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 104172 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 104173 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 104174 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 104175 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 104176 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 104177 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 104178 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 104179 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 104180 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 104181 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 104182 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 104183 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 104184 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 104185 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 104186 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 104187 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 104188 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 104189 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 104190 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 104191 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 104192 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 104193 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 104194 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 104195 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 104196 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 104197 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 104198 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 104199 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS |
|---|
| 104200 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 104201 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 104202 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 104203 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 104204 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 104205 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 104206 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 104207 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 104208 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 104209 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 104210 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 104211 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 104212 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 104213 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 104214 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 104215 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 104216 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK |
|---|
| 104217 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 104218 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 104219 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 104220 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 104221 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 104222 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 104223 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 104224 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 104225 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 104226 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 104227 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 104228 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 104229 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 104230 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 104231 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 104232 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 104233 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 104234 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 104235 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 104236 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 104237 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 104238 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 104239 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 104240 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 104241 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 104242 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 104243 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 104244 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 104245 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 104246 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 104247 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 104248 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 104249 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 104250 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 104251 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 104252 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0 |
|---|
| 104253 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 104254 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 104255 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1 |
|---|
| 104256 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 104257 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 104258 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2 |
|---|
| 104259 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 104260 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 104261 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3 |
|---|
| 104262 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 104263 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 104264 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 104265 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 104266 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 104267 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 104268 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 104269 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 104270 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 104271 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 104272 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 104273 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 104274 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 104275 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 104276 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 104277 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104278 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 104279 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 104280 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 104281 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 104282 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 104283 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP |
|---|
| 104284 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 104285 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 104286 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 104287 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 104288 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 104289 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 104290 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL |
|---|
| 104291 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 104292 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 104293 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 104294 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 104295 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 104296 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104297 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 104298 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 104299 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 104300 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 104301 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 104302 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP |
|---|
| 104303 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 104304 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 104305 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 104306 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 104307 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 104308 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 104309 | //BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL |
|---|
| 104310 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 104311 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 104312 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 104313 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 104314 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 104315 | #define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 104316 | |
|---|
| 104317 | |
|---|
| 104318 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp |
|---|
| 104319 | //BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID |
|---|
| 104320 | #define BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 104321 | #define BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 104322 | //BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID |
|---|
| 104323 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 104324 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 104325 | //BIF_CFG_DEV0_EPF0_VF8_1_COMMAND |
|---|
| 104326 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 104327 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 104328 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 104329 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 104330 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 104331 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 104332 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 104333 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 104334 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 104335 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 104336 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 104337 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 104338 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 104339 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 104340 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 104341 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 104342 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 104343 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 104344 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 104345 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 104346 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 104347 | #define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 104348 | //BIF_CFG_DEV0_EPF0_VF8_1_STATUS |
|---|
| 104349 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 104350 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 104351 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 104352 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 104353 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 104354 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 104355 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 104356 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 104357 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 104358 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 104359 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 104360 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 104361 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 104362 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 104363 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 104364 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 104365 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 104366 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 104367 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 104368 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 104369 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 104370 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 104371 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 104372 | #define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 104373 | //BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID |
|---|
| 104374 | #define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 104375 | #define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 104376 | #define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 104377 | #define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 104378 | //BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE |
|---|
| 104379 | #define BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 104380 | #define BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 104381 | //BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS |
|---|
| 104382 | #define BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 104383 | #define BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 104384 | //BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS |
|---|
| 104385 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 104386 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 104387 | //BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE |
|---|
| 104388 | #define BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 104389 | #define BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 104390 | //BIF_CFG_DEV0_EPF0_VF8_1_LATENCY |
|---|
| 104391 | #define BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 104392 | #define BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 104393 | //BIF_CFG_DEV0_EPF0_VF8_1_HEADER |
|---|
| 104394 | #define 0x0 |
|---|
| 104395 | #define 0x7 |
|---|
| 104396 | #define 0x7FL |
|---|
| 104397 | #define 0x80L |
|---|
| 104398 | //BIF_CFG_DEV0_EPF0_VF8_1_BIST |
|---|
| 104399 | #define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 104400 | #define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 104401 | #define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 104402 | #define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 104403 | #define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 104404 | #define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 104405 | //BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1 |
|---|
| 104406 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 104407 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 104408 | //BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2 |
|---|
| 104409 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 104410 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 104411 | //BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3 |
|---|
| 104412 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 104413 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 104414 | //BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4 |
|---|
| 104415 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 104416 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 104417 | //BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5 |
|---|
| 104418 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 104419 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 104420 | //BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6 |
|---|
| 104421 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 104422 | #define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 104423 | //BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR |
|---|
| 104424 | #define BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 104425 | #define BIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 104426 | //BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID |
|---|
| 104427 | #define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 104428 | #define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 104429 | #define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 104430 | #define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 104431 | //BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR |
|---|
| 104432 | #define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 104433 | #define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 104434 | //BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR |
|---|
| 104435 | #define BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 104436 | #define BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 104437 | //BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE |
|---|
| 104438 | #define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 104439 | #define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 104440 | //BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN |
|---|
| 104441 | #define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 104442 | #define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 104443 | //BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT |
|---|
| 104444 | #define BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 104445 | #define BIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 104446 | //BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY |
|---|
| 104447 | #define BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 104448 | #define BIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 104449 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST |
|---|
| 104450 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104451 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 104452 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 104453 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 104454 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP |
|---|
| 104455 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 104456 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 104457 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 104458 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 104459 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 104460 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 104461 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 104462 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 104463 | //BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP |
|---|
| 104464 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 104465 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 104466 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 104467 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 104468 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 104469 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 104470 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 104471 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 104472 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 104473 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 104474 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 104475 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 104476 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 104477 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 104478 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 104479 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 104480 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 104481 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 104482 | //BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL |
|---|
| 104483 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 104484 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 104485 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 104486 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 104487 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 104488 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 104489 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 104490 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 104491 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 104492 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 104493 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 104494 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 104495 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 104496 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 104497 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 104498 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 104499 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 104500 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 104501 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 104502 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 104503 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 104504 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 104505 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 104506 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 104507 | //BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS |
|---|
| 104508 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 104509 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 104510 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 104511 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 104512 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 104513 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 104514 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 104515 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 104516 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 104517 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 104518 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 104519 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 104520 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 104521 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 104522 | //BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP |
|---|
| 104523 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 104524 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 104525 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 104526 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 104527 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 104528 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 104529 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 104530 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 104531 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 104532 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 104533 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 104534 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 104535 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 104536 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 104537 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 104538 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 104539 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 104540 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 104541 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 104542 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 104543 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 104544 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 104545 | //BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL |
|---|
| 104546 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 104547 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 104548 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 104549 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 104550 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 104551 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 104552 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 104553 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 104554 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 104555 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 104556 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 104557 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 104558 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 104559 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 104560 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 104561 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 104562 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 104563 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 104564 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 104565 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 104566 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 104567 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 104568 | //BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS |
|---|
| 104569 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 104570 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 104571 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 104572 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 104573 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 104574 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 104575 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 104576 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 104577 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 104578 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 104579 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 104580 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 104581 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 104582 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 104583 | //BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2 |
|---|
| 104584 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 104585 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 104586 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 104587 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 104588 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 104589 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 104590 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 104591 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 104592 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 104593 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 104594 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 104595 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 104596 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 104597 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 104598 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 104599 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 104600 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 104601 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 104602 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 104603 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 104604 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 104605 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 104606 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 104607 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 104608 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 104609 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 104610 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 104611 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 104612 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 104613 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 104614 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 104615 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 104616 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 104617 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 104618 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 104619 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 104620 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 104621 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 104622 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 104623 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 104624 | //BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2 |
|---|
| 104625 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 104626 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 104627 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 104628 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 104629 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 104630 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 104631 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 104632 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 104633 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 104634 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 104635 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 104636 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 104637 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 104638 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 104639 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 104640 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 104641 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 104642 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 104643 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 104644 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 104645 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 104646 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 104647 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 104648 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 104649 | //BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2 |
|---|
| 104650 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 104651 | #define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 104652 | //BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2 |
|---|
| 104653 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 104654 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 104655 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 104656 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 104657 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 104658 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 104659 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 104660 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 104661 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 104662 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 104663 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 104664 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 104665 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 104666 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 104667 | //BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2 |
|---|
| 104668 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 104669 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 104670 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 104671 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 104672 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 104673 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 104674 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 104675 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 104676 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 104677 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 104678 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 104679 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 104680 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 104681 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 104682 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 104683 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 104684 | //BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2 |
|---|
| 104685 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 104686 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 104687 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 104688 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 104689 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 104690 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 104691 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 104692 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 104693 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 104694 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 104695 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 104696 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 104697 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 104698 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 104699 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 104700 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 104701 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 104702 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 104703 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 104704 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 104705 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 104706 | #define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 104707 | //BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST |
|---|
| 104708 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104709 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 104710 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 104711 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 104712 | //BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL |
|---|
| 104713 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 104714 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 104715 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 104716 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 104717 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 104718 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 104719 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 104720 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 104721 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 104722 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 104723 | //BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO |
|---|
| 104724 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 104725 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 104726 | //BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI |
|---|
| 104727 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 104728 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 104729 | //BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA |
|---|
| 104730 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 104731 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 104732 | //BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK |
|---|
| 104733 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 104734 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 104735 | //BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64 |
|---|
| 104736 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 104737 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 104738 | //BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64 |
|---|
| 104739 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 104740 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 104741 | //BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING |
|---|
| 104742 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 104743 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 104744 | //BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64 |
|---|
| 104745 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 104746 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 104747 | //BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST |
|---|
| 104748 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104749 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 104750 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 104751 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 104752 | //BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL |
|---|
| 104753 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 104754 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 104755 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 104756 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 104757 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 104758 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 104759 | //BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE |
|---|
| 104760 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 104761 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 104762 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 104763 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 104764 | //BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA |
|---|
| 104765 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 104766 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 104767 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 104768 | #define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 104769 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 104770 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104771 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 104772 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 104773 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 104774 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 104775 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 104776 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 104777 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 104778 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 104779 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 104780 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 104781 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 104782 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 104783 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 104784 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 104785 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 104786 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 104787 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 104788 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 104789 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 104790 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104791 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 104792 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 104793 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 104794 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 104795 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 104796 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 104797 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 104798 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 104799 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 104800 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 104801 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 104802 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 104803 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 104804 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 104805 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 104806 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 104807 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 104808 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 104809 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 104810 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 104811 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 104812 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 104813 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 104814 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 104815 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 104816 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 104817 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 104818 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 104819 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 104820 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 104821 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 104822 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 104823 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 104824 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 104825 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 104826 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 104827 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 104828 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 104829 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK |
|---|
| 104830 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 104831 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 104832 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 104833 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 104834 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 104835 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 104836 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 104837 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 104838 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 104839 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 104840 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 104841 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 104842 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 104843 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 104844 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 104845 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 104846 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 104847 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 104848 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 104849 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 104850 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 104851 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 104852 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 104853 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 104854 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 104855 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 104856 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 104857 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 104858 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 104859 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 104860 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 104861 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 104862 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 104863 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 104864 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 104865 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 104866 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 104867 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 104868 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 104869 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 104870 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 104871 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 104872 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 104873 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 104874 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 104875 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 104876 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 104877 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 104878 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 104879 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 104880 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 104881 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 104882 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 104883 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 104884 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 104885 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 104886 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 104887 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 104888 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 104889 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 104890 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 104891 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 104892 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 104893 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 104894 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 104895 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS |
|---|
| 104896 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 104897 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 104898 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 104899 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 104900 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 104901 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 104902 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 104903 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 104904 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 104905 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 104906 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 104907 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 104908 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 104909 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 104910 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 104911 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 104912 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK |
|---|
| 104913 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 104914 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 104915 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 104916 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 104917 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 104918 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 104919 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 104920 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 104921 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 104922 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 104923 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 104924 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 104925 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 104926 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 104927 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 104928 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 104929 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 104930 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 104931 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 104932 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 104933 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 104934 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 104935 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 104936 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 104937 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 104938 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 104939 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 104940 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 104941 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 104942 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 104943 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 104944 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 104945 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 104946 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 104947 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 104948 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0 |
|---|
| 104949 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 104950 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 104951 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1 |
|---|
| 104952 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 104953 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 104954 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2 |
|---|
| 104955 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 104956 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 104957 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3 |
|---|
| 104958 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 104959 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 104960 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 104961 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 104962 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 104963 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 104964 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 104965 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 104966 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 104967 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 104968 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 104969 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 104970 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 104971 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 104972 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 104973 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 104974 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 104975 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 104976 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 104977 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 104978 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 104979 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP |
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| 104980 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
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| 104981 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 104982 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
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| 104983 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 104984 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 104985 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 104986 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL |
|---|
| 104987 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 104988 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 104989 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
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| 104990 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
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| 104991 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 104992 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 104993 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 104994 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 104995 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 104996 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 104997 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 104998 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP |
|---|
| 104999 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 105000 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 105001 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 105002 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 105003 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 105004 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 105005 | //BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL |
|---|
| 105006 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 105007 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 105008 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 105009 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 105010 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 105011 | #define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 105012 | |
|---|
| 105013 | |
|---|
| 105014 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp |
|---|
| 105015 | //BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID |
|---|
| 105016 | #define BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 105017 | #define BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 105018 | //BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID |
|---|
| 105019 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 105020 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 105021 | //BIF_CFG_DEV0_EPF0_VF9_1_COMMAND |
|---|
| 105022 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 105023 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 105024 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 105025 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 105026 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 105027 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 105028 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
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| 105029 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 105030 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 105031 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
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| 105032 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 105033 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 105034 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 105035 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 105036 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 105037 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 105038 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
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| 105039 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
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| 105040 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 105041 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN_MASK 0x0100L |
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| 105042 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
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| 105043 | #define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS_MASK 0x0400L |
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| 105044 | //BIF_CFG_DEV0_EPF0_VF9_1_STATUS |
|---|
| 105045 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
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| 105046 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS__SHIFT 0x3 |
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| 105047 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST__SHIFT 0x4 |
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| 105048 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
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| 105049 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
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| 105050 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 105051 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
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| 105052 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 105053 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
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| 105054 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
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| 105055 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
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| 105056 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
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| 105057 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
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| 105058 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS_MASK 0x0008L |
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| 105059 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST_MASK 0x0010L |
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| 105060 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_CAP_MASK 0x0020L |
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| 105061 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
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| 105062 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
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| 105063 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
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| 105064 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
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| 105065 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
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| 105066 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
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| 105067 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
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| 105068 | #define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
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| 105069 | //BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID |
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| 105070 | #define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
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| 105071 | #define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
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| 105072 | #define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
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| 105073 | #define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
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| 105074 | //BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE |
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| 105075 | #define BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
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| 105076 | #define BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
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| 105077 | //BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS |
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| 105078 | #define BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
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| 105079 | #define BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
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| 105080 | //BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS |
|---|
| 105081 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
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| 105082 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
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| 105083 | //BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE |
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| 105084 | #define BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
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| 105085 | #define BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
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| 105086 | //BIF_CFG_DEV0_EPF0_VF9_1_LATENCY |
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| 105087 | #define BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
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| 105088 | #define BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
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| 105089 | //BIF_CFG_DEV0_EPF0_VF9_1_HEADER |
|---|
| 105090 | #define 0x0 |
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| 105091 | #define 0x7 |
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| 105092 | #define 0x7FL |
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| 105093 | #define 0x80L |
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| 105094 | //BIF_CFG_DEV0_EPF0_VF9_1_BIST |
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| 105095 | #define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP__SHIFT 0x0 |
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| 105096 | #define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT__SHIFT 0x6 |
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| 105097 | #define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP__SHIFT 0x7 |
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| 105098 | #define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP_MASK 0x0FL |
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| 105099 | #define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT_MASK 0x40L |
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| 105100 | #define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP_MASK 0x80L |
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| 105101 | //BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1 |
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| 105102 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
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| 105103 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 105104 | //BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2 |
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| 105105 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
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| 105106 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 105107 | //BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3 |
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| 105108 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
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| 105109 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 105110 | //BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4 |
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| 105111 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
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| 105112 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 105113 | //BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5 |
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| 105114 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
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| 105115 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 105116 | //BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6 |
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| 105117 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
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| 105118 | #define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 105119 | //BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR |
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| 105120 | #define BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
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| 105121 | #define BIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
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| 105122 | //BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID |
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| 105123 | #define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
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| 105124 | #define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
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| 105125 | #define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
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| 105126 | #define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
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| 105127 | //BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR |
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| 105128 | #define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
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| 105129 | #define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 105130 | //BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR |
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| 105131 | #define BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
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| 105132 | #define BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
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| 105133 | //BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE |
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| 105134 | #define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
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| 105135 | #define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
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| 105136 | //BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN |
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| 105137 | #define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
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| 105138 | #define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
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| 105139 | //BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT |
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| 105140 | #define BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
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| 105141 | #define BIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
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| 105142 | //BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY |
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| 105143 | #define BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
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| 105144 | #define BIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
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| 105145 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST |
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| 105146 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 105147 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 105148 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 105149 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 105150 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP |
|---|
| 105151 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION__SHIFT 0x0 |
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| 105152 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 105153 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 105154 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
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| 105155 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION_MASK 0x000FL |
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| 105156 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
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| 105157 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 105158 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 105159 | //BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP |
|---|
| 105160 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 105161 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 105162 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 105163 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 105164 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 105165 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 105166 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 105167 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 105168 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 105169 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 105170 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 105171 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 105172 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 105173 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 105174 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 105175 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 105176 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 105177 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 105178 | //BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL |
|---|
| 105179 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 105180 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 105181 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 105182 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 105183 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 105184 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 105185 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 105186 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 105187 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 105188 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 105189 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 105190 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 105191 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 105192 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 105193 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 105194 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 105195 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 105196 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 105197 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 105198 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 105199 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 105200 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 105201 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 105202 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 105203 | //BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS |
|---|
| 105204 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 105205 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 105206 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 105207 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 105208 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 105209 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 105210 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 105211 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 105212 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 105213 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 105214 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 105215 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 105216 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 105217 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 105218 | //BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP |
|---|
| 105219 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 105220 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 105221 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 105222 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 105223 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 105224 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 105225 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 105226 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 105227 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 105228 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 105229 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 105230 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 105231 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 105232 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 105233 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 105234 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 105235 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 105236 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 105237 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 105238 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 105239 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 105240 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 105241 | //BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL |
|---|
| 105242 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 105243 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 105244 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 105245 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 105246 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 105247 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 105248 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 105249 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 105250 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 105251 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 105252 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 105253 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 105254 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 105255 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 105256 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 105257 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 105258 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 105259 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 105260 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 105261 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 105262 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 105263 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 105264 | //BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS |
|---|
| 105265 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 105266 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 105267 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 105268 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 105269 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 105270 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 105271 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 105272 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 105273 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 105274 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 105275 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 105276 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 105277 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 105278 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 105279 | //BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2 |
|---|
| 105280 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 105281 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 105282 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 105283 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 105284 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 105285 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 105286 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 105287 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 105288 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 105289 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 105290 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 105291 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 105292 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 105293 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 105294 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 105295 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 105296 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 105297 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 105298 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 105299 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 105300 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 105301 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 105302 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 105303 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 105304 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 105305 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 105306 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 105307 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 105308 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 105309 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 105310 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 105311 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 105312 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 105313 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 105314 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 105315 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 105316 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 105317 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 105318 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 105319 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 105320 | //BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2 |
|---|
| 105321 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 105322 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 105323 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 105324 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 105325 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 105326 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 105327 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 105328 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 105329 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 105330 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 105331 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 105332 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 105333 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 105334 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 105335 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 105336 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 105337 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 105338 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 105339 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 105340 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 105341 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 105342 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 105343 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 105344 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 105345 | //BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2 |
|---|
| 105346 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 105347 | #define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 105348 | //BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2 |
|---|
| 105349 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 105350 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 105351 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 105352 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 105353 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 105354 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 105355 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 105356 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 105357 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 105358 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 105359 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 105360 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 105361 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 105362 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 105363 | //BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2 |
|---|
| 105364 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 105365 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 105366 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 105367 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 105368 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 105369 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 105370 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 105371 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 105372 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 105373 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 105374 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 105375 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 105376 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 105377 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 105378 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 105379 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 105380 | //BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2 |
|---|
| 105381 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 105382 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 105383 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 105384 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 105385 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 105386 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 105387 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 105388 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 105389 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 105390 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 105391 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 105392 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 105393 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 105394 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 105395 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 105396 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 105397 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 105398 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 105399 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 105400 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 105401 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 105402 | #define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 105403 | //BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST |
|---|
| 105404 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 105405 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 105406 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 105407 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 105408 | //BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL |
|---|
| 105409 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 105410 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 105411 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 105412 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 105413 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 105414 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 105415 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 105416 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 105417 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 105418 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 105419 | //BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO |
|---|
| 105420 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 105421 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 105422 | //BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI |
|---|
| 105423 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 105424 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 105425 | //BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA |
|---|
| 105426 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 105427 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 105428 | //BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK |
|---|
| 105429 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 105430 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 105431 | //BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64 |
|---|
| 105432 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 105433 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 105434 | //BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64 |
|---|
| 105435 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 105436 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 105437 | //BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING |
|---|
| 105438 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 105439 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 105440 | //BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64 |
|---|
| 105441 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 105442 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 105443 | //BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST |
|---|
| 105444 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 105445 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 105446 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 105447 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 105448 | //BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL |
|---|
| 105449 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 105450 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 105451 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 105452 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 105453 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 105454 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 105455 | //BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE |
|---|
| 105456 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 105457 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 105458 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 105459 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 105460 | //BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA |
|---|
| 105461 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 105462 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 105463 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 105464 | #define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 105465 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 105466 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 105467 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 105468 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 105469 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 105470 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 105471 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 105472 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 105473 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 105474 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 105475 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 105476 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 105477 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 105478 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 105479 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 105480 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 105481 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 105482 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 105483 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 105484 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 105485 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 105486 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 105487 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 105488 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 105489 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 105490 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 105491 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 105492 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 105493 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 105494 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 105495 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 105496 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 105497 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 105498 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 105499 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 105500 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 105501 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 105502 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 105503 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 105504 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 105505 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 105506 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 105507 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 105508 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 105509 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 105510 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 105511 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 105512 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 105513 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 105514 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 105515 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 105516 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 105517 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 105518 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 105519 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 105520 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 105521 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 105522 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 105523 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 105524 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 105525 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK |
|---|
| 105526 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 105527 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 105528 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 105529 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 105530 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 105531 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 105532 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 105533 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 105534 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 105535 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 105536 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 105537 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 105538 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 105539 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 105540 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 105541 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 105542 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 105543 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 105544 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 105545 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 105546 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 105547 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 105548 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 105549 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 105550 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 105551 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 105552 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 105553 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 105554 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 105555 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 105556 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 105557 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 105558 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 105559 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 105560 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 105561 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 105562 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 105563 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 105564 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 105565 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 105566 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 105567 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 105568 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 105569 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 105570 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 105571 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 105572 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 105573 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 105574 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 105575 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 105576 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 105577 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 105578 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 105579 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 105580 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 105581 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 105582 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 105583 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 105584 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 105585 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 105586 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 105587 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 105588 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 105589 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 105590 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 105591 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS |
|---|
| 105592 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 105593 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 105594 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 105595 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 105596 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 105597 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 105598 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 105599 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 105600 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 105601 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 105602 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 105603 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 105604 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 105605 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 105606 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 105607 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 105608 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK |
|---|
| 105609 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 105610 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 105611 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 105612 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 105613 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 105614 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 105615 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 105616 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 105617 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 105618 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 105619 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 105620 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 105621 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 105622 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 105623 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 105624 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 105625 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 105626 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 105627 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 105628 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 105629 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 105630 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 105631 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 105632 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 105633 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 105634 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 105635 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 105636 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 105637 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 105638 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 105639 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 105640 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 105641 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 105642 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 105643 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 105644 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0 |
|---|
| 105645 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 105646 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 105647 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1 |
|---|
| 105648 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 105649 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 105650 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2 |
|---|
| 105651 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 105652 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 105653 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3 |
|---|
| 105654 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 105655 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 105656 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 105657 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 105658 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 105659 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 105660 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 105661 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 105662 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 105663 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 105664 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 105665 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 105666 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 105667 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 105668 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 105669 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 105670 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 105671 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 105672 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 105673 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 105674 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 105675 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP |
|---|
| 105676 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 105677 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 105678 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 105679 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 105680 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 105681 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 105682 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL |
|---|
| 105683 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 105684 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 105685 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 105686 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 105687 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 105688 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 105689 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 105690 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 105691 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 105692 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 105693 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 105694 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP |
|---|
| 105695 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 105696 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 105697 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 105698 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 105699 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 105700 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 105701 | //BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL |
|---|
| 105702 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 105703 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 105704 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 105705 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 105706 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 105707 | #define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 105708 | |
|---|
| 105709 | |
|---|
| 105710 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp |
|---|
| 105711 | //BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID |
|---|
| 105712 | #define BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 105713 | #define BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 105714 | //BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID |
|---|
| 105715 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 105716 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 105717 | //BIF_CFG_DEV0_EPF0_VF10_1_COMMAND |
|---|
| 105718 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 105719 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 105720 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 105721 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 105722 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 105723 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 105724 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 105725 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 105726 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 105727 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 105728 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 105729 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 105730 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 105731 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 105732 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 105733 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 105734 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 105735 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 105736 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 105737 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 105738 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 105739 | #define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 105740 | //BIF_CFG_DEV0_EPF0_VF10_1_STATUS |
|---|
| 105741 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 105742 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 105743 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 105744 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 105745 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 105746 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 105747 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 105748 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 105749 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 105750 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 105751 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 105752 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 105753 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 105754 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 105755 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 105756 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 105757 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 105758 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 105759 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 105760 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 105761 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 105762 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 105763 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 105764 | #define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 105765 | //BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID |
|---|
| 105766 | #define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 105767 | #define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 105768 | #define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 105769 | #define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 105770 | //BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE |
|---|
| 105771 | #define BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 105772 | #define BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 105773 | //BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS |
|---|
| 105774 | #define BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 105775 | #define BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 105776 | //BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS |
|---|
| 105777 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 105778 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 105779 | //BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE |
|---|
| 105780 | #define BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 105781 | #define BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 105782 | //BIF_CFG_DEV0_EPF0_VF10_1_LATENCY |
|---|
| 105783 | #define BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 105784 | #define BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 105785 | //BIF_CFG_DEV0_EPF0_VF10_1_HEADER |
|---|
| 105786 | #define 0x0 |
|---|
| 105787 | #define 0x7 |
|---|
| 105788 | #define 0x7FL |
|---|
| 105789 | #define 0x80L |
|---|
| 105790 | //BIF_CFG_DEV0_EPF0_VF10_1_BIST |
|---|
| 105791 | #define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 105792 | #define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 105793 | #define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 105794 | #define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 105795 | #define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 105796 | #define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 105797 | //BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1 |
|---|
| 105798 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 105799 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 105800 | //BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2 |
|---|
| 105801 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 105802 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 105803 | //BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3 |
|---|
| 105804 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 105805 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 105806 | //BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4 |
|---|
| 105807 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 105808 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 105809 | //BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5 |
|---|
| 105810 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 105811 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 105812 | //BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6 |
|---|
| 105813 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 105814 | #define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 105815 | //BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR |
|---|
| 105816 | #define BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 105817 | #define BIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 105818 | //BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID |
|---|
| 105819 | #define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 105820 | #define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 105821 | #define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 105822 | #define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 105823 | //BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR |
|---|
| 105824 | #define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 105825 | #define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 105826 | //BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR |
|---|
| 105827 | #define BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 105828 | #define BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 105829 | //BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE |
|---|
| 105830 | #define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 105831 | #define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 105832 | //BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN |
|---|
| 105833 | #define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 105834 | #define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 105835 | //BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT |
|---|
| 105836 | #define BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 105837 | #define BIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 105838 | //BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY |
|---|
| 105839 | #define BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 105840 | #define BIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 105841 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST |
|---|
| 105842 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 105843 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 105844 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 105845 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 105846 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP |
|---|
| 105847 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 105848 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 105849 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 105850 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 105851 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 105852 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 105853 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 105854 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 105855 | //BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP |
|---|
| 105856 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 105857 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 105858 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 105859 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 105860 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 105861 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 105862 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 105863 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 105864 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 105865 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 105866 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 105867 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 105868 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 105869 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 105870 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 105871 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 105872 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 105873 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 105874 | //BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL |
|---|
| 105875 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 105876 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 105877 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 105878 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 105879 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 105880 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 105881 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 105882 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 105883 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 105884 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 105885 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 105886 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 105887 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 105888 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 105889 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 105890 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 105891 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 105892 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 105893 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 105894 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 105895 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 105896 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 105897 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 105898 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 105899 | //BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS |
|---|
| 105900 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 105901 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 105902 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 105903 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 105904 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 105905 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 105906 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 105907 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 105908 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 105909 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 105910 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 105911 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 105912 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 105913 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 105914 | //BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP |
|---|
| 105915 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 105916 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 105917 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 105918 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 105919 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 105920 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 105921 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 105922 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 105923 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 105924 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 105925 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 105926 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 105927 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 105928 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 105929 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 105930 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 105931 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 105932 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 105933 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 105934 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 105935 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 105936 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 105937 | //BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL |
|---|
| 105938 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 105939 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 105940 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 105941 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 105942 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 105943 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 105944 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 105945 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 105946 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 105947 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 105948 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 105949 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 105950 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 105951 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 105952 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 105953 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 105954 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 105955 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 105956 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 105957 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 105958 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 105959 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 105960 | //BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS |
|---|
| 105961 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 105962 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 105963 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 105964 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 105965 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 105966 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 105967 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 105968 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 105969 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 105970 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 105971 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 105972 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 105973 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 105974 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 105975 | //BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2 |
|---|
| 105976 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 105977 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 105978 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 105979 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 105980 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 105981 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 105982 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 105983 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 105984 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 105985 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 105986 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 105987 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 105988 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 105989 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 105990 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 105991 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 105992 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 105993 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 105994 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 105995 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 105996 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 105997 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 105998 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 105999 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 106000 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 106001 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 106002 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 106003 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 106004 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 106005 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 106006 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 106007 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 106008 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 106009 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 106010 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 106011 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 106012 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 106013 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 106014 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 106015 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 106016 | //BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2 |
|---|
| 106017 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 106018 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 106019 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 106020 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 106021 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 106022 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 106023 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 106024 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 106025 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 106026 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 106027 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 106028 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 106029 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 106030 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 106031 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 106032 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 106033 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 106034 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 106035 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 106036 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 106037 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 106038 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 106039 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 106040 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 106041 | //BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2 |
|---|
| 106042 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 106043 | #define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 106044 | //BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2 |
|---|
| 106045 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 106046 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 106047 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 106048 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 106049 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 106050 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 106051 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 106052 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 106053 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 106054 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 106055 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 106056 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 106057 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 106058 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 106059 | //BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2 |
|---|
| 106060 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 106061 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 106062 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 106063 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 106064 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 106065 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 106066 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 106067 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 106068 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 106069 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 106070 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 106071 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 106072 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 106073 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 106074 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 106075 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 106076 | //BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2 |
|---|
| 106077 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 106078 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 106079 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 106080 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 106081 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 106082 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 106083 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 106084 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 106085 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 106086 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 106087 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 106088 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 106089 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 106090 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 106091 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 106092 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 106093 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 106094 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 106095 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 106096 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 106097 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 106098 | #define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 106099 | //BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST |
|---|
| 106100 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 106101 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 106102 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 106103 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 106104 | //BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL |
|---|
| 106105 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 106106 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 106107 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 106108 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 106109 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 106110 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 106111 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 106112 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 106113 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 106114 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 106115 | //BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO |
|---|
| 106116 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 106117 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 106118 | //BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI |
|---|
| 106119 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 106120 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 106121 | //BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA |
|---|
| 106122 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 106123 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 106124 | //BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK |
|---|
| 106125 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 106126 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 106127 | //BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64 |
|---|
| 106128 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 106129 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 106130 | //BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64 |
|---|
| 106131 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 106132 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 106133 | //BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING |
|---|
| 106134 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 106135 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 106136 | //BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64 |
|---|
| 106137 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 106138 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 106139 | //BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST |
|---|
| 106140 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 106141 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 106142 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 106143 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 106144 | //BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL |
|---|
| 106145 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 106146 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 106147 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 106148 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 106149 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 106150 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 106151 | //BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE |
|---|
| 106152 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 106153 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 106154 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 106155 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 106156 | //BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA |
|---|
| 106157 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 106158 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 106159 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 106160 | #define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 106161 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 106162 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 106163 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 106164 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 106165 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 106166 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 106167 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 106168 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR |
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| 106169 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
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| 106170 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
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| 106171 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
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| 106172 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
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| 106173 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
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| 106174 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
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| 106175 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1 |
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| 106176 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 106177 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 106178 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2 |
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| 106179 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 106180 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
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| 106181 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 106182 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 106183 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 106184 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 106185 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 106186 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 106187 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 106188 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS |
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| 106189 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 106190 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 106191 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 106192 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 106193 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 106194 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 106195 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 106196 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 106197 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 106198 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 106199 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 106200 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 106201 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 106202 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 106203 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 106204 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 106205 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 106206 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 106207 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 106208 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 106209 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 106210 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 106211 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 106212 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 106213 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 106214 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 106215 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 106216 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 106217 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 106218 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 106219 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 106220 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 106221 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK |
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| 106222 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 106223 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 106224 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 106225 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 106226 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 106227 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 106228 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 106229 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 106230 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 106231 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 106232 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 106233 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 106234 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 106235 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 106236 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 106237 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 106238 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 106239 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 106240 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 106241 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 106242 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 106243 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 106244 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 106245 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 106246 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 106247 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 106248 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 106249 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 106250 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 106251 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 106252 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 106253 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 106254 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY |
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| 106255 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 106256 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 106257 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 106258 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 106259 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 106260 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 106261 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 106262 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 106263 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 106264 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 106265 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 106266 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 106267 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 106268 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 106269 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 106270 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 106271 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 106272 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 106273 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 106274 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 106275 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 106276 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 106277 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 106278 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 106279 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 106280 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 106281 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 106282 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 106283 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 106284 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 106285 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 106286 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 106287 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS |
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| 106288 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 106289 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 106290 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 106291 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 106292 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 106293 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 106294 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 106295 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 106296 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 106297 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 106298 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 106299 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 106300 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 106301 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 106302 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 106303 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 106304 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK |
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| 106305 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 106306 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 106307 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 106308 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 106309 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 106310 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 106311 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 106312 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 106313 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 106314 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 106315 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 106316 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 106317 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 106318 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 106319 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 106320 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 106321 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 106322 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 106323 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 106324 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 106325 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 106326 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 106327 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 106328 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 106329 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 106330 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 106331 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 106332 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 106333 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 106334 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 106335 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 106336 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 106337 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 106338 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 106339 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 106340 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0 |
|---|
| 106341 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 106342 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 106343 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1 |
|---|
| 106344 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 106345 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 106346 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2 |
|---|
| 106347 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 106348 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 106349 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3 |
|---|
| 106350 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 106351 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 106352 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 106353 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 106354 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 106355 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 106356 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 106357 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 106358 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 106359 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 106360 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 106361 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 106362 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 106363 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 106364 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 106365 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 106366 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 106367 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 106368 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 106369 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 106370 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 106371 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP |
|---|
| 106372 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 106373 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 106374 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 106375 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 106376 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 106377 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 106378 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL |
|---|
| 106379 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 106380 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 106381 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 106382 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 106383 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 106384 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 106385 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 106386 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 106387 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 106388 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 106389 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 106390 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP |
|---|
| 106391 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 106392 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 106393 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 106394 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 106395 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 106396 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 106397 | //BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL |
|---|
| 106398 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 106399 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 106400 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 106401 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 106402 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 106403 | #define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 106404 | |
|---|
| 106405 | |
|---|
| 106406 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp |
|---|
| 106407 | //BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID |
|---|
| 106408 | #define BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 106409 | #define BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 106410 | //BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID |
|---|
| 106411 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 106412 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 106413 | //BIF_CFG_DEV0_EPF0_VF11_1_COMMAND |
|---|
| 106414 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 106415 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 106416 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 106417 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 106418 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 106419 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 106420 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 106421 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 106422 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 106423 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 106424 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 106425 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 106426 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 106427 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 106428 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 106429 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 106430 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 106431 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 106432 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 106433 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 106434 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 106435 | #define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 106436 | //BIF_CFG_DEV0_EPF0_VF11_1_STATUS |
|---|
| 106437 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 106438 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 106439 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 106440 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 106441 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 106442 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 106443 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 106444 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 106445 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 106446 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 106447 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 106448 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 106449 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 106450 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 106451 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 106452 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 106453 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 106454 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 106455 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 106456 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 106457 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 106458 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 106459 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 106460 | #define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 106461 | //BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID |
|---|
| 106462 | #define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 106463 | #define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 106464 | #define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 106465 | #define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 106466 | //BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE |
|---|
| 106467 | #define BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 106468 | #define BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 106469 | //BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS |
|---|
| 106470 | #define BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 106471 | #define BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 106472 | //BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS |
|---|
| 106473 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 106474 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 106475 | //BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE |
|---|
| 106476 | #define BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 106477 | #define BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 106478 | //BIF_CFG_DEV0_EPF0_VF11_1_LATENCY |
|---|
| 106479 | #define BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 106480 | #define BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 106481 | //BIF_CFG_DEV0_EPF0_VF11_1_HEADER |
|---|
| 106482 | #define 0x0 |
|---|
| 106483 | #define 0x7 |
|---|
| 106484 | #define 0x7FL |
|---|
| 106485 | #define 0x80L |
|---|
| 106486 | //BIF_CFG_DEV0_EPF0_VF11_1_BIST |
|---|
| 106487 | #define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 106488 | #define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 106489 | #define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 106490 | #define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 106491 | #define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 106492 | #define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 106493 | //BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1 |
|---|
| 106494 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 106495 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 106496 | //BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2 |
|---|
| 106497 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 106498 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 106499 | //BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3 |
|---|
| 106500 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 106501 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 106502 | //BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4 |
|---|
| 106503 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 106504 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 106505 | //BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5 |
|---|
| 106506 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 106507 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 106508 | //BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6 |
|---|
| 106509 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 106510 | #define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 106511 | //BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR |
|---|
| 106512 | #define BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 106513 | #define BIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 106514 | //BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID |
|---|
| 106515 | #define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 106516 | #define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 106517 | #define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 106518 | #define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 106519 | //BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR |
|---|
| 106520 | #define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 106521 | #define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 106522 | //BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR |
|---|
| 106523 | #define BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 106524 | #define BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 106525 | //BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE |
|---|
| 106526 | #define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 106527 | #define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 106528 | //BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN |
|---|
| 106529 | #define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 106530 | #define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 106531 | //BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT |
|---|
| 106532 | #define BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 106533 | #define BIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 106534 | //BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY |
|---|
| 106535 | #define BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 106536 | #define BIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 106537 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST |
|---|
| 106538 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 106539 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 106540 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 106541 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 106542 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP |
|---|
| 106543 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 106544 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 106545 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 106546 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 106547 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 106548 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 106549 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 106550 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 106551 | //BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP |
|---|
| 106552 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 106553 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 106554 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 106555 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 106556 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 106557 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 106558 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 106559 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 106560 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 106561 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 106562 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 106563 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 106564 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 106565 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 106566 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 106567 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 106568 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 106569 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 106570 | //BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL |
|---|
| 106571 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 106572 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 106573 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 106574 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 106575 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 106576 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 106577 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 106578 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 106579 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 106580 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 106581 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 106582 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 106583 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 106584 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 106585 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 106586 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 106587 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 106588 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 106589 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 106590 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 106591 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 106592 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 106593 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 106594 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 106595 | //BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS |
|---|
| 106596 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 106597 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 106598 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 106599 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 106600 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 106601 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 106602 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 106603 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 106604 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 106605 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 106606 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 106607 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 106608 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 106609 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 106610 | //BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP |
|---|
| 106611 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 106612 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 106613 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 106614 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 106615 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 106616 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 106617 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 106618 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 106619 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 106620 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 106621 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 106622 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 106623 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 106624 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 106625 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 106626 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 106627 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 106628 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 106629 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 106630 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 106631 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 106632 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 106633 | //BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL |
|---|
| 106634 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 106635 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 106636 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 106637 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 106638 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 106639 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 106640 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 106641 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 106642 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 106643 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 106644 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 106645 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 106646 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 106647 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 106648 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 106649 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 106650 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 106651 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 106652 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 106653 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 106654 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 106655 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 106656 | //BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS |
|---|
| 106657 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 106658 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 106659 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 106660 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 106661 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 106662 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 106663 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 106664 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 106665 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 106666 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 106667 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 106668 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 106669 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 106670 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 106671 | //BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2 |
|---|
| 106672 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 106673 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 106674 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 106675 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 106676 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 106677 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 106678 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 106679 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 106680 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 106681 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 106682 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 106683 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 106684 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 106685 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 106686 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 106687 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 106688 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 106689 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 106690 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 106691 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 106692 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 106693 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 106694 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 106695 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 106696 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 106697 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 106698 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 106699 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 106700 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 106701 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 106702 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 106703 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 106704 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 106705 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 106706 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 106707 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 106708 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 106709 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 106710 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 106711 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 106712 | //BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2 |
|---|
| 106713 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 106714 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 106715 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 106716 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 106717 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 106718 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 106719 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 106720 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 106721 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 106722 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 106723 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 106724 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 106725 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 106726 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 106727 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 106728 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 106729 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 106730 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 106731 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 106732 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 106733 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 106734 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 106735 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 106736 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 106737 | //BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2 |
|---|
| 106738 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 106739 | #define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 106740 | //BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2 |
|---|
| 106741 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 106742 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 106743 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 106744 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 106745 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 106746 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 106747 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 106748 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 106749 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 106750 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 106751 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 106752 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 106753 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 106754 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 106755 | //BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2 |
|---|
| 106756 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 106757 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 106758 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 106759 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 106760 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 106761 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 106762 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 106763 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 106764 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 106765 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 106766 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 106767 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 106768 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 106769 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 106770 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 106771 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 106772 | //BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2 |
|---|
| 106773 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 106774 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 106775 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 106776 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 106777 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 106778 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 106779 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 106780 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 106781 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 106782 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 106783 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 106784 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 106785 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 106786 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 106787 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 106788 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 106789 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 106790 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 106791 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 106792 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 106793 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 106794 | #define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 106795 | //BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST |
|---|
| 106796 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 106797 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 106798 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 106799 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 106800 | //BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL |
|---|
| 106801 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 106802 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 106803 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 106804 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 106805 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 106806 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 106807 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 106808 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 106809 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 106810 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 106811 | //BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO |
|---|
| 106812 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 106813 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 106814 | //BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI |
|---|
| 106815 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 106816 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 106817 | //BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA |
|---|
| 106818 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 106819 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 106820 | //BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK |
|---|
| 106821 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 106822 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 106823 | //BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64 |
|---|
| 106824 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 106825 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 106826 | //BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64 |
|---|
| 106827 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
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| 106828 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
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| 106829 | //BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING |
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| 106830 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
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| 106831 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
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| 106832 | //BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64 |
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| 106833 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
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| 106834 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
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| 106835 | //BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST |
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| 106836 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 106837 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 106838 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 106839 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 106840 | //BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL |
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| 106841 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
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| 106842 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
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| 106843 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
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| 106844 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
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| 106845 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
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| 106846 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
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| 106847 | //BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE |
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| 106848 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
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| 106849 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
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| 106850 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
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| 106851 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
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| 106852 | //BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA |
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| 106853 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
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| 106854 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
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| 106855 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
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| 106856 | #define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
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| 106857 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
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| 106858 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 106859 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 106860 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 106861 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 106862 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 106863 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 106864 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR |
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| 106865 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
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| 106866 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
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| 106867 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
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| 106868 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
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| 106869 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 106870 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 106871 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 106872 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 106873 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 106874 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2 |
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| 106875 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 106876 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 106877 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 106878 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 106879 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 106880 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 106881 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 106882 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 106883 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 106884 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 106885 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 106886 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 106887 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 106888 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 106889 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 106890 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 106891 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 106892 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 106893 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 106894 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 106895 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 106896 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 106897 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 106898 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 106899 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 106900 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 106901 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 106902 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 106903 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 106904 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 106905 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 106906 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 106907 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 106908 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 106909 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 106910 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 106911 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 106912 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 106913 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 106914 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 106915 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 106916 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 106917 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK |
|---|
| 106918 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 106919 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 106920 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 106921 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 106922 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 106923 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 106924 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 106925 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 106926 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 106927 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 106928 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 106929 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 106930 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 106931 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 106932 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 106933 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 106934 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 106935 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 106936 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 106937 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 106938 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 106939 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 106940 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 106941 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 106942 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 106943 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 106944 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 106945 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 106946 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 106947 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 106948 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 106949 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 106950 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 106951 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 106952 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 106953 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 106954 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 106955 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 106956 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 106957 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 106958 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 106959 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 106960 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 106961 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 106962 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 106963 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 106964 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 106965 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 106966 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 106967 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 106968 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 106969 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 106970 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 106971 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 106972 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 106973 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 106974 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 106975 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 106976 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 106977 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 106978 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 106979 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 106980 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 106981 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 106982 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 106983 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS |
|---|
| 106984 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 106985 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 106986 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 106987 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 106988 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 106989 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 106990 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 106991 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 106992 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 106993 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 106994 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 106995 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 106996 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 106997 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 106998 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 106999 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 107000 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK |
|---|
| 107001 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 107002 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 107003 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 107004 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 107005 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 107006 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 107007 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 107008 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 107009 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 107010 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 107011 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 107012 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 107013 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 107014 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 107015 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 107016 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 107017 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 107018 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 107019 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 107020 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 107021 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 107022 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 107023 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 107024 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 107025 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 107026 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 107027 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 107028 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 107029 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 107030 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 107031 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 107032 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 107033 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 107034 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 107035 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 107036 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0 |
|---|
| 107037 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 107038 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 107039 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1 |
|---|
| 107040 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 107041 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 107042 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2 |
|---|
| 107043 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 107044 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 107045 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3 |
|---|
| 107046 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 107047 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 107048 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 107049 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 107050 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 107051 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 107052 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 107053 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 107054 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 107055 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 107056 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 107057 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 107058 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 107059 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 107060 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 107061 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 107062 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 107063 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 107064 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 107065 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 107066 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 107067 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP |
|---|
| 107068 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 107069 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 107070 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 107071 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 107072 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 107073 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 107074 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL |
|---|
| 107075 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 107076 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 107077 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 107078 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 107079 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 107080 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 107081 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 107082 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 107083 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 107084 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 107085 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 107086 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP |
|---|
| 107087 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 107088 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 107089 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 107090 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 107091 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 107092 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 107093 | //BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL |
|---|
| 107094 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 107095 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 107096 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 107097 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 107098 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 107099 | #define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 107100 | |
|---|
| 107101 | |
|---|
| 107102 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp |
|---|
| 107103 | //BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID |
|---|
| 107104 | #define BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 107105 | #define BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 107106 | //BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID |
|---|
| 107107 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 107108 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 107109 | //BIF_CFG_DEV0_EPF0_VF12_1_COMMAND |
|---|
| 107110 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 107111 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 107112 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 107113 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 107114 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 107115 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 107116 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 107117 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 107118 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 107119 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 107120 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 107121 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 107122 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 107123 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 107124 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 107125 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 107126 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 107127 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 107128 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 107129 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 107130 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 107131 | #define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 107132 | //BIF_CFG_DEV0_EPF0_VF12_1_STATUS |
|---|
| 107133 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 107134 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 107135 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 107136 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 107137 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 107138 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 107139 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 107140 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 107141 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 107142 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 107143 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 107144 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 107145 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 107146 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 107147 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 107148 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 107149 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 107150 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 107151 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 107152 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 107153 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 107154 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 107155 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 107156 | #define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 107157 | //BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID |
|---|
| 107158 | #define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 107159 | #define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 107160 | #define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 107161 | #define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 107162 | //BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE |
|---|
| 107163 | #define BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 107164 | #define BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 107165 | //BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS |
|---|
| 107166 | #define BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 107167 | #define BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 107168 | //BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS |
|---|
| 107169 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 107170 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 107171 | //BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE |
|---|
| 107172 | #define BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 107173 | #define BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 107174 | //BIF_CFG_DEV0_EPF0_VF12_1_LATENCY |
|---|
| 107175 | #define BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 107176 | #define BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 107177 | //BIF_CFG_DEV0_EPF0_VF12_1_HEADER |
|---|
| 107178 | #define 0x0 |
|---|
| 107179 | #define 0x7 |
|---|
| 107180 | #define 0x7FL |
|---|
| 107181 | #define 0x80L |
|---|
| 107182 | //BIF_CFG_DEV0_EPF0_VF12_1_BIST |
|---|
| 107183 | #define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 107184 | #define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 107185 | #define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 107186 | #define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 107187 | #define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 107188 | #define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 107189 | //BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1 |
|---|
| 107190 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 107191 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107192 | //BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2 |
|---|
| 107193 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 107194 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107195 | //BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3 |
|---|
| 107196 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 107197 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107198 | //BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4 |
|---|
| 107199 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 107200 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107201 | //BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5 |
|---|
| 107202 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 107203 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107204 | //BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6 |
|---|
| 107205 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 107206 | #define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107207 | //BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR |
|---|
| 107208 | #define BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 107209 | #define BIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 107210 | //BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID |
|---|
| 107211 | #define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 107212 | #define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 107213 | #define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 107214 | #define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 107215 | //BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR |
|---|
| 107216 | #define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 107217 | #define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107218 | //BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR |
|---|
| 107219 | #define BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 107220 | #define BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 107221 | //BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE |
|---|
| 107222 | #define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 107223 | #define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 107224 | //BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN |
|---|
| 107225 | #define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 107226 | #define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 107227 | //BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT |
|---|
| 107228 | #define BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 107229 | #define BIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 107230 | //BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY |
|---|
| 107231 | #define BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 107232 | #define BIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 107233 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST |
|---|
| 107234 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 107235 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 107236 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 107237 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 107238 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP |
|---|
| 107239 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 107240 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 107241 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 107242 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 107243 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 107244 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 107245 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 107246 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 107247 | //BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP |
|---|
| 107248 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 107249 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 107250 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 107251 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 107252 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 107253 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 107254 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 107255 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 107256 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 107257 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 107258 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 107259 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 107260 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 107261 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 107262 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 107263 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 107264 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 107265 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 107266 | //BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL |
|---|
| 107267 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 107268 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 107269 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 107270 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 107271 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 107272 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 107273 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 107274 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 107275 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 107276 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 107277 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 107278 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 107279 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 107280 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 107281 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 107282 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 107283 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 107284 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 107285 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 107286 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 107287 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 107288 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 107289 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 107290 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 107291 | //BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS |
|---|
| 107292 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 107293 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 107294 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 107295 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 107296 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 107297 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 107298 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 107299 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 107300 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 107301 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 107302 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 107303 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 107304 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 107305 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 107306 | //BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP |
|---|
| 107307 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 107308 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 107309 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 107310 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 107311 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 107312 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 107313 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 107314 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 107315 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 107316 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 107317 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 107318 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 107319 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 107320 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 107321 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 107322 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 107323 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 107324 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 107325 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 107326 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 107327 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 107328 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 107329 | //BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL |
|---|
| 107330 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 107331 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 107332 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 107333 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 107334 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 107335 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 107336 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 107337 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 107338 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 107339 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 107340 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 107341 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 107342 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 107343 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 107344 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 107345 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 107346 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 107347 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 107348 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 107349 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 107350 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 107351 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 107352 | //BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS |
|---|
| 107353 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 107354 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 107355 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 107356 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 107357 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 107358 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 107359 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 107360 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 107361 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 107362 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 107363 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 107364 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 107365 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 107366 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 107367 | //BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2 |
|---|
| 107368 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 107369 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 107370 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 107371 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 107372 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 107373 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 107374 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 107375 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 107376 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 107377 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 107378 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 107379 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 107380 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 107381 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 107382 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 107383 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 107384 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 107385 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 107386 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 107387 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 107388 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 107389 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 107390 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 107391 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 107392 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 107393 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 107394 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 107395 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 107396 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 107397 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 107398 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 107399 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 107400 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 107401 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 107402 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 107403 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 107404 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 107405 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 107406 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 107407 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 107408 | //BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2 |
|---|
| 107409 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 107410 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 107411 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 107412 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 107413 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 107414 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 107415 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 107416 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 107417 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 107418 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 107419 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 107420 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 107421 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 107422 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 107423 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 107424 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 107425 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 107426 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 107427 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 107428 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 107429 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 107430 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 107431 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 107432 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 107433 | //BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2 |
|---|
| 107434 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 107435 | #define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 107436 | //BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2 |
|---|
| 107437 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 107438 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 107439 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 107440 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 107441 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 107442 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 107443 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 107444 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 107445 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 107446 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 107447 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 107448 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 107449 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 107450 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 107451 | //BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2 |
|---|
| 107452 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 107453 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 107454 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 107455 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 107456 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 107457 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 107458 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 107459 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 107460 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 107461 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 107462 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 107463 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 107464 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 107465 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 107466 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 107467 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 107468 | //BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2 |
|---|
| 107469 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 107470 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 107471 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 107472 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 107473 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 107474 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 107475 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 107476 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 107477 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 107478 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 107479 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 107480 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 107481 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 107482 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 107483 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 107484 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 107485 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 107486 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 107487 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 107488 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 107489 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 107490 | #define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 107491 | //BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST |
|---|
| 107492 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 107493 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 107494 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 107495 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 107496 | //BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL |
|---|
| 107497 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 107498 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 107499 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 107500 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 107501 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 107502 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 107503 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 107504 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 107505 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 107506 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 107507 | //BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO |
|---|
| 107508 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 107509 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 107510 | //BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI |
|---|
| 107511 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 107512 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 107513 | //BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA |
|---|
| 107514 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 107515 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 107516 | //BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK |
|---|
| 107517 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 107518 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 107519 | //BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64 |
|---|
| 107520 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 107521 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 107522 | //BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64 |
|---|
| 107523 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 107524 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 107525 | //BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING |
|---|
| 107526 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 107527 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 107528 | //BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64 |
|---|
| 107529 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 107530 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 107531 | //BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST |
|---|
| 107532 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 107533 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 107534 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 107535 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 107536 | //BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL |
|---|
| 107537 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 107538 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 107539 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 107540 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 107541 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 107542 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 107543 | //BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE |
|---|
| 107544 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 107545 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 107546 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 107547 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 107548 | //BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA |
|---|
| 107549 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 107550 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 107551 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 107552 | #define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 107553 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 107554 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 107555 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 107556 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 107557 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 107558 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 107559 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 107560 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 107561 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 107562 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 107563 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 107564 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 107565 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 107566 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 107567 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 107568 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 107569 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 107570 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 107571 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 107572 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 107573 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 107574 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 107575 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 107576 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 107577 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 107578 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 107579 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 107580 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 107581 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 107582 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 107583 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 107584 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 107585 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 107586 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 107587 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 107588 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 107589 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 107590 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 107591 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 107592 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 107593 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 107594 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 107595 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 107596 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 107597 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 107598 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 107599 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 107600 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 107601 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 107602 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 107603 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 107604 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 107605 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 107606 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 107607 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 107608 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 107609 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 107610 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 107611 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 107612 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 107613 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK |
|---|
| 107614 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 107615 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 107616 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 107617 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 107618 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 107619 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 107620 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 107621 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 107622 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 107623 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 107624 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 107625 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 107626 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 107627 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 107628 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 107629 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 107630 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 107631 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 107632 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 107633 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 107634 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 107635 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 107636 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 107637 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 107638 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 107639 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 107640 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 107641 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 107642 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 107643 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 107644 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 107645 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 107646 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 107647 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 107648 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 107649 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 107650 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 107651 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 107652 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 107653 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 107654 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 107655 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 107656 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 107657 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 107658 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 107659 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 107660 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 107661 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 107662 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 107663 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 107664 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 107665 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 107666 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 107667 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 107668 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 107669 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 107670 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 107671 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 107672 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 107673 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 107674 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 107675 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 107676 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 107677 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 107678 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 107679 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS |
|---|
| 107680 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 107681 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 107682 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 107683 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 107684 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 107685 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 107686 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 107687 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 107688 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 107689 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 107690 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 107691 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 107692 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 107693 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 107694 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 107695 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 107696 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK |
|---|
| 107697 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 107698 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 107699 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 107700 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 107701 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 107702 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 107703 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 107704 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 107705 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 107706 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 107707 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 107708 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 107709 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 107710 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 107711 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 107712 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 107713 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 107714 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 107715 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 107716 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 107717 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 107718 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 107719 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 107720 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 107721 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 107722 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 107723 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 107724 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 107725 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 107726 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 107727 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 107728 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 107729 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 107730 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 107731 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 107732 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0 |
|---|
| 107733 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 107734 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 107735 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1 |
|---|
| 107736 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 107737 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 107738 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2 |
|---|
| 107739 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 107740 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 107741 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3 |
|---|
| 107742 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 107743 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 107744 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 107745 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 107746 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 107747 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 107748 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 107749 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 107750 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 107751 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 107752 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 107753 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 107754 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 107755 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 107756 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 107757 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 107758 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 107759 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 107760 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 107761 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 107762 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 107763 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP |
|---|
| 107764 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 107765 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 107766 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 107767 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 107768 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 107769 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 107770 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL |
|---|
| 107771 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 107772 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 107773 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 107774 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 107775 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 107776 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 107777 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 107778 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 107779 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 107780 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 107781 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 107782 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP |
|---|
| 107783 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 107784 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 107785 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 107786 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 107787 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 107788 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 107789 | //BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL |
|---|
| 107790 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 107791 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 107792 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 107793 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 107794 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 107795 | #define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 107796 | |
|---|
| 107797 | |
|---|
| 107798 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp |
|---|
| 107799 | //BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID |
|---|
| 107800 | #define BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 107801 | #define BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 107802 | //BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID |
|---|
| 107803 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 107804 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 107805 | //BIF_CFG_DEV0_EPF0_VF13_1_COMMAND |
|---|
| 107806 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 107807 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 107808 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 107809 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 107810 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 107811 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 107812 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 107813 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 107814 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 107815 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 107816 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 107817 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 107818 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 107819 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 107820 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 107821 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 107822 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 107823 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 107824 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 107825 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 107826 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 107827 | #define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 107828 | //BIF_CFG_DEV0_EPF0_VF13_1_STATUS |
|---|
| 107829 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 107830 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 107831 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 107832 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 107833 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 107834 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 107835 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 107836 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 107837 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 107838 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 107839 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 107840 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 107841 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 107842 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 107843 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 107844 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 107845 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 107846 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 107847 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 107848 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 107849 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 107850 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 107851 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 107852 | #define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 107853 | //BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID |
|---|
| 107854 | #define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 107855 | #define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 107856 | #define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 107857 | #define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 107858 | //BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE |
|---|
| 107859 | #define BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 107860 | #define BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 107861 | //BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS |
|---|
| 107862 | #define BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 107863 | #define BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 107864 | //BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS |
|---|
| 107865 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 107866 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 107867 | //BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE |
|---|
| 107868 | #define BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 107869 | #define BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 107870 | //BIF_CFG_DEV0_EPF0_VF13_1_LATENCY |
|---|
| 107871 | #define BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 107872 | #define BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 107873 | //BIF_CFG_DEV0_EPF0_VF13_1_HEADER |
|---|
| 107874 | #define 0x0 |
|---|
| 107875 | #define 0x7 |
|---|
| 107876 | #define 0x7FL |
|---|
| 107877 | #define 0x80L |
|---|
| 107878 | //BIF_CFG_DEV0_EPF0_VF13_1_BIST |
|---|
| 107879 | #define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 107880 | #define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 107881 | #define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 107882 | #define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 107883 | #define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 107884 | #define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 107885 | //BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1 |
|---|
| 107886 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 107887 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107888 | //BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2 |
|---|
| 107889 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 107890 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107891 | //BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3 |
|---|
| 107892 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 107893 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107894 | //BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4 |
|---|
| 107895 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 107896 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107897 | //BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5 |
|---|
| 107898 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 107899 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107900 | //BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6 |
|---|
| 107901 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 107902 | #define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107903 | //BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR |
|---|
| 107904 | #define BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 107905 | #define BIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 107906 | //BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID |
|---|
| 107907 | #define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 107908 | #define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 107909 | #define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 107910 | #define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 107911 | //BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR |
|---|
| 107912 | #define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 107913 | #define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 107914 | //BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR |
|---|
| 107915 | #define BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 107916 | #define BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 107917 | //BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE |
|---|
| 107918 | #define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 107919 | #define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 107920 | //BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN |
|---|
| 107921 | #define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 107922 | #define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 107923 | //BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT |
|---|
| 107924 | #define BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 107925 | #define BIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 107926 | //BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY |
|---|
| 107927 | #define BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 107928 | #define BIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 107929 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST |
|---|
| 107930 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 107931 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 107932 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 107933 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 107934 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP |
|---|
| 107935 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 107936 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 107937 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 107938 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 107939 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 107940 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 107941 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 107942 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 107943 | //BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP |
|---|
| 107944 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 107945 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 107946 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 107947 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 107948 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 107949 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 107950 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 107951 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 107952 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 107953 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 107954 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 107955 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 107956 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 107957 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 107958 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 107959 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 107960 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 107961 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 107962 | //BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL |
|---|
| 107963 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 107964 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 107965 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 107966 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 107967 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 107968 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 107969 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 107970 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 107971 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 107972 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 107973 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 107974 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 107975 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 107976 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 107977 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 107978 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 107979 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 107980 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 107981 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 107982 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 107983 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 107984 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 107985 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 107986 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 107987 | //BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS |
|---|
| 107988 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 107989 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 107990 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 107991 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 107992 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 107993 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 107994 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
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| 107995 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
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| 107996 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 107997 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
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| 107998 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
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| 107999 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
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| 108000 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
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| 108001 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
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| 108002 | //BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP |
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| 108003 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 108004 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 108005 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 108006 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 108007 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 108008 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 108009 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
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| 108010 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 108011 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
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| 108012 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 108013 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 108014 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
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| 108015 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
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| 108016 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
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| 108017 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 108018 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 108019 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 108020 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 108021 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 108022 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 108023 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 108024 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 108025 | //BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL |
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| 108026 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 108027 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
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| 108028 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 108029 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
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| 108030 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 108031 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 108032 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 108033 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 108034 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 108035 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 108036 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 108037 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 108038 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 108039 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 108040 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 108041 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 108042 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
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| 108043 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 108044 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 108045 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 108046 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 108047 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 108048 | //BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS |
|---|
| 108049 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 108050 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
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| 108051 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
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| 108052 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 108053 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 108054 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 108055 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
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| 108056 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
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| 108057 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 108058 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 108059 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 108060 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 108061 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
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| 108062 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 108063 | //BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2 |
|---|
| 108064 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 108065 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 108066 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 108067 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 108068 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 108069 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 108070 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 108071 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 108072 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
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| 108073 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
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| 108074 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
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| 108075 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 108076 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 108077 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 108078 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 108079 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 108080 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 108081 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
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| 108082 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 108083 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 108084 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 108085 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 108086 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 108087 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 108088 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 108089 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 108090 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 108091 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 108092 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 108093 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 108094 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 108095 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 108096 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 108097 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 108098 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 108099 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 108100 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 108101 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 108102 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 108103 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 108104 | //BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2 |
|---|
| 108105 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 108106 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 108107 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 108108 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 108109 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 108110 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 108111 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 108112 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 108113 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 108114 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 108115 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 108116 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 108117 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 108118 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 108119 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 108120 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 108121 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 108122 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 108123 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 108124 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 108125 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 108126 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 108127 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 108128 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 108129 | //BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2 |
|---|
| 108130 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 108131 | #define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 108132 | //BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2 |
|---|
| 108133 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 108134 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 108135 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 108136 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 108137 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 108138 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 108139 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 108140 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 108141 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 108142 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 108143 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 108144 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 108145 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 108146 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 108147 | //BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2 |
|---|
| 108148 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 108149 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 108150 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 108151 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 108152 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 108153 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 108154 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 108155 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 108156 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 108157 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 108158 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 108159 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 108160 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 108161 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 108162 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 108163 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 108164 | //BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2 |
|---|
| 108165 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 108166 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 108167 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 108168 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 108169 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 108170 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 108171 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 108172 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 108173 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 108174 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 108175 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 108176 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 108177 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 108178 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 108179 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 108180 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 108181 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 108182 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 108183 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 108184 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 108185 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 108186 | #define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 108187 | //BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST |
|---|
| 108188 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108189 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 108190 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 108191 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 108192 | //BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL |
|---|
| 108193 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 108194 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 108195 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 108196 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 108197 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 108198 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 108199 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 108200 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 108201 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 108202 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 108203 | //BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO |
|---|
| 108204 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 108205 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 108206 | //BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI |
|---|
| 108207 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 108208 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 108209 | //BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA |
|---|
| 108210 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 108211 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 108212 | //BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK |
|---|
| 108213 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 108214 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 108215 | //BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64 |
|---|
| 108216 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 108217 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 108218 | //BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64 |
|---|
| 108219 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 108220 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 108221 | //BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING |
|---|
| 108222 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 108223 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 108224 | //BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64 |
|---|
| 108225 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 108226 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 108227 | //BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST |
|---|
| 108228 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108229 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 108230 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 108231 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 108232 | //BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL |
|---|
| 108233 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 108234 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 108235 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 108236 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 108237 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 108238 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 108239 | //BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE |
|---|
| 108240 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 108241 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 108242 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 108243 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 108244 | //BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA |
|---|
| 108245 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 108246 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 108247 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 108248 | #define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 108249 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 108250 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108251 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 108252 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 108253 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 108254 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 108255 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 108256 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 108257 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 108258 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 108259 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 108260 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 108261 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 108262 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 108263 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 108264 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 108265 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 108266 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 108267 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 108268 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 108269 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 108270 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108271 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 108272 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 108273 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 108274 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 108275 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 108276 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 108277 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 108278 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 108279 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 108280 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 108281 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 108282 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 108283 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 108284 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 108285 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 108286 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 108287 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 108288 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 108289 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 108290 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 108291 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 108292 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 108293 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 108294 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 108295 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 108296 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 108297 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 108298 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 108299 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 108300 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 108301 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 108302 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 108303 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 108304 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 108305 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 108306 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 108307 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 108308 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 108309 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK |
|---|
| 108310 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 108311 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 108312 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 108313 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 108314 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 108315 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 108316 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 108317 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 108318 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 108319 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 108320 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 108321 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 108322 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 108323 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 108324 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 108325 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 108326 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 108327 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 108328 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 108329 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 108330 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 108331 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 108332 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 108333 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 108334 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 108335 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 108336 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 108337 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 108338 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 108339 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 108340 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 108341 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 108342 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 108343 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 108344 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 108345 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 108346 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 108347 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 108348 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 108349 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 108350 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 108351 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 108352 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 108353 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 108354 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 108355 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 108356 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 108357 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 108358 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 108359 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 108360 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 108361 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 108362 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 108363 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 108364 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 108365 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 108366 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 108367 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 108368 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 108369 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 108370 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 108371 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 108372 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 108373 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 108374 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 108375 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS |
|---|
| 108376 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 108377 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 108378 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 108379 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 108380 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 108381 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 108382 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 108383 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 108384 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 108385 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 108386 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 108387 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 108388 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 108389 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 108390 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 108391 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 108392 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK |
|---|
| 108393 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 108394 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 108395 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 108396 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 108397 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 108398 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 108399 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 108400 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 108401 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 108402 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 108403 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 108404 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 108405 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 108406 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 108407 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 108408 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 108409 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 108410 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 108411 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 108412 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 108413 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 108414 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 108415 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 108416 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 108417 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 108418 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 108419 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 108420 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 108421 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 108422 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 108423 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 108424 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 108425 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 108426 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 108427 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 108428 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0 |
|---|
| 108429 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 108430 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 108431 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1 |
|---|
| 108432 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 108433 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 108434 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2 |
|---|
| 108435 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 108436 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 108437 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3 |
|---|
| 108438 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 108439 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 108440 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 108441 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 108442 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 108443 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 108444 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 108445 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 108446 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 108447 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 108448 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 108449 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 108450 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 108451 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 108452 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 108453 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108454 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 108455 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 108456 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 108457 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 108458 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 108459 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP |
|---|
| 108460 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 108461 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 108462 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 108463 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 108464 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 108465 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 108466 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL |
|---|
| 108467 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 108468 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 108469 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 108470 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 108471 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 108472 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108473 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 108474 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 108475 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 108476 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 108477 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 108478 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP |
|---|
| 108479 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 108480 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 108481 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 108482 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 108483 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 108484 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 108485 | //BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL |
|---|
| 108486 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 108487 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 108488 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 108489 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 108490 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 108491 | #define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 108492 | |
|---|
| 108493 | |
|---|
| 108494 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp |
|---|
| 108495 | //BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID |
|---|
| 108496 | #define BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 108497 | #define BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 108498 | //BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID |
|---|
| 108499 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 108500 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 108501 | //BIF_CFG_DEV0_EPF0_VF14_1_COMMAND |
|---|
| 108502 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 108503 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 108504 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 108505 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 108506 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 108507 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 108508 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 108509 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 108510 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 108511 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 108512 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 108513 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 108514 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 108515 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 108516 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 108517 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 108518 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 108519 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 108520 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 108521 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 108522 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 108523 | #define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 108524 | //BIF_CFG_DEV0_EPF0_VF14_1_STATUS |
|---|
| 108525 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 108526 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 108527 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 108528 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 108529 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 108530 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 108531 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 108532 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 108533 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 108534 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 108535 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 108536 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 108537 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 108538 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 108539 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 108540 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 108541 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 108542 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 108543 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 108544 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 108545 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 108546 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 108547 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 108548 | #define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 108549 | //BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID |
|---|
| 108550 | #define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 108551 | #define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 108552 | #define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 108553 | #define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 108554 | //BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE |
|---|
| 108555 | #define BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 108556 | #define BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 108557 | //BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS |
|---|
| 108558 | #define BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 108559 | #define BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 108560 | //BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS |
|---|
| 108561 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 108562 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 108563 | //BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE |
|---|
| 108564 | #define BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 108565 | #define BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 108566 | //BIF_CFG_DEV0_EPF0_VF14_1_LATENCY |
|---|
| 108567 | #define BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 108568 | #define BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 108569 | //BIF_CFG_DEV0_EPF0_VF14_1_HEADER |
|---|
| 108570 | #define 0x0 |
|---|
| 108571 | #define 0x7 |
|---|
| 108572 | #define 0x7FL |
|---|
| 108573 | #define 0x80L |
|---|
| 108574 | //BIF_CFG_DEV0_EPF0_VF14_1_BIST |
|---|
| 108575 | #define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 108576 | #define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 108577 | #define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 108578 | #define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 108579 | #define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 108580 | #define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 108581 | //BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1 |
|---|
| 108582 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 108583 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 108584 | //BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2 |
|---|
| 108585 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 108586 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 108587 | //BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3 |
|---|
| 108588 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 108589 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 108590 | //BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4 |
|---|
| 108591 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 108592 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 108593 | //BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5 |
|---|
| 108594 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 108595 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 108596 | //BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6 |
|---|
| 108597 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 108598 | #define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 108599 | //BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR |
|---|
| 108600 | #define BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 108601 | #define BIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 108602 | //BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID |
|---|
| 108603 | #define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 108604 | #define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 108605 | #define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 108606 | #define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 108607 | //BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR |
|---|
| 108608 | #define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 108609 | #define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 108610 | //BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR |
|---|
| 108611 | #define BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 108612 | #define BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 108613 | //BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE |
|---|
| 108614 | #define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 108615 | #define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 108616 | //BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN |
|---|
| 108617 | #define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 108618 | #define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 108619 | //BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT |
|---|
| 108620 | #define BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 108621 | #define BIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 108622 | //BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY |
|---|
| 108623 | #define BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 108624 | #define BIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 108625 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST |
|---|
| 108626 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108627 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 108628 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 108629 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 108630 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP |
|---|
| 108631 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 108632 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 108633 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 108634 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 108635 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 108636 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 108637 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 108638 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 108639 | //BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP |
|---|
| 108640 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 108641 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 108642 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 108643 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 108644 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 108645 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 108646 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 108647 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 108648 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 108649 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 108650 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 108651 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 108652 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 108653 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 108654 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 108655 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 108656 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 108657 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 108658 | //BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL |
|---|
| 108659 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 108660 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 108661 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 108662 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 108663 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 108664 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 108665 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 108666 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 108667 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 108668 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 108669 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 108670 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 108671 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 108672 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 108673 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 108674 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 108675 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 108676 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 108677 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 108678 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 108679 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 108680 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 108681 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 108682 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 108683 | //BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS |
|---|
| 108684 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 108685 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 108686 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 108687 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 108688 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 108689 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 108690 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 108691 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 108692 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 108693 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 108694 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 108695 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 108696 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 108697 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 108698 | //BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP |
|---|
| 108699 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 108700 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 108701 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 108702 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 108703 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 108704 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 108705 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 108706 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 108707 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 108708 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 108709 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 108710 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 108711 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 108712 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 108713 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 108714 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 108715 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 108716 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 108717 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 108718 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 108719 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 108720 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 108721 | //BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL |
|---|
| 108722 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 108723 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 108724 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 108725 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 108726 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 108727 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 108728 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 108729 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 108730 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 108731 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 108732 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 108733 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 108734 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 108735 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 108736 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 108737 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 108738 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 108739 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 108740 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 108741 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 108742 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 108743 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 108744 | //BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS |
|---|
| 108745 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 108746 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 108747 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 108748 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 108749 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 108750 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 108751 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 108752 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 108753 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 108754 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 108755 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 108756 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 108757 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 108758 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 108759 | //BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2 |
|---|
| 108760 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 108761 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 108762 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 108763 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 108764 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 108765 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 108766 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 108767 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 108768 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 108769 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 108770 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 108771 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 108772 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 108773 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 108774 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 108775 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 108776 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 108777 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 108778 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 108779 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 108780 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 108781 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 108782 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 108783 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 108784 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 108785 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 108786 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 108787 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 108788 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 108789 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 108790 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 108791 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 108792 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 108793 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 108794 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 108795 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 108796 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 108797 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 108798 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 108799 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 108800 | //BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2 |
|---|
| 108801 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 108802 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 108803 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 108804 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 108805 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 108806 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 108807 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 108808 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 108809 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 108810 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 108811 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 108812 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 108813 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 108814 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 108815 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 108816 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 108817 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 108818 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 108819 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 108820 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 108821 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 108822 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 108823 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 108824 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 108825 | //BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2 |
|---|
| 108826 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 108827 | #define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 108828 | //BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2 |
|---|
| 108829 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 108830 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 108831 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 108832 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 108833 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 108834 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 108835 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 108836 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 108837 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 108838 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 108839 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 108840 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 108841 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 108842 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 108843 | //BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2 |
|---|
| 108844 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 108845 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 108846 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 108847 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 108848 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 108849 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 108850 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 108851 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 108852 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 108853 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 108854 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 108855 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 108856 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 108857 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 108858 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 108859 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 108860 | //BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2 |
|---|
| 108861 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 108862 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 108863 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 108864 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 108865 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 108866 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 108867 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 108868 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 108869 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 108870 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 108871 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 108872 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 108873 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 108874 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 108875 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 108876 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 108877 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 108878 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 108879 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 108880 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 108881 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 108882 | #define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 108883 | //BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST |
|---|
| 108884 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108885 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 108886 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 108887 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 108888 | //BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL |
|---|
| 108889 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 108890 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 108891 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 108892 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 108893 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 108894 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 108895 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 108896 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 108897 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 108898 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 108899 | //BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO |
|---|
| 108900 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 108901 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 108902 | //BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI |
|---|
| 108903 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 108904 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 108905 | //BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA |
|---|
| 108906 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 108907 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 108908 | //BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK |
|---|
| 108909 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 108910 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 108911 | //BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64 |
|---|
| 108912 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 108913 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 108914 | //BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64 |
|---|
| 108915 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 108916 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 108917 | //BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING |
|---|
| 108918 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 108919 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 108920 | //BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64 |
|---|
| 108921 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 108922 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 108923 | //BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST |
|---|
| 108924 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108925 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 108926 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 108927 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 108928 | //BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL |
|---|
| 108929 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 108930 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 108931 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 108932 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 108933 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 108934 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 108935 | //BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE |
|---|
| 108936 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 108937 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 108938 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 108939 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 108940 | //BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA |
|---|
| 108941 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 108942 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 108943 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 108944 | #define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 108945 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 108946 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108947 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 108948 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 108949 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 108950 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 108951 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 108952 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 108953 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 108954 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 108955 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 108956 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 108957 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 108958 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 108959 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 108960 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 108961 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 108962 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 108963 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 108964 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 108965 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 108966 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 108967 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 108968 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 108969 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 108970 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 108971 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 108972 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 108973 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 108974 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 108975 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 108976 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 108977 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 108978 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 108979 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 108980 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 108981 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 108982 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 108983 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 108984 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 108985 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 108986 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 108987 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 108988 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 108989 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 108990 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 108991 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 108992 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 108993 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 108994 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 108995 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 108996 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 108997 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 108998 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 108999 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 109000 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 109001 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 109002 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 109003 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 109004 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 109005 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK |
|---|
| 109006 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 109007 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 109008 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 109009 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 109010 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 109011 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 109012 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 109013 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 109014 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 109015 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 109016 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 109017 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 109018 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 109019 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 109020 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 109021 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 109022 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 109023 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 109024 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 109025 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 109026 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 109027 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 109028 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 109029 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 109030 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 109031 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 109032 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 109033 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 109034 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 109035 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 109036 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 109037 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 109038 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 109039 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 109040 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 109041 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 109042 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 109043 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 109044 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 109045 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 109046 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 109047 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 109048 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 109049 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 109050 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 109051 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 109052 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 109053 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 109054 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 109055 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 109056 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 109057 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 109058 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 109059 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 109060 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 109061 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 109062 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 109063 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 109064 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 109065 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 109066 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 109067 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 109068 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 109069 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 109070 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 109071 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS |
|---|
| 109072 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 109073 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 109074 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 109075 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 109076 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 109077 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 109078 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 109079 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 109080 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 109081 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 109082 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 109083 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 109084 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 109085 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 109086 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 109087 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 109088 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK |
|---|
| 109089 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 109090 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 109091 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 109092 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 109093 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 109094 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 109095 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 109096 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 109097 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 109098 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 109099 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 109100 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 109101 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 109102 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 109103 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 109104 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 109105 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 109106 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 109107 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 109108 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 109109 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 109110 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 109111 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 109112 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 109113 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 109114 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 109115 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 109116 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 109117 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 109118 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 109119 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 109120 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 109121 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 109122 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 109123 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 109124 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0 |
|---|
| 109125 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 109126 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 109127 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1 |
|---|
| 109128 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 109129 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 109130 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2 |
|---|
| 109131 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 109132 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 109133 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3 |
|---|
| 109134 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 109135 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 109136 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 109137 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 109138 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 109139 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 109140 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 109141 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 109142 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 109143 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 109144 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 109145 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 109146 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 109147 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 109148 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 109149 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 109150 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 109151 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 109152 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 109153 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 109154 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 109155 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP |
|---|
| 109156 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 109157 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 109158 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 109159 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 109160 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 109161 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 109162 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL |
|---|
| 109163 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 109164 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 109165 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 109166 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 109167 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 109168 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 109169 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 109170 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 109171 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 109172 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 109173 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 109174 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP |
|---|
| 109175 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 109176 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 109177 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 109178 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 109179 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 109180 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 109181 | //BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL |
|---|
| 109182 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 109183 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 109184 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 109185 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 109186 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 109187 | #define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 109188 | |
|---|
| 109189 | |
|---|
| 109190 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp |
|---|
| 109191 | //BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID |
|---|
| 109192 | #define BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 109193 | #define BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 109194 | //BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID |
|---|
| 109195 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 109196 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 109197 | //BIF_CFG_DEV0_EPF0_VF15_1_COMMAND |
|---|
| 109198 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 109199 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 109200 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 109201 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 109202 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 109203 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 109204 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 109205 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 109206 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 109207 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 109208 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 109209 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 109210 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 109211 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 109212 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 109213 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 109214 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 109215 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 109216 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 109217 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 109218 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 109219 | #define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 109220 | //BIF_CFG_DEV0_EPF0_VF15_1_STATUS |
|---|
| 109221 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 109222 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 109223 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 109224 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 109225 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 109226 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 109227 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 109228 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 109229 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 109230 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 109231 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 109232 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 109233 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 109234 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 109235 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 109236 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 109237 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 109238 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 109239 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 109240 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 109241 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 109242 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 109243 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 109244 | #define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 109245 | //BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID |
|---|
| 109246 | #define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 109247 | #define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 109248 | #define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 109249 | #define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 109250 | //BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE |
|---|
| 109251 | #define BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 109252 | #define BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 109253 | //BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS |
|---|
| 109254 | #define BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 109255 | #define BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 109256 | //BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS |
|---|
| 109257 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 109258 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 109259 | //BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE |
|---|
| 109260 | #define BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 109261 | #define BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 109262 | //BIF_CFG_DEV0_EPF0_VF15_1_LATENCY |
|---|
| 109263 | #define BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 109264 | #define BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 109265 | //BIF_CFG_DEV0_EPF0_VF15_1_HEADER |
|---|
| 109266 | #define 0x0 |
|---|
| 109267 | #define 0x7 |
|---|
| 109268 | #define 0x7FL |
|---|
| 109269 | #define 0x80L |
|---|
| 109270 | //BIF_CFG_DEV0_EPF0_VF15_1_BIST |
|---|
| 109271 | #define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 109272 | #define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 109273 | #define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 109274 | #define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 109275 | #define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 109276 | #define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 109277 | //BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1 |
|---|
| 109278 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 109279 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109280 | //BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2 |
|---|
| 109281 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 109282 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109283 | //BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3 |
|---|
| 109284 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 109285 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109286 | //BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4 |
|---|
| 109287 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 109288 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109289 | //BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5 |
|---|
| 109290 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 109291 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109292 | //BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6 |
|---|
| 109293 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 109294 | #define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109295 | //BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR |
|---|
| 109296 | #define BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 109297 | #define BIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 109298 | //BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID |
|---|
| 109299 | #define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 109300 | #define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 109301 | #define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 109302 | #define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 109303 | //BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR |
|---|
| 109304 | #define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 109305 | #define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109306 | //BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR |
|---|
| 109307 | #define BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 109308 | #define BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 109309 | //BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE |
|---|
| 109310 | #define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 109311 | #define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 109312 | //BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN |
|---|
| 109313 | #define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 109314 | #define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 109315 | //BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT |
|---|
| 109316 | #define BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 109317 | #define BIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 109318 | //BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY |
|---|
| 109319 | #define BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 109320 | #define BIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 109321 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST |
|---|
| 109322 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 109323 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 109324 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 109325 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 109326 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP |
|---|
| 109327 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 109328 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 109329 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 109330 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 109331 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 109332 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 109333 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 109334 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 109335 | //BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP |
|---|
| 109336 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 109337 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 109338 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 109339 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 109340 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 109341 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 109342 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 109343 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 109344 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 109345 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 109346 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 109347 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 109348 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 109349 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 109350 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 109351 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 109352 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 109353 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 109354 | //BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL |
|---|
| 109355 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 109356 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 109357 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 109358 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 109359 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 109360 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 109361 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 109362 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 109363 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 109364 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 109365 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 109366 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 109367 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 109368 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 109369 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 109370 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 109371 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 109372 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 109373 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 109374 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 109375 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 109376 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 109377 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 109378 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 109379 | //BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS |
|---|
| 109380 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 109381 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 109382 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 109383 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 109384 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 109385 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 109386 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 109387 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 109388 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 109389 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 109390 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 109391 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 109392 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 109393 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 109394 | //BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP |
|---|
| 109395 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 109396 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 109397 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 109398 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 109399 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 109400 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 109401 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 109402 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 109403 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 109404 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 109405 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 109406 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 109407 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 109408 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 109409 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 109410 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 109411 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 109412 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 109413 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 109414 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 109415 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 109416 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 109417 | //BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL |
|---|
| 109418 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 109419 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 109420 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 109421 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 109422 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 109423 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 109424 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 109425 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 109426 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 109427 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 109428 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 109429 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 109430 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 109431 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 109432 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 109433 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 109434 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 109435 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 109436 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 109437 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 109438 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 109439 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 109440 | //BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS |
|---|
| 109441 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 109442 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 109443 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 109444 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 109445 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 109446 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 109447 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 109448 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 109449 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 109450 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 109451 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 109452 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 109453 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 109454 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 109455 | //BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2 |
|---|
| 109456 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 109457 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 109458 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 109459 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 109460 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 109461 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 109462 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 109463 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 109464 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 109465 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 109466 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 109467 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 109468 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 109469 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 109470 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 109471 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 109472 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 109473 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 109474 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 109475 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 109476 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 109477 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 109478 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 109479 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 109480 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 109481 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 109482 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 109483 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 109484 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 109485 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 109486 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 109487 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 109488 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 109489 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 109490 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 109491 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 109492 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 109493 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 109494 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 109495 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 109496 | //BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2 |
|---|
| 109497 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 109498 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 109499 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 109500 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 109501 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 109502 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 109503 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 109504 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 109505 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 109506 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 109507 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 109508 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 109509 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 109510 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 109511 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 109512 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 109513 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 109514 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 109515 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 109516 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 109517 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 109518 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 109519 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 109520 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 109521 | //BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2 |
|---|
| 109522 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 109523 | #define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 109524 | //BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2 |
|---|
| 109525 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 109526 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 109527 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 109528 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 109529 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 109530 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 109531 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 109532 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 109533 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 109534 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 109535 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 109536 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 109537 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 109538 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 109539 | //BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2 |
|---|
| 109540 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 109541 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 109542 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 109543 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 109544 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 109545 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 109546 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 109547 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 109548 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 109549 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 109550 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 109551 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 109552 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 109553 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 109554 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 109555 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 109556 | //BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2 |
|---|
| 109557 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 109558 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 109559 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 109560 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 109561 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 109562 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 109563 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 109564 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 109565 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 109566 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 109567 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 109568 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 109569 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 109570 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 109571 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 109572 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 109573 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 109574 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 109575 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 109576 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 109577 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 109578 | #define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 109579 | //BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST |
|---|
| 109580 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 109581 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 109582 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 109583 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 109584 | //BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL |
|---|
| 109585 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 109586 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 109587 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 109588 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 109589 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 109590 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 109591 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 109592 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 109593 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 109594 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 109595 | //BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO |
|---|
| 109596 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 109597 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 109598 | //BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI |
|---|
| 109599 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 109600 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 109601 | //BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA |
|---|
| 109602 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 109603 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 109604 | //BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK |
|---|
| 109605 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 109606 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 109607 | //BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64 |
|---|
| 109608 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 109609 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 109610 | //BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64 |
|---|
| 109611 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 109612 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 109613 | //BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING |
|---|
| 109614 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 109615 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 109616 | //BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64 |
|---|
| 109617 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 109618 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 109619 | //BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST |
|---|
| 109620 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 109621 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 109622 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 109623 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 109624 | //BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL |
|---|
| 109625 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 109626 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 109627 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 109628 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 109629 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 109630 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 109631 | //BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE |
|---|
| 109632 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 109633 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 109634 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 109635 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 109636 | //BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA |
|---|
| 109637 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 109638 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 109639 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 109640 | #define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 109641 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 109642 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 109643 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 109644 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 109645 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 109646 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 109647 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 109648 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 109649 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 109650 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 109651 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 109652 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 109653 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 109654 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 109655 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 109656 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 109657 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 109658 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 109659 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 109660 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 109661 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 109662 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 109663 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 109664 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 109665 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 109666 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 109667 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 109668 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS |
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| 109669 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 109670 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 109671 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 109672 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 109673 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 109674 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 109675 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 109676 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 109677 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 109678 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 109679 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 109680 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 109681 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 109682 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 109683 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 109684 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 109685 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 109686 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 109687 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 109688 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 109689 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 109690 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 109691 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 109692 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 109693 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 109694 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 109695 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 109696 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 109697 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 109698 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 109699 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 109700 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 109701 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK |
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| 109702 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 109703 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 109704 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 109705 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 109706 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 109707 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 109708 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 109709 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 109710 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 109711 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 109712 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 109713 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 109714 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 109715 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 109716 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 109717 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 109718 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 109719 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 109720 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 109721 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 109722 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 109723 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 109724 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 109725 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 109726 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 109727 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 109728 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 109729 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 109730 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 109731 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 109732 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 109733 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 109734 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY |
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| 109735 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 109736 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 109737 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 109738 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 109739 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 109740 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 109741 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 109742 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 109743 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 109744 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 109745 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 109746 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 109747 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 109748 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 109749 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 109750 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 109751 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 109752 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 109753 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 109754 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 109755 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 109756 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 109757 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 109758 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 109759 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 109760 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 109761 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 109762 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 109763 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 109764 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 109765 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 109766 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 109767 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS |
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| 109768 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 109769 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 109770 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 109771 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 109772 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 109773 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 109774 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 109775 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 109776 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 109777 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 109778 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 109779 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 109780 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 109781 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 109782 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 109783 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 109784 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK |
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| 109785 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 109786 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 109787 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 109788 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 109789 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 109790 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 109791 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 109792 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 109793 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 109794 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 109795 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 109796 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
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| 109797 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
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| 109798 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
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| 109799 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
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| 109800 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 109801 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL |
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| 109802 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 109803 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 109804 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 109805 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
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| 109806 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
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| 109807 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 109808 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 109809 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 109810 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 109811 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 109812 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 109813 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 109814 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 109815 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 109816 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 109817 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 109818 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 109819 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 109820 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0 |
|---|
| 109821 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 109822 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 109823 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1 |
|---|
| 109824 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 109825 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 109826 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2 |
|---|
| 109827 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 109828 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 109829 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3 |
|---|
| 109830 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 109831 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 109832 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 109833 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 109834 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 109835 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 109836 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 109837 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 109838 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 109839 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 109840 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 109841 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 109842 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 109843 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 109844 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 109845 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 109846 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 109847 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 109848 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 109849 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 109850 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 109851 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP |
|---|
| 109852 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 109853 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 109854 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 109855 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 109856 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 109857 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 109858 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL |
|---|
| 109859 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 109860 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 109861 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 109862 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 109863 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 109864 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 109865 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 109866 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 109867 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 109868 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 109869 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 109870 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP |
|---|
| 109871 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 109872 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 109873 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 109874 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 109875 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 109876 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 109877 | //BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL |
|---|
| 109878 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 109879 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 109880 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 109881 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 109882 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 109883 | #define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 109884 | |
|---|
| 109885 | |
|---|
| 109886 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp |
|---|
| 109887 | //BIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID |
|---|
| 109888 | #define BIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 109889 | #define BIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 109890 | //BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID |
|---|
| 109891 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 109892 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 109893 | //BIF_CFG_DEV0_EPF0_VF16_1_COMMAND |
|---|
| 109894 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 109895 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 109896 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 109897 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 109898 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 109899 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 109900 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 109901 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 109902 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 109903 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 109904 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 109905 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 109906 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 109907 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 109908 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 109909 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 109910 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 109911 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 109912 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 109913 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 109914 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 109915 | #define BIF_CFG_DEV0_EPF0_VF16_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 109916 | //BIF_CFG_DEV0_EPF0_VF16_1_STATUS |
|---|
| 109917 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 109918 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 109919 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 109920 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 109921 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 109922 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 109923 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 109924 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 109925 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 109926 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 109927 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 109928 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 109929 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 109930 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 109931 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 109932 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 109933 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 109934 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 109935 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 109936 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 109937 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 109938 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 109939 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 109940 | #define BIF_CFG_DEV0_EPF0_VF16_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 109941 | //BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID |
|---|
| 109942 | #define BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 109943 | #define BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 109944 | #define BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 109945 | #define BIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 109946 | //BIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE |
|---|
| 109947 | #define BIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 109948 | #define BIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 109949 | //BIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS |
|---|
| 109950 | #define BIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 109951 | #define BIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 109952 | //BIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS |
|---|
| 109953 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 109954 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 109955 | //BIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE |
|---|
| 109956 | #define BIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 109957 | #define BIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 109958 | //BIF_CFG_DEV0_EPF0_VF16_1_LATENCY |
|---|
| 109959 | #define BIF_CFG_DEV0_EPF0_VF16_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 109960 | #define BIF_CFG_DEV0_EPF0_VF16_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 109961 | //BIF_CFG_DEV0_EPF0_VF16_1_HEADER |
|---|
| 109962 | #define 0x0 |
|---|
| 109963 | #define 0x7 |
|---|
| 109964 | #define 0x7FL |
|---|
| 109965 | #define 0x80L |
|---|
| 109966 | //BIF_CFG_DEV0_EPF0_VF16_1_BIST |
|---|
| 109967 | #define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 109968 | #define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 109969 | #define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 109970 | #define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 109971 | #define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 109972 | #define BIF_CFG_DEV0_EPF0_VF16_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 109973 | //BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1 |
|---|
| 109974 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 109975 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109976 | //BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2 |
|---|
| 109977 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 109978 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109979 | //BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3 |
|---|
| 109980 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 109981 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109982 | //BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4 |
|---|
| 109983 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 109984 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109985 | //BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5 |
|---|
| 109986 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 109987 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109988 | //BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6 |
|---|
| 109989 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 109990 | #define BIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 109991 | //BIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR |
|---|
| 109992 | #define BIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 109993 | #define BIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 109994 | //BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID |
|---|
| 109995 | #define BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 109996 | #define BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 109997 | #define BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 109998 | #define BIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 109999 | //BIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR |
|---|
| 110000 | #define BIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 110001 | #define BIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 110002 | //BIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR |
|---|
| 110003 | #define BIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 110004 | #define BIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 110005 | //BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE |
|---|
| 110006 | #define BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 110007 | #define BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 110008 | //BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN |
|---|
| 110009 | #define BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 110010 | #define BIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 110011 | //BIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT |
|---|
| 110012 | #define BIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 110013 | #define BIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 110014 | //BIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY |
|---|
| 110015 | #define BIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 110016 | #define BIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 110017 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST |
|---|
| 110018 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 110019 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 110020 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 110021 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 110022 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP |
|---|
| 110023 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 110024 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 110025 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 110026 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 110027 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 110028 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 110029 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 110030 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 110031 | //BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP |
|---|
| 110032 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 110033 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 110034 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 110035 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 110036 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 110037 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 110038 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 110039 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 110040 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 110041 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 110042 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 110043 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 110044 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 110045 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 110046 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 110047 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 110048 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 110049 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 110050 | //BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL |
|---|
| 110051 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 110052 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 110053 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 110054 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 110055 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 110056 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 110057 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 110058 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 110059 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 110060 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 110061 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 110062 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 110063 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 110064 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 110065 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 110066 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 110067 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 110068 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 110069 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 110070 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 110071 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 110072 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 110073 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 110074 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 110075 | //BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS |
|---|
| 110076 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 110077 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 110078 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 110079 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 110080 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 110081 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 110082 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 110083 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 110084 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 110085 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 110086 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 110087 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 110088 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 110089 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 110090 | //BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP |
|---|
| 110091 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 110092 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 110093 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 110094 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 110095 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 110096 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 110097 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 110098 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 110099 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 110100 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 110101 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 110102 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 110103 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 110104 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 110105 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 110106 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 110107 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 110108 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 110109 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 110110 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 110111 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 110112 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 110113 | //BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL |
|---|
| 110114 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 110115 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 110116 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 110117 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 110118 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 110119 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 110120 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 110121 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 110122 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 110123 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 110124 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 110125 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 110126 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 110127 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 110128 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 110129 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 110130 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 110131 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 110132 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 110133 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 110134 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 110135 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 110136 | //BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS |
|---|
| 110137 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 110138 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 110139 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 110140 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 110141 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 110142 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 110143 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 110144 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 110145 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 110146 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 110147 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 110148 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 110149 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 110150 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 110151 | //BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2 |
|---|
| 110152 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 110153 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 110154 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 110155 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 110156 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 110157 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 110158 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 110159 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 110160 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 110161 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 110162 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 110163 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 110164 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 110165 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 110166 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 110167 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 110168 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 110169 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 110170 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 110171 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 110172 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 110173 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 110174 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 110175 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 110176 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 110177 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 110178 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 110179 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 110180 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 110181 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 110182 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 110183 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 110184 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 110185 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 110186 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 110187 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 110188 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 110189 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 110190 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 110191 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 110192 | //BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2 |
|---|
| 110193 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 110194 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 110195 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 110196 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 110197 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 110198 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 110199 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 110200 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 110201 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 110202 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 110203 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 110204 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 110205 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 110206 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 110207 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 110208 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 110209 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 110210 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 110211 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 110212 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 110213 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 110214 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 110215 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 110216 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 110217 | //BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2 |
|---|
| 110218 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 110219 | #define BIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 110220 | //BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2 |
|---|
| 110221 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 110222 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 110223 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 110224 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 110225 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 110226 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 110227 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 110228 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 110229 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 110230 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 110231 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 110232 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 110233 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 110234 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 110235 | //BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2 |
|---|
| 110236 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 110237 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 110238 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 110239 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 110240 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 110241 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 110242 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 110243 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 110244 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 110245 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 110246 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 110247 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 110248 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 110249 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 110250 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 110251 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 110252 | //BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2 |
|---|
| 110253 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 110254 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 110255 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 110256 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 110257 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 110258 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 110259 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 110260 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 110261 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 110262 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 110263 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 110264 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 110265 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 110266 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 110267 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 110268 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 110269 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 110270 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 110271 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 110272 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 110273 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 110274 | #define BIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 110275 | //BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST |
|---|
| 110276 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 110277 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 110278 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 110279 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 110280 | //BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL |
|---|
| 110281 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 110282 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 110283 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 110284 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 110285 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 110286 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 110287 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 110288 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 110289 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 110290 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 110291 | //BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO |
|---|
| 110292 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 110293 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 110294 | //BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI |
|---|
| 110295 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 110296 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 110297 | //BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA |
|---|
| 110298 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 110299 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 110300 | //BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK |
|---|
| 110301 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 110302 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 110303 | //BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64 |
|---|
| 110304 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 110305 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 110306 | //BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64 |
|---|
| 110307 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 110308 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 110309 | //BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING |
|---|
| 110310 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 110311 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 110312 | //BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64 |
|---|
| 110313 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 110314 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 110315 | //BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST |
|---|
| 110316 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 110317 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 110318 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 110319 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 110320 | //BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL |
|---|
| 110321 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 110322 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 110323 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 110324 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 110325 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 110326 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 110327 | //BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE |
|---|
| 110328 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 110329 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 110330 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
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| 110331 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
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| 110332 | //BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA |
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| 110333 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
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| 110334 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
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| 110335 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
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| 110336 | #define BIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
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| 110337 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
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| 110338 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 110339 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 110340 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 110341 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 110342 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 110343 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 110344 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR |
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| 110345 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
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| 110346 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
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| 110347 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
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| 110348 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
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| 110349 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
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| 110350 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
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| 110351 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1 |
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| 110352 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 110353 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 110354 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2 |
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| 110355 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 110356 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 110357 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 110358 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 110359 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 110360 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 110361 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 110362 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 110363 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 110364 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 110365 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 110366 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 110367 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 110368 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 110369 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 110370 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 110371 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 110372 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 110373 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 110374 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 110375 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 110376 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 110377 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 110378 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 110379 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 110380 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 110381 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 110382 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 110383 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 110384 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 110385 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 110386 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 110387 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 110388 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 110389 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 110390 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 110391 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 110392 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 110393 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 110394 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 110395 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 110396 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 110397 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK |
|---|
| 110398 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 110399 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 110400 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 110401 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 110402 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 110403 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 110404 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 110405 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 110406 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 110407 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 110408 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 110409 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 110410 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 110411 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 110412 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 110413 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 110414 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 110415 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 110416 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 110417 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 110418 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 110419 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 110420 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 110421 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 110422 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 110423 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 110424 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 110425 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 110426 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 110427 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 110428 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 110429 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 110430 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 110431 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 110432 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 110433 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 110434 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 110435 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 110436 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 110437 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 110438 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 110439 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 110440 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 110441 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 110442 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 110443 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 110444 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 110445 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 110446 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 110447 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 110448 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 110449 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 110450 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 110451 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 110452 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 110453 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 110454 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 110455 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 110456 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 110457 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 110458 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 110459 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 110460 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 110461 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 110462 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 110463 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS |
|---|
| 110464 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 110465 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 110466 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 110467 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 110468 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 110469 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 110470 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 110471 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 110472 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 110473 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 110474 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 110475 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 110476 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 110477 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 110478 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 110479 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 110480 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK |
|---|
| 110481 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 110482 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 110483 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 110484 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 110485 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 110486 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 110487 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 110488 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 110489 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 110490 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 110491 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 110492 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 110493 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 110494 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 110495 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 110496 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 110497 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 110498 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 110499 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 110500 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 110501 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 110502 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 110503 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 110504 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 110505 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 110506 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 110507 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 110508 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 110509 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 110510 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 110511 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 110512 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 110513 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 110514 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 110515 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 110516 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0 |
|---|
| 110517 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 110518 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 110519 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1 |
|---|
| 110520 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 110521 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 110522 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2 |
|---|
| 110523 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 110524 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 110525 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3 |
|---|
| 110526 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 110527 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 110528 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 110529 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 110530 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 110531 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 110532 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 110533 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 110534 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 110535 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 110536 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 110537 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 110538 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 110539 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 110540 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 110541 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 110542 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 110543 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 110544 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 110545 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 110546 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 110547 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP |
|---|
| 110548 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 110549 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 110550 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 110551 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 110552 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 110553 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 110554 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL |
|---|
| 110555 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 110556 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 110557 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 110558 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 110559 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 110560 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 110561 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 110562 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 110563 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 110564 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 110565 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 110566 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP |
|---|
| 110567 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 110568 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 110569 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 110570 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 110571 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 110572 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 110573 | //BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL |
|---|
| 110574 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 110575 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 110576 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 110577 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 110578 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 110579 | #define BIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 110580 | |
|---|
| 110581 | |
|---|
| 110582 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp |
|---|
| 110583 | //BIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID |
|---|
| 110584 | #define BIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 110585 | #define BIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 110586 | //BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID |
|---|
| 110587 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 110588 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 110589 | //BIF_CFG_DEV0_EPF0_VF17_1_COMMAND |
|---|
| 110590 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 110591 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 110592 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 110593 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 110594 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 110595 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 110596 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 110597 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 110598 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 110599 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 110600 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 110601 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 110602 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 110603 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 110604 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 110605 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 110606 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 110607 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 110608 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 110609 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 110610 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 110611 | #define BIF_CFG_DEV0_EPF0_VF17_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 110612 | //BIF_CFG_DEV0_EPF0_VF17_1_STATUS |
|---|
| 110613 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 110614 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 110615 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 110616 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 110617 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 110618 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 110619 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 110620 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 110621 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 110622 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 110623 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 110624 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 110625 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 110626 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 110627 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 110628 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 110629 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 110630 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 110631 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 110632 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 110633 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 110634 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 110635 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 110636 | #define BIF_CFG_DEV0_EPF0_VF17_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 110637 | //BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID |
|---|
| 110638 | #define BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 110639 | #define BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 110640 | #define BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 110641 | #define BIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 110642 | //BIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE |
|---|
| 110643 | #define BIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 110644 | #define BIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 110645 | //BIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS |
|---|
| 110646 | #define BIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 110647 | #define BIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 110648 | //BIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS |
|---|
| 110649 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 110650 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 110651 | //BIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE |
|---|
| 110652 | #define BIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 110653 | #define BIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 110654 | //BIF_CFG_DEV0_EPF0_VF17_1_LATENCY |
|---|
| 110655 | #define BIF_CFG_DEV0_EPF0_VF17_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 110656 | #define BIF_CFG_DEV0_EPF0_VF17_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 110657 | //BIF_CFG_DEV0_EPF0_VF17_1_HEADER |
|---|
| 110658 | #define 0x0 |
|---|
| 110659 | #define 0x7 |
|---|
| 110660 | #define 0x7FL |
|---|
| 110661 | #define 0x80L |
|---|
| 110662 | //BIF_CFG_DEV0_EPF0_VF17_1_BIST |
|---|
| 110663 | #define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 110664 | #define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 110665 | #define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 110666 | #define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 110667 | #define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 110668 | #define BIF_CFG_DEV0_EPF0_VF17_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 110669 | //BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1 |
|---|
| 110670 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 110671 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 110672 | //BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2 |
|---|
| 110673 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 110674 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 110675 | //BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3 |
|---|
| 110676 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 110677 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 110678 | //BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4 |
|---|
| 110679 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 110680 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 110681 | //BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5 |
|---|
| 110682 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 110683 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 110684 | //BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6 |
|---|
| 110685 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 110686 | #define BIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 110687 | //BIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR |
|---|
| 110688 | #define BIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 110689 | #define BIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 110690 | //BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID |
|---|
| 110691 | #define BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 110692 | #define BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 110693 | #define BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 110694 | #define BIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 110695 | //BIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR |
|---|
| 110696 | #define BIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 110697 | #define BIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 110698 | //BIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR |
|---|
| 110699 | #define BIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 110700 | #define BIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 110701 | //BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE |
|---|
| 110702 | #define BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 110703 | #define BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 110704 | //BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN |
|---|
| 110705 | #define BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 110706 | #define BIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 110707 | //BIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT |
|---|
| 110708 | #define BIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 110709 | #define BIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 110710 | //BIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY |
|---|
| 110711 | #define BIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 110712 | #define BIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 110713 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST |
|---|
| 110714 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 110715 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 110716 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 110717 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 110718 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP |
|---|
| 110719 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 110720 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 110721 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 110722 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 110723 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 110724 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 110725 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 110726 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 110727 | //BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP |
|---|
| 110728 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 110729 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 110730 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 110731 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 110732 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 110733 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 110734 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 110735 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 110736 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 110737 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 110738 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 110739 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 110740 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 110741 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 110742 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 110743 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 110744 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 110745 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 110746 | //BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL |
|---|
| 110747 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 110748 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 110749 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 110750 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 110751 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 110752 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 110753 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 110754 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 110755 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 110756 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 110757 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 110758 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 110759 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 110760 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 110761 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 110762 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 110763 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 110764 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 110765 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 110766 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 110767 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 110768 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 110769 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 110770 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 110771 | //BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS |
|---|
| 110772 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 110773 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 110774 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 110775 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 110776 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 110777 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 110778 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 110779 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 110780 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 110781 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 110782 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 110783 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 110784 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 110785 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 110786 | //BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP |
|---|
| 110787 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 110788 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 110789 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 110790 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 110791 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 110792 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 110793 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 110794 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 110795 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 110796 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 110797 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 110798 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 110799 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 110800 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 110801 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 110802 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 110803 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 110804 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 110805 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 110806 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 110807 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 110808 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 110809 | //BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL |
|---|
| 110810 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 110811 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 110812 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 110813 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 110814 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 110815 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 110816 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 110817 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 110818 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 110819 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 110820 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 110821 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 110822 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 110823 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 110824 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 110825 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 110826 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 110827 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 110828 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 110829 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 110830 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 110831 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 110832 | //BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS |
|---|
| 110833 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 110834 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 110835 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 110836 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 110837 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 110838 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 110839 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 110840 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 110841 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 110842 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 110843 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 110844 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 110845 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 110846 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 110847 | //BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2 |
|---|
| 110848 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 110849 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 110850 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 110851 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 110852 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 110853 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 110854 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 110855 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 110856 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 110857 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 110858 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 110859 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 110860 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 110861 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 110862 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 110863 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 110864 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 110865 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 110866 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 110867 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 110868 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 110869 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 110870 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 110871 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 110872 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 110873 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 110874 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 110875 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 110876 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 110877 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 110878 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 110879 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 110880 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 110881 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 110882 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 110883 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 110884 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 110885 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 110886 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 110887 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 110888 | //BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2 |
|---|
| 110889 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 110890 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 110891 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 110892 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 110893 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 110894 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 110895 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 110896 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 110897 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 110898 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 110899 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 110900 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 110901 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 110902 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 110903 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 110904 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 110905 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 110906 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 110907 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 110908 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 110909 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 110910 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 110911 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 110912 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 110913 | //BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2 |
|---|
| 110914 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 110915 | #define BIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 110916 | //BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2 |
|---|
| 110917 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 110918 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 110919 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 110920 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 110921 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 110922 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 110923 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 110924 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 110925 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 110926 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 110927 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 110928 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 110929 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 110930 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 110931 | //BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2 |
|---|
| 110932 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 110933 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 110934 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 110935 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 110936 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 110937 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 110938 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 110939 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 110940 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 110941 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 110942 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 110943 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 110944 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 110945 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 110946 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 110947 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 110948 | //BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2 |
|---|
| 110949 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 110950 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 110951 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 110952 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 110953 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 110954 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 110955 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 110956 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 110957 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 110958 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 110959 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 110960 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 110961 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 110962 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 110963 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 110964 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 110965 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 110966 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 110967 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 110968 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 110969 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 110970 | #define BIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 110971 | //BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST |
|---|
| 110972 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 110973 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 110974 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 110975 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 110976 | //BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL |
|---|
| 110977 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 110978 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 110979 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 110980 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 110981 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 110982 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 110983 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 110984 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 110985 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 110986 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 110987 | //BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO |
|---|
| 110988 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 110989 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 110990 | //BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI |
|---|
| 110991 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 110992 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 110993 | //BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA |
|---|
| 110994 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 110995 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 110996 | //BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK |
|---|
| 110997 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 110998 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 110999 | //BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64 |
|---|
| 111000 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
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| 111001 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
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| 111002 | //BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64 |
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| 111003 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
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| 111004 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
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| 111005 | //BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING |
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| 111006 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
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| 111007 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
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| 111008 | //BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64 |
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| 111009 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
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| 111010 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
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| 111011 | //BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST |
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| 111012 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 111013 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 111014 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 111015 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 111016 | //BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL |
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| 111017 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
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| 111018 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
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| 111019 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
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| 111020 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
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| 111021 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
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| 111022 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
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| 111023 | //BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE |
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| 111024 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
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| 111025 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
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| 111026 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
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| 111027 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
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| 111028 | //BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA |
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| 111029 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
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| 111030 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
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| 111031 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
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| 111032 | #define BIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
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| 111033 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
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| 111034 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 111035 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 111036 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 111037 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 111038 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 111039 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 111040 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR |
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| 111041 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
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| 111042 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
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| 111043 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
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| 111044 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
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| 111045 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
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| 111046 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
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| 111047 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1 |
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| 111048 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 111049 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 111050 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2 |
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| 111051 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 111052 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
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| 111053 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
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| 111054 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 111055 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 111056 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 111057 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 111058 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
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| 111059 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 111060 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS |
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| 111061 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 111062 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
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| 111063 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
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| 111064 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
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| 111065 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
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| 111066 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
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| 111067 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
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| 111068 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
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| 111069 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
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| 111070 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
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| 111071 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
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| 111072 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
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| 111073 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
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| 111074 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
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| 111075 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
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| 111076 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
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| 111077 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
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| 111078 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
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| 111079 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
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| 111080 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
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| 111081 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
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| 111082 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
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| 111083 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
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| 111084 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
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| 111085 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
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| 111086 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
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| 111087 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
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| 111088 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
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| 111089 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
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| 111090 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
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| 111091 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
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| 111092 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
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| 111093 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK |
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| 111094 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 111095 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 111096 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 111097 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 111098 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 111099 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 111100 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 111101 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 111102 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 111103 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 111104 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 111105 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 111106 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 111107 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 111108 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 111109 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 111110 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 111111 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 111112 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 111113 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 111114 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 111115 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 111116 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 111117 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 111118 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 111119 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 111120 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 111121 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 111122 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 111123 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 111124 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 111125 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 111126 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY |
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| 111127 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 111128 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 111129 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 111130 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 111131 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 111132 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 111133 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 111134 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 111135 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 111136 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 111137 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 111138 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 111139 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 111140 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 111141 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 111142 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 111143 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 111144 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 111145 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 111146 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 111147 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 111148 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 111149 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 111150 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 111151 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 111152 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 111153 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 111154 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 111155 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 111156 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 111157 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 111158 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 111159 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS |
|---|
| 111160 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 111161 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 111162 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 111163 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 111164 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 111165 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 111166 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 111167 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 111168 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 111169 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 111170 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 111171 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 111172 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 111173 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 111174 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 111175 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 111176 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK |
|---|
| 111177 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 111178 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 111179 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 111180 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 111181 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 111182 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 111183 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 111184 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 111185 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 111186 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 111187 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 111188 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 111189 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 111190 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 111191 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 111192 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 111193 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 111194 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 111195 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 111196 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 111197 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 111198 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 111199 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 111200 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 111201 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 111202 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 111203 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 111204 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 111205 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 111206 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 111207 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 111208 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 111209 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 111210 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 111211 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 111212 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0 |
|---|
| 111213 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 111214 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 111215 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1 |
|---|
| 111216 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 111217 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 111218 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2 |
|---|
| 111219 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 111220 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 111221 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3 |
|---|
| 111222 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 111223 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 111224 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 111225 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 111226 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 111227 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 111228 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 111229 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 111230 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 111231 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 111232 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 111233 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 111234 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 111235 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 111236 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 111237 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 111238 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 111239 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 111240 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 111241 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 111242 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 111243 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP |
|---|
| 111244 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 111245 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 111246 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 111247 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 111248 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 111249 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 111250 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL |
|---|
| 111251 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 111252 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 111253 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 111254 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 111255 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 111256 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 111257 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 111258 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 111259 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 111260 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 111261 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 111262 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP |
|---|
| 111263 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 111264 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 111265 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 111266 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 111267 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 111268 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 111269 | //BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL |
|---|
| 111270 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 111271 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 111272 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 111273 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 111274 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 111275 | #define BIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 111276 | |
|---|
| 111277 | |
|---|
| 111278 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp |
|---|
| 111279 | //BIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID |
|---|
| 111280 | #define BIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 111281 | #define BIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 111282 | //BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID |
|---|
| 111283 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 111284 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 111285 | //BIF_CFG_DEV0_EPF0_VF18_1_COMMAND |
|---|
| 111286 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 111287 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 111288 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 111289 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 111290 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 111291 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 111292 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 111293 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 111294 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 111295 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 111296 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 111297 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 111298 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 111299 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 111300 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 111301 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 111302 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 111303 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 111304 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 111305 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 111306 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 111307 | #define BIF_CFG_DEV0_EPF0_VF18_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 111308 | //BIF_CFG_DEV0_EPF0_VF18_1_STATUS |
|---|
| 111309 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 111310 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 111311 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 111312 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 111313 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 111314 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 111315 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 111316 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 111317 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 111318 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
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| 111319 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 111320 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 111321 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 111322 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 111323 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 111324 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 111325 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 111326 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
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| 111327 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 111328 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 111329 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 111330 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
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| 111331 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 111332 | #define BIF_CFG_DEV0_EPF0_VF18_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 111333 | //BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID |
|---|
| 111334 | #define BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
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| 111335 | #define BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
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| 111336 | #define BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 111337 | #define BIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 111338 | //BIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE |
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| 111339 | #define BIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 111340 | #define BIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 111341 | //BIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS |
|---|
| 111342 | #define BIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 111343 | #define BIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 111344 | //BIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS |
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| 111345 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
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| 111346 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
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| 111347 | //BIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE |
|---|
| 111348 | #define BIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
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| 111349 | #define BIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 111350 | //BIF_CFG_DEV0_EPF0_VF18_1_LATENCY |
|---|
| 111351 | #define BIF_CFG_DEV0_EPF0_VF18_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 111352 | #define BIF_CFG_DEV0_EPF0_VF18_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 111353 | //BIF_CFG_DEV0_EPF0_VF18_1_HEADER |
|---|
| 111354 | #define 0x0 |
|---|
| 111355 | #define 0x7 |
|---|
| 111356 | #define 0x7FL |
|---|
| 111357 | #define 0x80L |
|---|
| 111358 | //BIF_CFG_DEV0_EPF0_VF18_1_BIST |
|---|
| 111359 | #define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 111360 | #define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 111361 | #define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 111362 | #define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 111363 | #define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 111364 | #define BIF_CFG_DEV0_EPF0_VF18_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 111365 | //BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1 |
|---|
| 111366 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 111367 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 111368 | //BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2 |
|---|
| 111369 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 111370 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 111371 | //BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3 |
|---|
| 111372 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 111373 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 111374 | //BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4 |
|---|
| 111375 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 111376 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 111377 | //BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5 |
|---|
| 111378 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 111379 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 111380 | //BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6 |
|---|
| 111381 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
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| 111382 | #define BIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 111383 | //BIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR |
|---|
| 111384 | #define BIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 111385 | #define BIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
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| 111386 | //BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID |
|---|
| 111387 | #define BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 111388 | #define BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 111389 | #define BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 111390 | #define BIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 111391 | //BIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR |
|---|
| 111392 | #define BIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 111393 | #define BIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 111394 | //BIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR |
|---|
| 111395 | #define BIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 111396 | #define BIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 111397 | //BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE |
|---|
| 111398 | #define BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 111399 | #define BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 111400 | //BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN |
|---|
| 111401 | #define BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 111402 | #define BIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 111403 | //BIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT |
|---|
| 111404 | #define BIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 111405 | #define BIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 111406 | //BIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY |
|---|
| 111407 | #define BIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 111408 | #define BIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 111409 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST |
|---|
| 111410 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 111411 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 111412 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 111413 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 111414 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP |
|---|
| 111415 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 111416 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 111417 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 111418 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 111419 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 111420 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 111421 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 111422 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 111423 | //BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP |
|---|
| 111424 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 111425 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 111426 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 111427 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 111428 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 111429 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 111430 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 111431 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 111432 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 111433 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 111434 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 111435 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 111436 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 111437 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 111438 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 111439 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 111440 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 111441 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 111442 | //BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL |
|---|
| 111443 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 111444 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 111445 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 111446 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 111447 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 111448 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 111449 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 111450 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 111451 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 111452 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 111453 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 111454 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 111455 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 111456 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 111457 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 111458 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 111459 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 111460 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 111461 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 111462 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 111463 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 111464 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 111465 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 111466 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 111467 | //BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS |
|---|
| 111468 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 111469 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 111470 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 111471 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 111472 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 111473 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 111474 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 111475 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 111476 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 111477 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 111478 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 111479 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 111480 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 111481 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 111482 | //BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP |
|---|
| 111483 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 111484 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 111485 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 111486 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 111487 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 111488 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 111489 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 111490 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 111491 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 111492 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 111493 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 111494 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 111495 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 111496 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 111497 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 111498 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 111499 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 111500 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 111501 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 111502 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 111503 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 111504 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 111505 | //BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL |
|---|
| 111506 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 111507 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 111508 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 111509 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 111510 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 111511 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 111512 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 111513 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 111514 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 111515 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 111516 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 111517 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 111518 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 111519 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 111520 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 111521 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 111522 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 111523 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 111524 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 111525 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 111526 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 111527 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 111528 | //BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS |
|---|
| 111529 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 111530 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 111531 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 111532 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 111533 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 111534 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 111535 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 111536 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 111537 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 111538 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 111539 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 111540 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 111541 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 111542 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 111543 | //BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2 |
|---|
| 111544 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 111545 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 111546 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 111547 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 111548 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 111549 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 111550 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 111551 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 111552 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 111553 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 111554 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 111555 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 111556 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 111557 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 111558 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 111559 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 111560 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 111561 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 111562 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 111563 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 111564 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 111565 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 111566 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 111567 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 111568 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 111569 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 111570 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 111571 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 111572 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 111573 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 111574 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 111575 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 111576 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 111577 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 111578 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 111579 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 111580 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 111581 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 111582 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 111583 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 111584 | //BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2 |
|---|
| 111585 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 111586 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 111587 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 111588 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 111589 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 111590 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 111591 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 111592 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 111593 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 111594 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 111595 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 111596 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 111597 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 111598 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 111599 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 111600 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 111601 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 111602 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 111603 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 111604 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 111605 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 111606 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 111607 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 111608 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 111609 | //BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2 |
|---|
| 111610 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 111611 | #define BIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 111612 | //BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2 |
|---|
| 111613 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 111614 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 111615 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 111616 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 111617 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 111618 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 111619 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 111620 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 111621 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 111622 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 111623 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 111624 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 111625 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 111626 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 111627 | //BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2 |
|---|
| 111628 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 111629 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 111630 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 111631 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 111632 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 111633 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 111634 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 111635 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 111636 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 111637 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 111638 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 111639 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 111640 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 111641 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 111642 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 111643 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 111644 | //BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2 |
|---|
| 111645 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 111646 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 111647 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 111648 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 111649 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 111650 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 111651 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 111652 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 111653 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 111654 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 111655 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 111656 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 111657 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 111658 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 111659 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 111660 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 111661 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 111662 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 111663 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 111664 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 111665 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 111666 | #define BIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 111667 | //BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST |
|---|
| 111668 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 111669 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 111670 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 111671 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 111672 | //BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL |
|---|
| 111673 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 111674 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 111675 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 111676 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 111677 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 111678 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 111679 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 111680 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 111681 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 111682 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 111683 | //BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO |
|---|
| 111684 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 111685 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 111686 | //BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI |
|---|
| 111687 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 111688 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 111689 | //BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA |
|---|
| 111690 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 111691 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 111692 | //BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK |
|---|
| 111693 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 111694 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 111695 | //BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64 |
|---|
| 111696 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 111697 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 111698 | //BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64 |
|---|
| 111699 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 111700 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 111701 | //BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING |
|---|
| 111702 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 111703 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 111704 | //BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64 |
|---|
| 111705 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 111706 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 111707 | //BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST |
|---|
| 111708 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 111709 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 111710 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 111711 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 111712 | //BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL |
|---|
| 111713 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 111714 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 111715 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 111716 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 111717 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 111718 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 111719 | //BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE |
|---|
| 111720 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 111721 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 111722 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 111723 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 111724 | //BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA |
|---|
| 111725 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 111726 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 111727 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 111728 | #define BIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 111729 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 111730 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 111731 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 111732 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 111733 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 111734 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 111735 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 111736 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 111737 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 111738 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 111739 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 111740 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 111741 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 111742 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 111743 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 111744 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 111745 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 111746 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 111747 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 111748 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 111749 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 111750 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 111751 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 111752 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 111753 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 111754 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 111755 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 111756 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 111757 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 111758 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 111759 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 111760 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 111761 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 111762 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 111763 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 111764 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 111765 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 111766 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 111767 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 111768 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 111769 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 111770 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 111771 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 111772 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 111773 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 111774 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 111775 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 111776 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 111777 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 111778 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 111779 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 111780 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 111781 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 111782 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 111783 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 111784 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 111785 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 111786 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 111787 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 111788 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 111789 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK |
|---|
| 111790 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 111791 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 111792 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 111793 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 111794 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 111795 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 111796 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 111797 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 111798 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 111799 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 111800 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 111801 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 111802 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 111803 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 111804 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 111805 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 111806 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 111807 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 111808 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 111809 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 111810 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 111811 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 111812 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 111813 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 111814 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 111815 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 111816 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 111817 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 111818 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 111819 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 111820 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 111821 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 111822 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 111823 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 111824 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 111825 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 111826 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 111827 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 111828 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 111829 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 111830 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 111831 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 111832 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 111833 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 111834 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 111835 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 111836 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 111837 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 111838 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 111839 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 111840 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 111841 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 111842 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 111843 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 111844 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 111845 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 111846 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 111847 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 111848 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 111849 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 111850 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 111851 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 111852 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 111853 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 111854 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 111855 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS |
|---|
| 111856 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 111857 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 111858 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 111859 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 111860 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 111861 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 111862 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 111863 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 111864 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 111865 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 111866 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 111867 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 111868 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 111869 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 111870 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 111871 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 111872 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK |
|---|
| 111873 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 111874 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 111875 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 111876 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 111877 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 111878 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 111879 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 111880 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 111881 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 111882 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 111883 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 111884 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 111885 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 111886 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 111887 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 111888 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 111889 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 111890 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 111891 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 111892 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 111893 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 111894 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 111895 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 111896 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 111897 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 111898 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 111899 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 111900 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 111901 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 111902 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 111903 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 111904 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 111905 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 111906 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 111907 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 111908 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0 |
|---|
| 111909 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 111910 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 111911 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1 |
|---|
| 111912 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 111913 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 111914 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2 |
|---|
| 111915 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 111916 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 111917 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3 |
|---|
| 111918 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 111919 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 111920 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 111921 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 111922 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 111923 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 111924 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 111925 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 111926 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 111927 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 111928 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 111929 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 111930 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 111931 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 111932 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 111933 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 111934 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 111935 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 111936 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 111937 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 111938 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 111939 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP |
|---|
| 111940 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 111941 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 111942 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 111943 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 111944 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 111945 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 111946 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL |
|---|
| 111947 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 111948 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 111949 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 111950 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 111951 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 111952 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 111953 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 111954 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 111955 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 111956 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 111957 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 111958 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP |
|---|
| 111959 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 111960 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 111961 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 111962 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 111963 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 111964 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 111965 | //BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL |
|---|
| 111966 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 111967 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 111968 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 111969 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 111970 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 111971 | #define BIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 111972 | |
|---|
| 111973 | |
|---|
| 111974 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp |
|---|
| 111975 | //BIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID |
|---|
| 111976 | #define BIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 111977 | #define BIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 111978 | //BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID |
|---|
| 111979 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 111980 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 111981 | //BIF_CFG_DEV0_EPF0_VF19_1_COMMAND |
|---|
| 111982 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 111983 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 111984 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 111985 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 111986 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 111987 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 111988 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 111989 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 111990 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 111991 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 111992 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 111993 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 111994 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 111995 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 111996 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 111997 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 111998 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 111999 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 112000 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 112001 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 112002 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 112003 | #define BIF_CFG_DEV0_EPF0_VF19_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 112004 | //BIF_CFG_DEV0_EPF0_VF19_1_STATUS |
|---|
| 112005 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 112006 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 112007 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 112008 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 112009 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 112010 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 112011 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 112012 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 112013 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 112014 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 112015 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 112016 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 112017 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 112018 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 112019 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 112020 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 112021 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 112022 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 112023 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 112024 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 112025 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 112026 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 112027 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 112028 | #define BIF_CFG_DEV0_EPF0_VF19_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 112029 | //BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID |
|---|
| 112030 | #define BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 112031 | #define BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 112032 | #define BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 112033 | #define BIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 112034 | //BIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE |
|---|
| 112035 | #define BIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 112036 | #define BIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 112037 | //BIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS |
|---|
| 112038 | #define BIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 112039 | #define BIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 112040 | //BIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS |
|---|
| 112041 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 112042 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 112043 | //BIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE |
|---|
| 112044 | #define BIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 112045 | #define BIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 112046 | //BIF_CFG_DEV0_EPF0_VF19_1_LATENCY |
|---|
| 112047 | #define BIF_CFG_DEV0_EPF0_VF19_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 112048 | #define BIF_CFG_DEV0_EPF0_VF19_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 112049 | //BIF_CFG_DEV0_EPF0_VF19_1_HEADER |
|---|
| 112050 | #define 0x0 |
|---|
| 112051 | #define 0x7 |
|---|
| 112052 | #define 0x7FL |
|---|
| 112053 | #define 0x80L |
|---|
| 112054 | //BIF_CFG_DEV0_EPF0_VF19_1_BIST |
|---|
| 112055 | #define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 112056 | #define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 112057 | #define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 112058 | #define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 112059 | #define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 112060 | #define BIF_CFG_DEV0_EPF0_VF19_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 112061 | //BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1 |
|---|
| 112062 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 112063 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112064 | //BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2 |
|---|
| 112065 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 112066 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112067 | //BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3 |
|---|
| 112068 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 112069 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112070 | //BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4 |
|---|
| 112071 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 112072 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112073 | //BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5 |
|---|
| 112074 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 112075 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112076 | //BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6 |
|---|
| 112077 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 112078 | #define BIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112079 | //BIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR |
|---|
| 112080 | #define BIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 112081 | #define BIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 112082 | //BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID |
|---|
| 112083 | #define BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 112084 | #define BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 112085 | #define BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 112086 | #define BIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 112087 | //BIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR |
|---|
| 112088 | #define BIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 112089 | #define BIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112090 | //BIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR |
|---|
| 112091 | #define BIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 112092 | #define BIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 112093 | //BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE |
|---|
| 112094 | #define BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 112095 | #define BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 112096 | //BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN |
|---|
| 112097 | #define BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 112098 | #define BIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 112099 | //BIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT |
|---|
| 112100 | #define BIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 112101 | #define BIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 112102 | //BIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY |
|---|
| 112103 | #define BIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 112104 | #define BIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 112105 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST |
|---|
| 112106 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 112107 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 112108 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 112109 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 112110 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP |
|---|
| 112111 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 112112 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 112113 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 112114 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 112115 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 112116 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 112117 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 112118 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 112119 | //BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP |
|---|
| 112120 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 112121 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 112122 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 112123 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 112124 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 112125 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 112126 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 112127 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 112128 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 112129 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 112130 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 112131 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 112132 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 112133 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 112134 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 112135 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 112136 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 112137 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 112138 | //BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL |
|---|
| 112139 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 112140 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 112141 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 112142 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 112143 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 112144 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 112145 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 112146 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 112147 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 112148 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 112149 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 112150 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 112151 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 112152 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 112153 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 112154 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 112155 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 112156 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 112157 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 112158 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 112159 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 112160 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 112161 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 112162 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 112163 | //BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS |
|---|
| 112164 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 112165 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 112166 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 112167 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 112168 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 112169 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 112170 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 112171 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 112172 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 112173 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 112174 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 112175 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 112176 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 112177 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 112178 | //BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP |
|---|
| 112179 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 112180 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 112181 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 112182 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 112183 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 112184 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 112185 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 112186 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 112187 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 112188 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 112189 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 112190 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 112191 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 112192 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 112193 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 112194 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 112195 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 112196 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 112197 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 112198 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 112199 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 112200 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 112201 | //BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL |
|---|
| 112202 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 112203 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 112204 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 112205 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 112206 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 112207 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 112208 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 112209 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 112210 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 112211 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 112212 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 112213 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 112214 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 112215 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 112216 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 112217 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 112218 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 112219 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 112220 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 112221 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 112222 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 112223 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 112224 | //BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS |
|---|
| 112225 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 112226 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 112227 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 112228 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 112229 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 112230 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 112231 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 112232 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 112233 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 112234 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 112235 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 112236 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 112237 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 112238 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 112239 | //BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2 |
|---|
| 112240 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 112241 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 112242 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 112243 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 112244 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 112245 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 112246 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 112247 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 112248 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 112249 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 112250 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 112251 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 112252 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 112253 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 112254 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 112255 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 112256 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 112257 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 112258 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 112259 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 112260 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 112261 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 112262 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 112263 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 112264 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 112265 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 112266 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 112267 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 112268 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 112269 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 112270 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 112271 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 112272 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 112273 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 112274 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 112275 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 112276 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 112277 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 112278 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 112279 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 112280 | //BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2 |
|---|
| 112281 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 112282 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 112283 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 112284 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 112285 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 112286 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 112287 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 112288 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 112289 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 112290 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 112291 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 112292 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 112293 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 112294 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 112295 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 112296 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 112297 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 112298 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 112299 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 112300 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 112301 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 112302 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 112303 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 112304 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 112305 | //BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2 |
|---|
| 112306 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 112307 | #define BIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 112308 | //BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2 |
|---|
| 112309 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 112310 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 112311 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 112312 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 112313 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 112314 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 112315 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 112316 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 112317 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 112318 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 112319 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 112320 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 112321 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 112322 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 112323 | //BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2 |
|---|
| 112324 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 112325 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 112326 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 112327 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 112328 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 112329 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 112330 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 112331 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 112332 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 112333 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 112334 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 112335 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 112336 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 112337 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 112338 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 112339 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 112340 | //BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2 |
|---|
| 112341 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 112342 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 112343 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 112344 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 112345 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 112346 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 112347 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 112348 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 112349 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 112350 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 112351 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 112352 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 112353 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 112354 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 112355 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 112356 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 112357 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 112358 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 112359 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 112360 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 112361 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 112362 | #define BIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 112363 | //BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST |
|---|
| 112364 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 112365 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 112366 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 112367 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 112368 | //BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL |
|---|
| 112369 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 112370 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 112371 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 112372 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 112373 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 112374 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 112375 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 112376 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 112377 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 112378 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 112379 | //BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO |
|---|
| 112380 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 112381 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 112382 | //BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI |
|---|
| 112383 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 112384 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 112385 | //BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA |
|---|
| 112386 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 112387 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 112388 | //BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK |
|---|
| 112389 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 112390 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 112391 | //BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64 |
|---|
| 112392 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 112393 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 112394 | //BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64 |
|---|
| 112395 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 112396 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 112397 | //BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING |
|---|
| 112398 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 112399 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 112400 | //BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64 |
|---|
| 112401 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 112402 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 112403 | //BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST |
|---|
| 112404 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 112405 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 112406 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 112407 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 112408 | //BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL |
|---|
| 112409 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 112410 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 112411 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 112412 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 112413 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 112414 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 112415 | //BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE |
|---|
| 112416 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 112417 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 112418 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 112419 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 112420 | //BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA |
|---|
| 112421 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 112422 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 112423 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 112424 | #define BIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 112425 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 112426 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 112427 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 112428 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 112429 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 112430 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 112431 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 112432 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 112433 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 112434 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 112435 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 112436 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 112437 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 112438 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 112439 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 112440 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 112441 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 112442 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 112443 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 112444 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 112445 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 112446 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 112447 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 112448 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 112449 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 112450 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 112451 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 112452 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 112453 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 112454 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 112455 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 112456 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 112457 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 112458 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 112459 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 112460 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 112461 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 112462 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 112463 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 112464 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 112465 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 112466 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 112467 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 112468 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 112469 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 112470 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 112471 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 112472 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 112473 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 112474 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 112475 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 112476 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 112477 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 112478 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 112479 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 112480 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 112481 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 112482 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 112483 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 112484 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 112485 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK |
|---|
| 112486 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 112487 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 112488 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 112489 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 112490 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 112491 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 112492 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 112493 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 112494 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 112495 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 112496 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 112497 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 112498 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 112499 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 112500 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 112501 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 112502 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 112503 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 112504 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 112505 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 112506 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 112507 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 112508 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 112509 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 112510 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 112511 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 112512 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 112513 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 112514 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 112515 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 112516 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 112517 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 112518 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 112519 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 112520 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 112521 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 112522 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 112523 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 112524 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 112525 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 112526 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 112527 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 112528 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 112529 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 112530 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 112531 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 112532 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 112533 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 112534 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 112535 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 112536 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 112537 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 112538 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 112539 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 112540 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 112541 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 112542 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 112543 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 112544 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 112545 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 112546 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 112547 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 112548 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 112549 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 112550 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 112551 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS |
|---|
| 112552 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 112553 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 112554 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 112555 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 112556 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 112557 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 112558 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 112559 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 112560 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 112561 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 112562 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 112563 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 112564 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 112565 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 112566 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 112567 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 112568 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK |
|---|
| 112569 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 112570 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 112571 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 112572 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 112573 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 112574 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 112575 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 112576 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 112577 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 112578 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 112579 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 112580 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 112581 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 112582 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 112583 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 112584 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 112585 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 112586 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 112587 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 112588 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 112589 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 112590 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 112591 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 112592 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 112593 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 112594 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 112595 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 112596 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 112597 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 112598 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 112599 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 112600 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 112601 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 112602 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 112603 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 112604 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0 |
|---|
| 112605 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 112606 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 112607 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1 |
|---|
| 112608 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 112609 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 112610 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2 |
|---|
| 112611 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 112612 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 112613 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3 |
|---|
| 112614 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 112615 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 112616 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 112617 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 112618 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 112619 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 112620 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 112621 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 112622 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 112623 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 112624 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 112625 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 112626 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 112627 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 112628 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 112629 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 112630 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 112631 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 112632 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 112633 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 112634 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 112635 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP |
|---|
| 112636 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 112637 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 112638 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 112639 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 112640 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 112641 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 112642 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL |
|---|
| 112643 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 112644 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 112645 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 112646 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 112647 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 112648 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 112649 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 112650 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 112651 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 112652 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 112653 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 112654 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP |
|---|
| 112655 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 112656 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 112657 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 112658 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 112659 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 112660 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 112661 | //BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL |
|---|
| 112662 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 112663 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 112664 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 112665 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 112666 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 112667 | #define BIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 112668 | |
|---|
| 112669 | |
|---|
| 112670 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp |
|---|
| 112671 | //BIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID |
|---|
| 112672 | #define BIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 112673 | #define BIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 112674 | //BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID |
|---|
| 112675 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 112676 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 112677 | //BIF_CFG_DEV0_EPF0_VF20_1_COMMAND |
|---|
| 112678 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 112679 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 112680 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 112681 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 112682 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 112683 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 112684 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 112685 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 112686 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 112687 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 112688 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 112689 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 112690 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 112691 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 112692 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 112693 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 112694 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 112695 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 112696 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 112697 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 112698 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 112699 | #define BIF_CFG_DEV0_EPF0_VF20_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 112700 | //BIF_CFG_DEV0_EPF0_VF20_1_STATUS |
|---|
| 112701 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 112702 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 112703 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 112704 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 112705 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 112706 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 112707 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 112708 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 112709 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 112710 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 112711 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 112712 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 112713 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 112714 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 112715 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 112716 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 112717 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 112718 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 112719 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 112720 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 112721 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 112722 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 112723 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 112724 | #define BIF_CFG_DEV0_EPF0_VF20_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 112725 | //BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID |
|---|
| 112726 | #define BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 112727 | #define BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 112728 | #define BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 112729 | #define BIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 112730 | //BIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE |
|---|
| 112731 | #define BIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 112732 | #define BIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 112733 | //BIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS |
|---|
| 112734 | #define BIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 112735 | #define BIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 112736 | //BIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS |
|---|
| 112737 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 112738 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 112739 | //BIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE |
|---|
| 112740 | #define BIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 112741 | #define BIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 112742 | //BIF_CFG_DEV0_EPF0_VF20_1_LATENCY |
|---|
| 112743 | #define BIF_CFG_DEV0_EPF0_VF20_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 112744 | #define BIF_CFG_DEV0_EPF0_VF20_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 112745 | //BIF_CFG_DEV0_EPF0_VF20_1_HEADER |
|---|
| 112746 | #define 0x0 |
|---|
| 112747 | #define 0x7 |
|---|
| 112748 | #define 0x7FL |
|---|
| 112749 | #define 0x80L |
|---|
| 112750 | //BIF_CFG_DEV0_EPF0_VF20_1_BIST |
|---|
| 112751 | #define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 112752 | #define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 112753 | #define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 112754 | #define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 112755 | #define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 112756 | #define BIF_CFG_DEV0_EPF0_VF20_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 112757 | //BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1 |
|---|
| 112758 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 112759 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112760 | //BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2 |
|---|
| 112761 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 112762 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112763 | //BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3 |
|---|
| 112764 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 112765 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112766 | //BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4 |
|---|
| 112767 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 112768 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112769 | //BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5 |
|---|
| 112770 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 112771 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112772 | //BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6 |
|---|
| 112773 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 112774 | #define BIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112775 | //BIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR |
|---|
| 112776 | #define BIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 112777 | #define BIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 112778 | //BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID |
|---|
| 112779 | #define BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 112780 | #define BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 112781 | #define BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 112782 | #define BIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 112783 | //BIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR |
|---|
| 112784 | #define BIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 112785 | #define BIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 112786 | //BIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR |
|---|
| 112787 | #define BIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 112788 | #define BIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 112789 | //BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE |
|---|
| 112790 | #define BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 112791 | #define BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 112792 | //BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN |
|---|
| 112793 | #define BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 112794 | #define BIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 112795 | //BIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT |
|---|
| 112796 | #define BIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 112797 | #define BIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 112798 | //BIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY |
|---|
| 112799 | #define BIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 112800 | #define BIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 112801 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST |
|---|
| 112802 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 112803 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 112804 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 112805 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 112806 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP |
|---|
| 112807 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 112808 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 112809 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 112810 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 112811 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 112812 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 112813 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 112814 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 112815 | //BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP |
|---|
| 112816 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 112817 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 112818 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 112819 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 112820 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 112821 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 112822 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 112823 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 112824 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 112825 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 112826 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 112827 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 112828 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 112829 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 112830 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 112831 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 112832 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 112833 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 112834 | //BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL |
|---|
| 112835 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 112836 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 112837 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 112838 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 112839 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 112840 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 112841 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 112842 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 112843 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 112844 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 112845 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 112846 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 112847 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 112848 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 112849 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 112850 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 112851 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 112852 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 112853 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 112854 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 112855 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 112856 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 112857 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 112858 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 112859 | //BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS |
|---|
| 112860 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 112861 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 112862 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 112863 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 112864 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 112865 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 112866 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 112867 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 112868 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 112869 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 112870 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 112871 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 112872 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 112873 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 112874 | //BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP |
|---|
| 112875 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 112876 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 112877 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 112878 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 112879 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 112880 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 112881 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 112882 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 112883 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 112884 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 112885 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 112886 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 112887 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 112888 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 112889 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 112890 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 112891 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 112892 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 112893 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 112894 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 112895 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 112896 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 112897 | //BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL |
|---|
| 112898 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 112899 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 112900 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 112901 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 112902 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 112903 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 112904 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 112905 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 112906 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 112907 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 112908 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 112909 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 112910 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 112911 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 112912 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 112913 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 112914 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 112915 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 112916 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 112917 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 112918 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 112919 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 112920 | //BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS |
|---|
| 112921 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 112922 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 112923 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 112924 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 112925 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 112926 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 112927 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 112928 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 112929 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 112930 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 112931 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 112932 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 112933 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 112934 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 112935 | //BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2 |
|---|
| 112936 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 112937 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 112938 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 112939 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 112940 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 112941 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 112942 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 112943 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 112944 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 112945 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 112946 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 112947 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 112948 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 112949 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 112950 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 112951 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 112952 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 112953 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 112954 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 112955 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 112956 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 112957 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 112958 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 112959 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 112960 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 112961 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 112962 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 112963 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 112964 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 112965 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 112966 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 112967 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 112968 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 112969 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 112970 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 112971 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 112972 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 112973 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 112974 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 112975 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 112976 | //BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2 |
|---|
| 112977 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 112978 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 112979 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 112980 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 112981 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 112982 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 112983 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 112984 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 112985 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 112986 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 112987 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 112988 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 112989 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 112990 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 112991 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 112992 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 112993 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 112994 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 112995 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 112996 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 112997 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 112998 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 112999 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 113000 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 113001 | //BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2 |
|---|
| 113002 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 113003 | #define BIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 113004 | //BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2 |
|---|
| 113005 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 113006 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 113007 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 113008 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 113009 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 113010 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 113011 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 113012 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 113013 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 113014 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 113015 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 113016 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 113017 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 113018 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 113019 | //BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2 |
|---|
| 113020 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 113021 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 113022 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 113023 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 113024 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 113025 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 113026 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 113027 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 113028 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 113029 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 113030 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 113031 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 113032 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 113033 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 113034 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 113035 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 113036 | //BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2 |
|---|
| 113037 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 113038 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 113039 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 113040 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 113041 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 113042 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 113043 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 113044 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 113045 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 113046 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 113047 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 113048 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 113049 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 113050 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 113051 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 113052 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 113053 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 113054 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 113055 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 113056 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 113057 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 113058 | #define BIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 113059 | //BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST |
|---|
| 113060 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113061 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 113062 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 113063 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 113064 | //BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL |
|---|
| 113065 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 113066 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 113067 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 113068 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 113069 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 113070 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 113071 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 113072 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 113073 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 113074 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 113075 | //BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO |
|---|
| 113076 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 113077 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 113078 | //BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI |
|---|
| 113079 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 113080 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 113081 | //BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA |
|---|
| 113082 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 113083 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 113084 | //BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK |
|---|
| 113085 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 113086 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 113087 | //BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64 |
|---|
| 113088 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 113089 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 113090 | //BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64 |
|---|
| 113091 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 113092 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 113093 | //BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING |
|---|
| 113094 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 113095 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 113096 | //BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64 |
|---|
| 113097 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 113098 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 113099 | //BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST |
|---|
| 113100 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113101 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 113102 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 113103 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 113104 | //BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL |
|---|
| 113105 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 113106 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 113107 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 113108 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 113109 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 113110 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 113111 | //BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE |
|---|
| 113112 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 113113 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 113114 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 113115 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 113116 | //BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA |
|---|
| 113117 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 113118 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 113119 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 113120 | #define BIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 113121 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 113122 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113123 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 113124 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 113125 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 113126 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 113127 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 113128 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 113129 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 113130 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 113131 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 113132 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 113133 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 113134 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 113135 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 113136 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 113137 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 113138 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 113139 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 113140 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 113141 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 113142 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113143 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 113144 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 113145 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 113146 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 113147 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 113148 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 113149 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 113150 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 113151 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 113152 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 113153 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 113154 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 113155 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 113156 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 113157 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 113158 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 113159 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 113160 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 113161 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 113162 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 113163 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 113164 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 113165 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 113166 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 113167 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 113168 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 113169 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 113170 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 113171 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 113172 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 113173 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 113174 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 113175 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 113176 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 113177 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 113178 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 113179 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 113180 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 113181 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK |
|---|
| 113182 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 113183 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 113184 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 113185 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 113186 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 113187 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 113188 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 113189 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 113190 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 113191 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 113192 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 113193 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 113194 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 113195 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 113196 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 113197 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 113198 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 113199 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 113200 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 113201 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 113202 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 113203 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 113204 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 113205 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 113206 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 113207 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 113208 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 113209 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 113210 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 113211 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 113212 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 113213 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 113214 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 113215 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 113216 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 113217 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 113218 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 113219 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 113220 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 113221 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 113222 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 113223 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 113224 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 113225 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 113226 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 113227 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 113228 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 113229 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 113230 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 113231 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 113232 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 113233 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 113234 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 113235 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 113236 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 113237 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 113238 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 113239 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 113240 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 113241 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 113242 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 113243 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 113244 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 113245 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 113246 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 113247 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS |
|---|
| 113248 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 113249 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 113250 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 113251 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 113252 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 113253 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 113254 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 113255 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 113256 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 113257 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 113258 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 113259 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 113260 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 113261 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 113262 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 113263 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 113264 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK |
|---|
| 113265 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 113266 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 113267 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 113268 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 113269 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 113270 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 113271 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 113272 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 113273 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 113274 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 113275 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 113276 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 113277 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 113278 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 113279 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 113280 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 113281 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 113282 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 113283 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 113284 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 113285 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 113286 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 113287 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 113288 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 113289 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 113290 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 113291 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 113292 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 113293 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 113294 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 113295 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 113296 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 113297 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 113298 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 113299 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 113300 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0 |
|---|
| 113301 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 113302 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 113303 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1 |
|---|
| 113304 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 113305 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 113306 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2 |
|---|
| 113307 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 113308 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 113309 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3 |
|---|
| 113310 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 113311 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 113312 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 113313 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 113314 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 113315 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 113316 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 113317 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 113318 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 113319 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 113320 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 113321 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 113322 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 113323 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 113324 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 113325 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113326 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 113327 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 113328 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 113329 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 113330 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 113331 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP |
|---|
| 113332 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 113333 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 113334 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 113335 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 113336 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 113337 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 113338 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL |
|---|
| 113339 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 113340 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 113341 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 113342 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 113343 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 113344 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113345 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 113346 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 113347 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 113348 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 113349 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 113350 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP |
|---|
| 113351 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 113352 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 113353 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 113354 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 113355 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 113356 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 113357 | //BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL |
|---|
| 113358 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 113359 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 113360 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 113361 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 113362 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 113363 | #define BIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 113364 | |
|---|
| 113365 | |
|---|
| 113366 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp |
|---|
| 113367 | //BIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID |
|---|
| 113368 | #define BIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 113369 | #define BIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 113370 | //BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID |
|---|
| 113371 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 113372 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 113373 | //BIF_CFG_DEV0_EPF0_VF21_1_COMMAND |
|---|
| 113374 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 113375 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 113376 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 113377 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 113378 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 113379 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 113380 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 113381 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 113382 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 113383 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 113384 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 113385 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 113386 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 113387 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 113388 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 113389 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 113390 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 113391 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 113392 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 113393 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 113394 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 113395 | #define BIF_CFG_DEV0_EPF0_VF21_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 113396 | //BIF_CFG_DEV0_EPF0_VF21_1_STATUS |
|---|
| 113397 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 113398 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 113399 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 113400 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 113401 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 113402 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 113403 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 113404 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 113405 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 113406 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 113407 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 113408 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 113409 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 113410 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 113411 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 113412 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 113413 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 113414 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 113415 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 113416 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 113417 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 113418 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 113419 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 113420 | #define BIF_CFG_DEV0_EPF0_VF21_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 113421 | //BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID |
|---|
| 113422 | #define BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 113423 | #define BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 113424 | #define BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 113425 | #define BIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 113426 | //BIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE |
|---|
| 113427 | #define BIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 113428 | #define BIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 113429 | //BIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS |
|---|
| 113430 | #define BIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 113431 | #define BIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 113432 | //BIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS |
|---|
| 113433 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 113434 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 113435 | //BIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE |
|---|
| 113436 | #define BIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 113437 | #define BIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 113438 | //BIF_CFG_DEV0_EPF0_VF21_1_LATENCY |
|---|
| 113439 | #define BIF_CFG_DEV0_EPF0_VF21_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 113440 | #define BIF_CFG_DEV0_EPF0_VF21_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 113441 | //BIF_CFG_DEV0_EPF0_VF21_1_HEADER |
|---|
| 113442 | #define 0x0 |
|---|
| 113443 | #define 0x7 |
|---|
| 113444 | #define 0x7FL |
|---|
| 113445 | #define 0x80L |
|---|
| 113446 | //BIF_CFG_DEV0_EPF0_VF21_1_BIST |
|---|
| 113447 | #define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 113448 | #define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 113449 | #define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 113450 | #define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 113451 | #define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 113452 | #define BIF_CFG_DEV0_EPF0_VF21_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 113453 | //BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1 |
|---|
| 113454 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 113455 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 113456 | //BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2 |
|---|
| 113457 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 113458 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 113459 | //BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3 |
|---|
| 113460 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 113461 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 113462 | //BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4 |
|---|
| 113463 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 113464 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 113465 | //BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5 |
|---|
| 113466 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 113467 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 113468 | //BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6 |
|---|
| 113469 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 113470 | #define BIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 113471 | //BIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR |
|---|
| 113472 | #define BIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 113473 | #define BIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 113474 | //BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID |
|---|
| 113475 | #define BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 113476 | #define BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 113477 | #define BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 113478 | #define BIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 113479 | //BIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR |
|---|
| 113480 | #define BIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 113481 | #define BIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 113482 | //BIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR |
|---|
| 113483 | #define BIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 113484 | #define BIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 113485 | //BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE |
|---|
| 113486 | #define BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 113487 | #define BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 113488 | //BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN |
|---|
| 113489 | #define BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 113490 | #define BIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 113491 | //BIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT |
|---|
| 113492 | #define BIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 113493 | #define BIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 113494 | //BIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY |
|---|
| 113495 | #define BIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 113496 | #define BIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 113497 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST |
|---|
| 113498 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113499 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 113500 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 113501 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 113502 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP |
|---|
| 113503 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 113504 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 113505 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 113506 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 113507 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 113508 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 113509 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 113510 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 113511 | //BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP |
|---|
| 113512 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 113513 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 113514 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 113515 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 113516 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 113517 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 113518 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 113519 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 113520 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 113521 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 113522 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 113523 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 113524 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 113525 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 113526 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 113527 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 113528 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 113529 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 113530 | //BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL |
|---|
| 113531 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 113532 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 113533 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 113534 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 113535 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 113536 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 113537 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 113538 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 113539 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 113540 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 113541 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 113542 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 113543 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 113544 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 113545 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 113546 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 113547 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 113548 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 113549 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 113550 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 113551 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 113552 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 113553 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 113554 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 113555 | //BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS |
|---|
| 113556 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 113557 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 113558 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 113559 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 113560 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 113561 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 113562 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 113563 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 113564 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 113565 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 113566 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 113567 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 113568 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 113569 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 113570 | //BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP |
|---|
| 113571 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 113572 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 113573 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 113574 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 113575 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 113576 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 113577 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 113578 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 113579 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 113580 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 113581 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 113582 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 113583 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 113584 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 113585 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 113586 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 113587 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 113588 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 113589 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 113590 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 113591 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 113592 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 113593 | //BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL |
|---|
| 113594 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 113595 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 113596 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 113597 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 113598 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 113599 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 113600 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 113601 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 113602 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 113603 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 113604 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 113605 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 113606 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 113607 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 113608 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 113609 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 113610 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 113611 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 113612 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 113613 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 113614 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 113615 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 113616 | //BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS |
|---|
| 113617 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 113618 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 113619 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 113620 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 113621 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 113622 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 113623 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 113624 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 113625 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 113626 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 113627 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 113628 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 113629 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 113630 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 113631 | //BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2 |
|---|
| 113632 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 113633 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 113634 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 113635 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 113636 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 113637 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 113638 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 113639 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 113640 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 113641 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 113642 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 113643 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 113644 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 113645 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 113646 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 113647 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 113648 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 113649 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 113650 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 113651 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 113652 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 113653 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 113654 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 113655 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 113656 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 113657 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 113658 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 113659 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 113660 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 113661 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 113662 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 113663 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 113664 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 113665 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 113666 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 113667 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 113668 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 113669 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 113670 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 113671 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 113672 | //BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2 |
|---|
| 113673 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 113674 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 113675 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 113676 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 113677 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 113678 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 113679 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 113680 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 113681 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 113682 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 113683 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 113684 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 113685 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 113686 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 113687 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 113688 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 113689 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 113690 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 113691 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 113692 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 113693 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 113694 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 113695 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 113696 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 113697 | //BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2 |
|---|
| 113698 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 113699 | #define BIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 113700 | //BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2 |
|---|
| 113701 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 113702 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 113703 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 113704 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 113705 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 113706 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 113707 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 113708 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 113709 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 113710 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 113711 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 113712 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 113713 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 113714 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 113715 | //BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2 |
|---|
| 113716 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 113717 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 113718 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 113719 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 113720 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 113721 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 113722 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 113723 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 113724 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 113725 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 113726 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 113727 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 113728 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 113729 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 113730 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 113731 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 113732 | //BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2 |
|---|
| 113733 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 113734 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 113735 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 113736 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 113737 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 113738 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 113739 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 113740 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 113741 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 113742 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 113743 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 113744 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 113745 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 113746 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 113747 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 113748 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 113749 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 113750 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 113751 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 113752 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 113753 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 113754 | #define BIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 113755 | //BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST |
|---|
| 113756 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113757 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 113758 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 113759 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 113760 | //BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL |
|---|
| 113761 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 113762 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 113763 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 113764 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 113765 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 113766 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 113767 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 113768 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 113769 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 113770 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 113771 | //BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO |
|---|
| 113772 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 113773 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 113774 | //BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI |
|---|
| 113775 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 113776 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 113777 | //BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA |
|---|
| 113778 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 113779 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 113780 | //BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK |
|---|
| 113781 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 113782 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 113783 | //BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64 |
|---|
| 113784 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 113785 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 113786 | //BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64 |
|---|
| 113787 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 113788 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 113789 | //BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING |
|---|
| 113790 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 113791 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 113792 | //BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64 |
|---|
| 113793 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 113794 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 113795 | //BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST |
|---|
| 113796 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113797 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 113798 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 113799 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 113800 | //BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL |
|---|
| 113801 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 113802 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 113803 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 113804 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 113805 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 113806 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 113807 | //BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE |
|---|
| 113808 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 113809 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 113810 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 113811 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 113812 | //BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA |
|---|
| 113813 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 113814 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 113815 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 113816 | #define BIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 113817 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 113818 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113819 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 113820 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 113821 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 113822 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 113823 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 113824 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 113825 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 113826 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 113827 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 113828 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 113829 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 113830 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 113831 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 113832 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 113833 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 113834 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 113835 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 113836 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 113837 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 113838 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 113839 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 113840 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 113841 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 113842 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 113843 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 113844 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 113845 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 113846 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 113847 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 113848 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 113849 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 113850 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 113851 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 113852 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 113853 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 113854 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 113855 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 113856 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 113857 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 113858 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 113859 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 113860 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 113861 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 113862 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 113863 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 113864 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 113865 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 113866 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 113867 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 113868 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 113869 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 113870 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 113871 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 113872 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 113873 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 113874 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 113875 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 113876 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 113877 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK |
|---|
| 113878 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 113879 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 113880 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 113881 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 113882 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 113883 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 113884 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 113885 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 113886 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 113887 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 113888 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 113889 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 113890 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 113891 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 113892 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 113893 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 113894 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 113895 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 113896 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 113897 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 113898 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 113899 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 113900 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 113901 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 113902 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 113903 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 113904 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 113905 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 113906 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 113907 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 113908 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 113909 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 113910 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 113911 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 113912 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 113913 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 113914 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 113915 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 113916 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 113917 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 113918 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 113919 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 113920 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 113921 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 113922 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 113923 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 113924 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 113925 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 113926 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 113927 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 113928 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 113929 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 113930 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 113931 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 113932 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 113933 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 113934 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 113935 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 113936 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 113937 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 113938 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 113939 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 113940 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 113941 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 113942 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 113943 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS |
|---|
| 113944 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 113945 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 113946 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 113947 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 113948 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 113949 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 113950 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 113951 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 113952 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 113953 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 113954 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 113955 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 113956 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 113957 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 113958 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 113959 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 113960 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK |
|---|
| 113961 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 113962 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 113963 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 113964 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 113965 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 113966 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 113967 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 113968 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 113969 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 113970 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 113971 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 113972 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 113973 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 113974 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 113975 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 113976 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 113977 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 113978 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 113979 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 113980 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 113981 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 113982 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 113983 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 113984 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 113985 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 113986 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 113987 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 113988 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 113989 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 113990 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 113991 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 113992 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 113993 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 113994 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 113995 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 113996 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0 |
|---|
| 113997 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
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| 113998 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 113999 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1 |
|---|
| 114000 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 114001 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 114002 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2 |
|---|
| 114003 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 114004 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 114005 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3 |
|---|
| 114006 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 114007 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 114008 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 114009 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 114010 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 114011 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 114012 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 114013 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 114014 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 114015 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 114016 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 114017 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 114018 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 114019 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 114020 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 114021 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 114022 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 114023 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 114024 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 114025 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 114026 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 114027 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP |
|---|
| 114028 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 114029 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 114030 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 114031 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 114032 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 114033 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 114034 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL |
|---|
| 114035 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 114036 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 114037 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 114038 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 114039 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 114040 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 114041 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 114042 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 114043 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 114044 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 114045 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 114046 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP |
|---|
| 114047 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 114048 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 114049 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 114050 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 114051 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 114052 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 114053 | //BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL |
|---|
| 114054 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 114055 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 114056 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 114057 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 114058 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 114059 | #define BIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 114060 | |
|---|
| 114061 | |
|---|
| 114062 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp |
|---|
| 114063 | //BIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID |
|---|
| 114064 | #define BIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 114065 | #define BIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 114066 | //BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID |
|---|
| 114067 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 114068 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 114069 | //BIF_CFG_DEV0_EPF0_VF22_1_COMMAND |
|---|
| 114070 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 114071 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 114072 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 114073 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 114074 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 114075 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 114076 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 114077 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 114078 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 114079 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 114080 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 114081 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 114082 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 114083 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 114084 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 114085 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 114086 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 114087 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 114088 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 114089 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 114090 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 114091 | #define BIF_CFG_DEV0_EPF0_VF22_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 114092 | //BIF_CFG_DEV0_EPF0_VF22_1_STATUS |
|---|
| 114093 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 114094 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 114095 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 114096 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 114097 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 114098 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 114099 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 114100 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 114101 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 114102 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 114103 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 114104 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 114105 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 114106 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 114107 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 114108 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 114109 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 114110 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 114111 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 114112 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 114113 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 114114 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 114115 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 114116 | #define BIF_CFG_DEV0_EPF0_VF22_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 114117 | //BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID |
|---|
| 114118 | #define BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 114119 | #define BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 114120 | #define BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 114121 | #define BIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 114122 | //BIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE |
|---|
| 114123 | #define BIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 114124 | #define BIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 114125 | //BIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS |
|---|
| 114126 | #define BIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 114127 | #define BIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 114128 | //BIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS |
|---|
| 114129 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 114130 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 114131 | //BIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE |
|---|
| 114132 | #define BIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 114133 | #define BIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 114134 | //BIF_CFG_DEV0_EPF0_VF22_1_LATENCY |
|---|
| 114135 | #define BIF_CFG_DEV0_EPF0_VF22_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 114136 | #define BIF_CFG_DEV0_EPF0_VF22_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 114137 | //BIF_CFG_DEV0_EPF0_VF22_1_HEADER |
|---|
| 114138 | #define 0x0 |
|---|
| 114139 | #define 0x7 |
|---|
| 114140 | #define 0x7FL |
|---|
| 114141 | #define 0x80L |
|---|
| 114142 | //BIF_CFG_DEV0_EPF0_VF22_1_BIST |
|---|
| 114143 | #define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 114144 | #define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 114145 | #define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 114146 | #define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 114147 | #define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 114148 | #define BIF_CFG_DEV0_EPF0_VF22_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 114149 | //BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1 |
|---|
| 114150 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 114151 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114152 | //BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2 |
|---|
| 114153 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 114154 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114155 | //BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3 |
|---|
| 114156 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 114157 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114158 | //BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4 |
|---|
| 114159 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 114160 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114161 | //BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5 |
|---|
| 114162 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 114163 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114164 | //BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6 |
|---|
| 114165 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 114166 | #define BIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114167 | //BIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR |
|---|
| 114168 | #define BIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 114169 | #define BIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 114170 | //BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID |
|---|
| 114171 | #define BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 114172 | #define BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 114173 | #define BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 114174 | #define BIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 114175 | //BIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR |
|---|
| 114176 | #define BIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 114177 | #define BIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114178 | //BIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR |
|---|
| 114179 | #define BIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 114180 | #define BIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 114181 | //BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE |
|---|
| 114182 | #define BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 114183 | #define BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 114184 | //BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN |
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| 114185 | #define BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
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| 114186 | #define BIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
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| 114187 | //BIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT |
|---|
| 114188 | #define BIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 114189 | #define BIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 114190 | //BIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY |
|---|
| 114191 | #define BIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
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| 114192 | #define BIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
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| 114193 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST |
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| 114194 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 114195 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 114196 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 114197 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 114198 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP |
|---|
| 114199 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 114200 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 114201 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 114202 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
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| 114203 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__VERSION_MASK 0x000FL |
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| 114204 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
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| 114205 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
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| 114206 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
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| 114207 | //BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP |
|---|
| 114208 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 114209 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
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| 114210 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
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| 114211 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
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| 114212 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
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| 114213 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 114214 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
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| 114215 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
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| 114216 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 114217 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 114218 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 114219 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 114220 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 114221 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 114222 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 114223 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 114224 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 114225 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 114226 | //BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL |
|---|
| 114227 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 114228 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 114229 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 114230 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 114231 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 114232 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 114233 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 114234 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 114235 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 114236 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 114237 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 114238 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 114239 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 114240 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 114241 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 114242 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 114243 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 114244 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 114245 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 114246 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 114247 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 114248 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 114249 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 114250 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 114251 | //BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS |
|---|
| 114252 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 114253 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 114254 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 114255 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 114256 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 114257 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 114258 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 114259 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 114260 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 114261 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 114262 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 114263 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 114264 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 114265 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 114266 | //BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP |
|---|
| 114267 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 114268 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 114269 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 114270 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 114271 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 114272 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 114273 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 114274 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 114275 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 114276 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 114277 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 114278 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 114279 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 114280 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 114281 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 114282 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 114283 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 114284 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 114285 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 114286 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 114287 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 114288 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 114289 | //BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL |
|---|
| 114290 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 114291 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 114292 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 114293 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 114294 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 114295 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 114296 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 114297 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 114298 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 114299 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 114300 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 114301 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 114302 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 114303 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 114304 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 114305 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 114306 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 114307 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 114308 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 114309 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 114310 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 114311 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 114312 | //BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS |
|---|
| 114313 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 114314 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 114315 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 114316 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 114317 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 114318 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 114319 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 114320 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 114321 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 114322 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 114323 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 114324 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 114325 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 114326 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 114327 | //BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2 |
|---|
| 114328 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 114329 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 114330 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 114331 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 114332 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 114333 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 114334 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 114335 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 114336 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 114337 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 114338 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 114339 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 114340 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 114341 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 114342 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 114343 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 114344 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 114345 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 114346 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 114347 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 114348 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 114349 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 114350 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 114351 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 114352 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 114353 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 114354 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 114355 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 114356 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 114357 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 114358 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 114359 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 114360 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 114361 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 114362 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 114363 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 114364 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 114365 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 114366 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 114367 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 114368 | //BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2 |
|---|
| 114369 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 114370 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 114371 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 114372 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 114373 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 114374 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 114375 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 114376 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 114377 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 114378 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 114379 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 114380 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 114381 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 114382 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 114383 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 114384 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 114385 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 114386 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 114387 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 114388 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 114389 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 114390 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 114391 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 114392 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 114393 | //BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2 |
|---|
| 114394 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 114395 | #define BIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 114396 | //BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2 |
|---|
| 114397 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 114398 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 114399 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 114400 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 114401 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 114402 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 114403 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 114404 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 114405 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 114406 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 114407 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 114408 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 114409 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 114410 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 114411 | //BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2 |
|---|
| 114412 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 114413 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 114414 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 114415 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 114416 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 114417 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 114418 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 114419 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 114420 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 114421 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 114422 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 114423 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 114424 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 114425 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 114426 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 114427 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 114428 | //BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2 |
|---|
| 114429 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 114430 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 114431 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 114432 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 114433 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 114434 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 114435 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 114436 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 114437 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 114438 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 114439 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 114440 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 114441 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 114442 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 114443 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 114444 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 114445 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 114446 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 114447 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 114448 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 114449 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 114450 | #define BIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 114451 | //BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST |
|---|
| 114452 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 114453 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 114454 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 114455 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 114456 | //BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL |
|---|
| 114457 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 114458 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 114459 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 114460 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 114461 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 114462 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 114463 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 114464 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 114465 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 114466 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 114467 | //BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO |
|---|
| 114468 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 114469 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 114470 | //BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI |
|---|
| 114471 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 114472 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 114473 | //BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA |
|---|
| 114474 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 114475 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 114476 | //BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK |
|---|
| 114477 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 114478 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 114479 | //BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64 |
|---|
| 114480 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 114481 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 114482 | //BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64 |
|---|
| 114483 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 114484 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 114485 | //BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING |
|---|
| 114486 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 114487 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 114488 | //BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64 |
|---|
| 114489 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 114490 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 114491 | //BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST |
|---|
| 114492 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 114493 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 114494 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 114495 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 114496 | //BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL |
|---|
| 114497 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 114498 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 114499 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 114500 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 114501 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 114502 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 114503 | //BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE |
|---|
| 114504 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 114505 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 114506 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 114507 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 114508 | //BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA |
|---|
| 114509 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 114510 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 114511 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 114512 | #define BIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 114513 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 114514 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 114515 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 114516 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 114517 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 114518 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 114519 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 114520 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 114521 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 114522 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 114523 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 114524 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 114525 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 114526 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 114527 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 114528 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 114529 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 114530 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 114531 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 114532 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 114533 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 114534 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 114535 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 114536 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 114537 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 114538 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 114539 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 114540 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 114541 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 114542 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 114543 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 114544 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 114545 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 114546 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 114547 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 114548 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 114549 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 114550 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 114551 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 114552 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 114553 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 114554 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 114555 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 114556 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 114557 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 114558 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 114559 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 114560 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 114561 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 114562 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 114563 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 114564 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 114565 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 114566 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 114567 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 114568 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 114569 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 114570 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 114571 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 114572 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 114573 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK |
|---|
| 114574 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 114575 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 114576 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 114577 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 114578 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 114579 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 114580 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 114581 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 114582 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 114583 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 114584 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 114585 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 114586 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 114587 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 114588 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 114589 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 114590 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 114591 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 114592 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 114593 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 114594 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 114595 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 114596 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 114597 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 114598 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 114599 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 114600 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 114601 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 114602 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 114603 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 114604 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 114605 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 114606 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 114607 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 114608 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 114609 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 114610 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 114611 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 114612 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 114613 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 114614 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 114615 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 114616 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 114617 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 114618 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 114619 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 114620 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 114621 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 114622 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 114623 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 114624 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 114625 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 114626 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 114627 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 114628 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 114629 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 114630 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 114631 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 114632 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 114633 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 114634 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 114635 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 114636 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 114637 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 114638 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 114639 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS |
|---|
| 114640 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 114641 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 114642 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 114643 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 114644 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 114645 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 114646 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 114647 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 114648 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 114649 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 114650 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 114651 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 114652 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 114653 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 114654 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 114655 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 114656 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK |
|---|
| 114657 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 114658 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 114659 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 114660 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 114661 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 114662 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 114663 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 114664 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 114665 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 114666 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 114667 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 114668 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 114669 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 114670 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 114671 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 114672 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 114673 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 114674 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 114675 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 114676 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 114677 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 114678 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 114679 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 114680 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 114681 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 114682 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 114683 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 114684 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 114685 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 114686 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 114687 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 114688 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 114689 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 114690 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 114691 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 114692 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0 |
|---|
| 114693 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 114694 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 114695 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1 |
|---|
| 114696 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
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| 114697 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 114698 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2 |
|---|
| 114699 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
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| 114700 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 114701 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3 |
|---|
| 114702 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
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| 114703 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 114704 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 114705 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 114706 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 114707 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 114708 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 114709 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 114710 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 114711 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 114712 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 114713 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 114714 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 114715 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 114716 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 114717 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 114718 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 114719 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 114720 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 114721 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 114722 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 114723 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP |
|---|
| 114724 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 114725 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 114726 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 114727 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 114728 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 114729 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 114730 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL |
|---|
| 114731 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 114732 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 114733 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 114734 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 114735 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 114736 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 114737 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 114738 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 114739 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 114740 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 114741 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 114742 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP |
|---|
| 114743 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 114744 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 114745 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 114746 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 114747 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 114748 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 114749 | //BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL |
|---|
| 114750 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 114751 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 114752 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 114753 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 114754 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 114755 | #define BIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 114756 | |
|---|
| 114757 | |
|---|
| 114758 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp |
|---|
| 114759 | //BIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID |
|---|
| 114760 | #define BIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 114761 | #define BIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 114762 | //BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID |
|---|
| 114763 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 114764 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 114765 | //BIF_CFG_DEV0_EPF0_VF23_1_COMMAND |
|---|
| 114766 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 114767 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 114768 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 114769 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 114770 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 114771 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 114772 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 114773 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 114774 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 114775 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 114776 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 114777 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 114778 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 114779 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 114780 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 114781 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 114782 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 114783 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 114784 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 114785 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 114786 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 114787 | #define BIF_CFG_DEV0_EPF0_VF23_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 114788 | //BIF_CFG_DEV0_EPF0_VF23_1_STATUS |
|---|
| 114789 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 114790 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 114791 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 114792 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 114793 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 114794 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 114795 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 114796 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 114797 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 114798 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 114799 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 114800 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 114801 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 114802 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 114803 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 114804 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 114805 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 114806 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 114807 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 114808 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 114809 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 114810 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 114811 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 114812 | #define BIF_CFG_DEV0_EPF0_VF23_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 114813 | //BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID |
|---|
| 114814 | #define BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 114815 | #define BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 114816 | #define BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 114817 | #define BIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 114818 | //BIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE |
|---|
| 114819 | #define BIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 114820 | #define BIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 114821 | //BIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS |
|---|
| 114822 | #define BIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 114823 | #define BIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 114824 | //BIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS |
|---|
| 114825 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 114826 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 114827 | //BIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE |
|---|
| 114828 | #define BIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 114829 | #define BIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 114830 | //BIF_CFG_DEV0_EPF0_VF23_1_LATENCY |
|---|
| 114831 | #define BIF_CFG_DEV0_EPF0_VF23_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 114832 | #define BIF_CFG_DEV0_EPF0_VF23_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 114833 | //BIF_CFG_DEV0_EPF0_VF23_1_HEADER |
|---|
| 114834 | #define 0x0 |
|---|
| 114835 | #define 0x7 |
|---|
| 114836 | #define 0x7FL |
|---|
| 114837 | #define 0x80L |
|---|
| 114838 | //BIF_CFG_DEV0_EPF0_VF23_1_BIST |
|---|
| 114839 | #define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 114840 | #define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 114841 | #define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 114842 | #define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 114843 | #define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 114844 | #define BIF_CFG_DEV0_EPF0_VF23_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 114845 | //BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1 |
|---|
| 114846 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 114847 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114848 | //BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2 |
|---|
| 114849 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 114850 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114851 | //BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3 |
|---|
| 114852 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 114853 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114854 | //BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4 |
|---|
| 114855 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 114856 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114857 | //BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5 |
|---|
| 114858 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 114859 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114860 | //BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6 |
|---|
| 114861 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 114862 | #define BIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114863 | //BIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR |
|---|
| 114864 | #define BIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 114865 | #define BIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 114866 | //BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID |
|---|
| 114867 | #define BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 114868 | #define BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 114869 | #define BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 114870 | #define BIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 114871 | //BIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR |
|---|
| 114872 | #define BIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 114873 | #define BIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 114874 | //BIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR |
|---|
| 114875 | #define BIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 114876 | #define BIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 114877 | //BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE |
|---|
| 114878 | #define BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 114879 | #define BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 114880 | //BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN |
|---|
| 114881 | #define BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 114882 | #define BIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 114883 | //BIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT |
|---|
| 114884 | #define BIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 114885 | #define BIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 114886 | //BIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY |
|---|
| 114887 | #define BIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 114888 | #define BIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 114889 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST |
|---|
| 114890 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 114891 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 114892 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 114893 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 114894 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP |
|---|
| 114895 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 114896 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 114897 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 114898 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 114899 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 114900 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 114901 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 114902 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 114903 | //BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP |
|---|
| 114904 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 114905 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 114906 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 114907 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 114908 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 114909 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 114910 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 114911 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 114912 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 114913 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 114914 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 114915 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 114916 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 114917 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 114918 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 114919 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 114920 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 114921 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 114922 | //BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL |
|---|
| 114923 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 114924 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 114925 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 114926 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 114927 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 114928 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 114929 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 114930 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 114931 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 114932 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 114933 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 114934 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 114935 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 114936 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 114937 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 114938 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 114939 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 114940 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 114941 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 114942 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 114943 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 114944 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 114945 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 114946 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 114947 | //BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS |
|---|
| 114948 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 114949 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 114950 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 114951 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 114952 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 114953 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 114954 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 114955 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 114956 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 114957 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 114958 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 114959 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 114960 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 114961 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 114962 | //BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP |
|---|
| 114963 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 114964 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 114965 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 114966 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 114967 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 114968 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 114969 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 114970 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 114971 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 114972 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 114973 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 114974 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 114975 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 114976 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 114977 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 114978 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 114979 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 114980 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 114981 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 114982 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 114983 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 114984 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 114985 | //BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL |
|---|
| 114986 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 114987 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 114988 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 114989 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 114990 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 114991 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 114992 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 114993 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 114994 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 114995 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 114996 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 114997 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 114998 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 114999 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 115000 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 115001 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 115002 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 115003 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 115004 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 115005 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 115006 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 115007 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 115008 | //BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS |
|---|
| 115009 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 115010 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 115011 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 115012 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 115013 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 115014 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 115015 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 115016 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 115017 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 115018 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 115019 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 115020 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 115021 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 115022 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 115023 | //BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2 |
|---|
| 115024 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 115025 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 115026 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 115027 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 115028 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 115029 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 115030 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 115031 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 115032 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 115033 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 115034 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 115035 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 115036 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 115037 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 115038 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 115039 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 115040 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 115041 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 115042 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 115043 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 115044 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 115045 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 115046 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 115047 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 115048 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 115049 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 115050 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 115051 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 115052 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 115053 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 115054 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 115055 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 115056 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 115057 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 115058 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 115059 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 115060 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 115061 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 115062 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 115063 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 115064 | //BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2 |
|---|
| 115065 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 115066 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 115067 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 115068 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 115069 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 115070 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 115071 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 115072 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 115073 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 115074 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 115075 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 115076 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 115077 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 115078 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 115079 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 115080 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 115081 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 115082 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 115083 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 115084 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 115085 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 115086 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 115087 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 115088 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 115089 | //BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2 |
|---|
| 115090 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 115091 | #define BIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 115092 | //BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2 |
|---|
| 115093 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 115094 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 115095 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 115096 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 115097 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 115098 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 115099 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 115100 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 115101 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 115102 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 115103 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 115104 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 115105 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 115106 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 115107 | //BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2 |
|---|
| 115108 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 115109 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 115110 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 115111 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 115112 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 115113 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 115114 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 115115 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 115116 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 115117 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 115118 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 115119 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 115120 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 115121 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 115122 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 115123 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 115124 | //BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2 |
|---|
| 115125 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 115126 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 115127 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 115128 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 115129 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 115130 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 115131 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 115132 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 115133 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 115134 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 115135 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 115136 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 115137 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 115138 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 115139 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 115140 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 115141 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 115142 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 115143 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 115144 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 115145 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 115146 | #define BIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 115147 | //BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST |
|---|
| 115148 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115149 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 115150 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 115151 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 115152 | //BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL |
|---|
| 115153 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 115154 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 115155 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 115156 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 115157 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 115158 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 115159 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 115160 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 115161 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 115162 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 115163 | //BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO |
|---|
| 115164 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 115165 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 115166 | //BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI |
|---|
| 115167 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 115168 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 115169 | //BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA |
|---|
| 115170 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 115171 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 115172 | //BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK |
|---|
| 115173 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 115174 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 115175 | //BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64 |
|---|
| 115176 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 115177 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 115178 | //BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64 |
|---|
| 115179 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 115180 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 115181 | //BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING |
|---|
| 115182 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 115183 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 115184 | //BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64 |
|---|
| 115185 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 115186 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 115187 | //BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST |
|---|
| 115188 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115189 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 115190 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 115191 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 115192 | //BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL |
|---|
| 115193 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 115194 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 115195 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 115196 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 115197 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 115198 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 115199 | //BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE |
|---|
| 115200 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 115201 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 115202 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 115203 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 115204 | //BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA |
|---|
| 115205 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 115206 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 115207 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 115208 | #define BIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 115209 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 115210 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115211 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 115212 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 115213 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 115214 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 115215 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 115216 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 115217 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 115218 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 115219 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 115220 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 115221 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 115222 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 115223 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 115224 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 115225 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 115226 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 115227 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 115228 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 115229 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 115230 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115231 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 115232 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 115233 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 115234 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 115235 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 115236 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 115237 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 115238 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 115239 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 115240 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 115241 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 115242 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 115243 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 115244 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 115245 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 115246 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 115247 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 115248 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 115249 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 115250 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 115251 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 115252 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 115253 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 115254 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 115255 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 115256 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 115257 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 115258 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 115259 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 115260 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 115261 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 115262 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 115263 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 115264 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 115265 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 115266 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 115267 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 115268 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 115269 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK |
|---|
| 115270 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 115271 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 115272 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 115273 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 115274 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 115275 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 115276 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 115277 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 115278 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 115279 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 115280 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 115281 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 115282 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 115283 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 115284 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 115285 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 115286 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 115287 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 115288 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 115289 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 115290 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 115291 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 115292 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 115293 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 115294 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 115295 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 115296 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 115297 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 115298 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 115299 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 115300 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 115301 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 115302 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 115303 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 115304 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 115305 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 115306 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 115307 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 115308 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 115309 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 115310 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 115311 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 115312 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 115313 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 115314 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 115315 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 115316 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 115317 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 115318 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 115319 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 115320 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 115321 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 115322 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 115323 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 115324 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 115325 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 115326 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 115327 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 115328 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 115329 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 115330 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 115331 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 115332 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 115333 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 115334 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 115335 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS |
|---|
| 115336 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 115337 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 115338 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 115339 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 115340 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 115341 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 115342 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 115343 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 115344 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 115345 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 115346 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 115347 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 115348 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 115349 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 115350 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 115351 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 115352 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK |
|---|
| 115353 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 115354 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 115355 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 115356 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 115357 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 115358 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 115359 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 115360 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 115361 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 115362 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 115363 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 115364 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 115365 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 115366 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 115367 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 115368 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 115369 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 115370 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 115371 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 115372 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 115373 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 115374 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 115375 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 115376 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 115377 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 115378 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 115379 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 115380 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 115381 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 115382 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 115383 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 115384 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 115385 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 115386 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 115387 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 115388 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0 |
|---|
| 115389 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 115390 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 115391 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1 |
|---|
| 115392 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 115393 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 115394 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2 |
|---|
| 115395 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 115396 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 115397 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3 |
|---|
| 115398 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 115399 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 115400 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 115401 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 115402 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 115403 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 115404 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 115405 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 115406 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 115407 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 115408 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 115409 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 115410 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 115411 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 115412 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 115413 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115414 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 115415 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 115416 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 115417 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 115418 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 115419 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP |
|---|
| 115420 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 115421 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 115422 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 115423 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 115424 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 115425 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 115426 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL |
|---|
| 115427 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 115428 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 115429 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 115430 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 115431 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 115432 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115433 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 115434 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 115435 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 115436 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 115437 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 115438 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP |
|---|
| 115439 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 115440 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 115441 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 115442 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 115443 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 115444 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 115445 | //BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL |
|---|
| 115446 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 115447 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 115448 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 115449 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 115450 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 115451 | #define BIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 115452 | |
|---|
| 115453 | |
|---|
| 115454 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp |
|---|
| 115455 | //BIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID |
|---|
| 115456 | #define BIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 115457 | #define BIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 115458 | //BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID |
|---|
| 115459 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 115460 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 115461 | //BIF_CFG_DEV0_EPF0_VF24_1_COMMAND |
|---|
| 115462 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 115463 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 115464 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 115465 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 115466 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 115467 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 115468 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 115469 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 115470 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 115471 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 115472 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 115473 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 115474 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 115475 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 115476 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 115477 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 115478 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 115479 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 115480 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 115481 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 115482 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 115483 | #define BIF_CFG_DEV0_EPF0_VF24_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 115484 | //BIF_CFG_DEV0_EPF0_VF24_1_STATUS |
|---|
| 115485 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 115486 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 115487 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 115488 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 115489 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 115490 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 115491 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 115492 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 115493 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 115494 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 115495 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 115496 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 115497 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 115498 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 115499 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 115500 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 115501 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 115502 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 115503 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 115504 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 115505 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 115506 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 115507 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 115508 | #define BIF_CFG_DEV0_EPF0_VF24_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 115509 | //BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID |
|---|
| 115510 | #define BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 115511 | #define BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 115512 | #define BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 115513 | #define BIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 115514 | //BIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE |
|---|
| 115515 | #define BIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 115516 | #define BIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 115517 | //BIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS |
|---|
| 115518 | #define BIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 115519 | #define BIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 115520 | //BIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS |
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| 115521 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 115522 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 115523 | //BIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE |
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| 115524 | #define BIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 115525 | #define BIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 115526 | //BIF_CFG_DEV0_EPF0_VF24_1_LATENCY |
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| 115527 | #define BIF_CFG_DEV0_EPF0_VF24_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
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| 115528 | #define BIF_CFG_DEV0_EPF0_VF24_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 115529 | //BIF_CFG_DEV0_EPF0_VF24_1_HEADER |
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| 115530 | #define 0x0 |
|---|
| 115531 | #define 0x7 |
|---|
| 115532 | #define 0x7FL |
|---|
| 115533 | #define 0x80L |
|---|
| 115534 | //BIF_CFG_DEV0_EPF0_VF24_1_BIST |
|---|
| 115535 | #define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_COMP__SHIFT 0x0 |
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| 115536 | #define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 115537 | #define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 115538 | #define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 115539 | #define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_STRT_MASK 0x40L |
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| 115540 | #define BIF_CFG_DEV0_EPF0_VF24_1_BIST__BIST_CAP_MASK 0x80L |
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| 115541 | //BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1 |
|---|
| 115542 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
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| 115543 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 115544 | //BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2 |
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| 115545 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
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| 115546 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 115547 | //BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3 |
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| 115548 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
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| 115549 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 115550 | //BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4 |
|---|
| 115551 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 115552 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 115553 | //BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5 |
|---|
| 115554 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
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| 115555 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 115556 | //BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6 |
|---|
| 115557 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 115558 | #define BIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 115559 | //BIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR |
|---|
| 115560 | #define BIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 115561 | #define BIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 115562 | //BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID |
|---|
| 115563 | #define BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 115564 | #define BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 115565 | #define BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 115566 | #define BIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 115567 | //BIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR |
|---|
| 115568 | #define BIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 115569 | #define BIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 115570 | //BIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR |
|---|
| 115571 | #define BIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 115572 | #define BIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 115573 | //BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE |
|---|
| 115574 | #define BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 115575 | #define BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 115576 | //BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN |
|---|
| 115577 | #define BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 115578 | #define BIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 115579 | //BIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT |
|---|
| 115580 | #define BIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 115581 | #define BIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 115582 | //BIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY |
|---|
| 115583 | #define BIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 115584 | #define BIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 115585 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST |
|---|
| 115586 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115587 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 115588 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 115589 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 115590 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP |
|---|
| 115591 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 115592 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 115593 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 115594 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 115595 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__VERSION_MASK 0x000FL |
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| 115596 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 115597 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 115598 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 115599 | //BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP |
|---|
| 115600 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 115601 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
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| 115602 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
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| 115603 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 115604 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
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| 115605 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 115606 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 115607 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 115608 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
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| 115609 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 115610 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 115611 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 115612 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 115613 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 115614 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 115615 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 115616 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 115617 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 115618 | //BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL |
|---|
| 115619 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 115620 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 115621 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 115622 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 115623 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 115624 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 115625 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 115626 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 115627 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 115628 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 115629 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 115630 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 115631 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 115632 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 115633 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 115634 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 115635 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 115636 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 115637 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 115638 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 115639 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 115640 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 115641 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 115642 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 115643 | //BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS |
|---|
| 115644 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 115645 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 115646 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 115647 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 115648 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 115649 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 115650 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 115651 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 115652 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 115653 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 115654 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 115655 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 115656 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 115657 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 115658 | //BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP |
|---|
| 115659 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 115660 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 115661 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 115662 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 115663 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 115664 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 115665 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 115666 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 115667 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 115668 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 115669 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 115670 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 115671 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 115672 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 115673 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 115674 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 115675 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 115676 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 115677 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 115678 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 115679 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 115680 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 115681 | //BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL |
|---|
| 115682 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 115683 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 115684 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 115685 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 115686 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 115687 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 115688 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 115689 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 115690 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 115691 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 115692 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 115693 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 115694 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 115695 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 115696 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 115697 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 115698 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 115699 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 115700 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 115701 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 115702 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 115703 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 115704 | //BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS |
|---|
| 115705 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 115706 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 115707 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 115708 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 115709 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 115710 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 115711 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 115712 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 115713 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 115714 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 115715 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 115716 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 115717 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 115718 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 115719 | //BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2 |
|---|
| 115720 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 115721 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 115722 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 115723 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 115724 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 115725 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 115726 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 115727 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 115728 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 115729 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 115730 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 115731 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 115732 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 115733 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 115734 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 115735 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 115736 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 115737 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 115738 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 115739 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 115740 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 115741 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 115742 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 115743 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 115744 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 115745 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 115746 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 115747 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 115748 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 115749 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 115750 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 115751 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 115752 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 115753 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 115754 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 115755 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 115756 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 115757 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 115758 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 115759 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 115760 | //BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2 |
|---|
| 115761 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 115762 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 115763 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 115764 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 115765 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 115766 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 115767 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 115768 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 115769 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 115770 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 115771 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 115772 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 115773 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 115774 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 115775 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 115776 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 115777 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 115778 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 115779 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 115780 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 115781 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 115782 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 115783 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 115784 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 115785 | //BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2 |
|---|
| 115786 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 115787 | #define BIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 115788 | //BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2 |
|---|
| 115789 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 115790 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 115791 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 115792 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 115793 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 115794 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 115795 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 115796 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 115797 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 115798 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 115799 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 115800 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 115801 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 115802 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 115803 | //BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2 |
|---|
| 115804 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 115805 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 115806 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 115807 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 115808 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 115809 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 115810 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 115811 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 115812 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 115813 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 115814 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 115815 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 115816 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 115817 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 115818 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 115819 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 115820 | //BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2 |
|---|
| 115821 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 115822 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 115823 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 115824 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 115825 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 115826 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 115827 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 115828 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 115829 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 115830 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 115831 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 115832 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 115833 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 115834 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 115835 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 115836 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 115837 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 115838 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 115839 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 115840 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 115841 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 115842 | #define BIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 115843 | //BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST |
|---|
| 115844 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115845 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 115846 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 115847 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 115848 | //BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL |
|---|
| 115849 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 115850 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 115851 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 115852 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 115853 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 115854 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 115855 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 115856 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 115857 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 115858 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 115859 | //BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO |
|---|
| 115860 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 115861 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 115862 | //BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI |
|---|
| 115863 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 115864 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 115865 | //BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA |
|---|
| 115866 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 115867 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 115868 | //BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK |
|---|
| 115869 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 115870 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 115871 | //BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64 |
|---|
| 115872 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 115873 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 115874 | //BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64 |
|---|
| 115875 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 115876 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 115877 | //BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING |
|---|
| 115878 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 115879 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 115880 | //BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64 |
|---|
| 115881 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 115882 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
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| 115883 | //BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST |
|---|
| 115884 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115885 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 115886 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 115887 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 115888 | //BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL |
|---|
| 115889 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 115890 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 115891 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 115892 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 115893 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 115894 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
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| 115895 | //BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE |
|---|
| 115896 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
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| 115897 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 115898 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 115899 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 115900 | //BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA |
|---|
| 115901 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 115902 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 115903 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 115904 | #define BIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 115905 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 115906 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115907 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 115908 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 115909 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 115910 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 115911 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 115912 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 115913 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 115914 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 115915 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 115916 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 115917 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 115918 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 115919 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 115920 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 115921 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 115922 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 115923 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 115924 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 115925 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 115926 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 115927 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 115928 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 115929 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 115930 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 115931 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 115932 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 115933 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 115934 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 115935 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 115936 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 115937 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 115938 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 115939 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 115940 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 115941 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 115942 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 115943 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 115944 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 115945 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 115946 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 115947 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 115948 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 115949 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 115950 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 115951 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 115952 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 115953 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 115954 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 115955 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 115956 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 115957 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 115958 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 115959 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 115960 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 115961 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 115962 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 115963 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 115964 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 115965 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK |
|---|
| 115966 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 115967 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 115968 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 115969 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 115970 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 115971 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 115972 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 115973 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 115974 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 115975 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 115976 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 115977 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 115978 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 115979 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 115980 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 115981 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 115982 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 115983 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 115984 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 115985 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 115986 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 115987 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 115988 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 115989 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 115990 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 115991 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 115992 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 115993 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 115994 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 115995 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 115996 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 115997 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 115998 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 115999 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 116000 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 116001 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 116002 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 116003 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 116004 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 116005 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 116006 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 116007 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 116008 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 116009 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 116010 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 116011 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 116012 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 116013 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 116014 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 116015 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 116016 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 116017 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 116018 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 116019 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 116020 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 116021 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 116022 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 116023 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 116024 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 116025 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 116026 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 116027 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 116028 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 116029 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 116030 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 116031 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS |
|---|
| 116032 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 116033 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 116034 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 116035 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 116036 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 116037 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 116038 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 116039 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 116040 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 116041 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 116042 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 116043 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 116044 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 116045 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 116046 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 116047 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 116048 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK |
|---|
| 116049 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 116050 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 116051 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 116052 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 116053 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 116054 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 116055 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 116056 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 116057 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 116058 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 116059 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 116060 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 116061 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 116062 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 116063 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 116064 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 116065 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 116066 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 116067 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 116068 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 116069 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 116070 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 116071 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 116072 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 116073 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 116074 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 116075 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 116076 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 116077 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 116078 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 116079 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 116080 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 116081 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 116082 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 116083 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 116084 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0 |
|---|
| 116085 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 116086 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 116087 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1 |
|---|
| 116088 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 116089 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 116090 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2 |
|---|
| 116091 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 116092 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 116093 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3 |
|---|
| 116094 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 116095 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 116096 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 116097 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 116098 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 116099 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 116100 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 116101 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 116102 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 116103 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 116104 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 116105 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 116106 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 116107 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 116108 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 116109 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 116110 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 116111 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 116112 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 116113 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 116114 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 116115 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP |
|---|
| 116116 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 116117 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 116118 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 116119 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 116120 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 116121 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 116122 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL |
|---|
| 116123 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 116124 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 116125 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 116126 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 116127 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 116128 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 116129 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 116130 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 116131 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 116132 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 116133 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 116134 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP |
|---|
| 116135 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 116136 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 116137 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 116138 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 116139 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 116140 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 116141 | //BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL |
|---|
| 116142 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 116143 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 116144 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 116145 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 116146 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 116147 | #define BIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 116148 | |
|---|
| 116149 | |
|---|
| 116150 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp |
|---|
| 116151 | //BIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID |
|---|
| 116152 | #define BIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 116153 | #define BIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 116154 | //BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID |
|---|
| 116155 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 116156 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 116157 | //BIF_CFG_DEV0_EPF0_VF25_1_COMMAND |
|---|
| 116158 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 116159 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 116160 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 116161 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 116162 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 116163 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 116164 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 116165 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 116166 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 116167 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 116168 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 116169 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 116170 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 116171 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 116172 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 116173 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 116174 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 116175 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 116176 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 116177 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 116178 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 116179 | #define BIF_CFG_DEV0_EPF0_VF25_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 116180 | //BIF_CFG_DEV0_EPF0_VF25_1_STATUS |
|---|
| 116181 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 116182 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 116183 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 116184 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 116185 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 116186 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 116187 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 116188 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 116189 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 116190 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 116191 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 116192 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 116193 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 116194 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 116195 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 116196 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 116197 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 116198 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 116199 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 116200 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 116201 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 116202 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 116203 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 116204 | #define BIF_CFG_DEV0_EPF0_VF25_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 116205 | //BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID |
|---|
| 116206 | #define BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 116207 | #define BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 116208 | #define BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 116209 | #define BIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 116210 | //BIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE |
|---|
| 116211 | #define BIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 116212 | #define BIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 116213 | //BIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS |
|---|
| 116214 | #define BIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 116215 | #define BIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 116216 | //BIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS |
|---|
| 116217 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 116218 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 116219 | //BIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE |
|---|
| 116220 | #define BIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 116221 | #define BIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 116222 | //BIF_CFG_DEV0_EPF0_VF25_1_LATENCY |
|---|
| 116223 | #define BIF_CFG_DEV0_EPF0_VF25_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 116224 | #define BIF_CFG_DEV0_EPF0_VF25_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 116225 | //BIF_CFG_DEV0_EPF0_VF25_1_HEADER |
|---|
| 116226 | #define 0x0 |
|---|
| 116227 | #define 0x7 |
|---|
| 116228 | #define 0x7FL |
|---|
| 116229 | #define 0x80L |
|---|
| 116230 | //BIF_CFG_DEV0_EPF0_VF25_1_BIST |
|---|
| 116231 | #define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 116232 | #define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 116233 | #define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 116234 | #define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 116235 | #define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 116236 | #define BIF_CFG_DEV0_EPF0_VF25_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 116237 | //BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1 |
|---|
| 116238 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 116239 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116240 | //BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2 |
|---|
| 116241 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 116242 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116243 | //BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3 |
|---|
| 116244 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 116245 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116246 | //BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4 |
|---|
| 116247 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 116248 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116249 | //BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5 |
|---|
| 116250 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 116251 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116252 | //BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6 |
|---|
| 116253 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 116254 | #define BIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116255 | //BIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR |
|---|
| 116256 | #define BIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 116257 | #define BIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 116258 | //BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID |
|---|
| 116259 | #define BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 116260 | #define BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 116261 | #define BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 116262 | #define BIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 116263 | //BIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR |
|---|
| 116264 | #define BIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 116265 | #define BIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116266 | //BIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR |
|---|
| 116267 | #define BIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 116268 | #define BIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 116269 | //BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE |
|---|
| 116270 | #define BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 116271 | #define BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 116272 | //BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN |
|---|
| 116273 | #define BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 116274 | #define BIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 116275 | //BIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT |
|---|
| 116276 | #define BIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 116277 | #define BIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 116278 | //BIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY |
|---|
| 116279 | #define BIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 116280 | #define BIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 116281 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST |
|---|
| 116282 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 116283 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 116284 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 116285 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 116286 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP |
|---|
| 116287 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 116288 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 116289 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 116290 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 116291 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 116292 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 116293 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 116294 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 116295 | //BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP |
|---|
| 116296 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 116297 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 116298 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 116299 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 116300 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 116301 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 116302 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 116303 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 116304 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 116305 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 116306 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 116307 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 116308 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 116309 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 116310 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 116311 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 116312 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 116313 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 116314 | //BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL |
|---|
| 116315 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 116316 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 116317 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 116318 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 116319 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 116320 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 116321 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 116322 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 116323 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 116324 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 116325 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 116326 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 116327 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 116328 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 116329 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 116330 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 116331 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 116332 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 116333 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 116334 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 116335 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 116336 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 116337 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 116338 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 116339 | //BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS |
|---|
| 116340 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 116341 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 116342 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 116343 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 116344 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 116345 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 116346 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 116347 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 116348 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 116349 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 116350 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 116351 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 116352 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 116353 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 116354 | //BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP |
|---|
| 116355 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 116356 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 116357 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 116358 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 116359 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 116360 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 116361 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 116362 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 116363 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 116364 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 116365 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 116366 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 116367 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 116368 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 116369 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 116370 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 116371 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 116372 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 116373 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 116374 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 116375 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 116376 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 116377 | //BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL |
|---|
| 116378 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 116379 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 116380 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 116381 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 116382 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 116383 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 116384 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 116385 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 116386 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 116387 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 116388 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 116389 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 116390 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 116391 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 116392 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 116393 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 116394 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 116395 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 116396 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 116397 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 116398 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 116399 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 116400 | //BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS |
|---|
| 116401 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 116402 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 116403 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 116404 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 116405 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 116406 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 116407 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 116408 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 116409 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 116410 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 116411 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 116412 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 116413 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 116414 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 116415 | //BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2 |
|---|
| 116416 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 116417 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 116418 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 116419 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 116420 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 116421 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 116422 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 116423 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 116424 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 116425 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 116426 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 116427 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 116428 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 116429 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 116430 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 116431 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 116432 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 116433 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 116434 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 116435 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 116436 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 116437 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 116438 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 116439 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 116440 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 116441 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 116442 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 116443 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 116444 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 116445 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 116446 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 116447 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 116448 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 116449 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 116450 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 116451 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 116452 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 116453 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 116454 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 116455 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 116456 | //BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2 |
|---|
| 116457 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 116458 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 116459 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 116460 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 116461 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 116462 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 116463 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 116464 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 116465 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 116466 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 116467 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 116468 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 116469 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 116470 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 116471 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 116472 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 116473 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 116474 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 116475 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 116476 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 116477 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 116478 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 116479 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 116480 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 116481 | //BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2 |
|---|
| 116482 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 116483 | #define BIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 116484 | //BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2 |
|---|
| 116485 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 116486 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 116487 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 116488 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 116489 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 116490 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 116491 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 116492 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 116493 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 116494 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 116495 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 116496 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 116497 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 116498 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 116499 | //BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2 |
|---|
| 116500 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 116501 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 116502 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 116503 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 116504 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 116505 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 116506 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 116507 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 116508 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 116509 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 116510 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 116511 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 116512 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 116513 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 116514 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 116515 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 116516 | //BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2 |
|---|
| 116517 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 116518 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 116519 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 116520 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 116521 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 116522 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 116523 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 116524 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 116525 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 116526 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 116527 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 116528 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 116529 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 116530 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 116531 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 116532 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 116533 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 116534 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 116535 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 116536 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 116537 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 116538 | #define BIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 116539 | //BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST |
|---|
| 116540 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 116541 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 116542 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 116543 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 116544 | //BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL |
|---|
| 116545 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 116546 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 116547 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 116548 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 116549 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 116550 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 116551 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 116552 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 116553 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 116554 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 116555 | //BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO |
|---|
| 116556 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 116557 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 116558 | //BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI |
|---|
| 116559 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 116560 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 116561 | //BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA |
|---|
| 116562 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 116563 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 116564 | //BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK |
|---|
| 116565 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 116566 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 116567 | //BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64 |
|---|
| 116568 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 116569 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 116570 | //BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64 |
|---|
| 116571 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 116572 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 116573 | //BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING |
|---|
| 116574 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 116575 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 116576 | //BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64 |
|---|
| 116577 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 116578 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 116579 | //BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST |
|---|
| 116580 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 116581 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 116582 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 116583 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 116584 | //BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL |
|---|
| 116585 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 116586 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 116587 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 116588 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 116589 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 116590 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 116591 | //BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE |
|---|
| 116592 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 116593 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 116594 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 116595 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 116596 | //BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA |
|---|
| 116597 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 116598 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 116599 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 116600 | #define BIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 116601 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 116602 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 116603 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 116604 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 116605 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 116606 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 116607 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 116608 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 116609 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 116610 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 116611 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 116612 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 116613 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 116614 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 116615 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 116616 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 116617 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 116618 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 116619 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 116620 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 116621 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 116622 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 116623 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 116624 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 116625 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 116626 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 116627 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 116628 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 116629 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 116630 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 116631 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 116632 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 116633 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 116634 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 116635 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 116636 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 116637 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 116638 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 116639 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 116640 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 116641 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 116642 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 116643 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 116644 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 116645 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 116646 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 116647 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 116648 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 116649 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 116650 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 116651 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 116652 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 116653 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 116654 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 116655 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 116656 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 116657 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 116658 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 116659 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 116660 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 116661 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK |
|---|
| 116662 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 116663 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 116664 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 116665 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 116666 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 116667 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 116668 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 116669 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 116670 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 116671 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 116672 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 116673 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 116674 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 116675 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 116676 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 116677 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 116678 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 116679 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 116680 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 116681 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 116682 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 116683 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 116684 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 116685 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 116686 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 116687 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 116688 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 116689 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 116690 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 116691 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 116692 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 116693 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 116694 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 116695 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 116696 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 116697 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 116698 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 116699 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 116700 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 116701 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 116702 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 116703 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 116704 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 116705 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 116706 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 116707 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 116708 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 116709 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 116710 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 116711 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 116712 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 116713 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 116714 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 116715 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 116716 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 116717 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 116718 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 116719 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 116720 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 116721 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 116722 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 116723 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 116724 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 116725 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 116726 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 116727 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS |
|---|
| 116728 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 116729 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 116730 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 116731 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 116732 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 116733 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 116734 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 116735 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 116736 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 116737 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 116738 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 116739 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 116740 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 116741 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 116742 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 116743 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 116744 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK |
|---|
| 116745 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 116746 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 116747 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 116748 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 116749 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 116750 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 116751 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 116752 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 116753 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 116754 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 116755 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 116756 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 116757 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 116758 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 116759 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 116760 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 116761 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 116762 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 116763 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 116764 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 116765 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 116766 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 116767 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 116768 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 116769 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 116770 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 116771 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 116772 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 116773 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 116774 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 116775 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 116776 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 116777 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 116778 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 116779 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 116780 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0 |
|---|
| 116781 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 116782 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 116783 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1 |
|---|
| 116784 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 116785 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 116786 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2 |
|---|
| 116787 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 116788 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 116789 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3 |
|---|
| 116790 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 116791 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 116792 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 116793 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 116794 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 116795 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 116796 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 116797 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 116798 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 116799 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 116800 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 116801 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 116802 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 116803 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 116804 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 116805 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 116806 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 116807 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 116808 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 116809 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 116810 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 116811 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP |
|---|
| 116812 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 116813 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 116814 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 116815 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 116816 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 116817 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 116818 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL |
|---|
| 116819 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 116820 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 116821 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 116822 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 116823 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 116824 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 116825 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 116826 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 116827 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 116828 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 116829 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 116830 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP |
|---|
| 116831 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 116832 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 116833 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 116834 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 116835 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 116836 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 116837 | //BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL |
|---|
| 116838 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 116839 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 116840 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 116841 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 116842 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 116843 | #define BIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 116844 | |
|---|
| 116845 | |
|---|
| 116846 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp |
|---|
| 116847 | //BIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID |
|---|
| 116848 | #define BIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 116849 | #define BIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 116850 | //BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID |
|---|
| 116851 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 116852 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 116853 | //BIF_CFG_DEV0_EPF0_VF26_1_COMMAND |
|---|
| 116854 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 116855 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 116856 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 116857 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 116858 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 116859 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 116860 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 116861 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 116862 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 116863 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 116864 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 116865 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 116866 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 116867 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 116868 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 116869 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 116870 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 116871 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 116872 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 116873 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 116874 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 116875 | #define BIF_CFG_DEV0_EPF0_VF26_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 116876 | //BIF_CFG_DEV0_EPF0_VF26_1_STATUS |
|---|
| 116877 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 116878 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 116879 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 116880 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 116881 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 116882 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 116883 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 116884 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 116885 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 116886 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 116887 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 116888 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 116889 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 116890 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 116891 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 116892 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 116893 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 116894 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 116895 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 116896 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 116897 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 116898 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 116899 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 116900 | #define BIF_CFG_DEV0_EPF0_VF26_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 116901 | //BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID |
|---|
| 116902 | #define BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 116903 | #define BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 116904 | #define BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 116905 | #define BIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 116906 | //BIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE |
|---|
| 116907 | #define BIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 116908 | #define BIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 116909 | //BIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS |
|---|
| 116910 | #define BIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 116911 | #define BIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 116912 | //BIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS |
|---|
| 116913 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 116914 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 116915 | //BIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE |
|---|
| 116916 | #define BIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 116917 | #define BIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 116918 | //BIF_CFG_DEV0_EPF0_VF26_1_LATENCY |
|---|
| 116919 | #define BIF_CFG_DEV0_EPF0_VF26_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 116920 | #define BIF_CFG_DEV0_EPF0_VF26_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 116921 | //BIF_CFG_DEV0_EPF0_VF26_1_HEADER |
|---|
| 116922 | #define 0x0 |
|---|
| 116923 | #define 0x7 |
|---|
| 116924 | #define 0x7FL |
|---|
| 116925 | #define 0x80L |
|---|
| 116926 | //BIF_CFG_DEV0_EPF0_VF26_1_BIST |
|---|
| 116927 | #define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 116928 | #define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 116929 | #define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 116930 | #define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 116931 | #define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 116932 | #define BIF_CFG_DEV0_EPF0_VF26_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 116933 | //BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1 |
|---|
| 116934 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 116935 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116936 | //BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2 |
|---|
| 116937 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 116938 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116939 | //BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3 |
|---|
| 116940 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 116941 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116942 | //BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4 |
|---|
| 116943 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 116944 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116945 | //BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5 |
|---|
| 116946 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 116947 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116948 | //BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6 |
|---|
| 116949 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 116950 | #define BIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116951 | //BIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR |
|---|
| 116952 | #define BIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 116953 | #define BIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 116954 | //BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID |
|---|
| 116955 | #define BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 116956 | #define BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 116957 | #define BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 116958 | #define BIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 116959 | //BIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR |
|---|
| 116960 | #define BIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 116961 | #define BIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 116962 | //BIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR |
|---|
| 116963 | #define BIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 116964 | #define BIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 116965 | //BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE |
|---|
| 116966 | #define BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 116967 | #define BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 116968 | //BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN |
|---|
| 116969 | #define BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 116970 | #define BIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 116971 | //BIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT |
|---|
| 116972 | #define BIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 116973 | #define BIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 116974 | //BIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY |
|---|
| 116975 | #define BIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 116976 | #define BIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 116977 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST |
|---|
| 116978 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 116979 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 116980 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 116981 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 116982 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP |
|---|
| 116983 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 116984 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 116985 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 116986 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 116987 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 116988 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 116989 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 116990 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 116991 | //BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP |
|---|
| 116992 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 116993 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 116994 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 116995 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 116996 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 116997 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 116998 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 116999 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 117000 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 117001 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 117002 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 117003 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 117004 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 117005 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 117006 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 117007 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 117008 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 117009 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 117010 | //BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL |
|---|
| 117011 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 117012 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 117013 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 117014 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 117015 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 117016 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 117017 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 117018 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 117019 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 117020 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 117021 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 117022 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 117023 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 117024 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 117025 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 117026 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 117027 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 117028 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 117029 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 117030 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 117031 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 117032 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 117033 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 117034 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 117035 | //BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS |
|---|
| 117036 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 117037 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 117038 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 117039 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 117040 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 117041 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 117042 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 117043 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 117044 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 117045 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 117046 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 117047 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 117048 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 117049 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 117050 | //BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP |
|---|
| 117051 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 117052 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 117053 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 117054 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 117055 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 117056 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 117057 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 117058 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 117059 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 117060 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 117061 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 117062 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 117063 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 117064 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 117065 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 117066 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 117067 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 117068 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 117069 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 117070 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 117071 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 117072 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 117073 | //BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL |
|---|
| 117074 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 117075 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 117076 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 117077 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 117078 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 117079 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 117080 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 117081 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 117082 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 117083 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 117084 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 117085 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 117086 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 117087 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 117088 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 117089 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 117090 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 117091 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 117092 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 117093 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 117094 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 117095 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 117096 | //BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS |
|---|
| 117097 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 117098 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 117099 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 117100 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 117101 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 117102 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 117103 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 117104 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 117105 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 117106 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 117107 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 117108 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 117109 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 117110 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 117111 | //BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2 |
|---|
| 117112 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 117113 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 117114 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 117115 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 117116 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 117117 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 117118 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 117119 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 117120 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 117121 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 117122 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 117123 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 117124 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 117125 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 117126 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 117127 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 117128 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 117129 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 117130 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 117131 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 117132 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 117133 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 117134 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 117135 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 117136 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 117137 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 117138 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 117139 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 117140 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 117141 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 117142 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 117143 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 117144 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 117145 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 117146 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 117147 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 117148 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 117149 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 117150 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 117151 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 117152 | //BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2 |
|---|
| 117153 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 117154 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 117155 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 117156 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 117157 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 117158 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 117159 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 117160 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 117161 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 117162 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 117163 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 117164 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 117165 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 117166 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 117167 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 117168 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 117169 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 117170 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 117171 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 117172 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 117173 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 117174 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 117175 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 117176 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 117177 | //BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2 |
|---|
| 117178 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 117179 | #define BIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 117180 | //BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2 |
|---|
| 117181 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 117182 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 117183 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 117184 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 117185 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 117186 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 117187 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 117188 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 117189 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 117190 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 117191 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 117192 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 117193 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 117194 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 117195 | //BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2 |
|---|
| 117196 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 117197 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 117198 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 117199 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 117200 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 117201 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 117202 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 117203 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 117204 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 117205 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 117206 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 117207 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 117208 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 117209 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 117210 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 117211 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 117212 | //BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2 |
|---|
| 117213 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 117214 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 117215 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 117216 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 117217 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 117218 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 117219 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 117220 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 117221 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 117222 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 117223 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 117224 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 117225 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 117226 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 117227 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 117228 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 117229 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 117230 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 117231 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 117232 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 117233 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 117234 | #define BIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 117235 | //BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST |
|---|
| 117236 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 117237 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 117238 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 117239 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 117240 | //BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL |
|---|
| 117241 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 117242 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 117243 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 117244 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 117245 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 117246 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 117247 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 117248 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 117249 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 117250 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 117251 | //BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO |
|---|
| 117252 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 117253 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 117254 | //BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI |
|---|
| 117255 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 117256 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 117257 | //BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA |
|---|
| 117258 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 117259 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 117260 | //BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK |
|---|
| 117261 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 117262 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 117263 | //BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64 |
|---|
| 117264 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 117265 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 117266 | //BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64 |
|---|
| 117267 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 117268 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 117269 | //BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING |
|---|
| 117270 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 117271 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 117272 | //BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64 |
|---|
| 117273 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 117274 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 117275 | //BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST |
|---|
| 117276 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 117277 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 117278 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 117279 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 117280 | //BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL |
|---|
| 117281 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 117282 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 117283 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 117284 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 117285 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 117286 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 117287 | //BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE |
|---|
| 117288 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 117289 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 117290 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 117291 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 117292 | //BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA |
|---|
| 117293 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 117294 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 117295 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 117296 | #define BIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 117297 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 117298 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 117299 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 117300 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 117301 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 117302 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 117303 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 117304 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 117305 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 117306 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 117307 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 117308 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 117309 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 117310 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 117311 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 117312 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 117313 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 117314 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 117315 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 117316 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 117317 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 117318 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 117319 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 117320 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 117321 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 117322 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 117323 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 117324 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 117325 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 117326 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 117327 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 117328 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 117329 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 117330 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 117331 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 117332 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 117333 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 117334 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 117335 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 117336 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 117337 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 117338 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 117339 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 117340 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 117341 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 117342 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 117343 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 117344 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 117345 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 117346 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 117347 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 117348 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 117349 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 117350 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 117351 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 117352 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 117353 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 117354 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 117355 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 117356 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 117357 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK |
|---|
| 117358 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 117359 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 117360 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 117361 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 117362 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 117363 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 117364 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 117365 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 117366 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 117367 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 117368 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 117369 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 117370 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 117371 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 117372 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 117373 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 117374 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 117375 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 117376 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 117377 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 117378 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 117379 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 117380 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 117381 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 117382 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 117383 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 117384 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 117385 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 117386 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 117387 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 117388 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 117389 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 117390 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 117391 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 117392 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 117393 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 117394 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 117395 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 117396 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 117397 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 117398 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 117399 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 117400 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 117401 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 117402 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 117403 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 117404 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 117405 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 117406 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 117407 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 117408 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 117409 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 117410 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 117411 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 117412 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 117413 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 117414 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 117415 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 117416 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 117417 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 117418 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 117419 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 117420 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 117421 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 117422 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 117423 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS |
|---|
| 117424 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 117425 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 117426 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 117427 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 117428 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 117429 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 117430 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 117431 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 117432 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 117433 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 117434 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 117435 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 117436 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 117437 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 117438 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 117439 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 117440 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK |
|---|
| 117441 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 117442 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 117443 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 117444 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 117445 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 117446 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 117447 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 117448 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 117449 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 117450 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 117451 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 117452 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 117453 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 117454 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 117455 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 117456 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 117457 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 117458 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 117459 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 117460 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 117461 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 117462 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 117463 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 117464 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 117465 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 117466 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 117467 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 117468 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 117469 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 117470 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 117471 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 117472 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 117473 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 117474 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 117475 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 117476 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0 |
|---|
| 117477 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 117478 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 117479 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1 |
|---|
| 117480 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 117481 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 117482 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2 |
|---|
| 117483 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 117484 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 117485 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3 |
|---|
| 117486 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 117487 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 117488 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 117489 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 117490 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 117491 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 117492 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 117493 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 117494 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 117495 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 117496 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 117497 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 117498 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 117499 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 117500 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 117501 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 117502 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 117503 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 117504 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 117505 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 117506 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 117507 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP |
|---|
| 117508 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 117509 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 117510 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 117511 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 117512 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 117513 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 117514 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL |
|---|
| 117515 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 117516 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 117517 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 117518 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 117519 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 117520 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 117521 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 117522 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 117523 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 117524 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 117525 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 117526 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP |
|---|
| 117527 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 117528 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 117529 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 117530 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 117531 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 117532 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 117533 | //BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL |
|---|
| 117534 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 117535 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 117536 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 117537 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 117538 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 117539 | #define BIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 117540 | |
|---|
| 117541 | |
|---|
| 117542 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp |
|---|
| 117543 | //BIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID |
|---|
| 117544 | #define BIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 117545 | #define BIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 117546 | //BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID |
|---|
| 117547 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 117548 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 117549 | //BIF_CFG_DEV0_EPF0_VF27_1_COMMAND |
|---|
| 117550 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 117551 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 117552 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 117553 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 117554 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 117555 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 117556 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 117557 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 117558 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 117559 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 117560 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 117561 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 117562 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 117563 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 117564 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 117565 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 117566 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 117567 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 117568 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 117569 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 117570 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 117571 | #define BIF_CFG_DEV0_EPF0_VF27_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 117572 | //BIF_CFG_DEV0_EPF0_VF27_1_STATUS |
|---|
| 117573 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 117574 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 117575 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 117576 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 117577 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 117578 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 117579 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 117580 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 117581 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 117582 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 117583 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 117584 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 117585 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 117586 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 117587 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 117588 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 117589 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 117590 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 117591 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 117592 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 117593 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 117594 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 117595 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 117596 | #define BIF_CFG_DEV0_EPF0_VF27_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 117597 | //BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID |
|---|
| 117598 | #define BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 117599 | #define BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 117600 | #define BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 117601 | #define BIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 117602 | //BIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE |
|---|
| 117603 | #define BIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 117604 | #define BIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 117605 | //BIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS |
|---|
| 117606 | #define BIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 117607 | #define BIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 117608 | //BIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS |
|---|
| 117609 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 117610 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 117611 | //BIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE |
|---|
| 117612 | #define BIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 117613 | #define BIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 117614 | //BIF_CFG_DEV0_EPF0_VF27_1_LATENCY |
|---|
| 117615 | #define BIF_CFG_DEV0_EPF0_VF27_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 117616 | #define BIF_CFG_DEV0_EPF0_VF27_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 117617 | //BIF_CFG_DEV0_EPF0_VF27_1_HEADER |
|---|
| 117618 | #define 0x0 |
|---|
| 117619 | #define 0x7 |
|---|
| 117620 | #define 0x7FL |
|---|
| 117621 | #define 0x80L |
|---|
| 117622 | //BIF_CFG_DEV0_EPF0_VF27_1_BIST |
|---|
| 117623 | #define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 117624 | #define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 117625 | #define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 117626 | #define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 117627 | #define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 117628 | #define BIF_CFG_DEV0_EPF0_VF27_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 117629 | //BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1 |
|---|
| 117630 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 117631 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 117632 | //BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2 |
|---|
| 117633 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 117634 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 117635 | //BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3 |
|---|
| 117636 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 117637 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 117638 | //BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4 |
|---|
| 117639 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 117640 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 117641 | //BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5 |
|---|
| 117642 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 117643 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 117644 | //BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6 |
|---|
| 117645 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 117646 | #define BIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 117647 | //BIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR |
|---|
| 117648 | #define BIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 117649 | #define BIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 117650 | //BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID |
|---|
| 117651 | #define BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 117652 | #define BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 117653 | #define BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 117654 | #define BIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 117655 | //BIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR |
|---|
| 117656 | #define BIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 117657 | #define BIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 117658 | //BIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR |
|---|
| 117659 | #define BIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 117660 | #define BIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 117661 | //BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE |
|---|
| 117662 | #define BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 117663 | #define BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 117664 | //BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN |
|---|
| 117665 | #define BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 117666 | #define BIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 117667 | //BIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT |
|---|
| 117668 | #define BIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 117669 | #define BIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 117670 | //BIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY |
|---|
| 117671 | #define BIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 117672 | #define BIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 117673 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST |
|---|
| 117674 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 117675 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 117676 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 117677 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 117678 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP |
|---|
| 117679 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 117680 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 117681 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 117682 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 117683 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 117684 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 117685 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 117686 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 117687 | //BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP |
|---|
| 117688 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 117689 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 117690 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 117691 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 117692 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 117693 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 117694 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 117695 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 117696 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 117697 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 117698 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 117699 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 117700 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 117701 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 117702 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 117703 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 117704 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 117705 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 117706 | //BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL |
|---|
| 117707 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 117708 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 117709 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 117710 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 117711 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 117712 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 117713 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 117714 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 117715 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 117716 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 117717 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 117718 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 117719 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 117720 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 117721 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 117722 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 117723 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 117724 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 117725 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 117726 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 117727 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 117728 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 117729 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 117730 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 117731 | //BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS |
|---|
| 117732 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 117733 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 117734 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 117735 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 117736 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 117737 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 117738 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 117739 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 117740 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 117741 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 117742 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 117743 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 117744 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 117745 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 117746 | //BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP |
|---|
| 117747 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 117748 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 117749 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 117750 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 117751 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 117752 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 117753 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 117754 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 117755 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 117756 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 117757 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 117758 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 117759 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 117760 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 117761 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 117762 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 117763 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 117764 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 117765 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 117766 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 117767 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 117768 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 117769 | //BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL |
|---|
| 117770 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 117771 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 117772 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 117773 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 117774 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 117775 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 117776 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 117777 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 117778 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 117779 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 117780 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 117781 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 117782 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 117783 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 117784 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 117785 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 117786 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 117787 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 117788 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 117789 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 117790 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 117791 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 117792 | //BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS |
|---|
| 117793 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 117794 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 117795 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 117796 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 117797 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 117798 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 117799 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 117800 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 117801 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 117802 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 117803 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 117804 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 117805 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 117806 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 117807 | //BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2 |
|---|
| 117808 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 117809 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 117810 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 117811 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 117812 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 117813 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 117814 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 117815 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 117816 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 117817 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 117818 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 117819 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 117820 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 117821 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 117822 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 117823 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 117824 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 117825 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 117826 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 117827 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 117828 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 117829 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 117830 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 117831 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 117832 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 117833 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 117834 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 117835 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 117836 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 117837 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 117838 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 117839 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 117840 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 117841 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 117842 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 117843 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 117844 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 117845 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 117846 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 117847 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 117848 | //BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2 |
|---|
| 117849 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 117850 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 117851 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 117852 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 117853 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 117854 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 117855 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 117856 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 117857 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 117858 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 117859 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 117860 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 117861 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 117862 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 117863 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 117864 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 117865 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 117866 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 117867 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 117868 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 117869 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 117870 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 117871 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 117872 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 117873 | //BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2 |
|---|
| 117874 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 117875 | #define BIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 117876 | //BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2 |
|---|
| 117877 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 117878 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 117879 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 117880 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 117881 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 117882 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 117883 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 117884 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 117885 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 117886 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 117887 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 117888 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 117889 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 117890 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 117891 | //BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2 |
|---|
| 117892 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 117893 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 117894 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 117895 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 117896 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 117897 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 117898 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 117899 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 117900 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 117901 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 117902 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 117903 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 117904 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 117905 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 117906 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 117907 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 117908 | //BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2 |
|---|
| 117909 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 117910 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 117911 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 117912 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 117913 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 117914 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 117915 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 117916 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 117917 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 117918 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 117919 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 117920 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 117921 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 117922 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 117923 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 117924 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 117925 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 117926 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 117927 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 117928 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 117929 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 117930 | #define BIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 117931 | //BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST |
|---|
| 117932 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 117933 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 117934 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 117935 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 117936 | //BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL |
|---|
| 117937 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 117938 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 117939 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 117940 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 117941 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 117942 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 117943 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 117944 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 117945 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 117946 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 117947 | //BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO |
|---|
| 117948 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 117949 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 117950 | //BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI |
|---|
| 117951 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 117952 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 117953 | //BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA |
|---|
| 117954 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 117955 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 117956 | //BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK |
|---|
| 117957 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 117958 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 117959 | //BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64 |
|---|
| 117960 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 117961 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 117962 | //BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64 |
|---|
| 117963 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 117964 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 117965 | //BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING |
|---|
| 117966 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 117967 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 117968 | //BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64 |
|---|
| 117969 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 117970 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 117971 | //BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST |
|---|
| 117972 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 117973 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 117974 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 117975 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 117976 | //BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL |
|---|
| 117977 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 117978 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 117979 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 117980 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 117981 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 117982 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 117983 | //BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE |
|---|
| 117984 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 117985 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 117986 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 117987 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 117988 | //BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA |
|---|
| 117989 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 117990 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 117991 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 117992 | #define BIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 117993 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 117994 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 117995 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 117996 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 117997 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 117998 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 117999 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 118000 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 118001 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 118002 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 118003 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 118004 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 118005 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 118006 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 118007 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 118008 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 118009 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 118010 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 118011 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 118012 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 118013 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 118014 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 118015 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 118016 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 118017 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 118018 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 118019 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 118020 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 118021 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 118022 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 118023 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 118024 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 118025 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 118026 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 118027 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 118028 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 118029 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 118030 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 118031 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 118032 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 118033 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 118034 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 118035 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 118036 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 118037 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 118038 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 118039 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 118040 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 118041 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 118042 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 118043 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 118044 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 118045 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 118046 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 118047 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 118048 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 118049 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 118050 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 118051 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 118052 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 118053 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK |
|---|
| 118054 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 118055 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 118056 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 118057 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 118058 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 118059 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 118060 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 118061 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 118062 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 118063 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 118064 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 118065 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 118066 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 118067 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 118068 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 118069 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 118070 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 118071 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 118072 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 118073 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 118074 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 118075 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 118076 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 118077 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 118078 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 118079 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 118080 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 118081 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 118082 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 118083 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 118084 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 118085 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 118086 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 118087 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 118088 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 118089 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 118090 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 118091 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 118092 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 118093 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 118094 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 118095 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 118096 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 118097 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 118098 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 118099 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 118100 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 118101 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 118102 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 118103 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 118104 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 118105 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 118106 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 118107 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 118108 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 118109 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 118110 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 118111 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 118112 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 118113 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 118114 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 118115 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 118116 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 118117 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 118118 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 118119 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS |
|---|
| 118120 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 118121 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 118122 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 118123 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 118124 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 118125 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 118126 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 118127 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 118128 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 118129 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 118130 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 118131 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 118132 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 118133 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 118134 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 118135 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 118136 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK |
|---|
| 118137 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 118138 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 118139 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 118140 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 118141 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 118142 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 118143 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 118144 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 118145 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 118146 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 118147 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 118148 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 118149 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 118150 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 118151 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 118152 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 118153 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 118154 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 118155 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 118156 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 118157 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 118158 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 118159 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 118160 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 118161 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 118162 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 118163 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 118164 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 118165 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 118166 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 118167 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 118168 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 118169 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 118170 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 118171 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 118172 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0 |
|---|
| 118173 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 118174 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 118175 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1 |
|---|
| 118176 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 118177 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 118178 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2 |
|---|
| 118179 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 118180 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 118181 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3 |
|---|
| 118182 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 118183 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 118184 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 118185 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 118186 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 118187 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 118188 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 118189 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 118190 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 118191 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 118192 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 118193 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 118194 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 118195 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 118196 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 118197 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 118198 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 118199 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 118200 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 118201 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 118202 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 118203 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP |
|---|
| 118204 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
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| 118205 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 118206 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 118207 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 118208 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 118209 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 118210 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL |
|---|
| 118211 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 118212 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 118213 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 118214 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 118215 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 118216 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 118217 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 118218 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 118219 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 118220 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 118221 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 118222 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP |
|---|
| 118223 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 118224 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 118225 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 118226 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 118227 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 118228 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 118229 | //BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL |
|---|
| 118230 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 118231 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 118232 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 118233 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 118234 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 118235 | #define BIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 118236 | |
|---|
| 118237 | |
|---|
| 118238 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp |
|---|
| 118239 | //BIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID |
|---|
| 118240 | #define BIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 118241 | #define BIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 118242 | //BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID |
|---|
| 118243 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 118244 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 118245 | //BIF_CFG_DEV0_EPF0_VF28_1_COMMAND |
|---|
| 118246 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 118247 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 118248 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 118249 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 118250 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 118251 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 118252 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 118253 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 118254 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 118255 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 118256 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 118257 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 118258 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 118259 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 118260 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 118261 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 118262 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 118263 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 118264 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 118265 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 118266 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 118267 | #define BIF_CFG_DEV0_EPF0_VF28_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 118268 | //BIF_CFG_DEV0_EPF0_VF28_1_STATUS |
|---|
| 118269 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 118270 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 118271 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 118272 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 118273 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 118274 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 118275 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 118276 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 118277 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 118278 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 118279 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 118280 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 118281 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 118282 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 118283 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 118284 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 118285 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 118286 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 118287 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 118288 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 118289 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 118290 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 118291 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 118292 | #define BIF_CFG_DEV0_EPF0_VF28_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 118293 | //BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID |
|---|
| 118294 | #define BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 118295 | #define BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 118296 | #define BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 118297 | #define BIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 118298 | //BIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE |
|---|
| 118299 | #define BIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 118300 | #define BIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 118301 | //BIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS |
|---|
| 118302 | #define BIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 118303 | #define BIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 118304 | //BIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS |
|---|
| 118305 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 118306 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 118307 | //BIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE |
|---|
| 118308 | #define BIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 118309 | #define BIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 118310 | //BIF_CFG_DEV0_EPF0_VF28_1_LATENCY |
|---|
| 118311 | #define BIF_CFG_DEV0_EPF0_VF28_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 118312 | #define BIF_CFG_DEV0_EPF0_VF28_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 118313 | //BIF_CFG_DEV0_EPF0_VF28_1_HEADER |
|---|
| 118314 | #define 0x0 |
|---|
| 118315 | #define 0x7 |
|---|
| 118316 | #define 0x7FL |
|---|
| 118317 | #define 0x80L |
|---|
| 118318 | //BIF_CFG_DEV0_EPF0_VF28_1_BIST |
|---|
| 118319 | #define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 118320 | #define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 118321 | #define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 118322 | #define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 118323 | #define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 118324 | #define BIF_CFG_DEV0_EPF0_VF28_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 118325 | //BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1 |
|---|
| 118326 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 118327 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 118328 | //BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2 |
|---|
| 118329 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 118330 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 118331 | //BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3 |
|---|
| 118332 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 118333 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 118334 | //BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4 |
|---|
| 118335 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 118336 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 118337 | //BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5 |
|---|
| 118338 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 118339 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 118340 | //BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6 |
|---|
| 118341 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 118342 | #define BIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 118343 | //BIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR |
|---|
| 118344 | #define BIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 118345 | #define BIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 118346 | //BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID |
|---|
| 118347 | #define BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 118348 | #define BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 118349 | #define BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 118350 | #define BIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 118351 | //BIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR |
|---|
| 118352 | #define BIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 118353 | #define BIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 118354 | //BIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR |
|---|
| 118355 | #define BIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 118356 | #define BIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 118357 | //BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE |
|---|
| 118358 | #define BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 118359 | #define BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 118360 | //BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN |
|---|
| 118361 | #define BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 118362 | #define BIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 118363 | //BIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT |
|---|
| 118364 | #define BIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 118365 | #define BIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 118366 | //BIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY |
|---|
| 118367 | #define BIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 118368 | #define BIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 118369 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST |
|---|
| 118370 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 118371 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 118372 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 118373 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 118374 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP |
|---|
| 118375 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 118376 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 118377 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 118378 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 118379 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 118380 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 118381 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 118382 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 118383 | //BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP |
|---|
| 118384 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 118385 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 118386 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 118387 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 118388 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 118389 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 118390 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 118391 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 118392 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 118393 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
|---|
| 118394 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
|---|
| 118395 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 118396 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
|---|
| 118397 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
|---|
| 118398 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 118399 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
|---|
| 118400 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
|---|
| 118401 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
|---|
| 118402 | //BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL |
|---|
| 118403 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 118404 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
|---|
| 118405 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 118406 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
|---|
| 118407 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
|---|
| 118408 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
|---|
| 118409 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
|---|
| 118410 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
|---|
| 118411 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 118412 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
|---|
| 118413 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
|---|
| 118414 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
|---|
| 118415 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 118416 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 118417 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 118418 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 118419 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
|---|
| 118420 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
|---|
| 118421 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
|---|
| 118422 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
|---|
| 118423 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 118424 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
|---|
| 118425 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
|---|
| 118426 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
|---|
| 118427 | //BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS |
|---|
| 118428 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 118429 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 118430 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 118431 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
|---|
| 118432 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
|---|
| 118433 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
|---|
| 118434 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
|---|
| 118435 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 118436 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 118437 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 118438 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 118439 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 118440 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 118441 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 118442 | //BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP |
|---|
| 118443 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 118444 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
|---|
| 118445 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 118446 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 118447 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 118448 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 118449 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 118450 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
|---|
| 118451 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 118452 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 118453 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 118454 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 118455 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 118456 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 118457 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 118458 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 118459 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 118460 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 118461 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 118462 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 118463 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 118464 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 118465 | //BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL |
|---|
| 118466 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 118467 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 118468 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 118469 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 118470 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 118471 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 118472 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 118473 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 118474 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 118475 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 118476 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 118477 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 118478 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 118479 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 118480 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 118481 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 118482 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 118483 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 118484 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 118485 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 118486 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 118487 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 118488 | //BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS |
|---|
| 118489 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 118490 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 118491 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 118492 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 118493 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 118494 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 118495 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 118496 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 118497 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 118498 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 118499 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 118500 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 118501 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 118502 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 118503 | //BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2 |
|---|
| 118504 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 118505 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 118506 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 118507 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 118508 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 118509 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 118510 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 118511 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 118512 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 118513 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 118514 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 118515 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 118516 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 118517 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 118518 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 118519 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 118520 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 118521 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 118522 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 118523 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 118524 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 118525 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 118526 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 118527 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 118528 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 118529 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 118530 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 118531 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 118532 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 118533 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 118534 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 118535 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 118536 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 118537 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 118538 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 118539 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 118540 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 118541 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 118542 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 118543 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 118544 | //BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2 |
|---|
| 118545 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 118546 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 118547 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 118548 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 118549 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 118550 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 118551 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 118552 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 118553 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 118554 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 118555 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 118556 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 118557 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 118558 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 118559 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 118560 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 118561 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 118562 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 118563 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 118564 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 118565 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 118566 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 118567 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 118568 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 118569 | //BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2 |
|---|
| 118570 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 118571 | #define BIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 118572 | //BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2 |
|---|
| 118573 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 118574 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 118575 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 118576 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 118577 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 118578 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 118579 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 118580 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 118581 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 118582 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 118583 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 118584 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 118585 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 118586 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 118587 | //BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2 |
|---|
| 118588 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 118589 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 118590 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 118591 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 118592 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 118593 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 118594 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 118595 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 118596 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 118597 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 118598 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 118599 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 118600 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 118601 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 118602 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 118603 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 118604 | //BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2 |
|---|
| 118605 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 118606 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 118607 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 118608 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 118609 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 118610 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 118611 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 118612 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 118613 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 118614 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 118615 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 118616 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 118617 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 118618 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 118619 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 118620 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 118621 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 118622 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 118623 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 118624 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 118625 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 118626 | #define BIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 118627 | //BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST |
|---|
| 118628 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 118629 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 118630 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 118631 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 118632 | //BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL |
|---|
| 118633 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 118634 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 118635 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 118636 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 118637 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 118638 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 118639 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 118640 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 118641 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 118642 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 118643 | //BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO |
|---|
| 118644 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 118645 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 118646 | //BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI |
|---|
| 118647 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 118648 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 118649 | //BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA |
|---|
| 118650 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 118651 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 118652 | //BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK |
|---|
| 118653 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 118654 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 118655 | //BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64 |
|---|
| 118656 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 118657 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 118658 | //BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64 |
|---|
| 118659 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 118660 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 118661 | //BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING |
|---|
| 118662 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 118663 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 118664 | //BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64 |
|---|
| 118665 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 118666 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 118667 | //BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST |
|---|
| 118668 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 118669 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 118670 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 118671 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 118672 | //BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL |
|---|
| 118673 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 118674 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 118675 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 118676 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 118677 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 118678 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 118679 | //BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE |
|---|
| 118680 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 118681 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 118682 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 118683 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 118684 | //BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA |
|---|
| 118685 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 118686 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 118687 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 118688 | #define BIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 118689 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 118690 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 118691 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 118692 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 118693 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 118694 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 118695 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 118696 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 118697 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 118698 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 118699 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 118700 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 118701 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 118702 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 118703 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 118704 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 118705 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 118706 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 118707 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 118708 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 118709 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 118710 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 118711 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 118712 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 118713 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 118714 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 118715 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 118716 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 118717 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 118718 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 118719 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 118720 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 118721 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 118722 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 118723 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 118724 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 118725 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 118726 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 118727 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 118728 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 118729 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 118730 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 118731 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 118732 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 118733 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 118734 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 118735 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 118736 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 118737 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 118738 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 118739 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 118740 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 118741 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 118742 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 118743 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 118744 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 118745 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 118746 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 118747 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 118748 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 118749 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK |
|---|
| 118750 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 118751 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 118752 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 118753 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 118754 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 118755 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 118756 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 118757 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 118758 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 118759 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 118760 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 118761 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 118762 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 118763 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 118764 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 118765 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 118766 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 118767 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 118768 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 118769 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 118770 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 118771 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 118772 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 118773 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 118774 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 118775 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 118776 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 118777 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 118778 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 118779 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 118780 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 118781 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 118782 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 118783 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 118784 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 118785 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 118786 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 118787 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 118788 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 118789 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 118790 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 118791 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 118792 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 118793 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 118794 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 118795 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 118796 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 118797 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 118798 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 118799 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 118800 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 118801 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 118802 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 118803 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 118804 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 118805 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 118806 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 118807 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 118808 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 118809 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 118810 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 118811 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 118812 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 118813 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 118814 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 118815 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS |
|---|
| 118816 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 118817 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 118818 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 118819 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 118820 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 118821 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 118822 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 118823 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 118824 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 118825 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 118826 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 118827 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 118828 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 118829 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 118830 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 118831 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 118832 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK |
|---|
| 118833 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 118834 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 118835 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 118836 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 118837 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 118838 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 118839 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 118840 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 118841 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 118842 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 118843 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 118844 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 118845 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 118846 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 118847 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 118848 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 118849 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 118850 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 118851 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 118852 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 118853 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 118854 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 118855 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 118856 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 118857 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 118858 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 118859 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 118860 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 118861 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 118862 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 118863 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 118864 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 118865 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 118866 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 118867 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 118868 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0 |
|---|
| 118869 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 118870 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 118871 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1 |
|---|
| 118872 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 118873 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 118874 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2 |
|---|
| 118875 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 118876 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 118877 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3 |
|---|
| 118878 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 118879 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 118880 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 118881 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 118882 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 118883 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 118884 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 118885 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 118886 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 118887 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 118888 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 118889 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 118890 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 118891 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 118892 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 118893 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 118894 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 118895 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 118896 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 118897 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 118898 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 118899 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP |
|---|
| 118900 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 118901 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 118902 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 118903 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 118904 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 118905 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 118906 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL |
|---|
| 118907 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 118908 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 118909 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 118910 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 118911 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 118912 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 118913 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 118914 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 118915 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 118916 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 118917 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 118918 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP |
|---|
| 118919 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 118920 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 118921 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 118922 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 118923 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 118924 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 118925 | //BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL |
|---|
| 118926 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 118927 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 118928 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 118929 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 118930 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 118931 | #define BIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 118932 | |
|---|
| 118933 | |
|---|
| 118934 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp |
|---|
| 118935 | //BIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID |
|---|
| 118936 | #define BIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 118937 | #define BIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 118938 | //BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID |
|---|
| 118939 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 118940 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 118941 | //BIF_CFG_DEV0_EPF0_VF29_1_COMMAND |
|---|
| 118942 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 118943 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 118944 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 118945 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 118946 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 118947 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 118948 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 118949 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 118950 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 118951 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 118952 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 118953 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 118954 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 118955 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 118956 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 118957 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 118958 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 118959 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 118960 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 118961 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 118962 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 118963 | #define BIF_CFG_DEV0_EPF0_VF29_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 118964 | //BIF_CFG_DEV0_EPF0_VF29_1_STATUS |
|---|
| 118965 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 118966 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 118967 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 118968 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 118969 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 118970 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 118971 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 118972 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 118973 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 118974 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 118975 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 118976 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 118977 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 118978 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 118979 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 118980 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 118981 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 118982 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 118983 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 118984 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 118985 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 118986 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 118987 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 118988 | #define BIF_CFG_DEV0_EPF0_VF29_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 118989 | //BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID |
|---|
| 118990 | #define BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 118991 | #define BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 118992 | #define BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 118993 | #define BIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 118994 | //BIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE |
|---|
| 118995 | #define BIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 118996 | #define BIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 118997 | //BIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS |
|---|
| 118998 | #define BIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 118999 | #define BIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 119000 | //BIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS |
|---|
| 119001 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 119002 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 119003 | //BIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE |
|---|
| 119004 | #define BIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 119005 | #define BIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 119006 | //BIF_CFG_DEV0_EPF0_VF29_1_LATENCY |
|---|
| 119007 | #define BIF_CFG_DEV0_EPF0_VF29_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 119008 | #define BIF_CFG_DEV0_EPF0_VF29_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 119009 | //BIF_CFG_DEV0_EPF0_VF29_1_HEADER |
|---|
| 119010 | #define 0x0 |
|---|
| 119011 | #define 0x7 |
|---|
| 119012 | #define 0x7FL |
|---|
| 119013 | #define 0x80L |
|---|
| 119014 | //BIF_CFG_DEV0_EPF0_VF29_1_BIST |
|---|
| 119015 | #define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 119016 | #define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 119017 | #define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 119018 | #define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 119019 | #define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 119020 | #define BIF_CFG_DEV0_EPF0_VF29_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 119021 | //BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1 |
|---|
| 119022 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 119023 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 119024 | //BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2 |
|---|
| 119025 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 119026 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 119027 | //BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3 |
|---|
| 119028 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 119029 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 119030 | //BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4 |
|---|
| 119031 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 119032 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 119033 | //BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5 |
|---|
| 119034 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 119035 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 119036 | //BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6 |
|---|
| 119037 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 119038 | #define BIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 119039 | //BIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR |
|---|
| 119040 | #define BIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
|---|
| 119041 | #define BIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
|---|
| 119042 | //BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID |
|---|
| 119043 | #define BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 119044 | #define BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 119045 | #define BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 119046 | #define BIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 119047 | //BIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR |
|---|
| 119048 | #define BIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 119049 | #define BIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 119050 | //BIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR |
|---|
| 119051 | #define BIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 119052 | #define BIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
|---|
| 119053 | //BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE |
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| 119054 | #define BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
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| 119055 | #define BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
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| 119056 | //BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN |
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| 119057 | #define BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
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| 119058 | #define BIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
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| 119059 | //BIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT |
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| 119060 | #define BIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
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| 119061 | #define BIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
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| 119062 | //BIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY |
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| 119063 | #define BIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
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| 119064 | #define BIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
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| 119065 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST |
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| 119066 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 119067 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 119068 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 119069 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 119070 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP |
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| 119071 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__VERSION__SHIFT 0x0 |
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| 119072 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 119073 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 119074 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
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| 119075 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__VERSION_MASK 0x000FL |
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| 119076 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
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| 119077 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
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| 119078 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
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| 119079 | //BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP |
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| 119080 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
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| 119081 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
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| 119082 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
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| 119083 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
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| 119084 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
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| 119085 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
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| 119086 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
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| 119087 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
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| 119088 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
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| 119089 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 119090 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 119091 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
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| 119092 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
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| 119093 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
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| 119094 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
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| 119095 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
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| 119096 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
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| 119097 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
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| 119098 | //BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL |
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| 119099 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
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| 119100 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
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| 119101 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
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| 119102 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
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| 119103 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 119104 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 119105 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
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| 119106 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
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| 119107 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
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| 119108 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 119109 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 119110 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
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| 119111 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
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| 119112 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
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| 119113 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
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| 119114 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
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| 119115 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
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| 119116 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
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| 119117 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
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| 119118 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
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| 119119 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
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| 119120 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
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| 119121 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
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| 119122 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
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| 119123 | //BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS |
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| 119124 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
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| 119125 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
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| 119126 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
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| 119127 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 119128 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 119129 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 119130 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
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| 119131 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
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| 119132 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 119133 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
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| 119134 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
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| 119135 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
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| 119136 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
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| 119137 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
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| 119138 | //BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP |
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| 119139 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
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| 119140 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 119141 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 119142 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
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| 119143 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 119144 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
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| 119145 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
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| 119146 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 119147 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
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| 119148 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 119149 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 119150 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
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| 119151 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
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| 119152 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
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| 119153 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
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| 119154 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
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| 119155 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
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| 119156 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
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| 119157 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
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| 119158 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
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| 119159 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
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| 119160 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
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| 119161 | //BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL |
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| 119162 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
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| 119163 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
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| 119164 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
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| 119165 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
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| 119166 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
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| 119167 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
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| 119168 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
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| 119169 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
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| 119170 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
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| 119171 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
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| 119172 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
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| 119173 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
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| 119174 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
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| 119175 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
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| 119176 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
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| 119177 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
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| 119178 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
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| 119179 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
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| 119180 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
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| 119181 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
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| 119182 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
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| 119183 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
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| 119184 | //BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS |
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| 119185 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
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| 119186 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
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| 119187 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
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| 119188 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
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| 119189 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
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| 119190 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
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| 119191 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
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| 119192 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
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| 119193 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
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| 119194 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
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| 119195 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
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| 119196 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
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| 119197 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
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| 119198 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
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| 119199 | //BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2 |
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| 119200 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 119201 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
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| 119202 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
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| 119203 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
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| 119204 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
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| 119205 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
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| 119206 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
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| 119207 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 119208 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
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| 119209 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
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| 119210 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
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| 119211 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
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| 119212 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 119213 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
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| 119214 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
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| 119215 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
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| 119216 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
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| 119217 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 119218 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
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| 119219 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
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| 119220 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 119221 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 119222 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
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| 119223 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 119224 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 119225 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 119226 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 119227 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 119228 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 119229 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 119230 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 119231 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 119232 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 119233 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 119234 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 119235 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 119236 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 119237 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 119238 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 119239 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 119240 | //BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2 |
|---|
| 119241 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 119242 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 119243 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 119244 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 119245 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 119246 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 119247 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 119248 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 119249 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 119250 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 119251 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 119252 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 119253 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 119254 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 119255 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 119256 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 119257 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 119258 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 119259 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 119260 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 119261 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 119262 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 119263 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 119264 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 119265 | //BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2 |
|---|
| 119266 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 119267 | #define BIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 119268 | //BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2 |
|---|
| 119269 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 119270 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 119271 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 119272 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 119273 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 119274 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 119275 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 119276 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 119277 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 119278 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 119279 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 119280 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 119281 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 119282 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 119283 | //BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2 |
|---|
| 119284 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 119285 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 119286 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 119287 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 119288 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 119289 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 119290 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 119291 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 119292 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 119293 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 119294 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 119295 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 119296 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 119297 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 119298 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 119299 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 119300 | //BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2 |
|---|
| 119301 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 119302 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 119303 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 119304 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 119305 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 119306 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 119307 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 119308 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 119309 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 119310 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 119311 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 119312 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 119313 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 119314 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 119315 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 119316 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 119317 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 119318 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 119319 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 119320 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 119321 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 119322 | #define BIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 119323 | //BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST |
|---|
| 119324 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 119325 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 119326 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 119327 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 119328 | //BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL |
|---|
| 119329 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 119330 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 119331 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 119332 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 119333 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 119334 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 119335 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 119336 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 119337 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 119338 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 119339 | //BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO |
|---|
| 119340 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 119341 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 119342 | //BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI |
|---|
| 119343 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 119344 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 119345 | //BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA |
|---|
| 119346 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 119347 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 119348 | //BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK |
|---|
| 119349 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 119350 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 119351 | //BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64 |
|---|
| 119352 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 119353 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 119354 | //BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64 |
|---|
| 119355 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 119356 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 119357 | //BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING |
|---|
| 119358 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 119359 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 119360 | //BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64 |
|---|
| 119361 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 119362 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 119363 | //BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST |
|---|
| 119364 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 119365 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 119366 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 119367 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 119368 | //BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL |
|---|
| 119369 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 119370 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 119371 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 119372 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 119373 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 119374 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 119375 | //BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE |
|---|
| 119376 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 119377 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 119378 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 119379 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 119380 | //BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA |
|---|
| 119381 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 119382 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 119383 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 119384 | #define BIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 119385 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 119386 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 119387 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 119388 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 119389 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 119390 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 119391 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 119392 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 119393 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 119394 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 119395 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 119396 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
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| 119397 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 119398 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 119399 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 119400 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
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| 119401 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
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| 119402 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 119403 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
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| 119404 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 119405 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 119406 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 119407 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 119408 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 119409 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 119410 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 119411 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 119412 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 119413 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
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| 119414 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 119415 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 119416 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 119417 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 119418 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 119419 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 119420 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 119421 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 119422 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 119423 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 119424 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 119425 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 119426 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 119427 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 119428 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 119429 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 119430 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 119431 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 119432 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 119433 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 119434 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 119435 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 119436 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 119437 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 119438 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 119439 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 119440 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 119441 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 119442 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 119443 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 119444 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 119445 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK |
|---|
| 119446 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 119447 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 119448 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 119449 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 119450 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 119451 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 119452 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 119453 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 119454 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 119455 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 119456 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 119457 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 119458 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 119459 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 119460 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 119461 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 119462 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 119463 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 119464 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 119465 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 119466 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 119467 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 119468 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 119469 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 119470 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 119471 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 119472 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 119473 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 119474 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 119475 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 119476 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 119477 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 119478 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 119479 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 119480 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 119481 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 119482 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 119483 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 119484 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 119485 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 119486 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 119487 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 119488 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 119489 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 119490 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 119491 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 119492 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 119493 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 119494 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 119495 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 119496 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 119497 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 119498 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 119499 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 119500 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 119501 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 119502 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 119503 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 119504 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 119505 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 119506 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 119507 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 119508 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 119509 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 119510 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 119511 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS |
|---|
| 119512 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 119513 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 119514 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 119515 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 119516 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 119517 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 119518 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 119519 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 119520 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 119521 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 119522 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 119523 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 119524 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 119525 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 119526 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 119527 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 119528 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK |
|---|
| 119529 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 119530 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 119531 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 119532 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 119533 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 119534 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 119535 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 119536 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 119537 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 119538 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 119539 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 119540 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 119541 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 119542 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 119543 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 119544 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 119545 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 119546 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 119547 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 119548 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 119549 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 119550 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 119551 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 119552 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 119553 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 119554 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 119555 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 119556 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 119557 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 119558 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 119559 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 119560 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 119561 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 119562 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 119563 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 119564 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0 |
|---|
| 119565 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 119566 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 119567 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1 |
|---|
| 119568 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 119569 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 119570 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2 |
|---|
| 119571 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 119572 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 119573 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3 |
|---|
| 119574 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 119575 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 119576 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 119577 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 119578 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 119579 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 119580 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 119581 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 119582 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 119583 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 119584 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 119585 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 119586 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 119587 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 119588 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 119589 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 119590 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 119591 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 119592 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 119593 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 119594 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 119595 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP |
|---|
| 119596 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 119597 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 119598 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 119599 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 119600 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 119601 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 119602 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL |
|---|
| 119603 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 119604 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 119605 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 119606 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 119607 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 119608 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 119609 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 119610 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 119611 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 119612 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 119613 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 119614 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP |
|---|
| 119615 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 119616 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 119617 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 119618 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 119619 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 119620 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 119621 | //BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL |
|---|
| 119622 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 119623 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 119624 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 119625 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 119626 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 119627 | #define BIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 119628 | |
|---|
| 119629 | |
|---|
| 119630 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp |
|---|
| 119631 | //BIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID |
|---|
| 119632 | #define BIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 119633 | #define BIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 119634 | //BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID |
|---|
| 119635 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 119636 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 119637 | //BIF_CFG_DEV0_EPF0_VF30_1_COMMAND |
|---|
| 119638 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 119639 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 119640 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 119641 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 119642 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 119643 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 119644 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 119645 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 119646 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 119647 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 119648 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 119649 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 119650 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 119651 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 119652 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 119653 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 119654 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 119655 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 119656 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 119657 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 119658 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 119659 | #define BIF_CFG_DEV0_EPF0_VF30_1_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 119660 | //BIF_CFG_DEV0_EPF0_VF30_1_STATUS |
|---|
| 119661 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 |
|---|
| 119662 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 119663 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 119664 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PCI_66_CAP__SHIFT 0x5 |
|---|
| 119665 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 119666 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 119667 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 119668 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 119669 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 119670 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 119671 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 119672 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 119673 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L |
|---|
| 119674 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 119675 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 119676 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PCI_66_CAP_MASK 0x0020L |
|---|
| 119677 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 119678 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 119679 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 119680 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 119681 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 119682 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 119683 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 119684 | #define BIF_CFG_DEV0_EPF0_VF30_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 119685 | //BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID |
|---|
| 119686 | #define BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 119687 | #define BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 119688 | #define BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 119689 | #define BIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 119690 | //BIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE |
|---|
| 119691 | #define BIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 119692 | #define BIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 119693 | //BIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS |
|---|
| 119694 | #define BIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 119695 | #define BIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 119696 | //BIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS |
|---|
| 119697 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 119698 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 119699 | //BIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE |
|---|
| 119700 | #define BIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 119701 | #define BIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 119702 | //BIF_CFG_DEV0_EPF0_VF30_1_LATENCY |
|---|
| 119703 | #define BIF_CFG_DEV0_EPF0_VF30_1_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 119704 | #define BIF_CFG_DEV0_EPF0_VF30_1_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 119705 | //BIF_CFG_DEV0_EPF0_VF30_1_HEADER |
|---|
| 119706 | #define 0x0 |
|---|
| 119707 | #define 0x7 |
|---|
| 119708 | #define 0x7FL |
|---|
| 119709 | #define 0x80L |
|---|
| 119710 | //BIF_CFG_DEV0_EPF0_VF30_1_BIST |
|---|
| 119711 | #define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 119712 | #define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 119713 | #define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 119714 | #define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 119715 | #define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_STRT_MASK 0x40L |
|---|
| 119716 | #define BIF_CFG_DEV0_EPF0_VF30_1_BIST__BIST_CAP_MASK 0x80L |
|---|
| 119717 | //BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1 |
|---|
| 119718 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 119719 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 119720 | //BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2 |
|---|
| 119721 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 119722 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 119723 | //BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3 |
|---|
| 119724 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
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| 119725 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 119726 | //BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4 |
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| 119727 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
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| 119728 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 119729 | //BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5 |
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| 119730 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
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| 119731 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 119732 | //BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6 |
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| 119733 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
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| 119734 | #define BIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 119735 | //BIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR |
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| 119736 | #define BIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 |
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| 119737 | #define BIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL |
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| 119738 | //BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID |
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| 119739 | #define BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
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| 119740 | #define BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
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| 119741 | #define BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
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| 119742 | #define BIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
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| 119743 | //BIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR |
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| 119744 | #define BIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
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| 119745 | #define BIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
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| 119746 | //BIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR |
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| 119747 | #define BIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR__CAP_PTR__SHIFT 0x0 |
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| 119748 | #define BIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR__CAP_PTR_MASK 0xFFL |
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| 119749 | //BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE |
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| 119750 | #define BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
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| 119751 | #define BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
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| 119752 | //BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN |
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| 119753 | #define BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
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| 119754 | #define BIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
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| 119755 | //BIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT |
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| 119756 | #define BIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
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| 119757 | #define BIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT__MIN_GNT_MASK 0xFFL |
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| 119758 | //BIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY |
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| 119759 | #define BIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
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| 119760 | #define BIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
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| 119761 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST |
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| 119762 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 119763 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 119764 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 119765 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 119766 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP |
|---|
| 119767 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__VERSION__SHIFT 0x0 |
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| 119768 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 119769 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 119770 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
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| 119771 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 119772 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 119773 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 119774 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 119775 | //BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP |
|---|
| 119776 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 119777 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
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| 119778 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
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| 119779 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 119780 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
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| 119781 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 119782 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 119783 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
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| 119784 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
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| 119785 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 119786 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 119787 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
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| 119788 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
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| 119789 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
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| 119790 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 119791 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
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| 119792 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
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| 119793 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
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| 119794 | //BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL |
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| 119795 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
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| 119796 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
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| 119797 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
|---|
| 119798 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
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| 119799 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 119800 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 119801 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
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| 119802 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
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| 119803 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
|---|
| 119804 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 119805 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 119806 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
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| 119807 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
|---|
| 119808 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
|---|
| 119809 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
|---|
| 119810 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
|---|
| 119811 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
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| 119812 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
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| 119813 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
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| 119814 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
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| 119815 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
|---|
| 119816 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
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| 119817 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
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| 119818 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
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| 119819 | //BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS |
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| 119820 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
|---|
| 119821 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
|---|
| 119822 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
|---|
| 119823 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 119824 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 119825 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 119826 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 |
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| 119827 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
|---|
| 119828 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
|---|
| 119829 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
|---|
| 119830 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
|---|
| 119831 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
|---|
| 119832 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
|---|
| 119833 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L |
|---|
| 119834 | //BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP |
|---|
| 119835 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
|---|
| 119836 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 119837 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
|---|
| 119838 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
|---|
| 119839 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
|---|
| 119840 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
|---|
| 119841 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
|---|
| 119842 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 119843 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
|---|
| 119844 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
|---|
| 119845 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
|---|
| 119846 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
|---|
| 119847 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
|---|
| 119848 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
|---|
| 119849 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
|---|
| 119850 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
|---|
| 119851 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
|---|
| 119852 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
|---|
| 119853 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
|---|
| 119854 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
|---|
| 119855 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
|---|
| 119856 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
|---|
| 119857 | //BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL |
|---|
| 119858 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
|---|
| 119859 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
|---|
| 119860 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
|---|
| 119861 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
|---|
| 119862 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
|---|
| 119863 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
|---|
| 119864 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
|---|
| 119865 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
|---|
| 119866 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
|---|
| 119867 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
|---|
| 119868 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe |
|---|
| 119869 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
|---|
| 119870 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
|---|
| 119871 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_DIS_MASK 0x0010L |
|---|
| 119872 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
|---|
| 119873 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
|---|
| 119874 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
|---|
| 119875 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
|---|
| 119876 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
|---|
| 119877 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
|---|
| 119878 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
|---|
| 119879 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L |
|---|
| 119880 | //BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS |
|---|
| 119881 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
|---|
| 119882 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
|---|
| 119883 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
|---|
| 119884 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
|---|
| 119885 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
|---|
| 119886 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
|---|
| 119887 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
|---|
| 119888 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
|---|
| 119889 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
|---|
| 119890 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
|---|
| 119891 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
|---|
| 119892 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
|---|
| 119893 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
|---|
| 119894 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
|---|
| 119895 | //BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2 |
|---|
| 119896 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
|---|
| 119897 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
|---|
| 119898 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
|---|
| 119899 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
|---|
| 119900 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
|---|
| 119901 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
|---|
| 119902 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
|---|
| 119903 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
|---|
| 119904 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
|---|
| 119905 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
|---|
| 119906 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe |
|---|
| 119907 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 |
|---|
| 119908 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 |
|---|
| 119909 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
|---|
| 119910 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
|---|
| 119911 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
|---|
| 119912 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
|---|
| 119913 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 |
|---|
| 119914 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a |
|---|
| 119915 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f |
|---|
| 119916 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
|---|
| 119917 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
|---|
| 119918 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 119919 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 119920 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 119921 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 119922 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 119923 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 119924 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 119925 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 119926 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L |
|---|
| 119927 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L |
|---|
| 119928 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L |
|---|
| 119929 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 119930 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 119931 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 119932 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 119933 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L |
|---|
| 119934 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L |
|---|
| 119935 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L |
|---|
| 119936 | //BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2 |
|---|
| 119937 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 119938 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 119939 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 119940 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 119941 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 119942 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 119943 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 119944 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 119945 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb |
|---|
| 119946 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc |
|---|
| 119947 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 119948 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 119949 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 119950 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 119951 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 119952 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 119953 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 119954 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 119955 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 119956 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 119957 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L |
|---|
| 119958 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L |
|---|
| 119959 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 119960 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 119961 | //BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2 |
|---|
| 119962 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 119963 | #define BIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 119964 | //BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2 |
|---|
| 119965 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 119966 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 119967 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 119968 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 119969 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 |
|---|
| 119970 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 |
|---|
| 119971 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__DRS_SUPPORTEDRESERVED__SHIFT 0x1f |
|---|
| 119972 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 119973 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 119974 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L |
|---|
| 119975 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L |
|---|
| 119976 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L |
|---|
| 119977 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L |
|---|
| 119978 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2__DRS_SUPPORTEDRESERVED_MASK 0x80000000L |
|---|
| 119979 | //BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2 |
|---|
| 119980 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 119981 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 119982 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 119983 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 119984 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 119985 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 119986 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 119987 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 119988 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 119989 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 119990 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 119991 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 119992 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 119993 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 119994 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 119995 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 119996 | //BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2 |
|---|
| 119997 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 119998 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 |
|---|
| 119999 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 |
|---|
| 120000 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 |
|---|
| 120001 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 |
|---|
| 120002 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 |
|---|
| 120003 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 |
|---|
| 120004 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 |
|---|
| 120005 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 |
|---|
| 120006 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc |
|---|
| 120007 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf |
|---|
| 120008 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 120009 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L |
|---|
| 120010 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L |
|---|
| 120011 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L |
|---|
| 120012 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L |
|---|
| 120013 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L |
|---|
| 120014 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L |
|---|
| 120015 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L |
|---|
| 120016 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L |
|---|
| 120017 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L |
|---|
| 120018 | #define BIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L |
|---|
| 120019 | //BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST |
|---|
| 120020 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 120021 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 120022 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 120023 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 120024 | //BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL |
|---|
| 120025 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 120026 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 120027 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 120028 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 120029 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 120030 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 120031 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 120032 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 120033 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 120034 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 120035 | //BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO |
|---|
| 120036 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 120037 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 120038 | //BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI |
|---|
| 120039 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 120040 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 120041 | //BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA |
|---|
| 120042 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 120043 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL |
|---|
| 120044 | //BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK |
|---|
| 120045 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 120046 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 120047 | //BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64 |
|---|
| 120048 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 120049 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 120050 | //BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64 |
|---|
| 120051 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 120052 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 120053 | //BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING |
|---|
| 120054 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 120055 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 120056 | //BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64 |
|---|
| 120057 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 120058 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 120059 | //BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST |
|---|
| 120060 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 120061 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 120062 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 120063 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 120064 | //BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL |
|---|
| 120065 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 120066 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 120067 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 120068 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 120069 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 120070 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 120071 | //BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE |
|---|
| 120072 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 120073 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 120074 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 120075 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 120076 | //BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA |
|---|
| 120077 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 120078 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 120079 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 120080 | #define BIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 120081 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 120082 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 120083 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 120084 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 120085 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 120086 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 120087 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 120088 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 120089 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 120090 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 120091 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 120092 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 120093 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 120094 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 120095 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1 |
|---|
| 120096 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 120097 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 120098 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2 |
|---|
| 120099 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 120100 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 120101 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 120102 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 120103 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 120104 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 120105 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 120106 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 120107 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 120108 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS |
|---|
| 120109 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 120110 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 120111 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 120112 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 120113 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 120114 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 120115 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 120116 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 120117 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 120118 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 120119 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 120120 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 120121 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 120122 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 120123 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 120124 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 120125 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 120126 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 120127 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 120128 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 120129 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 120130 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 120131 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 120132 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 120133 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 120134 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 120135 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 120136 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 120137 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 120138 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 120139 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 120140 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 120141 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK |
|---|
| 120142 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 120143 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 120144 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 120145 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 120146 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 120147 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 120148 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 120149 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 120150 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 120151 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 120152 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 120153 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 120154 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 120155 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 120156 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 120157 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 120158 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 120159 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 120160 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 120161 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 120162 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 120163 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 120164 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 120165 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 120166 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 120167 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 120168 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 120169 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 120170 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 120171 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 120172 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 120173 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 120174 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 120175 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 120176 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 120177 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 120178 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 120179 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 120180 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 120181 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 120182 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 120183 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 120184 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 120185 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 120186 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 120187 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 120188 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 120189 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 120190 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 120191 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 120192 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 120193 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 120194 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 120195 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 120196 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 120197 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 120198 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 120199 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 120200 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 120201 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 120202 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 120203 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 120204 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 120205 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 120206 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 120207 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS |
|---|
| 120208 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 120209 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 120210 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 120211 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 120212 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 120213 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 120214 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 120215 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 120216 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 120217 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 120218 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 120219 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 120220 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 120221 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 120222 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 120223 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 120224 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK |
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| 120225 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 120226 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 120227 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 120228 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 120229 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 120230 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 120231 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 120232 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 120233 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 120234 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 120235 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 120236 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 120237 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 120238 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 120239 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 120240 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 120241 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 120242 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 120243 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 120244 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 120245 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 120246 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 120247 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 120248 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 120249 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 120250 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc |
|---|
| 120251 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 120252 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 120253 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 120254 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 120255 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 120256 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 120257 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 120258 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 120259 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L |
|---|
| 120260 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0 |
|---|
| 120261 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
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| 120262 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
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| 120263 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1 |
|---|
| 120264 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
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| 120265 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
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| 120266 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2 |
|---|
| 120267 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
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| 120268 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
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| 120269 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3 |
|---|
| 120270 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
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| 120271 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 120272 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0 |
|---|
| 120273 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 120274 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 120275 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1 |
|---|
| 120276 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 120277 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 120278 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2 |
|---|
| 120279 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 120280 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 120281 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3 |
|---|
| 120282 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 120283 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 120284 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST |
|---|
| 120285 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 120286 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 120287 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 120288 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 120289 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 120290 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 120291 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP |
|---|
| 120292 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
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| 120293 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
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| 120294 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 120295 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 120296 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
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| 120297 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
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| 120298 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL |
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| 120299 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
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| 120300 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 120301 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__STU_MASK 0x001FL |
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| 120302 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
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| 120303 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST |
|---|
| 120304 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 120305 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 120306 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 120307 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 120308 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 120309 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 120310 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP |
|---|
| 120311 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 120312 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 120313 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 120314 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 120315 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 120316 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 120317 | //BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL |
|---|
| 120318 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 120319 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 120320 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 120321 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 120322 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 120323 | #define BIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 120324 | |
|---|
| 120325 | |
|---|
| 120326 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
|---|
| 120327 | //BIF_BX_PF1_MM_INDEX |
|---|
| 120328 | #define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 |
|---|
| 120329 | #define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f |
|---|
| 120330 | #define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL |
|---|
| 120331 | #define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L |
|---|
| 120332 | //BIF_BX_PF1_MM_DATA |
|---|
| 120333 | #define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0 |
|---|
| 120334 | #define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL |
|---|
| 120335 | //BIF_BX_PF1_MM_INDEX_HI |
|---|
| 120336 | #define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 |
|---|
| 120337 | #define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL |
|---|
| 120338 | |
|---|
| 120339 | #endif |
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| 120340 | |
|---|
